WO2013145170A1 - 変換装置、周辺装置およびプログラマブルコントローラ - Google Patents
変換装置、周辺装置およびプログラマブルコントローラ Download PDFInfo
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- WO2013145170A1 WO2013145170A1 PCT/JP2012/058190 JP2012058190W WO2013145170A1 WO 2013145170 A1 WO2013145170 A1 WO 2013145170A1 JP 2012058190 W JP2012058190 W JP 2012058190W WO 2013145170 A1 WO2013145170 A1 WO 2013145170A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Definitions
- the present invention relates to a conversion device that performs digital-analog conversion (D / A conversion), a peripheral device that performs setting of the conversion device, and a programmable controller.
- a programmable controller includes a conversion device (hereinafter referred to as a D / A conversion device) that converts a digital value generated inside the PLC into an analog value for input to a controlled device.
- a D / A conversion device As a conventional D / A converter, when a digital value is written at predetermined intervals from the outside of the D / A converter (for example, a CPU device constituting the PLC), there is one that sequentially D / A converts this digital value. .
- the D / A conversion device has the ability to perform D / A conversion at high speed, since the actual D / A conversion speed depends on the speed at which the digital value is written from the outside, the actual D / A conversion is performed. There was a problem that the speed decreased.
- Patent Document 1 discloses a programmable controller analog signal processing that performs a series of operations from A / D conversion to D / A conversion based on an analog signal input from outside without using a CPU device. An apparatus is disclosed.
- Japanese Patent No. 2914100 (for example, paragraph 0033, FIG. 4)
- the present invention has been made in view of the above, and an object of the present invention is to obtain a conversion device, a peripheral device, and a programmable controller that can output a waveform as fast as possible and can debug the output waveform. To do.
- the present invention provides a waveform data string storage unit that stores a waveform data string composed of a plurality of digital values, operation mode designation data that designates an operation mode, A control data storage unit in which update request data is written, and when the operation mode designation data designates the first operation mode, the digital values constituting the waveform data sequence are read out in the waveform data sequence storage unit Are sequentially read and output for each output period from the address to be read while sequentially updating the addresses to the addresses in which subsequent digital values are stored for each preset output period, and the operation mode designation data is the second When the operation mode is designated, the digital value constituting the waveform data string, the read target address, and the update request data are set.
- a digital value output unit that reads out and outputs from the address to be read while updating at the timing of writing, and a D / A conversion unit that converts the digital value output from the digital value output unit into an analog value, It is characterized by providing.
- the conversion device sequentially converts a digital value prepared in advance as a waveform data string into an analog value, and when the second operation mode is designated. Since the read source address is updated at the timing when the update request data is written, the waveform can be output as fast as possible and the output waveform can be debugged.
- FIG. 1 is a diagram illustrating a configuration of a PLC system including a D / A conversion device according to an embodiment of the present invention.
- FIG. 2 is a diagram showing the data structure of the waveform data string storage area.
- FIG. 3 is a flowchart showing the operation of the digital value output unit of the D / A converter according to the embodiment of the present invention.
- FIG. 1 is a block diagram illustrating a configuration of a PLC system 10 including a D / A converter according to an embodiment.
- the PLC system 10 illustrated in FIG. 1 includes a PLC 1000 and a peripheral device 2000.
- PLC 1000 and peripheral device 2000 are connected to each other via connection cable 3000.
- Peripheral device 2000 includes waveform data string support tool 500 that can set and debug D / A conversion device 100 according to the embodiment of the present invention.
- the waveform data string support tool 500 is realized by installing waveform data string operation software in the peripheral device 2000.
- the peripheral device 2000 includes a CPU (Central Processing Unit), a ROM (Read Only Memory) that stores waveform data string operation software in advance, a RAM (Random Access Memory), a mouse and a keyboard that accept input from the user. And an input device (input unit) configured with a liquid crystal display or the like.
- the CPU expands the waveform data string operation software in the RAM, and functions as the waveform data string support tool 500 based on the control by the waveform data string operation software expanded in the RAM.
- the display contents generated by the waveform data string support tool 500 are displayed on the display device, and the user performs setting operations and debugging operations on the waveform data string support tool 500 by operating the input device while checking the display contents. Can do.
- the PLC 1000 includes a D / A conversion device 100 and a CPU device 200.
- PLC 1000 may further include a device (not shown). Examples of the device (not shown) include a motion controller device that realizes multi-axis position control by controlling a servo amplifier, and a temperature controller device that outputs a temperature control signal based on a command from the CPU device 200.
- the devices included in the PLC 1000 are connected to each other via an inter-device bus 300.
- the CPU device 200 includes an arithmetic unit 220 that executes control of the CPU device 200 as a whole, an external memory interface 210 connected to an external memory such as a memory card, and a built-in memory 230.
- the external memory or built-in memory 230 stores a user program, data used for executing the user program, and execution result data of the user program.
- the user program is a program for controlling an external device to be controlled by the PLC 1000, and is constituted by, for example, a ladder program or a C language program.
- the CPU device 200 includes a peripheral device interface 240 connected to the peripheral device 2000 and a bus interface 250 connected to the inter-device bus 300.
- the external memory interface 210, the arithmetic unit 220, the built-in memory 230, the peripheral device interface 240, and the bus interface 250 are connected to each other via the internal bus 260.
- the CPU device 200 repeatedly executes the user program, reads data used for executing the user program, and writes the execution result of the user program every predetermined control cycle. This control cycle is equal to the execution cycle of the user program executed by the CPU device 200.
- the writing of the execution result of the user program includes an operation of writing a digital value in the shared memory 140 of the D / A converter 100 described later.
- the D / A conversion device 100 includes a calculation unit 130 that controls the entire D / A conversion device 100, a shared memory 140 that can be written to and read from the CPU device 200, and a D that converts a digital value into an analog value. / A converter 120.
- the D / A conversion device 100 includes an analog output interface 110 connected to an external device (ie, a controlled device) to be controlled by the PLC 1000, and a trigger signal input interface connected to an external input terminal for inputting a trigger signal.
- 150 a bus interface 160 connected to the inter-device bus 300, and a counter 180 that outputs a counter signal for each D / A conversion cycle.
- the D / A conversion cycle is a value set as a cycle for converting one digital value into an analog value.
- the calculation unit 130, the shared memory 140, and the bus interface 160 are connected to each other via the internal bus 170.
- the D / A conversion unit 120 is connected to the calculation unit 130, and the analog output interface 110 is connected to the D / A conversion unit 120.
- the trigger signal input interface 150 is connected to the calculation unit 130.
- the shared memory 140 includes a waveform data string storage area 142 for storing a waveform data string.
- the waveform data string is a digital data string composed of a plurality of digital values.
- FIG. 2 is a diagram showing the data structure of the waveform data string storage area 142.
- the waveform data string storage area 142 is secured so that a plurality of waveform data strings can be stored.
- Each waveform data string can be composed of an arbitrary number of points.
- the number of points means the number of data.
- One point corresponds to, for example, 16 bits or 32 bits, and corresponds to one digital value.
- the shared memory 140 includes a waveform output format data storage area 143 for storing waveform output format data.
- the waveform output format data is a parameter that specifies the output format of the waveform output from the analog output interface 110 by the D / A converter 100. In this embodiment, the start address, the number of output data, and the output cycle are specified. To do.
- the head address is the address of the first digital value of the waveform data string stored in the waveform data string storage area 142. In the example of FIG. 2, the head address of “waveform data string A” stored in the waveform data string storage area 142 is “Aa”.
- the number of output data is the number of points in the waveform data string, that is, the number of digital values constituting the waveform data string. In the example of FIG. 2, the number of output data of “waveform data string A” is “An point”.
- the output period is specified by a value obtained by multiplying the D / A conversion period by an integer of 1 or more.
- the D / A conversion apparatus 100 sequentially sets addresses to be read in the waveform data string storage area 142 to addresses where subsequent digital values are stored for each preset output cycle. While updating, it is possible to sequentially read from the read target address every output cycle, and to sequentially output the read output data by D / A conversion. Thereby, D / A conversion can be performed without requiring input of a digital value for each D / A conversion from the CPU device 200. Further, since the D / A conversion apparatus 100 sequentially converts the digital value prepared in advance as a waveform data string into an analog value, the D / A conversion unit 120 performs analog conversion at a speed up to the D / A conversion speed by the D / A conversion unit 120. A value can be output.
- the D / A conversion device 100 does not automatically increment the address, but can debug the waveform output in the automatic control mode. It is possible to operate in an operation mode (second mode) in which an address is updated with an update command as a trigger.
- an operation mode for debugging a step execution mode and an output address change mode are prepared.
- the step execution mode is an operation mode in which the address is incremented every time an address update command is issued, that is, the read source address is updated to an address in which subsequent digital values constituting the waveform data string are stored. . Note that issuing an address update command while the D / A conversion device 100 is operating in the step execution mode is referred to as step execution.
- the output address change mode is an operation mode in which the address from which the output data is read is jumped from the address at which the output data was last read to the address specified by the output address specifying data.
- the jump destination address is specified by waveform output control data described later. Since the D / A conversion device 100 supports the step execution mode, the user can confirm whether or not the waveform output in the automatic control mode has a desired shape, for each output analog value data. can do. In addition, since the D / A conversion device 100 supports the output address change mode, the user can check the value at an arbitrary position in the waveform of the analog value that is continuously output. In addition, an arbitrary waveform data string among a plurality of waveform data strings can be confirmed.
- the shared memory 140 includes a waveform output control data storage area 144 for storing waveform output control data.
- the waveform output control data refers to commands and parameters for switching the operation mode of the D / A converter 100 and operating in each operation mode.
- the waveform output control data includes operation mode designation data that designates an operation mode. Any one of an automatic control mode, a step execution mode, and an output address change mode is designated by the operation mode designation data.
- the waveform output control data includes step execution request data used as an address update trigger, output address designation data for specifying the jump destination address in the output address change mode, and output data at the address designated by the output address designation data.
- Output address change request data used as a trigger for jumping the read source, a parameter indicating the current operation mode, and an address (hereinafter, read address) from which the output data is read in the next output cycle.
- the waveform output control data may include various parameters such as the current output address that is the address of the storage source of the last output data at that time.
- the storage source of the system program is not limited to the built-in memory 190 as long as the calculation unit 130 can read the system program.
- the storage source of the system program may be, for example, an external memory.
- the calculation unit 130 includes a waveform data string writing unit 131 that writes a waveform data string in the waveform data string storage area 142, a waveform data string generation unit 132 that generates a waveform data string based on waveform specifying data described later, and a waveform data string A digital value output unit 133 that reads a digital value from the storage area 142 and outputs the digital value to the D / A conversion unit 120.
- the waveform data string is written into the waveform data string storage area 142 by any one of the following five methods.
- the calculation unit 220 of the CPU device 200 creates a waveform data string by executing a user program stored in the built-in memory 230 or the external memory, and the waveform data string is stored in a waveform data string storage area. 142 is written. This is realized by providing the waveform data string storage area 142 in the shared memory 140 that can be directly written from the CPU device 200.
- the user first attaches an external memory in which a waveform data string is stored in advance to the external memory interface 210 of the CPU device 200.
- the CPU device 200 requests the D / A conversion device 100 to read from the external memory.
- the waveform data string writing unit 131 of the D / A converter 100 accepts this request, the waveform data string stored in the external memory is read out via the inter-device bus 300, and this waveform data string is read out.
- the data is written in the waveform data string storage area 142.
- the user creates waveform graphical data by drawing a waveform by operating the mouse on the waveform data string support tool 500 of the external peripheral device 2000.
- the waveform data string support tool 500 generates a waveform data string based on the graphical waveform data created by the user's operation, and the waveform data string is transmitted to the waveform data via the CPU device 200 and the inter-device bus 300.
- the data is written in the column storage area 142.
- the user first stores the CSV format or Excel format file in which the waveform data string is stored in the external peripheral device 2000.
- the waveform data string support tool 500 of the peripheral device 2000 reads the waveform data string from this file, and writes this waveform data string into the waveform data string storage area 142 via the CPU device 200 and the inter-device bus 300. is there.
- the waveform data string generation unit 132 receives data for specifying a basic waveform such as (hereinafter referred to as “waveform specifying data”) and the waveform specifying data.
- waveform specifying data include the type of waveform such as “sine wave”, the period of the waveform, and the amplitude of the waveform.
- the waveform data string generation unit 132 generates a waveform data string based on the waveform specifying data.
- the waveform data string writing unit 131 writes the waveform data string generated by the waveform data string generating unit 132 in the waveform data string storage area 142.
- the output confirmation of the D / A conversion device 100 and the wiring check can be easily performed without using a user program for the CPU device.
- the waveform data string is written into the waveform data string storage area 142 at any timing by any one of the above five methods.
- the start address of the waveform data string newly written in the waveform data string storage area 142 is an address one point after the last address of the waveform data string written in the waveform data string storage area 142 immediately before. That is, in the example of FIG. 2, the start address “Ba” of “waveform data string B” written in the waveform data string storage area 142 immediately after “waveform data string A” is the end of “waveform data string A”. This is an address one point after the address. Further, when “waveform data string B” is written, “waveform data string A” may be overwritten with “waveform data string B”. Further, the values stored at the address designated by the user among the digital values constituting the waveform data string may be individually rewritten.
- the waveform output format data is written in the waveform output format data storage area 143 when the waveform data string is written in the waveform data string storage area 142 or thereafter.
- the waveform output format data is written in the waveform output format data storage area 143 by the means for writing the waveform data string in the waveform data string storage area 142. That is, for example, when the waveform data string is written in the waveform data string storage area 142 by the first method, the calculation unit 220 of the CPU device 200 writes the waveform output format data in the waveform output format data storage area 143.
- the waveform output control data is written in the waveform output control data storage area 144 by one of the following three methods.
- the CPU device 200 writes waveform output control data in the waveform output control data storage area 144 by executing a user program. This is realized by providing the waveform output control data storage area 144 in the shared memory 140 that can be directly written from the CPU device 200.
- the user registers the waveform output control data on the waveform data string support tool 500 of the peripheral device 2000. Then, when the user issues a write command on the waveform data string support tool 500, the waveform output control data is written to the waveform output control data storage area 144 via the CPU device 200 and the inter-device bus 300.
- the digital value output unit 133 writes the waveform output control data in the waveform output control data storage area 144.
- the digital value output unit 133 detects the calculation result of the digital value output unit 133 and the input to the trigger signal input I / F 150 and writes the waveform output control data.
- the D / A conversion apparatus 100 can accept a step execution request serving as an address update trigger and an output address change request serving as a read address change trigger by any one of the following four methods. .
- the digital value output unit 133 itself issues a request based on the calculation result of the digital value output unit 133. Method in which digital value output unit 133 accepts the request / Method of accepting a request input from trigger signal input I / F 150
- the output address specification data may be described in any format as long as the jump destination address can be specified. For example, there are a method of relatively specifying a movement amount from the current output address, a method of specifying an absolute address of a jump destination, and the like.
- FIG. 3 is a flowchart illustrating the operation of the digital value output unit 133 of the D / A conversion device 100 according to the embodiment.
- the digital value output unit 133 determines whether or not the automatic control mode is designated by referring to the operation mode designation data included as parameters constituting the waveform output control data (step S1). If the automatic control mode is selected (step S1, Yes), the digital value output unit 133 determines whether there is an automatic control mode stop request (step S2).
- the digital value output unit 133 reads the digital value stored at the read address in the waveform data string storage area 142, and uses this digital value as D / The data is output to the A conversion unit 120 (step S3). Note that the read address when the first digital value of the waveform data string is output to the D / A converter 120 is the aforementioned start address.
- step S3 the digital value output to the D / A converter 120 in the process of step S3 is converted into an analog value by the D / A converter 120. Thereafter, the analog value is output as a current value or a voltage value to an external device via the analog output interface 110.
- step S3 the digital value output unit 133 determines whether or not the next output cycle has been reached (step S4).
- the digital value output unit 133 executes the determination process of step S4 based on the counter signal from the counter 180 and the output cycle recorded in the waveform output format data storage area 143.
- step S4 When the next output cycle has been reached (step S4, Yes), the digital value output unit 133 changes the read address so that only one point approaches the tail address (step S5), and executes the determination process of step S2. .
- step S4 When the next output cycle has not been reached (step S4, No), the digital value output unit 133 skips the process of step S5.
- step S2 When there is a request for stopping the automatic control mode (step S2, Yes), the digital value output unit 133 deletes the operation mode designation data (step S6), and then executes the determination process of step S1.
- the automatic control mode stop request and the output address change mode stop request to be described later may be given by a command constituting the waveform output control data in the same manner as the step execution request and the output address change request.
- the digital value output unit 133 determines whether or not the step execution mode is designated by the operation mode designation data (Step S7).
- the digital value output unit 133 determines whether there is a step execution mode stop request (step S8).
- the digital value output unit 133 determines whether a step execution request has been issued (step S9).
- a step execution request is issued can be confirmed by referring to the value of the step execution request data included as a parameter constituting the waveform output control data. For example, a state where the value of the step execution request data is “1” indicates a state where the step execution request is issued, and a state where the value of the step execution request data is “0” indicates that the step execution request is Indicates that has not been issued.
- the digital value output unit 133 executes the process at Step S8.
- the digital value output unit 133 reads the digital value stored at the read address in the waveform data string storage area 142, and uses this digital value as the D / A. It outputs to the conversion part 120 (step S10). Then, the digital value output unit 133 advances the read address by one point (step S11). Then, the digital value output unit 133 deletes the step execution request (step S12), and then executes the determination process of step S8.
- erasing a step execution request means rewriting the value of the step execution request data to a value indicating a state in which no step execution request has been issued.
- the digital value output unit 133 determines whether or not the output address change mode is designated by the operation mode designation data (Step S13).
- the digital value output unit 133 determines whether there is an output address change mode stop request (step S14).
- the digital value output unit 133 determines whether an output address change request has been issued (step S15). Whether or not an output address change request is issued can be confirmed by referring to the value of the output address change request data included as a parameter constituting the waveform output control data. For example, the state where the value of the output address change request data is “1” indicates the state where the output address change request is issued, and the state where the value of the output address change request data is “0” Indicates that no output address change request has been issued.
- the digital value output unit 133 executes the determination process at Step S14 again. If an output address change request has been issued (step S15, Yes), the digital value output unit 133 updates the read address with the address specified by the output address specification data in the waveform output control data storage area 144 (step S15). S16), the digital value stored at the read address in the waveform data string storage area 142 is read, and this digital value is output to the D / A converter 120 (step S17). Then, the digital value output unit 133 deletes the output address change request (step S18), and then executes the determination process of step S14. Note that erasing the output address change request means rewriting the value of the output address change request data to a value indicating a state in which no output address change request has been issued.
- step S8 When there is a step execution mode stop request (step S8, Yes), when the output address change mode is not specified (step S13, No), or when there is an output address change mode stop request (step S14, Yes), digital The value output unit 133 executes the process of step S6.
- Output, operation mode specification data specifies step execution mode or output address change mode A digital value output unit 133 that reads out and outputs the digital values constituting the waveform data string from the read target address while updating the read target address at the timing when the update request data is written, and a digital value output unit Since the D / A converter 100 is configured to include the D / A converter 120 that converts the digital value output by the 133 into an analog value, when the automatic control mode is designated, the D / A converter 100 Since a digital value prepared in advance as a waveform data string is sequentially converted into an analog value, an analog value can be output at a speed with the D / A conversion speed by the D / A converter 120 as an upper limit.
- the D / A converter 100 updates the address at the timing when the update request data is written, so that the user can output the waveform output in the automatic control mode. Can be confirmed. In other words, the waveform can be output as fast as possible, and the output waveform can be debugged.
- the waveform output control data storage area 144 is further written with output address designation data for designating the address in the waveform data string storage area 142, and the digital value output unit 133 designates the output address change mode with the operation mode designation data.
- the D / A converter 100 is configured to update the read target address to the address designated by the output address designation data, the user outputs the digital value constituting the waveform data from an arbitrary address. Will be able to.
- the digital value output unit 133 updates the address to be read to the address in which the subsequent digital value constituting the waveform data string is stored. Since the / A converter 100 is configured, the timing at which the waveform data string is D / A converted and output can be controlled by a pulse input from the outside.
- the waveform data string stored in the waveform data string storage area 142 can be rewritten at an arbitrary timing. That is, when the user operates the D / A converter 100 in the output address change mode or the step execution mode and determines that an analog value of a desired waveform is not obtained, the D / A converter 100, Using the CPU device 200 and the waveform data string support tool 500, the waveform data string stored in the waveform data string storage area 142 can be corrected. In addition, when the digital value corresponding to the currently output analog value is rewritten, the digital value output unit 133 may immediately update the output analog value based on the rewritten digital value. Good.
- the conversion device, the peripheral device, and the programmable controller according to the present invention are preferably applied to the conversion device that performs D / A conversion, the peripheral device that sets the conversion device, and the programmable controller.
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Abstract
Description
図1は、実施の形態におけるD/A変換装置を含むPLCシステム10の構成を示すブロック図である。図1に示すPLCシステム10は、PLC1000と周辺装置2000とを備える。PLC1000と周辺装置2000とは、接続ケーブル3000を介して互いに接続される。
・CPU装置200から発行される要求を受け付ける方法
・波形データ列支援ツール500から発行される要求を受け付ける方法
・デジタル値出力部133の演算結果により、デジタル値出力部133自身が要求を発行し、デジタル値出力部133が当該要求を受け付ける方法
・トリガ信号入力I/F150から入力される要求を受け付ける方法
100 D/A変換装置
110 アナログ出力インタフェース
120 D/A変換部
130 演算部
131 波形データ列書込部
132 波形データ列生成部
133 デジタル値出力部
140 共用メモリ
142 波形データ列記憶領域
143 波形出力形式データ記憶領域
144 波形出力制御データ記憶領域
150 トリガ信号入力インタフェース
160 バスインタフェース
170 内部バス
180 カウンタ
190 内蔵メモリ
200 CPU装置
210 外部メモリインタフェース
220 演算部
230 内蔵メモリ
240 周辺装置インタフェース
250 バスインタフェース
260 内部バス
300 装置間バス
500 波形データ列支援ツール
1000 PLC
2000 周辺装置
3000 接続ケーブル
Claims (9)
- 複数のデジタル値から構成される波形データ列を記憶する波形データ列記憶部と、
動作モードを指定する動作モード指定データと、更新要求データとが書き込まれる制御データ記憶部と、
前記動作モード指定データが第1の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記波形データ列記憶部内の読み出し対象のアドレスを予め設定された出力周期毎に後続のデジタル値が格納されたアドレスに順次更新しながら前記読み出し対象のアドレスから出力周期毎に順次読み出して出力し、前記動作モード指定データが第2の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記読み出し対象のアドレスを前記更新要求データが書き込まれたタイミングで更新しながら前記読み出し対象のアドレスから読み出して出力するデジタル値出力部と、
前記デジタル値出力部が出力する前記デジタル値をアナログ値に変換するD/A変換部と、
を備えることを特徴とする変換装置。 - 前記制御データ記憶部は、前記波形データ列記憶部内のアドレスを指定するアドレス指定データがさらに書き込まれ、
前記デジタル値出力部は、前記動作モード指定データが第2の動作モードを指定する場合、前記読み出し対象のアドレスを前記アドレス指定データが指定するアドレスに更新する、
ことを特徴とする請求項1に記載の変換装置。 - 前記デジタル値出力部は、前記動作モード指定データが第2の動作モードを指定する場合、前記読み出し対象のアドレスを前記波形データ列を構成する後続のデジタル値が格納されたアドレスに更新する、
ことを特徴とする請求項1に記載の変換装置。 - 複数のデジタル値から構成される波形データ列を記憶する波形データ列記憶部と、動作モードを指定する動作モード指定データと、更新要求データとが書き込まれる制御データ記憶部と、前記動作モード指定データが第1の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記波形データ列記憶部内の読み出し対象のアドレスを予め設定された出力周期毎に後続のデジタル値が格納されたアドレスに順次更新しながら前記読み出し対象のアドレスから出力周期毎に順次読み出して出力し、前記動作モード指定データが第2の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記読み出し対象のアドレスを前記更新要求データが書き込まれたタイミングで更新しながら前記読み出し対象のアドレスから読み出して出力するデジタル値出力部と、前記デジタル値出力部が出力する前記デジタル値をアナログ値に変換するD/A変換部と、を備える変換装置に接続され、
ユーザからの入力を受け付ける入力部と、
前記入力部が受け付けた入力に基づいて前記制御データ記憶部に前記動作モード指定データまたは前記更新要求データを書き込む波形データ列支援部と、
を備えることを特徴とする周辺装置。 - 前記波形データ列支援部は、前記入力部が受け付けた入力に基づいて、前記変換装置が備える制御データ記憶部に、前記波形データ列記憶部内のアドレスを指定するアドレス指定データを書き込み、
前記変換装置が備えるデジタル値出力部は、前記動作モード指定データが第2の動作モードを指定する場合、前記読み出し対象のアドレスを前記制御データ記憶部に書き込まれたアドレス指定データが指定するアドレスに更新する、
ことを特徴とする請求項4に記載の周辺装置。 - 前記波形データ列支援部は、前記入力部が受け付けた入力に基づいて、前記波形データ列記憶部に波形データ列を書き込む、
ことを特徴とする請求項4または請求項5に記載の周辺装置。 - 複数のデジタル値から構成される波形データ列を記憶する波形データ列記憶部と、
動作モードを指定する動作モード指定データと、更新要求データとが書き込まれる制御データ記憶部と、
前記動作モード指定データが第1の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記波形データ列記憶部内の読み出し対象のアドレスを予め設定された出力周期毎に後続のデジタル値が格納されたアドレスに順次更新しながら前記読み出し対象のアドレスから出力周期毎に順次読み出して出力し、前記動作モード指定データが第2の動作モードを指定する場合、前記波形データ列を構成する前記デジタル値を、前記読み出し対象のアドレスを前記更新要求データが書き込まれたタイミングで更新しながら前記読み出し対象のアドレスから読み出して出力するデジタル値出力部と、
前記デジタル値出力部が出力する前記デジタル値をアナログ値に変換するD/A変換部と、
を備えることを特徴とするプログラマブルコントローラ。 - 前記制御データ記憶部は、前記波形データ列記憶部内のアドレスを指定するアドレス指定データがさらに書き込まれ、
前記デジタル値出力部は、前記動作モード指定データが第2の動作モードを指定する場合、前記読み出し対象のアドレスを前記アドレス指定データが指定するアドレスに更新する、
ことを特徴とする請求項7に記載のプログラマブルコントローラ。 - 前記デジタル値出力部は、前記動作モード指定データが第2の動作モードを指定する場合、前記読み出し対象のアドレスを前記波形データ列を構成する後続のデジタル値が格納されたアドレスに更新する、
ことを特徴とする請求項7に記載のプログラマブルコントローラ。
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PCT/JP2012/058190 WO2013145170A1 (ja) | 2012-03-28 | 2012-03-28 | 変換装置、周辺装置およびプログラマブルコントローラ |
US13/810,027 US8775703B2 (en) | 2012-03-28 | 2012-03-28 | Conversion device, peripheral device, and programmable logic controller |
EP12808667.5A EP2750295B1 (en) | 2012-03-28 | 2012-03-28 | Conversion device, peripheral device, and programmable controller |
JP2012534884A JP5148021B1 (ja) | 2012-03-28 | 2012-03-28 | 変換装置、周辺装置およびプログラマブルコントローラ |
KR1020137000113A KR101409618B1 (ko) | 2012-03-28 | 2012-03-28 | 변환 장치, 주변장치 및 프로그래머블 콘트롤러 |
CN201280002010.8A CN103430454B (zh) | 2012-03-28 | 2012-03-28 | 转换装置、外围装置以及可编程控制器 |
TW101134429A TWI470400B (zh) | 2012-03-28 | 2012-09-20 | 變換裝置、周邊裝置及可編程邏輯控制器 |
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KR (1) | KR101409618B1 (ja) |
CN (1) | CN103430454B (ja) |
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KR101961603B1 (ko) * | 2016-04-22 | 2019-03-22 | 미쓰비시덴키 가부시키가이샤 | 디지털 아날로그 변환 장치, 제어 장치, 및 제어 시스템 |
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---|---|---|---|---|
JPH0353017U (ja) * | 1989-09-28 | 1991-05-22 | ||
JPH0563448A (ja) * | 1991-08-30 | 1993-03-12 | Yokogawa Electric Corp | 波形発生装置 |
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CN1058678A (zh) * | 1990-08-01 | 1992-02-12 | 高敏 | 高速高精度模数变换器 |
JPH0651813A (ja) * | 1992-07-28 | 1994-02-25 | Matsushita Electric Works Ltd | A/d変換ユニット |
JP2914100B2 (ja) | 1993-06-30 | 1999-06-28 | 三菱電機株式会社 | プログラマブルコントローラ用アナログ信号処理装置 |
US6366971B1 (en) * | 1998-01-09 | 2002-04-02 | Yamaha Corporation | Audio system for playback of waveform sample data |
JP4105831B2 (ja) * | 1998-09-11 | 2008-06-25 | 株式会社アドバンテスト | 波形発生装置、半導体試験装置、および半導体デバイス |
US6359575B1 (en) * | 1999-12-09 | 2002-03-19 | National Instruments Corporation | Analog to digital converter having a digital to analog converter mode |
EP1739841B1 (en) * | 2004-02-25 | 2016-04-13 | Mitsubishi Denki Kabushiki Kaisha | Waveform generation method, radar device, and oscillator for radar device |
US7668234B2 (en) * | 2005-06-14 | 2010-02-23 | Anritsu Corp. | Test signal generating apparatus for communications equipment and test signal generating method for communications equipment |
KR100753338B1 (ko) * | 2005-12-28 | 2007-08-30 | 엘에스산전 주식회사 | 아날로그 신호의 입력모듈 |
DE112008001574T5 (de) * | 2007-06-05 | 2010-04-29 | Advantest Corp. | Wellenform-Erzeugungsgerät, Wellenform-Erzeugungsverfahren und Programm |
CN102362232B (zh) * | 2009-03-23 | 2014-10-29 | 三菱电机株式会社 | A/d变换装置以及可编程控制器系统 |
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---|---|---|---|---|
JPH0353017U (ja) * | 1989-09-28 | 1991-05-22 | ||
JPH0563448A (ja) * | 1991-08-30 | 1993-03-12 | Yokogawa Electric Corp | 波形発生装置 |
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EP2750295A1 (en) | 2014-07-02 |
JPWO2013145170A1 (ja) | 2015-08-03 |
TWI470400B (zh) | 2015-01-21 |
EP2750295A4 (en) | 2015-02-25 |
KR20130119410A (ko) | 2013-10-31 |
JP5148021B1 (ja) | 2013-02-20 |
US8775703B2 (en) | 2014-07-08 |
TW201339796A (zh) | 2013-10-01 |
CN103430454B (zh) | 2016-10-12 |
US20130262722A1 (en) | 2013-10-03 |
CN103430454A (zh) | 2013-12-04 |
KR101409618B1 (ko) | 2014-06-18 |
EP2750295B1 (en) | 2016-07-27 |
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