WO2013139154A1 - Procédé de fabrication intégré pour couche d'oxyde multicouche du type locos - Google Patents

Procédé de fabrication intégré pour couche d'oxyde multicouche du type locos Download PDF

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Publication number
WO2013139154A1
WO2013139154A1 PCT/CN2012/086850 CN2012086850W WO2013139154A1 WO 2013139154 A1 WO2013139154 A1 WO 2013139154A1 CN 2012086850 W CN2012086850 W CN 2012086850W WO 2013139154 A1 WO2013139154 A1 WO 2013139154A1
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Prior art keywords
oxide layer
thickness
region
locos
multilayer
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PCT/CN2012/086850
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English (en)
Chinese (zh)
Inventor
吴孝嘉
罗泽煌
章舒
许剑
何延强
何敏
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无锡华润上华半导体有限公司
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Publication of WO2013139154A1 publication Critical patent/WO2013139154A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Definitions

  • the present invention relates to a method of fabricating an integrated circuit (IC), and more particularly to using LOCOS (LOCal Oxidation of Silicon) is an integrated fabrication method for fabricating oxide layers of various thicknesses and belongs to the field of semiconductor device manufacturing.
  • LOCOS LOCal Oxidation of Silicon
  • LDMOS Longeral Double-diffused The MOS
  • MOS Metal Organic Chemical Vapor
  • LOCOS LOCal Oxidation of
  • Silicon Processes and simultaneously fabricates a wide range of devices withstand voltage specifications.
  • the traditional LOCOS process is fabricated by first growing a pad oxide layer (PAD OX) and pad silicon nitride (PAD) on a silicon substrate. SIN), then use the photolithography and etching process to define the area where the oxide layer needs to be grown, and then use PAD OX and PAD SIN as the barrier growth oxide layer, and then remove the PAD by wet etching. SIN and PAD OX, finally leaving the required oxide layer.
  • the oxide layer is grown, the silicon under the edge of the barrier layer reacts with the invading oxygen atoms to form silicon dioxide, which arches the barrier layer to form a bird's beak. The beak will consume an active active area, resulting in an increase in device size.
  • a conventional LOCOS process is often used to form an isolation oxide layer and a drift region oxide layer. This has the phenomenon that oxide layers of various thicknesses exist at the same time, and the lengths of the oxide layers with different thicknesses are different.
  • repeated LOCOS fabrication processes will result in repeated growth and corrosion of the PAD. OX and PAD SIN are costly to produce and have a long production cycle.
  • STI Shallow Trench Isolation
  • the shallow trench isolation process creates isolation of the device and solves the problem of the beak.
  • STI achieves device isolation by trenching a deep trench on a silicon substrate and embedding an isolation oxide layer.
  • the STI process can solve the problem of the beak, but it also has disadvantages:
  • STI can only solve the problem of LOCOS isolated beak. It still needs multiple LOCOS processes to make drift oxide layers of different thicknesses.
  • the present invention will provide a new process for fabricating various thickness oxide layers using the LOCOS process to effectively integrate the fabrication of oxide layers of various thicknesses, reduce costs, and shorten the fabrication cycle.
  • the technical problem to be solved by the present invention is to provide an integrated manufacturing method of a multilayer oxide layer using a LOCOS process.
  • An integrated method for fabricating a LOCOS multilayer oxide layer comprising the steps of:
  • Step 1 providing a lower chip structure required to fabricate a multilayer oxide layer
  • Step two forming a liner on the underlying chip structure
  • Step 3 defining a first thickness oxide layer region on the pad by using a photolithography process, and opening in the first thickness oxide layer region by an etching process;
  • Step 4 performing first oxidation growth on the underlying chip structure having the opening of the first thickness oxide layer region
  • Step 5 after the first oxidation growth, defining a second thickness oxide layer region on the liner by a photolithography process, and opening in the second thickness oxide layer region by an etching process;
  • Step 6 performing a second oxidation growth after the opening of the second thickness oxide layer region is formed, thereby forming the first and second thickness oxide layers;
  • Step 7 Remove the liner, perform wet etching to adjust the bird's beak, and complete the production of the multilayer oxide layer.
  • the forming the spacer comprises first forming a pad oxide layer, and then forming a pad silicon nitride on the pad oxide layer.
  • the first thickness oxide layer includes an isolation region oxide layer and a drift region first oxide layer; and the second thickness oxide layer is a drift region second oxide layer.
  • the thickness of the isolation region oxide layer and the drift region first oxide layer is obtained by first oxidation growth and second oxidation growth accumulation, and both are greater than the thickness of the second oxide layer in the drift region, and the drift region is The thickness of the dioxide layer is obtained by the second oxidation growth.
  • the impurity concentration of the first and second oxide layers in the drift region is adjusted by an ion implantation process before the first and second oxidation growths are performed.
  • the thickness of the oxide layer formed by the first oxidation growth is 3.5 to 4.5K. ⁇ ;
  • the thickness of the oxide layer formed by the second oxidation growth is 2.5 ⁇ 3.5K ⁇ .
  • the first and second oxidation growths are carried out using a furnace tube at a temperature of 800 to 1100 °C.
  • n-thickness oxide layer is formed according to the above method, after step 6 and before step 7, the following steps are further included:
  • a third thickness oxide layer region is defined on the liner by photolithography and etching processes, and a third third oxide growth region is opened in the third thickness oxide layer region, and the third oxidation growth is repeated.
  • the steps are completed until the nth oxidation growth is completed, thereby forming first to nth thickness oxide layers, where n is a natural number greater than 2.
  • the invention adopts the LOCOS process to integrate the process of the LOCOS isolation oxide layer and the drift region oxide layer, optimizes the thickness ratio of the multilayer oxide layer and the wet etching, and solves the beak problem when the oxide layers of various thicknesses exist simultaneously. , achieving lower cost and shorter production cycle in the LDMOS process.
  • n oxide layers of different thicknesses are produced, (n-1) times of PAD can be saved Growth and removal processes of OX and PAD SIN.
  • FIG. 1 is a schematic flow chart of an integrated manufacturing method of a LOCOS multilayer oxide layer according to Embodiment 1 of the present invention
  • FIG. 2 is a graph showing the relationship between the breakdown voltage of the NLDMOS in the thin oxide region and the rinsing time of the bird's beak in the first embodiment of the present invention
  • FIG. 3 is a graph showing the relationship between the opening voltage of an NMOS narrow tube and the rinsing time of a bird's beak in a thick oxide layer region according to an embodiment of the present invention
  • FIG. 4 is a schematic view showing the L-directional shape of the NLDMOS groove length L direction of the bird's mouth rinsing time of 60 s according to the first embodiment of the present invention
  • FIG. 5 is a schematic diagram showing the L-directional shape of the NLDMOS groove length L direction of the bird's mouth rinsing time of 200 s according to the first embodiment of the present invention
  • FIG. 6 is a schematic diagram showing the shape of a groove width W direction of an NMOS with a bird's mouth rinsing time of 60 s according to the first embodiment of the present invention
  • FIG. 7 is a schematic diagram showing the shape of a groove width W direction of an NMOS with a bird's mouth rinsing time of 200 s according to the first embodiment of the present invention
  • Fig. 8 is a graph showing the fitting curve of the growth ratio of the laminated oxide layer in the second embodiment of the present invention.
  • the isolation oxide layer and the drift region oxide layer are formed by the conventional LOCOS process, since the oxide layers of various thicknesses exist simultaneously, in order to control the beak formed by the oxide layer of different thickness, LOCOS isolation needs to be separately fabricated. Oxide layer and drift oxide layer of various thicknesses, and repeated LOCOS fabrication process will lead to repeated growth and corrosion of PAD OX and PAD SIN, high production cost and long production cycle.
  • the isolation of devices using STI process can solve the problem of bird's beak, but it still needs multiple LOCOS processes to produce drift oxide layers of different thicknesses, and the isolation of devices made by STI process is higher than LOCOS.
  • the inventors of the present invention designed an integrated manufacturing method for fabricating a plurality of thickness oxide layers by the LOCOS process in order to reduce the production cost and shorten the fabrication cycle.
  • This method integrates the multi-step LOCOS process, using only one PAD OX and PAD
  • the growth and corrosion of SIN, adjusting the order and proportion of multi-step oxide growth, combined with wet etching to correct oxide thickness and bird's beak shape to meet the requirements of semiconductor devices, can reduce costs and shorten the production cycle.
  • the integrated manufacturing method of the LOCOS multilayer oxide layer comprises the following steps:
  • Step S1 provides a lower chip structure required to fabricate a multilayer oxide layer.
  • the underlying chip structure may be a wafer in which a part of the device structure has been fabricated by a process such as diffusion, photolithography, etching, thin film, or the like in the process of fabricating a semiconductor chip.
  • the lower chip structure refers to a part of the process in which the LDMOS process has been completed, and the wafer structure for continuing to fabricate the oxide layer of the isolation region and the oxide layer of the drift region.
  • Step S2 forming a liner on the underlying chip structure.
  • the pad is formed by first forming a pad oxide layer (PAD) OX), pad silicon nitride (PAD SIN) is then formed on the pad oxide layer.
  • PAD SIN pad silicon nitride
  • the furnace tube is used at 800 ⁇ 1100 °C, and the length is PAD OX 100 ⁇ 200. ⁇ , then use a furnace tube to grow PAD SIN 1000 ⁇ 2000 ⁇ at 600 ⁇ 900 °C.
  • PAD OX and PAD The manufacturing method and thickness of the SIN are conventionally selected by the conventional LOCOS process, and those skilled in the art can adjust and optimize according to actual conditions.
  • Step S3 defining a first thickness oxide layer region on the liner by a photolithography process, and opening in the first thickness oxide layer region by an etching process.
  • the oxide layer prepared in this embodiment is an isolation region and a drift region oxide layer (the final thickness of the oxide layer in the isolation region is greater than 4K ⁇ , and the final thickness of the two drift regions oxide layer is 5K ⁇ in the A region and the 2K ⁇ region B is taken as an example)
  • the first thickness oxide layer is an isolation region oxide layer and a drift region first oxide layer (A region);
  • the second thickness oxide layer described below is a drift region second oxide layer (B region).
  • step S3 may include the following fine steps: (1) defining device isolation regions by lithographic exposure, by etching PAD SIN and PAD OX opens the device isolation region and etches away excess photoresist; (2) defines the A region in the LDMOS drift region by photolithographic coating exposure, by etching PAD SIN and PAD OX opens the A region, adjusts the impurity concentration at the bottom of the A region by ion implantation, and removes excess photoresist by etching.
  • Step S4 performing the first oxidation growth on the underlying chip structure on which the opening of the first thickness oxide layer region is formed. Specifically, an oxide layer is formed in the isolation region and the region A in the drift region by the furnace tube at 800 to 1100 ° C, and the thickness of the oxide layer is 4 ⁇ 0.5 K ⁇ .
  • Step S5 after the first oxidation growth, defining a second thickness oxide layer region (ie, the B region in the drift region) on the liner by a photolithography process, and oxidizing at the second thickness by an etching process
  • the layer area is open.
  • the impurity concentration at the bottom of the B region is adjusted by ion implantation, and the excess photoresist is removed by etching.
  • Step S6 performing a second oxidation growth after the opening of the second thickness oxide layer region is formed, thereby completing the growth of the first and second thickness oxide layers.
  • an oxide layer of 3 ⁇ 0.5K ⁇ is formed in the B region in the drift region by the furnace tube at 800 to 1100° C., and a partial oxidation layer is regenerated on the oxide layer formed in the isolation region and the region A in the drift region. That is, the thickness of the first oxide layer of the isolation region oxide layer and the drift region is obtained by first oxidation growth and second oxidation growth accumulation, and both are larger than the thickness of the second oxide layer in the drift region, and the drift region is second. The thickness of the oxide layer is obtained only by the second oxidation growth.
  • Step S7 removing the liner and performing wet etching to adjust the bird's beak to complete the production of the multilayer oxide layer.
  • the removal of the oxide layer by the wet etchback of the bird's beak needs to be designed according to the length of the bird's beak (the main determinant is the thickness of the oxide layer) and the electrical performance of the oxide layer of different thicknesses. Satisfy: (1) ensuring that the edge damage of the oxide layer in the thin oxide layer region does not cause a significant decrease in the breakdown voltage; (2) ensuring that the bird's beak is reduced to an effective control range in the thick oxide layer region, and the low voltage MOS narrow tube turn-on voltage is not Obviously high.
  • the thickness of the oxide layer can be adjusted to increase the thickness of the thin oxide layer. The thickness is solved by increasing the amount of back.
  • the relationship between the NLDMOS breakdown voltage and the bird's mouth rinsing time in the thin oxide region is shown in Fig. 2.
  • the relationship between the NMOS narrow tube turn-on voltage and the bird's mouth rinsing time in the thick oxide region is shown in Fig. 3.
  • the A region is a thick oxide layer region
  • the B region is a thin oxide layer region.
  • FIG. 5 are schematic diagrams showing the shape of the groove length L direction of the NLDMOS after the bird's mouth rinsing time of 60s and 200s, respectively. It can be seen that the longer the rinsing time, the larger the damage amount of the edge of the oxide layer.
  • Fig. 6 and Fig. 7 are schematic diagrams showing the shape of the groove width W direction of the NMOS after the bird's mouth rinsing time is 60s and 200s, respectively. The longer the rinsing time, the smaller the bird's beak.
  • step S6 When the oxide layer of a plurality of thicknesses is formed by the integrated fabrication method of the LOCOS multilayer oxide layer provided by the present invention, after step S6 and before step S7, the following steps are included:
  • a third thickness oxide layer region is defined on the liner by photolithography and etching processes, a third oxidized layer region is opened in the third thickness oxide layer region, and a third oxidation growth is performed, and so on. This step is repeated until the nth oxidation growth is completed, thereby forming first to nth thickness oxide layers, where n is a natural number greater than 2.
  • the fourth thickness oxide layer region is further defined on the liner and opened for the fourth oxidation growth, thereby forming the first to The fourth thickness oxide layer.
  • the thicknesses of the first to nth thickness oxide layers formed are sequentially reduced. Therefore, the order of fabrication is in the order of thick to thin according to the thickness requirement of the oxide layer, which is the most cost-effective, for example, to make a thick oxide layer.
  • Zone A make Zone B, which requires a slightly thinner oxide layer, and so on.
  • Ti is the thickness of the oxide layer grown on the thickness of the oxide layer in the first time
  • yi is the thickness of the oxide layer regenerated on the (i-1)th oxide layer at the ith time.
  • the ratio of the thickness of the oxide layer grown on the silicon substrate region for the i-th time, and xi is the number of oxidative growths in the region.
  • Table 1 (required to supplement Table 1) is experimental data and thickness calculation model data for the laminated oxide layer grown by multiple oxidation.
  • Fig. 8 is a graph showing the fitting curve of the growth ratio of the laminated oxide layer obtained based on the data of Table 1.
  • the thickness calculation model is described:
  • isolation zone is the same as zone A:
  • Corrosion removal thickness including PAD SIN and PAD
  • the PAD SIN and PAD OX stripping depends on the thickness of the growth.
  • the wet etchback of the bird's beak is eliminated to simultaneously satisfy the breakdown voltage of the thin oxide layer NLDMOS region and the open voltage of the MOS narrow tube in the thick oxide region as a condition for eliminating the wet etchback time of the bird's beak. If the narrow-tube turn-on voltage is high in the thick oxide region, and the thin oxide region is significantly reduced due to the silicon exposure at the edge corner, the thickness of the oxide layer growth can be adjusted by the same as in the first embodiment. Thickening the thickness of the thin oxide layer to solve the problem of increasing the amount of re-etching, so as to select the best process conditions.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

L'invention concerne un procédé de fabrication intégré pour une couche d'oxyde multicouche LOCOS. Le procédé comprend les étapes suivantes : fabriquer un tampon situé sur une structure (S2) de puce de couche inférieure; définir une zone de couche d'oxyde de première épaisseur sur le tampon et former une ouverture dans la zone (S3) de couche d'oxyde de première épaisseur, et effectuer une première croissance d'oxyde (S4); définir ensuite une zone de couche d'oxyde de seconde épaisseur et former une ouverture (S5), et effectuer une seconde croissance d'oxyde (S6), de manière à former des couches d'oxyde avec une épaisseur différente; et enfin retirer le tampon, effectuer une gravure humide de rappel de manière à ajuster un bec, et terminer la fabrication de la couche d'oxyde multicouche (S7). Le procédé de fabrication intégré pour une couche d'oxyde multicouche LOCOS peut, par l'utilisation du procédé LOCOS et des procédés d'intégration de multiples couches d'oxyde, optimiser le rapport d'épaisseur et de gravure de rappel par voie humide de la couche d'oxyde multicouche, ce qui permet de résoudre le problème de bec lorsque les couches d'oxyde avec une épaisseur différente existent simultanément, et d'obtenir un coût inférieur et un cycle de fabrication plus court.
PCT/CN2012/086850 2012-03-21 2012-12-18 Procédé de fabrication intégré pour couche d'oxyde multicouche du type locos WO2013139154A1 (fr)

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CN201210075340.1A CN102593040B (zh) 2012-03-21 2012-03-21 Locos多层氧化层的集成制作方法
CN201210075340.1 2012-03-21

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CN102593040B (zh) * 2012-03-21 2014-12-10 无锡华润上华半导体有限公司 Locos多层氧化层的集成制作方法
CN103943548A (zh) * 2013-01-23 2014-07-23 无锡华润上华半导体有限公司 分立式场氧结构的半导体器件的制造方法
CN104576339B (zh) * 2013-10-16 2017-03-29 上海华虹宏力半导体制造有限公司 Rfldmos中栅场板的制作方法
CN106298628A (zh) * 2015-05-26 2017-01-04 北大方正集团有限公司 选择性氧化层的制备方法、选择性氧化层和集成电路

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CN102593040A (zh) * 2012-03-21 2012-07-18 无锡华润上华半导体有限公司 Locos多层氧化层的集成制作方法

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CN102237293A (zh) * 2010-04-23 2011-11-09 无锡华润上华半导体有限公司 半导体器件及其制造方法
CN102593040A (zh) * 2012-03-21 2012-07-18 无锡华润上华半导体有限公司 Locos多层氧化层的集成制作方法

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