WO2013139154A1 - Integrated fabrication method for locos multilayer oxide layer - Google Patents

Abstract

Disclosed is an integrated fabrication method for a LOCOS multilayer oxide layer. The method comprises: fabricating a pad on a lower layer chip structure (S2); defining a first-thickness oxide layer area on the pad and forming an opening in the first-thickness oxide layer area (S3), and performing first oxide growth (S4); then defining a second-thickness oxide layer area and forming an opening (S5), and performing second oxide growth (S6), so as to form oxide layers with different thickness; and finally, removing the pad, performing wet etching-back so as to adjust a beak, and completing fabrication of the multilayer oxide layer (S7). The integrated fabrication method for a LOCOS multilayer oxide layer can, by using the LOCOS process and integrating processes of multiple oxide layers, optimize the thickness ratio and wet etching-back of the multilayer oxide layer, thereby solving the beak problem when the oxide layers with different thickness exist simultaneously, and achieving a lower cost and a shorter fabrication cycle.

Description

Integrated manufacturing method of LOCOS multilayer oxide layer

[Technical Field]

The present invention relates to a method of fabricating an integrated circuit (IC), and more particularly to using LOCOS (LOCal Oxidation of Silicon) is an integrated fabrication method for fabricating oxide layers of various thicknesses and belongs to the field of semiconductor device manufacturing.

【Background technique】

With the continuous development of integrated circuits, LDMOS (Lateral Double-diffused The MOS) process integrates devices with various withstand voltage specifications on the same chip. Among them, LOCOS (LOCal Oxidation of) is often used on the same wafer. Silicon) Processes and simultaneously fabricates a wide range of devices withstand voltage specifications.

The traditional LOCOS process is fabricated by first growing a pad oxide layer (PAD OX) and pad silicon nitride (PAD) on a silicon substrate. SIN), then use the photolithography and etching process to define the area where the oxide layer needs to be grown, and then use PAD OX and PAD SIN as the barrier growth oxide layer, and then remove the PAD by wet etching. SIN and PAD OX, finally leaving the required oxide layer. When the oxide layer is grown, the silicon under the edge of the barrier layer reacts with the invading oxygen atoms to form silicon dioxide, which arches the barrier layer to form a bird's beak. The beak will consume an active active area, resulting in an increase in device size.

At present, in order to save costs, a conventional LOCOS process is often used to form an isolation oxide layer and a drift region oxide layer. This has the phenomenon that oxide layers of various thicknesses exist at the same time, and the lengths of the oxide layers with different thicknesses are different. In order to control the bird's beak formed by oxide layers of different thicknesses, it is necessary to separately fabricate a LOCOS isolation oxide layer and various thickness drift zone oxide layers to control the bird's beak respectively. However, repeated LOCOS fabrication processes will result in repeated growth and corrosion of the PAD. OX and PAD SIN are costly to produce and have a long production cycle.

The usual solution is to use STI (Shallow Trench Isolation) The shallow trench isolation process creates isolation of the device and solves the problem of the beak. STI achieves device isolation by trenching a deep trench on a silicon substrate and embedding an isolation oxide layer. The STI process can solve the problem of the beak, but it also has disadvantages:

1, STI production device isolation, the cost is higher than LOCOS;

2, STI can only solve the problem of LOCOS isolated beak. It still needs multiple LOCOS processes to make drift oxide layers of different thicknesses.

In view of this, the present invention will provide a new process for fabricating various thickness oxide layers using the LOCOS process to effectively integrate the fabrication of oxide layers of various thicknesses, reduce costs, and shorten the fabrication cycle.

[Summary of the Invention]

The technical problem to be solved by the present invention is to provide an integrated manufacturing method of a multilayer oxide layer using a LOCOS process.

In order to solve the above technical problem, the present invention adopts the following technical solutions:

An integrated method for fabricating a LOCOS multilayer oxide layer, comprising the steps of:

Step 1: providing a lower chip structure required to fabricate a multilayer oxide layer;

Step two, forming a liner on the underlying chip structure;

Step 3, defining a first thickness oxide layer region on the pad by using a photolithography process, and opening in the first thickness oxide layer region by an etching process;

Step 4, performing first oxidation growth on the underlying chip structure having the opening of the first thickness oxide layer region;

Step 5, after the first oxidation growth, defining a second thickness oxide layer region on the liner by a photolithography process, and opening in the second thickness oxide layer region by an etching process;

Step 6: performing a second oxidation growth after the opening of the second thickness oxide layer region is formed, thereby forming the first and second thickness oxide layers;

Step 7. Remove the liner, perform wet etching to adjust the bird's beak, and complete the production of the multilayer oxide layer.

As a preferred embodiment of the present invention, in the second step, the forming the spacer comprises first forming a pad oxide layer, and then forming a pad silicon nitride on the pad oxide layer.

As a preferred embodiment of the present invention, the first thickness oxide layer includes an isolation region oxide layer and a drift region first oxide layer; and the second thickness oxide layer is a drift region second oxide layer.

Further preferably, the thickness of the isolation region oxide layer and the drift region first oxide layer is obtained by first oxidation growth and second oxidation growth accumulation, and both are greater than the thickness of the second oxide layer in the drift region, and the drift region is The thickness of the dioxide layer is obtained by the second oxidation growth.

Further preferably, the impurity concentration of the first and second oxide layers in the drift region is adjusted by an ion implantation process before the first and second oxidation growths are performed.

As a preferred embodiment of the present invention, the thickness of the oxide layer formed by the first oxidation growth is 3.5 to 4.5K. Å; The thickness of the oxide layer formed by the second oxidation growth is 2.5~3.5K Å.

As a preferred embodiment of the present invention, the first and second oxidation growths are carried out using a furnace tube at a temperature of 800 to 1100 °C.

As a preferred embodiment of the present invention, the wet etching solution has a concentration of 49% HF: H ₂ O = 1:15 and a corrosion time of 190 to 210 s.

When the n-thickness oxide layer is formed according to the above method, after step 6 and before step 7, the following steps are further included:

After the second oxidation growth, a third thickness oxide layer region is defined on the liner by photolithography and etching processes, and a third third oxide growth region is opened in the third thickness oxide layer region, and the third oxidation growth is repeated. The steps are completed until the nth oxidation growth is completed, thereby forming first to nth thickness oxide layers, where n is a natural number greater than 2.

As a preferred embodiment of the present invention, the final growth thickness of the first to n-1th thickness oxide layers is obtained by cumulative multiple oxidation growth, and their final growth thickness T (final) Satisfy T(final) = T1 × y1 + T2 × y2 + ... + Ti × yi, yi = 0.9774 - 0.4482Ln (xi); Ti is the thickness of the oxide layer grown on the thick oxide layer region for the i-th time, and yi is the i-th thickness of the oxide layer regenerated on the (i-1)th oxide layer for the i-th time in the silicon substrate region. The ratio of the thickness of the oxide layer grown on the xi The number of oxidative growths in this area.

The beneficial effects of the invention are:

The invention adopts the LOCOS process to integrate the process of the LOCOS isolation oxide layer and the drift region oxide layer, optimizes the thickness ratio of the multilayer oxide layer and the wet etching, and solves the beak problem when the oxide layers of various thicknesses exist simultaneously. , achieving lower cost and shorter production cycle in the LDMOS process. When n oxide layers of different thicknesses are produced, (n-1) times of PAD can be saved Growth and removal processes of OX and PAD SIN.

[Description of the Drawings]

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic flow chart of an integrated manufacturing method of a LOCOS multilayer oxide layer according to Embodiment 1 of the present invention;

2 is a graph showing the relationship between the breakdown voltage of the NLDMOS in the thin oxide region and the rinsing time of the bird's beak in the first embodiment of the present invention;

3 is a graph showing the relationship between the opening voltage of an NMOS narrow tube and the rinsing time of a bird's beak in a thick oxide layer region according to an embodiment of the present invention;

4 is a schematic view showing the L-directional shape of the NLDMOS groove length L direction of the bird's mouth rinsing time of 60 s according to the first embodiment of the present invention;

FIG. 5 is a schematic diagram showing the L-directional shape of the NLDMOS groove length L direction of the bird's mouth rinsing time of 200 s according to the first embodiment of the present invention; FIG.

6 is a schematic diagram showing the shape of a groove width W direction of an NMOS with a bird's mouth rinsing time of 60 s according to the first embodiment of the present invention;

7 is a schematic diagram showing the shape of a groove width W direction of an NMOS with a bird's mouth rinsing time of 200 s according to the first embodiment of the present invention;

Fig. 8 is a graph showing the fitting curve of the growth ratio of the laminated oxide layer in the second embodiment of the present invention.

 【detailed description】

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

As used herein, the terms "substantially", "about" or "left and right" are used to provide industry-accepted tolerances for their respective modified terms.

As described in the background section, when the isolation oxide layer and the drift region oxide layer are formed by the conventional LOCOS process, since the oxide layers of various thicknesses exist simultaneously, in order to control the beak formed by the oxide layer of different thickness, LOCOS isolation needs to be separately fabricated. Oxide layer and drift oxide layer of various thicknesses, and repeated LOCOS fabrication process will lead to repeated growth and corrosion of PAD OX and PAD SIN, high production cost and long production cycle. In addition, the isolation of devices using STI process can solve the problem of bird's beak, but it still needs multiple LOCOS processes to produce drift oxide layers of different thicknesses, and the isolation of devices made by STI process is higher than LOCOS.

In view of this, the inventors of the present invention designed an integrated manufacturing method for fabricating a plurality of thickness oxide layers by the LOCOS process in order to reduce the production cost and shorten the fabrication cycle. This method integrates the multi-step LOCOS process, using only one PAD OX and PAD The growth and corrosion of SIN, adjusting the order and proportion of multi-step oxide growth, combined with wet etching to correct oxide thickness and bird's beak shape to meet the requirements of semiconductor devices, can reduce costs and shorten the production cycle.

In the following, taking the fabrication of the isolation oxide layer and the drift region oxide layer in the LDMOS process as an example, the integrated method for manufacturing the multilayer oxide layer provided by the present invention will be described in detail with reference to the accompanying drawings.

Embodiment 1

As shown in FIG. 1 , the integrated manufacturing method of the LOCOS multilayer oxide layer provided by the present invention comprises the following steps:

Step S1 provides a lower chip structure required to fabricate a multilayer oxide layer. The underlying chip structure may be a wafer in which a part of the device structure has been fabricated by a process such as diffusion, photolithography, etching, thin film, or the like in the process of fabricating a semiconductor chip. In this embodiment, the lower chip structure refers to a part of the process in which the LDMOS process has been completed, and the wafer structure for continuing to fabricate the oxide layer of the isolation region and the oxide layer of the drift region.

Step S2: forming a liner on the underlying chip structure. Wherein, the pad is formed by first forming a pad oxide layer (PAD) OX), pad silicon nitride (PAD SIN) is then formed on the pad oxide layer. In this embodiment, the furnace tube is used at 800~1100 °C, and the length is PAD OX 100~200. Å, then use a furnace tube to grow PAD SIN 1000~2000 Å at 600~900 °C. Among them, PAD OX and PAD The manufacturing method and thickness of the SIN are conventionally selected by the conventional LOCOS process, and those skilled in the art can adjust and optimize according to actual conditions.

Step S3, defining a first thickness oxide layer region on the liner by a photolithography process, and opening in the first thickness oxide layer region by an etching process.

The oxide layer prepared in this embodiment is an isolation region and a drift region oxide layer (the final thickness of the oxide layer in the isolation region is greater than 4KÅ, and the final thickness of the two drift regions oxide layer is 5KÅ in the A region and the 2KÅ region B is taken as an example) Wherein the first thickness oxide layer is an isolation region oxide layer and a drift region first oxide layer (A region); the second thickness oxide layer described below is a drift region second oxide layer (B region).

Specifically, step S3 may include the following fine steps: (1) defining device isolation regions by lithographic exposure, by etching PAD SIN and PAD OX opens the device isolation region and etches away excess photoresist; (2) defines the A region in the LDMOS drift region by photolithographic coating exposure, by etching PAD SIN and PAD OX opens the A region, adjusts the impurity concentration at the bottom of the A region by ion implantation, and removes excess photoresist by etching.

Step S4, performing the first oxidation growth on the underlying chip structure on which the opening of the first thickness oxide layer region is formed. Specifically, an oxide layer is formed in the isolation region and the region A in the drift region by the furnace tube at 800 to 1100 ° C, and the thickness of the oxide layer is 4±0.5 KÅ.

Step S5, after the first oxidation growth, defining a second thickness oxide layer region (ie, the B region in the drift region) on the liner by a photolithography process, and oxidizing at the second thickness by an etching process The layer area is open. Then, according to the needs of the LDMOS process, the impurity concentration at the bottom of the B region is adjusted by ion implantation, and the excess photoresist is removed by etching.

Step S6, performing a second oxidation growth after the opening of the second thickness oxide layer region is formed, thereby completing the growth of the first and second thickness oxide layers. Specifically, an oxide layer of 3±0.5KÅ is formed in the B region in the drift region by the furnace tube at 800 to 1100° C., and a partial oxidation layer is regenerated on the oxide layer formed in the isolation region and the region A in the drift region. That is, the thickness of the first oxide layer of the isolation region oxide layer and the drift region is obtained by first oxidation growth and second oxidation growth accumulation, and both are larger than the thickness of the second oxide layer in the drift region, and the drift region is second. The thickness of the oxide layer is obtained only by the second oxidation growth.

Step S7, removing the liner and performing wet etching to adjust the bird's beak to complete the production of the multilayer oxide layer. In this embodiment, the PAD SIN and PAD OX are removed by an etching process; the wet etching recipe is: 49% HF: H ₂ O=1:15, and other ratios (eg 1:50/) 1:100, etc., or other etching solution (such as BOE) that can remove SiO ₂ ; corrosion time is 190~210s.

According to the research of the inventors, it is found that the removal of the oxide layer by the wet etchback of the bird's beak needs to be designed according to the length of the bird's beak (the main determinant is the thickness of the oxide layer) and the electrical performance of the oxide layer of different thicknesses. Satisfy: (1) ensuring that the edge damage of the oxide layer in the thin oxide layer region does not cause a significant decrease in the breakdown voltage; (2) ensuring that the bird's beak is reduced to an effective control range in the thick oxide layer region, and the low voltage MOS narrow tube turn-on voltage is not Obviously high. If the narrow-tube turn-on voltage is high in the thick oxide region, and the breakdown voltage is significantly reduced due to the silicon exposure at the edge of the thin oxide layer, the thickness of the oxide layer can be adjusted to increase the thickness of the thin oxide layer. The thickness is solved by increasing the amount of back.

The relationship between the NLDMOS breakdown voltage and the bird's mouth rinsing time in the thin oxide region is shown in Fig. 2. The relationship between the NMOS narrow tube turn-on voltage and the bird's mouth rinsing time in the thick oxide region is shown in Fig. 3. In this embodiment, the A region is a thick oxide layer region, and the B region is a thin oxide layer region. Combining the performance of the two, in this embodiment, the bird rinsing time of 200s (HF49%: H ₂ O=1:15) is selected as the optimal condition, that is, the etching time of the wet etchback is preferably 200 s. Fig. 4 and Fig. 5 are schematic diagrams showing the shape of the groove length L direction of the NLDMOS after the bird's mouth rinsing time of 60s and 200s, respectively. It can be seen that the longer the rinsing time, the larger the damage amount of the edge of the oxide layer. Fig. 6 and Fig. 7 are schematic diagrams showing the shape of the groove width W direction of the NMOS after the bird's mouth rinsing time is 60s and 200s, respectively. The longer the rinsing time, the smaller the bird's beak.

Embodiment 2

When the oxide layer of a plurality of thicknesses is formed by the integrated fabrication method of the LOCOS multilayer oxide layer provided by the present invention, after step S6 and before step S7, the following steps are included:

After the second oxidative growth, a third thickness oxide layer region is defined on the liner by photolithography and etching processes, a third oxidized layer region is opened in the third thickness oxide layer region, and a third oxidation growth is performed, and so on. This step is repeated until the nth oxidation growth is completed, thereby forming first to nth thickness oxide layers, where n is a natural number greater than 2. For example, to make an oxide layer of four thicknesses, after performing the third oxidation growth, the fourth thickness oxide layer region is further defined on the liner and opened for the fourth oxidation growth, thereby forming the first to The fourth thickness oxide layer.

The thicknesses of the first to nth thickness oxide layers formed are sequentially reduced. Therefore, the order of fabrication is in the order of thick to thin according to the thickness requirement of the oxide layer, which is the most cost-effective, for example, to make a thick oxide layer. In Zone A, make Zone B, which requires a slightly thinner oxide layer, and so on. The resulting plurality of thickness oxide layers satisfy the final thickness = final growth thickness - corrosion removal thickness.

Wherein, the final growth thickness of the first to n-1th thickness oxide layers is obtained by cumulative oxidation growth, and their final growth thickness T (final) Should satisfy T(final) = T1×y1+T2×y2+...+Ti×yi,yi =0.9774-0.4482Ln(xi); Ti is the thickness of the oxide layer grown on the thickness of the oxide layer in the first time, and yi is the thickness of the oxide layer regenerated on the (i-1)th oxide layer at the ith time. The ratio of the thickness of the oxide layer grown on the silicon substrate region for the i-th time, and xi is the number of oxidative growths in the region. Table 1 (required to supplement Table 1) is experimental data and thickness calculation model data for the laminated oxide layer grown by multiple oxidation. Fig. 8 is a graph showing the fitting curve of the growth ratio of the laminated oxide layer obtained based on the data of Table 1.

Taking the calculation of the final growth thickness of the isolation zone, the A zone and the B zone in the first embodiment as an example, the thickness calculation model is described:

(1) The isolation zone is the same as zone A:

T(final)=T1*y1+T2*y2=4000*(0.9774-0.4482*Ln(1))+3000*(0.9774-0.4482*Ln(2))=5910Å.

(2), Area B: T(final)=T1*y1 =3000*(0.9774 -0.4482*Ln(1))=2932Å.

Corrosion removal thickness including PAD SIN and PAD The amount of oxide layer removed during OX stripping, and the amount of oxide layer removed by wet etchback of the bird's beak. The PAD SIN and PAD OX stripping depends on the thickness of the growth.

For the LDMOS process, the wet etchback of the bird's beak is eliminated to simultaneously satisfy the breakdown voltage of the thin oxide layer NLDMOS region and the open voltage of the MOS narrow tube in the thick oxide region as a condition for eliminating the wet etchback time of the bird's beak. If the narrow-tube turn-on voltage is high in the thick oxide region, and the thin oxide region is significantly reduced due to the silicon exposure at the edge corner, the thickness of the oxide layer growth can be adjusted by the same as in the first embodiment. Thickening the thickness of the thin oxide layer to solve the problem of increasing the amount of re-etching, so as to select the best process conditions.

It can be seen that by using the integrated fabrication method of the present invention, by optimizing the thickness ratio of the multilayer oxide layer and the wet etching, the beak problem in the presence of multiple thickness oxide layers can be solved. Saving (n-1) times of PAD OX and PAD SIN with different thicknesses of oxide layer The growth and removal process enables lower cost and shorter fabrication cycles in the LDMOS process.

It is to be understood that the term "comprises", "comprising" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a It also includes other elements that are not explicitly listed, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising", without limiting the invention, does not exclude the presence of additional elements in the process, method, article, or device.

The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments are obvious to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but the scope of the invention is to be accorded

Claims (10)

1. An integrated method for fabricating a LOCOS multilayer oxide layer, comprising the steps of:

   Step 1: providing a lower chip structure required to fabricate a multilayer oxide layer;

   Step two, forming a liner on the underlying chip structure;

   Step 3, defining a first thickness oxide layer region on the pad by using a photolithography process, and opening in the first thickness oxide layer region by an etching process;

   Step 4, performing first oxidation growth on the underlying chip structure having the opening of the first thickness oxide layer region;

   Step 5, after the first oxidation growth, defining a second thickness oxide layer region on the liner by a photolithography process, and opening in the second thickness oxide layer region by an etching process;

   Step 6: performing a second oxidation growth after the opening of the second thickness oxide layer region is formed, thereby forming the first and second thickness oxide layers;

   Step 7. Remove the liner, perform wet etching to adjust the bird's beak, and complete the production of the multilayer oxide layer.
2. The method for fabricating a LOCOS multilayer oxide layer according to claim 1, wherein in the second step, the pattern is formed by first forming a pad oxide layer and then forming a liner on the pad oxide layer. Silicon nitride.
3. The method of integrally fabricating a LOCOS multilayer oxide layer according to claim 1, wherein the first thickness oxide layer comprises an isolation region oxide layer and a drift region first oxide layer; and the second thickness oxide layer It is the second oxide layer in the drift region.
4. The method for fabricating a LOCOS multilayer oxide layer according to claim 3, wherein the thickness of the isolation region oxide layer and the drift region first oxide layer is the first oxidation growth and the second oxidation growth accumulation. And both are greater than the thickness of the second oxide layer in the drift region, and the thickness of the second oxide layer in the drift region is obtained by the second oxidation growth.
5. The method for integrally manufacturing a LOCOS multilayer oxide layer according to claim 3, wherein the first and second oxide layers are adjusted by an ion implantation process before the first and second oxidation growths are performed. Impurity concentration.
6. The method for integrally manufacturing a LOCOS multilayer oxide layer according to claim 3, wherein the oxide layer formed by the first oxidation growth has a thickness of 3.5 KÅ. ~4.5KÅ; the thickness of the oxide layer formed by the second oxidation growth is 2.5 KÅ ~ 3.5K Å.
7. The method for integrally manufacturing a LOCOS multilayer oxide layer according to claim 1, wherein the first and second oxidation growths are performed by using a furnace tube at a temperature of 800 to 1100 °C.
8. The method for integrally manufacturing a LOCOS multilayer oxide layer according to any one of claims 3 or 6, wherein the wet etching solution has a concentration of 49% HF: H ₂ O=1: 15, corrosion time is 190~210s.
9. The method for fabricating a LOCOS multilayer oxide layer according to claim 1, wherein when the oxide layers of the n thicknesses are formed, after the step 6 and before the step 7, the following steps are further included:

   After the second oxidation growth, a third thickness oxide layer region is defined on the liner by photolithography and etching processes, and a third third oxide growth region is opened in the third thickness oxide layer region, and the third oxidation growth is repeated. The steps are completed until the nth oxidation growth is completed, thereby forming first to nth thickness oxide layers, where n is a natural number greater than 2.
10. The method for integrally manufacturing a LOCOS multilayer oxide layer according to claim 9, wherein the final growth thickness of the first to n-1th thickness oxide layers is obtained by cumulative oxidation growth and their final growth. Thickness T (final) Satisfy T(final) = T1 × y1 + T2 × y2 + ... + Ti × yi, yi = 0.9774 - 0.4482Ln (xi); Ti is the thickness of the oxide layer grown on the thick oxide layer region for the i-th time, and yi is the i-th thickness of the oxide layer regenerated on the (i-1)th oxide layer for the i-th time in the silicon substrate region. The ratio of the thickness of the oxide layer grown on the xi The number of oxidative growths in this area.

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