JPS62296438A - Device for manufacturing semiconductor integrated circuit - Google Patents
Device for manufacturing semiconductor integrated circuitInfo
- Publication number
- JPS62296438A JPS62296438A JP13838086A JP13838086A JPS62296438A JP S62296438 A JPS62296438 A JP S62296438A JP 13838086 A JP13838086 A JP 13838086A JP 13838086 A JP13838086 A JP 13838086A JP S62296438 A JPS62296438 A JP S62296438A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- oxidation
- beak
- bird
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 30
- 241000293849 Cordylanthus Species 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000007796 conventional method Methods 0.000 claims 2
- 239000003990 capacitor Substances 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 108091006146 Channels Proteins 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000009271 trench method Methods 0.000 description 2
- 102000003691 T-Type Calcium Channels Human genes 0.000 description 1
- 108090000030 T-Type Calcium Channels Proteins 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体素子の製造方法に係シ、特に電荷蓄積に
より情報が記憶される記憶容量部(以後、キャノぐシタ
部と称する)の製造方法に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and in particular to a storage capacitor (hereinafter referred to as a canopy) in which information is stored by charge accumulation. The present invention relates to a method of manufacturing a bottom portion (referred to as a bottom portion).
半導体基板に多数の素子を形成して集積回路を製造する
場合、各素子間を電気的に絶縁分離する必要がある。従
来、各素子を絶縁分離する為の手法として選択酸化法が
広く用いられてきた。この選択酸化法は、素子領域とフ
ィールド領域とを自己整合的に形成できる等の利点を有
することから、現在のところ、−子間分離の最良の方法
と考えられており、高密度集積回路の製造には不可欠の
ものとなっている。When manufacturing an integrated circuit by forming a large number of elements on a semiconductor substrate, it is necessary to electrically insulate and separate each element. Conventionally, selective oxidation has been widely used as a method for insulating and isolating each element. This selective oxidation method has the advantage of being able to form element regions and field regions in a self-aligned manner, and is currently considered the best method for device-to-device isolation. It is essential for manufacturing.
以下、第2図に基き従来例を説明する。Hereinafter, a conventional example will be explained based on FIG.
まず第2図(a)に示すように、シリコン基板から成る
半導体基板21上にノミラド酸化膜(Sigh)22を
500A程度、シリコン窒化膜(SiiN4)から成る
耐酸化性被膜をzoooi程度順次形成する。First, as shown in FIG. 2(a), on a semiconductor substrate 21 made of a silicon substrate, a Nomurad oxide film (Sigh) 22 of about 500A and an oxidation-resistant film made of a silicon nitride film (SiiN4) are sequentially formed to about a zoooi degree. .
仁の後、レジストを塗布してノぐターニングすると”
とKよシレジストマスク(図示せず)を形成し、通常の
選択エツチング法を用いて上記シリコン窒化膜に開口部
23を設けて耐酸化性マスク24と成し、更にこの耐酸
化性マスク24を介してチャネルストップインプラを行
うことによ〕シリコン基板21にチャネルストップ領域
25を形成する。After coating, apply resist and turn.
A resist mask (not shown) is formed, and an opening 23 is formed in the silicon nitride film using a conventional selective etching method to form an oxidation-resistant mask 24. A channel stop region 25 is formed in the silicon substrate 21 by performing channel stop implantation via the silicon substrate 21.
そして上記レジストマスクを除去し、フッ酸系のエッチ
ャントを用いて開口部24のパッド酸化膜22を除去す
る。Then, the resist mask is removed, and the pad oxide film 22 in the opening 24 is removed using a hydrofluoric acid-based etchant.
次に第2図(b)に示す如く、高温酸化算囲気中で酸化
処理を行うととKより、フィールド酸化膜(St(h)
26を6000A程度成長させる。なおこの際、横方向
酸化によりバーズビーク26 a dZ発生する。Next, as shown in FIG. 2(b), when oxidation treatment is performed in a high-temperature oxidation atmosphere, the field oxide film (St(h)
26 to about 6000A. At this time, bird's beaks 26 a dZ are generated due to lateral oxidation.
この後、通常のMOSプロセスに従い、キャパシタ部り
1b用のシリコン酸化膜(SiC2から成る絶縁膜27
を200A程度、ポリシリコン(Po1y −St)か
ら成る電極層28を3sooi程度順次形成すると、第
1図(C)に示す如き断面構造が得られる。ここで、上
記開口部23の@に両側のノ々−ズピーク量が加算され
たパターン幅Wを有する領域がフィールド領域21aで
あり、21bが素子領域、ここではキャパシタ部である
。なお同図からも明らかなように、キャパシタ部21b
はフィールド領域21a近傍において略水平となってい
る(電子通信学会技術研究報告半導体・トランジスタ5
SD77−23P、l〜9参照)。Thereafter, according to a normal MOS process, a silicon oxide film (insulating film 27 made of SiC2) for the capacitor portion 1b is formed.
By sequentially forming electrode layers 28 made of polysilicon (Poly-St) of about 200 Å and about 3 sooi, a cross-sectional structure as shown in FIG. 1(C) is obtained. Here, a region having a pattern width W obtained by adding the nose peak amounts on both sides to the @ of the opening 23 is a field region 21a, and 21b is an element region, here a capacitor portion. Furthermore, as is clear from the figure, the capacitor section 21b
is approximately horizontal near the field region 21a (IEICE Technical Research Report Semiconductor/Transistor 5)
(See SD77-23P, 1-9).
しかしながら上述した従来例においては、選択酸化法に
よりフイールド酸化膜を形成する際、横方向酸化が進み
バーズビークが発生する。この・々−ズビークの発生は
、限られたチップ面積の中でフィールド領域を余分に拡
げ、素子領域を狭める為、高密度化を図る上で重大な障
害となっている。However, in the conventional example described above, when a field oxide film is formed by selective oxidation, lateral oxidation progresses and bird's beaks occur. The occurrence of this Z-beak is a serious hindrance in achieving higher density because it excessively expands the field area and narrows the element area within the limited chip area.
例えば、素子領域をキャパシタ部として使用する場合、
キャパシタ部の実効面積が減少する為、十分安定した素
子特性を得ることが困難であるという問題がある。For example, when using the element region as a capacitor section,
Since the effective area of the capacitor section is reduced, there is a problem in that it is difficult to obtain sufficiently stable device characteristics.
ところで上記バーズビークを解消する為に、シリコン基
板にトレンチを設け、これに絶R膜を埋め込むととくよ
シフイールド領域と素子領域とを絶縁分離する、所謂ト
レンチ法が発表されている。By the way, in order to eliminate the above-mentioned bird's beak, a so-called trench method has been announced in which a trench is provided in a silicon substrate and an insulating film is buried in the trench to insulate and separate the shield region and the element region.
しかし、このトレンチ法は従来の選択酸化法とは技法が
異なり、エツチング方法等に困難な技術が要求されてい
る。However, this trench method differs in technique from the conventional selective oxidation method, and requires difficult techniques such as etching.
従って、本発明は以上述べた問題を解消し、素子領域の
キャノぞシタ部面積を拡〈とれ、素子の高密度化及び高
安定化を実現できる半導体素子の展進方法を提供するこ
とを目的とする。Therefore, it is an object of the present invention to provide a method for developing a semiconductor device that can solve the above-mentioned problems, increase the area of the canopy of the device region, and realize higher density and higher stability of the device. shall be.
本発明に係る半導体素子の段進方法は、選択酸化法によ
りフィールド酸化膜を形成した後、耐酸化性マスクをエ
ツチング除去し、更にバーズビークを略除去する程度に
パッド酸化膜、フィールド酸化膜及びバーズビークを同
時にエツチングし、との後絶縁膜、電極層を順次形成す
るようにしたものである。In the semiconductor device staging method according to the present invention, after forming a field oxide film by selective oxidation, the oxidation-resistant mask is removed by etching, and the pad oxide film, field oxide film, and bird's beak are removed to the extent that the bird's beak is substantially removed. is etched at the same time, and then an insulating film and an electrode layer are sequentially formed.
以上のように本発明によれば、選択酸化の際の横方向酸
化により発生するバーズビークを、後工程のエツチング
処理によフ除去するようKしている。As described above, according to the present invention, bird's beaks generated due to lateral oxidation during selective oxidation are removed by etching in the post-process.
この為、最終的にけノぐ−ズピーク発生による素子領域
の面積低下が回避される。また素子領域は、フィールド
領域近傍においてバーズビーク発生に起因し表面が斜面
形状となる為、表面積が増し、これをキャノぐシタ部と
して用いる場合にはキャノぞシタ容量を増加することが
できる。Therefore, a reduction in the area of the element region due to the generation of a crystal peak can be avoided. Further, since the surface of the element region has a sloped shape due to the occurrence of bird's beak near the field region, the surface area increases, and when this is used as a canopy part, the canopy capacitance can be increased.
〔実施例〕
以下、第1図に基き本発明の一実施例を詳細に説明する
。[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail based on FIG.
まず第1図(a)に示す如く、P型シリコン基板(10
0)(以後、シリコン基板と略称する)から成る半導体
基板11上に、1000℃程度の酸化雰囲気中での高温
酸化によりシリコン酸化膜(SiOz)から成るパッド
酸化膜12を500A程度成長させ、続いてCVD法に
よりシリコン窒化膜(S 1sN4)から成る耐酸化性
被膜を1500A程度成長させる。次にレジストパター
ン(図示せず)を形成した後、これを介してエツチング
を施すことにより上記シリコン窒化膜に開口部13を設
は耐酸化性マスク14と成す。First, as shown in FIG. 1(a), a P-type silicon substrate (10
0) (hereinafter abbreviated as silicon substrate), a pad oxide film 12 made of a silicon oxide film (SiOz) of about 500A is grown by high-temperature oxidation in an oxidizing atmosphere of about 1000°C, and then Then, an oxidation-resistant film made of a silicon nitride film (S1sN4) is grown to a thickness of about 1500 Å using the CVD method. Next, a resist pattern (not shown) is formed and etched through the resist pattern to form an opening 13 in the silicon nitride film to form an oxidation-resistant mask 14.
次いで、この耐酸化性マスク24を介して30 KeV
。Then, 30 KeV was applied through this oxidation-resistant mask 24.
.
2X1013/−程度の打ち込み条件でB”Oイオン打
ち込みを行い、シリコン基板11にt型のチャネルスト
ップ領域15を形成する。そしてレジストマスクと、開
口部13のノぞラド酸化膜12を除去する。B"O ions are implanted under implantation conditions of about 2.times.10.sup.13/- to form a T-type channel stop region 15 in the silicon substrate 11. Then, the resist mask and the rad oxide film 12 in the opening 13 are removed.
ここで上記開口部130幅はWであり、前述の第2図(
C)に示すフィールド領域21aのパターン幅と同一に
しである。即ち、第2図(C)のフィールド領域21a
のパターン幅Wは、第2図(a)に示す開口部23の幅
よシ第2図(b)に示す両側のバーズビーク26aの拡
がり寸法だけ拡くなっているので、この第1図(a)に
示す開口部13の幅は、バーズビーク量の分だけ拡〈と
っであることになる。Here, the width of the opening 130 is W, and the width of the opening 130 is W, as shown in FIG.
The pattern width is the same as that of the field area 21a shown in C). That is, the field area 21a in FIG. 2(C)
The pattern width W in this figure 1(a) is wider than the width of the opening 23 shown in FIG. 2(a) by the width of the bird's beak 26a on both sides shown in FIG. The width of the opening 13 shown in ) is increased by the amount of bird's beak.
このように本実施例では、後述する如く最終的に得られ
るフィールド領域11aのパターン幅を、vlc2図(
c)に示す従来のフィールド領域21aと同一寸法に設
定し、本発明の効果が明確になるようにしている。As described above, in this embodiment, the pattern width of the field area 11a that is finally obtained as described later is set as shown in the vlc2 diagram (
It is set to have the same dimensions as the conventional field area 21a shown in c), so that the effect of the present invention becomes clear.
次に同図の)に示すように、耐酸化性マスク14を介し
て高温酸化雰囲気中で選択酸化を行うことにより、フィ
ールド酸化膜16を10000A程度成長させる。なお
この選択酸化の際、横方向酸化によりノ々−ズピーク1
6aが発生する。Next, as shown in ) in the figure, selective oxidation is performed in a high-temperature oxidizing atmosphere through an oxidation-resistant mask 14 to grow a field oxide film 16 of about 10,000 Å. Note that during this selective oxidation, nose peak 1 is generated due to lateral oxidation.
6a occurs.
続いて同図(C)に示す如く、熱リン酸溶液を用いてシ
リコン窒化膜から成る耐酸化性マスク14を除去し、更
にフッ酸系のウェットエツチングまたは通常のプラズマ
ドライエツチングを用いパッド酸化膜12、フィールド
酸化膜16及びバーズビーク16aにエツチングを施し
てシリコン基板11表面を露出させ、フィールド酸化膜
16のパターン幅が第1図(a)に示す開口部13の拡
さ、匙ち第1図(a)、Φ)の両破線A−A及びB−B
で狭まれる幅となるようにする。Next, as shown in FIG. 2C, the oxidation-resistant mask 14 made of silicon nitride film is removed using a hot phosphoric acid solution, and the pad oxide film is removed using hydrofluoric acid wet etching or ordinary plasma dry etching. 12. The field oxide film 16 and the bird's beak 16a are etched to expose the surface of the silicon substrate 11, and the pattern width of the field oxide film 16 is adjusted to the width of the opening 13 shown in FIG. (a), Φ) both broken lines A-A and B-B
The width should be narrowed by .
この後、第1図(d)に示すように通常のMOSプロセ
スに従って、キャパシタ部り1b用のシリコン酸化膜(
Stow)から成る絶縁膜17を200^程度、ポリシ
リコン(Poly−8t)から成る電極層18を350
0A程度順次成長させる。同図において、11aはフィ
ールド領域を、またllbはキャノぞシタ部としての素
子領域を夫々示している。Thereafter, as shown in FIG. 1(d), a silicon oxide film for the capacitor portion 1b (
The insulating film 17 made of Polysilicon (Stow) is about 200mm thick, and the electrode layer 18 made of polysilicon (Poly-8T) is about 350mm thick.
Gradually grow to about 0A. In the figure, 11a indicates a field region, and llb indicates an element region as a canopy-side portion.
ここで第1図(d)と前述の第2図(c)との比較から
明らかなように、両フィールド領域11 a、 21a
の幅Wは同じである。また両キャパシタ部1 l b。Here, as is clear from the comparison between FIG. 1(d) and the above-mentioned FIG. 2(c), both field regions 11a and 21a
have the same width W. Also, both capacitor parts 1 l b.
21bの幅も平面的には同一寸法となっている。The widths of 21b are also the same in plan view.
しかし本発明の場合は、第1図(d)に示す如く、フィ
ールド領域11a近傍のキャパシタ部11cは、バーズ
ビーク16aの発生に起因して表面形状が斜面となって
いるのに対し、従来例では第2図(c)に示す通シ略水
平面となっている。However, in the case of the present invention, as shown in FIG. 1(d), the surface shape of the capacitor portion 11c near the field region 11a is sloped due to the occurrence of the bird's beak 16a, whereas in the conventional example, It is a substantially horizontal plane as shown in FIG. 2(c).
従って、フィールド領域11a近傍のキャパシタ部11
cの表面形状の差により、本発明の場合はキャパシタ部
11bの表面積をよシ大きくとることができる。Therefore, the capacitor section 11 near the field region 11a
Due to the difference in surface shape c, in the case of the present invention, the surface area of the capacitor portion 11b can be made much larger.
以上詳細に説明したように、本発明は素子の高密度化を
図る上で重大な障害となるバーズビークを逆に利用する
もので、選択酸化後にこのバーズビークをエツチング除
去し半導体基板の表面を露出させ、更に絶縁膜、電極層
等を順次形成するようにしている。As explained in detail above, the present invention takes advantage of the bird's beak, which is a serious obstacle in increasing the density of devices, by etching away the bird's beak after selective oxidation to expose the surface of the semiconductor substrate. Furthermore, an insulating film, an electrode layer, etc. are sequentially formed.
従って1,6−ズビーク発生による素子領域の回積低下
を回避できると共に、バーズビークを除去した後の半導
体基板の斜面部をキャパシタ部として用いることにより
、このキャノぞシタ部の容量を増加でき、素子の安定性
を向上することができるという効果がある。Therefore, it is possible to avoid a decrease in the integral of the element area due to the occurrence of the 1,6-beak beak, and by using the slope part of the semiconductor substrate after removing the bird's beak as a capacitor part, the capacitance of this canopy part can be increased, and the element This has the effect of improving the stability of.
また、このようにバーズビークの形状を利用するキャパ
シタ部の面積増加分は、素子の高密度化が進めば進む程
キャパシタ全面積に占める割合が増大するので、本発明
の効果は一層顕著となる。Furthermore, the increased area of the capacitor section utilizing the bird's beak shape will occupy a larger proportion of the total area of the capacitor as the density of the device progresses, and therefore the effects of the present invention will become more significant.
第1図は本発明の一実施例を説明する工程断面図、gg
2図は従来例を説明する工程断面図である。
11・・・半導体基板(P型St基板(100))、1
1a・・・フィールド領域、llb、llc・・・素子
領域(キャパシタ部)、12・・・パッド酸化膜(Si
O2)、13・・・開口部、14・・・耐酸化性マスク
(S 1sN4)、15・・・チャネルストップ領域(
P+型)、16・・・フィールド酸化膜(Si(h)、
16a・・・バーズビーク、17・・・絶縁膜(Sig
h)、1830.電極層(Poly−8i)。
特許出願人 沖電気工業株式会社
! !!/!l−NNNイブ L xi 明Tる工1リ
ヒ道!「面し0第1図FIG. 1 is a process sectional view explaining one embodiment of the present invention, gg
FIG. 2 is a process sectional view explaining a conventional example. 11... Semiconductor substrate (P-type St substrate (100)), 1
1a... Field region, llb, llc... Element region (capacitor section), 12... Pad oxide film (Si
O2), 13... Opening, 14... Oxidation-resistant mask (S 1sN4), 15... Channel stop region (
P+ type), 16... field oxide film (Si(h),
16a... Bird's beak, 17... Insulating film (Sig
h), 1830. Electrode layer (Poly-8i). Patent applicant Oki Electric Industry Co., Ltd.! ! ! /! l-NNN Eve L xi Akira Turuko 1 Rihi road! "Face 0 Figure 1
Claims (1)
るようにした半導体素子の製造方法において、 (a)常法により、半導体基板上に開口部を有するパツ
ド酸化膜及び耐酸化性マスクの2層膜を介して選択酸化
を施すことによりフィールド酸化膜を形成する工程、 (b)上記耐酸化性マスクをエツチング除去した後、バ
ーズビークを除去する程度に上記パッド酸化膜、フィー
ルド酸化膜及びバーズビークを同時にエッチングして上
記半導体基板の表面を露出させ、残存する上記フィール
ド酸化膜により上記半導体基板をフィールド領域と素子
領域とに絶縁分離する工程、 (c)この後、常法により絶縁膜及び電極層を順次形成
する工程 とを含むことを特徴とする半導体素子の製造方法。(1) In a method of manufacturing a semiconductor device in which devices are insulated and separated by a thick field oxide film, (a) two layers of a pad oxide film having openings on a semiconductor substrate and an oxidation-resistant mask are formed by a conventional method; forming a field oxide film by performing selective oxidation through the film; (b) after etching and removing the oxidation-resistant mask, simultaneously etching the pad oxide film, field oxide film, and bird's beak to the extent that the bird's beak is removed; etching to expose the surface of the semiconductor substrate, and insulating and separating the semiconductor substrate into a field region and an element region using the remaining field oxide film; (c) After this, an insulating film and an electrode layer are removed by a conventional method 1. A method for manufacturing a semiconductor device, the method comprising the steps of sequentially forming a semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13838086A JPS62296438A (en) | 1986-06-16 | 1986-06-16 | Device for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13838086A JPS62296438A (en) | 1986-06-16 | 1986-06-16 | Device for manufacturing semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62296438A true JPS62296438A (en) | 1987-12-23 |
Family
ID=15220579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13838086A Pending JPS62296438A (en) | 1986-06-16 | 1986-06-16 | Device for manufacturing semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62296438A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233915A (en) * | 1988-07-22 | 1990-02-05 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
CN102593040A (en) * | 2012-03-21 | 2012-07-18 | 无锡华润上华半导体有限公司 | Integrated production method for local oxidation of silicon (LOCOS) multilayer oxide layer |
-
1986
- 1986-06-16 JP JP13838086A patent/JPS62296438A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233915A (en) * | 1988-07-22 | 1990-02-05 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
CN102593040A (en) * | 2012-03-21 | 2012-07-18 | 无锡华润上华半导体有限公司 | Integrated production method for local oxidation of silicon (LOCOS) multilayer oxide layer |
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