JPH0233915A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0233915A JPH0233915A JP63184021A JP18402188A JPH0233915A JP H0233915 A JPH0233915 A JP H0233915A JP 63184021 A JP63184021 A JP 63184021A JP 18402188 A JP18402188 A JP 18402188A JP H0233915 A JPH0233915 A JP H0233915A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- resist
- film
- nitride film
- field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 13
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置の製造方法におけるレジストの付
着力強化に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to strengthening the adhesion of a resist in a method of manufacturing a semiconductor device.
第２図は、Ｌ ＯＣＯＳ法などによる従来のフィールド
分離酸化膜の断面図である。半導体基板１内の所定領域
−Ｆには、耐酸化性のある酸化マスク用膜として例えば
シリコン窒化膜Ｓｉ３Ｎ４なとを、下敷酸化膜３上に積
層する。またフィールド分ｍ酸化膜２を形成覆る領域に
は下敷酸化膜３を露出させておく。この状態で酸化を行
うと、マスクされた下敷酸化膜３はほとんど厚さが変わ
らないが、露出された下敷酸化膜３は厚く成長してノイ
ールド分１ｍ酸化膜２となる。さらにその境界にはくち
ばし状の酸化膜６が左右対濠に形成される。FIG. 2 is a cross-sectional view of a conventional field isolation oxide film formed by the LOCOS method or the like. In a predetermined region -F in the semiconductor substrate 1, an oxidation-resistant oxidation mask film such as a silicon nitride film Si3N4 is laminated on the underlying oxide film 3. In addition, the underlying oxide film 3 is exposed in the area covered by the field m oxide film 2. When oxidation is performed in this state, the thickness of the masked underlying oxide film 3 hardly changes, but the exposed underlying oxide film 3 grows thicker and becomes a no yield oxide film 2 of 1 m. Furthermore, a beak-shaped oxide film 6 is formed on the boundary between the left and right moats.
また、フィールド分Ｉｉ１酸化膜２が形成さ゛れ４（い
領域の一部は素子形成領域７となる。フィールド分離酸
化膜２が厚いと、素子分離の耐圧は高（７Ｊり良い分離
特性が得られるが酸化膜６も大きく成Ｉｑする。In addition, a part of the area where the field isolation oxide film 2 is not formed becomes the element formation region 7. If the field isolation oxide film 2 is thick, the withstand voltage for element isolation is high (7J), and better isolation characteristics can be obtained. However, the oxide film 6 also grows to a large Iq.
従来のフィールド分離酸化膜２は以上のように構成され
ているので、高い分離耐圧を得るためにフィールド分離
酸化膜２を厚く成長させると酸化膜６も大きくなってし
まう。そのため、例えば素子形成領域７にキ１？バシタ
なとを形成してす、酸化膜６が大きいため素子形成領域
７の実効面積が減少し、キャパシタ容量が減ってしまう
なという問題点があった。Since the conventional field isolation oxide film 2 is constructed as described above, if the field isolation oxide film 2 is grown thickly in order to obtain a high isolation voltage, the oxide film 6 will also become large. Therefore, for example, if there is a hole in the element formation region 7? However, since the oxide film 6 is large, the effective area of the element forming region 7 is reduced, resulting in a reduction in capacitor capacity.
上記のような問題点を解消するために本願出願人は以下
に述べるような技術を提案している。第３図は上記提案
によるフィールド分離酸化膜の断面図である。第２図に
示した従来のフィールド分１１１ｆ酸化膜２に接して形
成された酸化膜６のうち、キャパシタなとを形成する素
子形成領域７側だけを例えばフッ酸系溶液などでエツチ
ングする。この時、キＶパシタ容吊に寄与しない側を含
むフィールド分離酸化膜２はレジストなどで保護し、厚
さを保つ。このようにして非対称フィールド分離酸化膜
２ａを形成する。なお、フッ酸系溶液としては１５：Ｉ
Ｂ＋−（Ｆや１０：１ＨＦなとを用い、それぞれ数分間
の処理を行う。In order to solve the above-mentioned problems, the applicant of the present application has proposed the following technology. FIG. 3 is a cross-sectional view of the field isolation oxide film proposed above. Of the oxide film 6 formed in contact with the conventional field 111f oxide film 2 shown in FIG. 2, only the element formation region 7 side where the capacitors and the like are to be formed is etched using, for example, a hydrofluoric acid solution. At this time, the field isolation oxide film 2 including the side that does not contribute to the capacitance reduction is protected with a resist or the like to maintain its thickness. In this way, an asymmetric field isolation oxide film 2a is formed. In addition, as a hydrofluoric acid solution, 15:I
Using B+-(F or 10:1 HF), perform treatment for several minutes each.
第４図は第３図に示す非対称フィールド分子ｆｌ酸化膜
２ａを用いて形成したメモリセルキャパシタの平面図で
あり、第５図は第４図に示すＡ−Ａ’線に沿った断面図
である。第５図において、半導体基板１上に非対称フィ
ールド分離酸化膜２ａによって分離された素子形成領域
７およびその間の分離領域８が存在する。素子形成領域
７１には第１層ポリシリコン９および絶縁膜１０を介し
て第２層ポリシリコン１１が積層される。第１層ポリシ
リコン９、絶縁１１１０および第２層ポリシリコン１１
はキャパシタを形成している。その対向面積は、非対称
フィールド分！ＩＨＱ化ＦＪ２ａの素子形成領域７側が
エツチングされているので増大している。また第２層ポ
リシリコン１１はトランス７７ゲートとじても動作し、
下敷酸化膜３を介しＣ分離領域８上にも連続的に形成さ
れている。さらにその上に層間絶縁膜１２およびポリシ
リコンなどで形成された第１層配線１３が形成される。4 is a plan view of a memory cell capacitor formed using the asymmetric field molecule fl oxide film 2a shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the line A-A' shown in FIG. be. In FIG. 5, on a semiconductor substrate 1 there are element formation regions 7 separated by an asymmetric field isolation oxide film 2a and isolation regions 8 therebetween. A second layer polysilicon 11 is laminated in the element formation region 71 with a first layer polysilicon 9 and an insulating film 10 interposed therebetween. First layer polysilicon 9, insulation 1110 and second layer polysilicon 11
forms a capacitor. The opposing area is equivalent to an asymmetric field! It increases because the element formation region 7 side of the IHQ FJ 2a is etched. In addition, the second layer polysilicon 11 also operates with the transformer 77 gate,
It is also continuously formed on the C isolation region 8 with the underlying oxide film 3 interposed therebetween. Furthermore, an interlayer insulating film 12 and a first layer wiring 13 made of polysilicon or the like are formed thereon.
居間絶縁ｌ９１２上にはアルミニウムなどで形成された
第２層配線１４が形成され、さらにその上には全面にわ
たってシリコン窒化膜１５が形成される。A second layer wiring 14 made of aluminum or the like is formed on the living room insulation 1912, and a silicon nitride film 15 is further formed over the entire surface.
非対称フィールド分離酸化膜２ａは、素子形成領域７（
Ｉｌｌｌは薄く、分離領１４８側は厚く形成されている
。そのため素子形成領域７の実効面積を増大させ、キャ
パシタを形成する時などはキャパシタの極板間の対向面
積が広くなり容量を増大させることができる。The asymmetric field isolation oxide film 2a is formed in the element formation region 7 (
Ill is thin and the separation region 148 side is thick. Therefore, the effective area of the element forming region 7 can be increased, and when forming a capacitor, the opposing area between the electrode plates of the capacitor is widened, and the capacitance can be increased.
また、非対称フィールド分！酸化膜２ａの分離領域８側
は充分に厚いので分離耐圧も充分高くなる。Also, asymmetrical field minutes! Since the oxide film 2a is sufficiently thick on the isolation region 8 side, the isolation breakdown voltage is also sufficiently high.
第６図は、第２図に示す非対称フィールド分離酸化膜２
ａを得るためのフィールド分離酸化膜エッチバック法に
おける問題点を示した工程断面図である。第６図（ａ）
において、半導体基板１上にフィールド分Ｉｌ！ｉ酸化
ＩＦ１２およびその両側に下敷酸化膜３が形成されてい
る。また、片側の下敷酸化膜３の上にはレジスト５が塗
布されている。FIG. 6 shows the asymmetric field isolation oxide film 2 shown in FIG.
FIG. 3 is a process cross-sectional view showing a problem in the field isolation oxide film etch-back method for obtaining a. Figure 6(a)
, a field portion Il! is formed on the semiconductor substrate 1. An underlying oxide film 3 is formed on the i-oxide IF 12 and both sides thereof. Further, a resist 5 is applied on the underlying oxide film 3 on one side.
第６図（ｂ）において、キャパシタなとを形成する素子
形成領域７上の下敷酸化膜３およびその側部のフィール
ド分１１１化膜２を例えば１０ ： １１−ＩＦ’＞ど
のフッ酸系溶液などでエツチングする。この時フッ酸系
溶液が付着度の低いレジスト５とフィールド分１１［化
膜２の界面にしみこみレジスト５がはがれはじめること
がある。In FIG. 6(b), the underlying oxide film 3 on the element formation region 7 that forms the capacitor and the field 111 film 2 on the side thereof are treated with a hydrofluoric acid solution such as 10:11-IF'> Etching with. At this time, the hydrofluoric acid solution may seep into the interface between the resist 5 and the field film 2, which have a low degree of adhesion, and the resist 5 may begin to peel off.
第６図（Ｃ）において、さらにエツチングが進むとレジ
スト５がさらに大きくはがれ、もはやパターンを保持で
きなくなることがある。In FIG. 6(C), as the etching progresses further, the resist 5 may peel off to a greater extent and may no longer be able to hold the pattern.
以上のようにフィールド分離酸化膜２エツチング時など
にレジスト５がはがれやすく安定したパターンを保持で
きなくなることがある。As described above, the resist 5 tends to peel off during etching of the field isolation oxide film 2, and a stable pattern may not be maintained.
この発明は上記のような問題点を解消するためになされ
たもので、エツチング処理なとを行なう時にも安定した
レジストパターンを保持し、高歩留り、高品質の装置を
１ワることができる半導体装置の製造方法を得ることを
目的とする。This invention was made to solve the above-mentioned problems, and it is a semiconductor that can maintain a stable resist pattern even when performing etching processing, and can achieve high yield and high quality equipment. The purpose is to obtain a method for manufacturing the device.
この発明に係る半導体装置の製造方法は、半導体基板上
に窒化膜を所定のパターンに形成Ｊる工程と、前記窒化
膜を耐酸化マスクとしてフィールド分ｌｌ！を酸化膜を
形成する工程と、前記窒化股上にレジストを塗布しパタ
ーニングする工程とを備えたものである。The method for manufacturing a semiconductor device according to the present invention includes the steps of forming a nitride film in a predetermined pattern on a semiconductor substrate, and using the nitride film as an oxidation-resistant mask to cover a field. The method includes a step of forming an oxide film, and a step of applying and patterning a resist on the nitrided layer.
（作用）
この発明におけるレジス１〜を塗布しパターニングする
工程は、半導体基板上に窒化膜を所定のパターンに形成
し、窒化膜を耐酸化マスクとしてフイールド分Ｉｌ！！
酸化膜を形成する工程のあとに行なわれるので、レジス
トの付着強度が増す。(Function) The step of applying and patterning the resists 1 to 1 in this invention involves forming a nitride film in a predetermined pattern on a semiconductor substrate, and using the nitride film as an oxidation-resistant mask to form a field portion Il! !
Since it is performed after the step of forming an oxide film, the adhesion strength of the resist increases.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例によるフィールド分！！ｔＭ化
膜エッヂバック法を示した工程断面図である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a field according to an embodiment of this invention! ! FIG. 3 is a process cross-sectional view showing a tM film edge-back method.
第１図（ａ）において、半導体基板１上にフィールド分
離酸化膜２およびその両側に、くちばし状ブ）酸化膜６
を介して下敷酸化膜３が形成される。In FIG. 1(a), a field isolation oxide film 2 is formed on a semiconductor substrate 1, and a beak-shaped oxide film 6 is formed on both sides of the field isolation oxide film 2.
An underlying oxide film 3 is formed through the oxide film 3.
下敷酸化膜３−トには、フィールド分１１酸化膜２を形
成する峙の耐酸化膜である窒化膜４が残っている。さら
に素子形成領域７と反対側の窒化膜４上にはレジスト５
が塗布され、パターニングされている。In the underlying oxide film 3--t, a nitride film 4, which is an oxidation-resistant film opposite to the field oxide film 2, remains. Furthermore, a resist 5 is formed on the nitride film 4 on the side opposite to the element formation region 7.
is coated and patterned.
第１図（ｂ）において、レジスト５で覆われていない窒
化膜４を除去する。なお図において、左側は全面にレジ
スト５が付着しているが、窒化膜４に開口部を設けるこ
ともあり、その時は図示されないパターンに応じて、レ
ジスト５がパターニングされている。窒化膜４はレジス
ト５のパターンに応じて除去されるので、その２層膜を
マスクとして、下敷酸化膜３のエツチングやさらにその
下の半導体基板１にイオン注入を行なうことができる。In FIG. 1(b), the nitride film 4 not covered with the resist 5 is removed. In the figure, the resist 5 is attached to the entire surface on the left side, but an opening may be provided in the nitride film 4, and in that case, the resist 5 is patterned according to a pattern not shown. Since the nitride film 4 is removed according to the pattern of the resist 5, using the two-layer film as a mask, it is possible to perform etching of the underlying oxide film 3 and implant ions into the semiconductor substrate 1 therebelow.
第１図（Ｃ）において、フィールド分離酸化膜２の内、
余分な部分を除去するため例えば１０：１ＨＦなどのフ
ッ酸系溶液でフィールド分離酸化膜２のエツチングを行
なう。この処理により素子形成領域７の実効面積を増加
させる。窒化膜４どレジスト５の付着力は充分強く、こ
の段階でフッ酸系溶液がその界面にしみこむことはほと
んどない。In FIG. 1(C), in the field isolation oxide film 2,
In order to remove the excess portion, the field isolation oxide film 2 is etched using a hydrofluoric acid solution such as 10:1 HF. This process increases the effective area of the element formation region 7. The adhesion of the resist 5 to the nitride film 4 is sufficiently strong, and the hydrofluoric acid solution hardly penetrates into the interface at this stage.
そのため、レジスト５のリフトオフは発生じずパターン
を安定して保持できる。Therefore, lift-off of the resist 5 does not occur and the pattern can be stably maintained.
第１図（ｄ）においてレジスト５を除去し、ざらに第１
図（ｅ）において残りの窒化！Ｉ！４を除去する。In FIG. 1(d), the resist 5 is removed and the first
In figure (e) the remaining nitridation! I! Remove 4.
なお、先に第１図（Ｃ）に示すフィールド分離酸化膜２
のエツチングを行なってから、第１図ｆｂ）に示す工程
において行なわれるエツチングやイオン注入を行なって
もよい。またその場合、レジメト５を先に除去し窒化膜
４のみをマスクとして使用してもよい。Note that the field isolation oxide film 2 shown in FIG.
After performing this etching, the etching or ion implantation performed in the step shown in FIG. 1 fb) may be performed. In that case, the regimen 5 may be removed first and only the nitride film 4 may be used as a mask.
以上のようにこの発明によれば、レジスｈを塗布しパタ
ーニングする工程は、半導体基板上に窒化膜を所定のパ
ターンに形成し、窒化膜を耐酸化マスクとしてフィール
ド分子ｎ酸化膜を形成する工程のあとに行なわれるので
、レジストの付着強度が増し、エツチング処理なとを行
なう時にも安定したレジストパターンを保持し、高歩留
り、高品質の装置を得ることができる半導体装置の！Ｆ
Ｊ造方決方法７ることができる。As described above, according to the present invention, the step of applying and patterning the resist h is a step of forming a nitride film in a predetermined pattern on a semiconductor substrate, and forming a field molecule n oxide film using the nitride film as an oxidation-resistant mask. Because it is carried out after etching, the adhesion strength of the resist increases, and a stable resist pattern is maintained even during etching processes, making it possible to obtain high-yield, high-quality devices! F
J construction method 7 can be done.
第１図はこの発明の一実施例によるフィールド分離酸化
膜のエッチバック法を示す工程断面図、第２図は従来の
フィールド分離酸化膜の断面図、第３図は非対称フィー
ルド分＋ｍ酸化膜の断面図、第４図は第３図に示す非対
称フィールド分Ｉ１１酸化膜を用いて形成したメモリセ
ルキャパシタの平面図、第５図は第４図に示すメモセル
キャパシタの断面図、第６図はフィールド分離酸化膜の
エッチバック法における問題点を示した工程断面図であ
る。
図において、１は半導体基板、２はフィールド分１１１
１１ｉ！２化膜、４は窒化膜、５はレジメ１へである。
なお、各図中同一符号は同一または相当部分を示す。FIG. 1 is a process cross-sectional view showing an etch-back method of a field isolation oxide film according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional field isolation oxide film, and FIG. 3 is a cross-sectional view of an asymmetric field + m oxide film. 4 is a plan view of a memory cell capacitor formed using the asymmetric field I11 oxide film shown in FIG. 3, FIG. 5 is a sectional view of the memory cell capacitor shown in FIG. 4, and FIG. FIG. 3 is a process cross-sectional view showing a problem in the etch-back method of a field isolation oxide film. In the figure, 1 is the semiconductor substrate, 2 is the field 111
11i! 2 is a nitride film, 4 is a nitride film, and 5 is a regimen 1. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
と、 前記窒化膜を耐酸化マスクとしてフィールド分離酸化膜
を形成する工程と、 前記窒化膜上にレジストを塗布しパターニングする工程
とを備えた半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, comprising: forming a nitride film in a predetermined pattern on a semiconductor substrate; forming a field isolation oxide film using the nitride film as an oxidation-resistant mask; and on the nitride film. A method for manufacturing a semiconductor device, comprising the steps of applying a resist to the surface and patterning the resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63184021A JP2705124B2 (en) | 1988-07-22 | 1988-07-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63184021A JP2705124B2 (en) | 1988-07-22 | 1988-07-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0233915A true JPH0233915A (en) | 1990-02-05 |
| JP2705124B2 JP2705124B2 (en) | 1998-01-26 |
Family
ID=16145955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63184021A Expired - Lifetime JP2705124B2 (en) | 1988-07-22 | 1988-07-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705124B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5234859A (en) * | 1988-06-28 | 1993-08-10 | Mitsubishi Denki Kabushiki Kaisha | LOCOS type field isolating film and semiconductor memory device formed therewith |
| US5538917A (en) * | 1993-10-07 | 1996-07-23 | Nec Corporation | Fabrication method of semiconductor integrated circuit device |
| US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296438A (en) * | 1986-06-16 | 1987-12-23 | Oki Electric Ind Co Ltd | Device for manufacturing semiconductor integrated circuit |
| JPS6379371A (en) * | 1986-09-24 | 1988-04-09 | Hitachi Vlsi Eng Corp | Manufacture of semiconductor integrated circuit device |
-
1988
- 1988-07-22 JP JP63184021A patent/JP2705124B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296438A (en) * | 1986-06-16 | 1987-12-23 | Oki Electric Ind Co Ltd | Device for manufacturing semiconductor integrated circuit |
| JPS6379371A (en) * | 1986-09-24 | 1988-04-09 | Hitachi Vlsi Eng Corp | Manufacture of semiconductor integrated circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5234859A (en) * | 1988-06-28 | 1993-08-10 | Mitsubishi Denki Kabushiki Kaisha | LOCOS type field isolating film and semiconductor memory device formed therewith |
| US5538917A (en) * | 1993-10-07 | 1996-07-23 | Nec Corporation | Fabrication method of semiconductor integrated circuit device |
| US5861339A (en) * | 1995-10-27 | 1999-01-19 | Integrated Device Technology, Inc. | Recessed isolation with double oxidation |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2705124B2 (en) | 1998-01-26 |
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