WO2013071804A1

WO2013071804A1 - Method for manufacturing cmos field effect transistor

Info

Publication number: WO2013071804A1
Application number: PCT/CN2012/082938
Authority: WO
Inventors: 吴孝嘉; 林峰; 陈正培; 钟海钰
Original assignee: 无锡华润上华半导体有限公司
Priority date: 2011-11-16
Filing date: 2012-10-15
Publication date: 2013-05-23
Also published as: CN103117251A

Abstract

In the technical field of semiconductor manufacturing, a method for manufacturing a CMOS field effect transistor is provided. The method comprises the steps of: providing a chip formed on a CMOS gate dielectric layer and used for forming a polysilicon layer (351, 551) of a gate end of a CMOS; etching the polysilicon layer (351, 551) using a first photoresist mask (390a, 590b) to form a gate end (350a, 550b) of an NMOS/PMOS of the CMOS, and forming a source end and a drain end (360a, 560b) of the NMOS/PMOS of the CMOS through mask patterning and doping using the first photoresist mask (390a, 590b); and etching the polysilicon layer (351, 551) using a second photoresist mask (390b, 590a) to form a gate end (350b, 550a) of a PMOS/NMOS of the CMOS, and forming a source end and a drain end (360b, 560a) of the PMOS/NMOS of the CMOS through mask patterning and doping using the second photoresist mask (390b, 590a). The method saves a photolithographic step and a corresponding mask, has a simple process and lower cost, shortens the process time and improves the production efficiency.

Description

Method for preparing CMOS field effect transistor

[Technical Field]

The invention belongs to the technical field of semiconductor manufacturing and relates to CMOS (Complementary Metal-Oxide-Semiconductor Transistor (Complementary Metal Oxide Semiconductor) field effect transistor fabrication, and in particular, a method of fabricating a CMOS field effect transistor having a feature size greater than or equal to 0.8 microns.

【Background technique】

An integrated circuit (IC) typically includes a plurality of CMOS field effect transistors (eg, more than 10 million) formed on a semiconductor substrate (or wafer) and wired to form a circuit to perform various functions, and thus, a CMOS field effect transistor It is the basic unit of an integrated circuit. Generally, a CMOS field effect transistor includes an NMOS transistor and a PMOS transistor; each NMOS transistor or PMOS transistor includes a gate terminal, a source terminal, and a drain terminal. In the fabrication of CMOS field effect transistors, photolithography is generally required to pattern the gate terminal, source terminal or drain terminal. And the lithography process is relatively costly and time consuming, and it is one of the main factors determining the fabrication cost of the CMOS field effect transistor.

FIG. 1 is a schematic flow chart of a method for fabricating a CMOS field effect transistor provided by the prior art, and FIG. 2 to FIG. 8 are schematic diagrams showing corresponding structures of the process shown in FIG. 1. A method of fabricating a conventional CMOS field effect transistor will be briefly described below with reference to FIGS. 1 through 8.

First, in step S11, a wafer including a polysilicon layer formed on a CMOS gate dielectric layer and used to form a gate terminal of the CMOS is provided. In the invention, the pattern formation process of the gate terminal, the source terminal, and the drain terminal of the CMOS field effect transistor is mainly described. Therefore, the formation of the well, the formation of the gate dielectric layer, and the like are not specifically described. As shown in FIG. 2, a P well 110 and an N well 130 for forming NMOS and PMOS, respectively, are disposed on the substrate 100, and an oxide layer (for example, SiO ₂ ) for forming a gate dielectric layer is formed on each well, and A LOCOS (Local Oxidation of Silicon) layer 170 for achieving isolation covers the oxide layer formed on the gate dielectric and the LOCOS layer 170. The following process steps will be further carried out on the wafer shown in FIG. 2.

Further, in step S12, the polysilicon is patterned by photolithography to form a gate end of the CMOS.

As shown in FIG. 3, in this step, the

gate terminals

150a and 150b are patterned by photolithography, and the polysilicon layer 151 is formed by etching a photoresist mask during patterning. The

gate terminals

150a and 150b are the gate terminal of the NMOS and the gate terminal of the PMOS, respectively. In this step, the oxide layer of the gate dielectric layer other than the gate terminal is also etched at the same time (only an ion implantation protective layer of about 100 angstroms is left, which is not shown in the drawing).

Further, in step S13, a third photoresist mask is photolithographically formed to prepare ion-drain doping of the source and drain terminals of the NMOS.

As shown in FIG. 4, after photolithography, a third photoresist mask 190a is formed, in which a region where N-doping is required is exposed, and a region where P-doping is required is performed by the third photoresist mask 190a. cover.

Further, in step S14, N-type ion implantation doping is performed, and then the third photoresist mask is removed.

As shown in FIG. 5, ion implantation is performed with an N-type dopant to dope to form a source terminal and a drain terminal 160a of the NMOS, and the source terminal and the drain terminal 160a are N+ highly doped regions. Meanwhile, in this example, an N well extraction region 165a (an extraction electrode for forming an N well) is also formed in the N well 130.

Further, in step S15, a fourth photoresist mask is photolithographically formed to prepare ion-drain doping of the source and drain terminals of the PMOS.

As shown in FIG. 6, after photolithography, a fourth photoresist mask 190b is formed. At this time, a region where P-doping is required is exposed, and a region where N-type doping has been performed is used by the fourth photoresist mask 190b. cover.

Further, in step S16, P-type ion implantation doping is performed.

As shown in FIG. 7, ion implantation is performed with a P-type dopant to dope to form a source and drain terminal 160b of the PMOS, and the source and drain terminals 160b are P+ highly doped regions. Meanwhile, in this example, a P well extraction region 165b (an extraction electrode for forming a P well) is also formed in the P well 110.

Further, in step S17, the fourth photoresist mask is removed. Thereby, a structure as shown in FIG. 8 is formed. Next, conventional electrode extraction process steps of the gate terminal, the source terminal and the drain terminal can be performed to form a complete CMOS field effect transistor.

It can be seen from the above preparation process of the CMOS field effect transistor that the patterning process of the gate terminal, the source terminal and the drain terminal requires at least three lithography processes, and correspondingly, three lithography plates are required. Therefore, there are complicated process flows and relatively high costs.

In view of this, it is necessary to improve the preparation method of the CMOS field effect transistor.

[Summary of the Invention]

The technical problem to be solved by the present invention is to reduce the preparation process steps of the CMOS field effect transistor and reduce the preparation cost thereof.

To solve the above technical problem, the present invention provides a method of fabricating a CMOS field effect transistor, the method comprising the steps of:

Providing a wafer including a polysilicon layer formed on a CMOS gate dielectric layer and used to form a gate terminal of a CMOS;

Etching the polysilicon layer by a first photoresist mask to form a gate end of the CMOS NMOS, and doping the source and drain terminals of the CMOS NMOS with the first photoresist mask pattern;

The polysilicon layer is etched through a second photoresist mask to form a gate end of the CMOS PMOS, and the source and drain terminals of the CMOS PMOS are doped by the second photoresist mask pattern.

Preferably, the CMOS field effect transistor has a feature size greater than or equal to 0.8 micrometers; and the CMOS field effect transistor has an operating voltage of 5 volts.

According to an embodiment of the preparation method provided by the present invention, the first photoresist mask covers a region where a gate terminal of the NMOS is to be formed and a region where a PMOS is to be formed, so that a region requiring N-type doping is exposed; The second photoresist mask covers a region where a gate terminal of the PMOS is to be formed and a region where an NMOS is to be formed, so that a region requiring P-type doping is exposed.

Preferably, the region requiring N-type doping includes a source terminal and a drain terminal of the NMOS, and a lead-out region for forming an N-well of the PMOS; the region requiring the P-type doping includes a source terminal and a drain of the PMOS. And a lead-out area for forming a P-well of the NMOS.

Preferably, the first photoresist mask and the second photoresist mask have a thickness ranging from 9080 angstroms to 9280 angstroms.

Preferably, the doping can be achieved by a method of ion implantation.

Preferably, the doping is N-type doping or P-type doping; when the doping is N-type doping, the dopant is P or As; when the doping is P-type doping, the doping is The dopant is B or BF ₂ .

The technical effect of the invention is that both the first photoresist mask and the second photoresist mask are used as a mask for ion implantation and polysilicon etching; thereby eliminating a photolithography step and corresponding photolithography The process is relatively simple, the cost is lower, the process time is shortened, and the production efficiency is greatly improved.

[Description of the Drawings]

The above and other objects and advantages of the present invention will be more fully understood from the aspects of the appended claims.

1 is a schematic flow chart of a method for fabricating a CMOS field effect transistor provided by the prior art;

2 to 8 are schematic views of corresponding structures of the flow shown in FIG. 1;

9 is a schematic flow chart of a method for fabricating a CMOS field effect transistor according to a first embodiment of the present invention;

10 to 18 are schematic views of corresponding structures of the flow shown in Fig. 9.

19 is a schematic flow chart of a method for fabricating a CMOS field effect transistor according to a second embodiment of the present invention;

20 to 28 are schematic views of corresponding structures of the flow shown in Fig. 19.

【detailed description】

The following is a description of some of the various possible embodiments of the invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention or the scope of the invention. It will be readily understood that those skilled in the art can propose other alternatives that can be interchanged without departing from the spirit of the invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the embodiments of the invention, and are not intended to

In the drawings, the thickness of layers and regions are exaggerated for clarity, and the shape features such as rounding due to etching are not illustrated in the drawings. In addition, the same reference numerals are given to the same elements or components, and the description thereof will be omitted.

In the following embodiments, a CMOS field effect transistor having a feature size greater than or equal to 0.8 micrometers is exemplified. Specifically, the CMOS field effect crystal has an operating voltage of 5 volts.

FIG. 9 is a schematic flow chart of a method for fabricating a CMOS field effect transistor according to a first embodiment of the present invention, and FIG. 10 to FIG. 18 are schematic diagrams showing corresponding structures of the process shown in FIG. A method of fabricating the CMOS field effect transistor of this embodiment will be specifically described below with reference to FIGS. 9 to 18.

First, in step S31, a wafer including a polysilicon layer formed on a CMOS gate dielectric layer and used to form a gate terminal of a CMOS is provided.

In this step, as shown in FIG. 10, a double well structure is formed on the substrate 300, wherein the P well 310 is used to form an NMOS device, the N well 330 is used to form a PMOS device, and the P well 310 and the N well 330 can pass through a double The well process is formed, but this is not limiting. An oxide layer (e.g., SiO ₂ ) for forming a gate dielectric layer, and a LOCOS layer 370 for effecting isolation are formed on each well, the polysilicon layer 351 overlying the oxide layer of the gate dielectric and the LOCOS layer 370. The LOCOS layer 370 is not limiting, and in other embodiments, shallow trench isolation (STI) or the like may also be employed. The polysilicon layer 351 is used to form the gate terminal, and therefore, its resistivity is low.

Those skilled in the art should understand that prior to this step, conventional steps such as N-well doping, P-well doping, active region formation, field implantation, threshold voltage adjustment implantation, etc. are performed, all of which are CMOS field effect transistors. Preparation method steps.

Further, in step S32, photolithography forms a first photoresist mask.

In this step, as shown in FIG. 11, the first photoresist mask 390a is formed by N gate photolithography; the first photoresist mask 390a covers the region where the NMOS gate terminal is to be formed and the PMOS is to be formed. The regions are such that regions requiring N-type doping are exposed. The first photoresist mask 390a can be used as a mask layer for etching polysilicon and N-type ion implantation doping in a subsequent step, and therefore, the thickness of the first photoresist mask 390a needs to be larger than that of the prior art FIG. The illustrated photoresist mask 190a is set to be thicker. Preferably, the first photoresist mask 390a has a thickness ranging from 9080 angstroms to 9280 angstroms. The thickness control of the first photoresist mask 390a can be achieved by controlling the spin speed of the photoresist.

Further, in step S33, the polysilicon layer is patterned by the first photoresist mask.

In this step, as shown in FIG. 12, the polysilicon layer 351 is patterned by using the first photoresist mask 390a as a mask, so that the gate terminal 350a of the NMOS can be formed. Through this step, the region requiring N-doping is opened. It should be noted that the specific etching method is not limited in the present invention.

Further, in step S34, N-type ion implantation doping is performed.

In this step, as shown in FIG. 13, the first photoresist mask 390a is used as a mask, and the N-type dopant is used for ion implantation, thereby doping to form the source and drain terminals 360a of the NMOS. The drain terminal 360a is an N+ highly doped region. Meanwhile, in this example, the N well lead-out region 365a is also formed in the N well 330. The specific type of dopant may be P or As; the specific doping amount is not limiting.

Further, in step S35, the first photoresist mask is removed. As shown in Figure 14. The photoresist mask may be etched by RIE (Reactive Ion Etching) or the like, and the remaining polysilicon 350c and the gate terminal 350a are exposed.

Further, in step S36, photolithography forms a second photoresist mask.

In this step, as shown in FIG. 15, a second photoresist mask 390b is formed by using a P gate photolithography photolithography; the second photoresist mask 390b covers a region where the PMOS gate terminal is to be formed and an NMOS is to be formed. The regions are such that regions requiring P-type doping are exposed. The second photoresist mask 390b can be used as a mask layer for etching polysilicon and P-type ion implantation doping in a subsequent step, and therefore, the thickness of the second photoresist mask 390b needs to be larger than that of the prior art FIG. The illustrated photoresist mask 190b is set to be thicker. Preferably, the thickness of the photoresist mask 390b ranges from 9080 angstroms to 9280 angstroms. The thickness control of the second photoresist mask 390b can be achieved by controlling the spin speed of the photoresist.

Further, in step S37, the polysilicon layer is patterned by etching with a second photoresist mask.

In this step, as shown in FIG. 16, the polysilicon layer 350c is patterned by using the second photoresist mask 390b as a mask, so that the gate terminal 350b of the PMOS can be formed. Through this step, a region requiring P-doping is opened. It should be noted that the specific etching method is not limited in the present invention.

Further, in step S38, P-type ion implantation doping is performed.

In this step, as shown in FIG. 17, the second photoresist mask 390b is used as a mask, and ion implantation is performed by a P-type dopant, thereby doping to form a source terminal and a drain terminal 360b of the PMOS. The drain terminal 360b is a P+ highly doped region. Meanwhile, in this example, the P well lead-out region 365b is also formed in the P well 310. The specific type of dopant may be B, or BF2; the specific doping amount is not limiting.

Further, in step S39, the second photoresist mask is removed, as shown in FIG. 18, the photoresist mask can be etched away by RIE or the like, thereby forming substantially the same structure as that shown in FIG. 8. Thus, CMOS The gate terminal, the source terminal and the drain terminal of the field effect transistor are basically formed.

As can be seen from the above, both the first photoresist mask 390a and the second photoresist mask 390b are used as a mask for ion implantation and polysilicon etching; the first photoresist mask 390a can be patterned. The gate terminal, the source terminal and the drain terminal of the NMOS; through the second photoresist mask 390b, the gate terminal, the source terminal and the drain terminal of the PMOS can be patterned. Therefore, compared with the prior art shown in FIG. 1, the photolithography step in step S12 is omitted, the process is relatively simple, the cost is lower, the process time is shortened, and the production efficiency is improved.

FIG. 19 is a schematic flow chart showing a method for fabricating a CMOS field effect transistor according to a second embodiment of the present invention, and FIG. 20 to FIG. 28 are schematic diagrams showing corresponding structures of the flow shown in FIG. A method of fabricating the CMOS field effect transistor of this embodiment will be specifically described below with reference to FIGS. 19 to 28.

First, in step S51, a wafer including a polysilicon layer formed on a CMOS gate dielectric layer and used to form a gate terminal of a CMOS is provided.

In this step, as shown in FIG. 20, a double well structure is formed on the substrate 500, wherein the P well 510 is used to form an NMOS device, the N well 530 is used to form a PMOS device, and the P well 510 and the N well 530 can pass through a double The well process is formed, but this is not limiting. An oxide layer (e.g., SiO ₂ ) for forming a gate dielectric layer, and a LOCOS layer 570 for effecting isolation are formed on each well, and the polysilicon layer 551 covers the oxide layer formed on the gate dielectric and the LOCOS layer 570. The LOCOS layer 570 is not limiting, and in other embodiments, shallow trench isolation (STI) or the like may also be employed. The polysilicon layer 551 is used to form the gate terminal, and therefore, its resistivity is low.

Further, in step S52, photolithography forms a second photoresist mask.

In this step, as shown in FIG. 21, a second photoresist mask 590b is formed by using P gate photolithography; the second photoresist mask 590b covers a region where the PMOS gate terminal is to be formed and an NMOS is to be formed. The regions are such that regions requiring P-type doping are exposed. The second photoresist mask 590b can be used as a mask layer for etching polysilicon and P-type ion implantation doping in a subsequent step, and therefore, the thickness of the second photoresist mask 590b needs to be larger than that of the prior art. The illustrated photoresist mask 190b is set to be thicker. Preferably, the thickness of the second photoresist mask 590b ranges from 9080 angstroms to 9280 angstroms. The thickness control of the second photoresist mask 590b can be achieved by controlling the spin speed of the photoresist.

Further, in step S53, the polysilicon layer is patterned by etching with a second photoresist mask.

In this step, as shown in FIG. 22, the polysilicon layer 551 is patterned by using the second photoresist mask 590b as a mask, so that the gate end 550b of the PMOS can be formed. Through this step, a region requiring P-doping is opened. It should be noted that the specific etching method is not limited in the present invention.

Further, in step S54, P-type ion implantation doping is performed.

In this step, as shown in FIG. 23, the second photoresist mask 590b is used as a mask, and ion implantation is performed with a P-type dopant, thereby doping to form a source terminal and a drain terminal 560b of the PMOS. The drain terminal 560b is a P+ highly doped region. Meanwhile, in this example, the P well lead-out region 565b is also formed in the P well 510. The specific type of dopant may be B or BF ₂ ; the specific doping amount is not limiting.

Further, in step S55, the second photoresist mask is removed. As shown in Figure 24. The photoresist mask can be etched away by RIE or the like, and the remaining polysilicon 550d and the gate terminal 550b are exposed.

Further, in step S56, photolithography forms a first photoresist mask.

In this step, as shown in FIG. 25, a first photoresist mask 590a is formed by N gate photolithography; the first photoresist mask 590a covers a region where the NMOS gate terminal is to be formed and a PMOS is to be formed. The regions are such that regions requiring N-type doping are exposed. The first photoresist mask 590a can be used as a mask layer for etching polysilicon and N-type ion implantation doping in a subsequent step, and therefore, the thickness of the first photoresist mask 590a needs to be larger than that of the prior art FIG. The illustrated photoresist mask 190a is set to be thicker. Preferably, the first photoresist mask 590a has a thickness ranging from 9080 angstroms to 9280 angstroms. The thickness control of the first photoresist mask 590a can be achieved by controlling the spin speed of the photoresist.

Further, in step S57, the polysilicon layer is patterned by the first photoresist mask.

In this step, as shown in FIG. 26, the polysilicon layer 550d is patterned by using the first photoresist mask 590a as a mask, so that the gate end 550a of the NMOS can be formed. Through this step, the region requiring N-doping is opened. It should be noted that the specific etching method is not limited in the present invention.

Further, in step S58, N-type ion implantation doping is performed.

In this step, as shown in FIG. 27, the first photoresist mask 590a is used as a mask, and the N-type dopant is used for ion implantation, thereby doping to form the source and drain terminals 560a of the NMOS. The drain terminal 560a is an N+ highly doped region. Meanwhile, in this example, the N well lead-out region 565a is also formed in the N well 530. The specific type of dopant may be P or As, and the specific doping amount is not limitative.

Further, in step S59, the first photoresist mask is removed. As shown in FIG. 28, the photoresist mask can be etched away by RIE or the like to form substantially the same structure as that shown in FIG. 8. Thus, the gate terminal, the source terminal and the drain terminal of the CMOS field effect transistor are substantially formed. .

It will be understood by those skilled in the art that after step S39 or S59 of the first and second embodiments above, conventional steps of a conventional conventional CMOS field effect transistor, such as depositing a PMD dielectric layer, are not performed here. A description. Also, in the middle of each step, it is also possible to insert conventional preparation steps of other CMOS field effect transistors.

The above examples mainly illustrate the preparation method of the CMOS field effect transistor of the present invention. Although only a few of the embodiments of the present invention have been described, it will be understood by those skilled in the art that the invention may be practiced in many other forms without departing from the spirit and scope of the invention. Accordingly, the present invention is to be construed as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims With replacement.

Claims

A method for preparing a CMOS field effect transistor, characterized in that the method comprises the steps of:

Providing a wafer including a polysilicon layer formed on a CMOS gate dielectric layer and used to form a gate terminal of a CMOS;

Etching the polysilicon layer by a first photoresist mask to form a gate end of the CMOS NMOS, and doping the source and drain terminals of the CMOS NMOS with the first photoresist mask pattern;

The polysilicon layer is etched through a second photoresist mask to form a gate end of the CMOS PMOS, and the source and drain terminals of the PMOS PMOS are doped by the second photoresist mask pattern.
The method according to claim 1, wherein the CMOS field effect transistor has a feature size greater than or equal to 0.8 micrometers.
The method according to claim 1 or 2, wherein the CMOS field effect transistor has an operating voltage of 5 volts.
The method according to claim 1, wherein the first photoresist mask covers a region where a gate terminal of the NMOS is to be formed and a region where a PMOS is to be formed, so that a region requiring N-type doping is exposed; The second photoresist mask covers a region where a gate terminal of the PMOS is to be formed and a region where an NMOS is to be formed, so that a region requiring P-type doping is exposed.
The method according to claim 4, wherein the region requiring N-type doping includes a source terminal and a drain terminal of the NMOS, and a lead-out region for forming an N-well of the PMOS.
The method according to claim 4, wherein the region requiring P-type doping includes a source terminal and a drain terminal of the PMOS, and a lead-out region for forming a P well of the NMOS.
The method according to claim 1, wherein the first photoresist mask and the second photoresist mask have a thickness ranging from 9080 angstroms to 9280 angstroms.
The method according to claim 1, wherein the doping is achieved by a method of ion implantation.
The method according to claim 1, wherein the doping is N-type doping or P-type doping; when the doping is N-type doping, the dopant is P or As; When the doping is P-type doping, the dopant is B or BF 2 .