WO2013133215A1 - Circuit amplificateur doherty - Google Patents

Circuit amplificateur doherty Download PDF

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Publication number
WO2013133215A1
WO2013133215A1 PCT/JP2013/055857 JP2013055857W WO2013133215A1 WO 2013133215 A1 WO2013133215 A1 WO 2013133215A1 JP 2013055857 W JP2013055857 W JP 2013055857W WO 2013133215 A1 WO2013133215 A1 WO 2013133215A1
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Prior art keywords
doherty amplifier
circuit
matching circuit
amplifier circuit
peak
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PCT/JP2013/055857
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English (en)
Japanese (ja)
Inventor
洋一郎 高山
本城　和彦
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国立大学法人 電気通信大学
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Publication of WO2013133215A1 publication Critical patent/WO2013133215A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/423—Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • the present invention relates to a Doherty amplifier circuit, and more particularly to a Doherty amplifier circuit whose operation mode is switched according to the strength of an input signal.
  • Doherty amplifiers are expected to be power amplifiers that meet these requirements, and their research and development are being conducted by many research institutions.
  • the characteristic of the Doherty amplifier is that the signal input level is relatively low and the state of saturation amplification is not reached, that is, the power efficiency in a state where a large back-off is taken is larger than amplifiers of other systems. Since such characteristics are extremely suitable as a power amplifier for the communication system described above, attention is focused on Doherty amplifiers.
  • the Doherty amplifier was conceived by Doherty in 1936 as described in Non-Patent Document 1.
  • Doherty has proposed a parallel connection load method and a series connection load method.
  • FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1A will be described.
  • the parallel connection load type Doherty amplifier circuit shown in FIG. 1A includes a first vacuum tube T1, a second vacuum tube T2, a parallel connection load LP, and an impedance inverting circuit IIN.
  • the connection relationship of the components of the parallel connection load type Doherty amplifier shown in FIG. 1A will be described.
  • the first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in parallel. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
  • FIG. 1B is a circuit diagram showing the configuration of a serial connection load type Doherty amplifier circuit according to the prior art. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1B will be described.
  • the serial connection load type Doherty amplifier circuit shown in FIG. 1B includes a first vacuum tube T1, a second vacuum tube T2, a serial connection load LS, and an impedance inverting circuit IIN.
  • the connection relationship of the components of the serial connection load type Doherty amplifier shown in FIG. 1B will be described.
  • the first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in series. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
  • FIG. 1C is a circuit diagram in a case where the parallel-connected load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power source assuming a transistor. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described.
  • the parallel connected load type Doherty amplifier circuit shown in FIG. 1C includes a first ideal current source I1, a second ideal current source I2, a parallel connected load LP, and a quarter wavelength line QW. Yes.
  • the connection relationship of the components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described.
  • the first ideal current source I1, the second ideal current source I2, and the parallel connection load LP are connected in parallel.
  • the quarter-wave line QW is connected in series between the first ideal current source I1 and the second ideal current source I2.
  • FIG. 1D is a circuit diagram in the case where the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power source assuming a transistor. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described. 1D includes a first ideal voltage source V1, a second ideal voltage source V2, a series connection load LS, and a quarter wavelength line QW. Yes.
  • the connection relationship of the components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described.
  • the first ideal voltage source V1, the second ideal voltage source V2, the series connection load LS, and the quarter wavelength line QW are connected in series.
  • the first vacuum tube T1 shown in FIGS. 1A and 1B, the first ideal current source I1 shown in FIG. 1C, and the first ideal voltage source V1 shown in FIG. 1D are all carriers.
  • the carrier amplifier is an amplifier having an operation corresponding to class AB to class B or equivalent to them, and amplifies the input signal if it is below a predetermined threshold, and saturates if it is above the predetermined threshold. It will be in the output state.
  • the second vacuum tube T2 shown in FIGS. 1A and 1B, the second ideal current source I2 shown in FIG. 1C, and the second ideal voltage source V2 shown in FIG. Functions as a peak amplifier.
  • the peak amplifier is an amplifier operating in the class B to class C or equivalent thereto, and is turned off when the intensity of the input signal is not more than a predetermined threshold, and if it is not less than the predetermined threshold, Is to amplify.
  • the threshold value of the peak amplifier is set to the same value as the threshold value of the carrier amplifier.
  • the quarter wavelength line QW shown in FIG. 1C and FIG. 1D is a transmission line having a length of almost a quarter of the wavelength of the input signal, and performs impedance conversion.
  • the impedance inverting circuit IIN shown in FIGS. 1A and 1B functions as the quarter wavelength line QW shown in FIGS. 1C and 1D.
  • the input signal is bisected by a distribution circuit, one being fed to the carrier amplifier and the other being fed to the peak amplifier via a line that is approximately a quarter wavelength of the input signal.
  • the Connected to the output section of the carrier amplifier is an impedance conversion circuit composed of a line having a quarter wavelength of the input signal.
  • the output signal of the carrier amplifier and the output signal of the peak amplifier output via the impedance conversion circuit and the output signal of the peak amplifier are directly coupled to obtain an amplified signal at the load.
  • the power of the input signal increases, and when the carrier amplifier reaches a state close to saturation output, the output of the peak amplifier rises. At this time, the power efficiency of the carrier amplifier is maximized, and this is ideally approximately 78% in an operation close to class B. As the power of the input signal further increases, the output power of both amplifiers is taken from the common load.
  • the carrier amplifier When increasing the power of the input signal, first, the carrier amplifier performs an amplification operation to dominate the amplification characteristic until the peak amplifier rises. The peak amplifier then rises at the input signal power at which the carrier amplifier reaches its maximum power efficiency. Furthermore, the output power and power efficiency are substantially maintained as the input signal increases.
  • FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FET field effect transistor
  • 2A and 2B each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier-side input impedance matching circuit IMNC.
  • the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases.
  • the output of the carrier transistor TC is supplied to the parallel connection load LP via the carrier side output impedance matching circuit OMNC.
  • the output of the peak transistor TP is also supplied to the parallel connection load LP via the peak side output impedance matching circuit OMNP and the transmission line TL.
  • the quarter wavelength line QW is arranged between the carrier side output impedance matching circuit OMNC and the parallel connection load LP in the normal type Doherty amplifier circuit of FIG. 2A, whereas the reverse type Doherty of FIG. In the amplifier circuit, it is arranged between the peak side output impedance matching circuit OMNP and the parallel connection load LP.
  • the phase adjustment line PL is also arranged between the distribution circuit DC and the peak transistor TP in the normal type Doherty amplification circuit of FIG. 2A, whereas the distribution circuit DC and the carrier are arranged in the reverse type Doherty amplification circuit of FIG. 2B. Arranged between the transistors TC.
  • FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FET field effect transistor
  • FIG. 2C and FIG. 2D each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier side input impedance matching circuit IMNC.
  • the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases.
  • the output of the carrier transistor TC is supplied to one end of the balanced port of the balun B through the carrier side output impedance matching circuit OMNC.
  • the output of the peak transistor TP is also supplied to the other end of the balanced port of the balun B via the peak side output impedance matching circuit OMNP and the transmission line TL.
  • the unbalanced port of the balun B is connected to the series connection load LS.
  • the transfer adjustment line PL is disposed between the distribution circuit DC and the peak transistor TP.
  • the quarter wavelength line QW is arranged between the balun B and the peak-side output impedance matching circuit OMNP in the normal type Doherty amplifier circuit of FIG. 2C, whereas the inverted Doherty amplifier circuit of FIG. Then, it is arranged between the balun B and the carrier side output impedance matching circuit OMNC.
  • a quarter-wave line functioning as an impedance conversion circuit is used as an important component.
  • the quarter-wave line occupies a large area in the Doherty amplifier circuit, and also causes a narrowing of the amplification frequency band and output power loss in terms of characteristics.
  • the quarter-wave line can also be constituted by a lumped element circuit.
  • An object of the present invention is to provide an ultra-high frequency Doherty power amplifier having a novel configuration that integrates a normal type and an inverted type without using a quarter-wave line as an impedance conversion circuit, eliminating the disadvantages of the prior art. It is in.
  • the operation mode is switched between the first amplification mode and the second amplification mode according to the strength of the input signal.
  • the Doherty amplifier circuit includes an input unit (I), a first amplifier (TC), a second amplifier (TP), a first matching circuit (OMNC), an output unit (O), and a second matching circuit ( OMNP) and a line (TL).
  • the input unit (I) distributes the input signal into two.
  • the first amplifier (TC) amplifies one of the input signals in the first amplification mode, and enters a saturated output state in the second amplification mode.
  • the second amplifier (TP) is turned off in the first amplification mode, and amplifies the other of the input signals in the second amplification mode.
  • the first matching circuit (OMNC) is connected to the subsequent stage of the first amplifier (TC).
  • the output unit (O) is connected to the subsequent stage of the first matching circuit (OMNC).
  • the second matching circuit (OMNP) is connected to the subsequent stage of the second amplifier (TP).
  • the line (TL) is connected between the output unit (O) and the output unit of the second matching circuit (OMNP).
  • the line (TL) has a length shorter than a quarter wavelength of the input signal.
  • the first matching circuit (OMNC) has four independent parameters. Here, the four independent parameters are designed and adjusted so as to satisfy the output impedance matching in both the first amplification mode and the second amplification mode.
  • the Doherty amplifier circuit according to the present invention does not have a quarter-wave line, its size can be greatly reduced.
  • FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art.
  • FIG. 1B is a circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the prior art.
  • FIG. 1C is a circuit diagram in the case where the parallel connection load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power supply.
  • FIG. 1D is a circuit diagram when the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power supply.
  • FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FET field effect transistor
  • FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FIG. 3A is a block circuit diagram schematically showing a basic form of the Doherty amplifier circuit according to the present invention.
  • FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 3C is a block circuit diagram showing a configuration of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4A is a block circuit diagram showing an output impedance in a peak amplifying unit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4A is a block circuit diagram showing an output impedance in a peak amplifying unit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the parallel connection load type Doherty amplifier
  • FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the low power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6A is a circuit diagram showing a configuration example of a carrier side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6B is a circuit diagram showing a configuration example of a peak-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6C is a circuit diagram illustrating another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 7A is a circuit diagram showing another configuration example of the carrier-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 8A is a block circuit diagram schematically showing a basic form of a serial connection load type Doherty amplifier circuit according to a second embodiment of the present invention.
  • FIG. 8B is a block circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 9A is a block circuit diagram showing an output impedance in a peak amplifying unit of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 10A is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the low power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 10B is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 11B is a circuit diagram illustrating a specific configuration example of the peak-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the present invention provides a Doherty amplifier circuit that does not use a quarter-wave line as an impedance conversion circuit, which is provided as a basic constituent circuit element in a Doherty amplifier circuit according to the prior art.
  • the basic principle of the present invention is based on the following two points.
  • the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the output parallel coupling terminal.
  • the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the combined terminal of the output balun.
  • an ultra-high frequency power amplifier configured using transistors includes an input impedance matching circuit and an output impedance matching circuit.
  • FIG. 3A is a block circuit diagram schematically showing the basic form of the Doherty amplifier circuit according to the present invention.
  • the Doherty amplifier circuit illustrated in FIG. 3A includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the carrier amplification section C and the peak amplification section P are connected in parallel or in series at the input section I and the output section O.
  • the input unit I inputs an input signal and distributes it into two, supplies one to the carrier amplification unit C, and supplies the other to the peak amplification unit P.
  • the carrier amplifier C amplifies one of the distributed input signals, and is designed to be in a saturated output state when the intensity of the input signal is equal to or higher than a predetermined threshold. Further, the output part of the carrier amplifier C is designed so that impedance matching is achieved with respect to the output part O that is the connection destination.
  • the peak amplifying unit P amplifies the other one of the distributed input signals, and is designed to be turned off when the intensity of the input signal is a predetermined threshold value or less. Moreover, the output part of the peak amplification part P is designed so that impedance matching is taken with respect to the output part O which is a connection destination. Note that the threshold value related to the peak amplification unit P is preferably the same value as the threshold value related to the saturation output state of the carrier amplification unit C.
  • the output unit O is designed to synthesize the output of the carrier amplification unit C and the output of the peak amplification unit P in parallel or in series.
  • FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the parallel connection load type Doherty amplification circuit shown in FIG. 3B includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LP. And an aggregate OO.
  • These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
  • the output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC.
  • the output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP.
  • the aggregate OO includes a line TL (not shown) and a parallel connection load LP.
  • FIG. 3C is a block circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • a configuration example of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention will be described in more detail than FIG. 3B using the block circuit diagram shown in FIG. 3C.
  • the parallel-connected load type Doherty amplifier circuit illustrated in FIG. 3C includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the input section I shown in FIG. 3C includes a distribution circuit DC and a phase adjustment line PL.
  • the carrier amplifying unit C shown in FIG. 3C includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC.
  • the peak amplifier P shown in FIG. 3C includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP.
  • the output unit O illustrated in FIG. 3C includes a transmission line TL and is connected to a parallel connection load LP.
  • One output portion of the distribution circuit DC is connected to one end of the phase adjustment line PL.
  • the other end of the phase adjustment line PL is connected to the input part of the carrier side input impedance matching circuit IMNC.
  • the output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC.
  • the drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC.
  • the source of the carrier transistor TC is grounded.
  • the output part of the carrier side output impedance matching circuit OMNC is commonly connected to one end of the transmission line TL and one end of the parallel connection load LP.
  • the other end of the parallel connection load LP is grounded.
  • the other output section of the distribution circuit DC is connected to the input section of the peak side input impedance matching circuit IMNP.
  • the output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP.
  • the drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP.
  • the source of the peak transistor TP is grounded.
  • the output part of the peak side output impedance matching circuit OMNP is connected to the other end of the transmission line TL.
  • the quarter-wave line QW required in the parallel-connected load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is replaced by the parallel according to the first embodiment of the present invention shown in FIG. 3C. Note that it is not used in a connected load Doherty amplifier.
  • FIG. 4A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • 4A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL not shown in FIG. 3B.
  • the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in series in this order.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the first impedance ZP1 shown in FIG. 4B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 4A when the intensity of the input signal is less than the threshold value of the peak amplifier.
  • the first impedance ZP1 is located in the upper half of the Smith chart shown in FIG. 4B, that is, is inductive.
  • the second impedance ZP2 shown in FIG. 4B indicates the output impedance of the transmission line TL shown in FIG. 4A.
  • the second impedance ZP2 is located near the right end of the Smith chart shown in FIG. 4B, that is, an impedance close to opening.
  • the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
  • FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the block circuit diagram shown in FIG. 5A, the carrier transistor TC, and a carrier-side output impedance matching circuit OMNC, and the load LP L, are connected in cascade.
  • Z optL shown in FIG. 5A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents.
  • Load LP L is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier transistor TC and a carrier-side output impedance matching circuit OMNC, and the load LP H, they are connected in cascade.
  • ZoptH shown in FIG. 5B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C becoming saturated. Represents impedance.
  • Load LP H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • the impedance of the load LP L in the low power amplification mode shown in FIG. 5A is half of the impedance of the load LP H in the gradient power amplification mode shown in FIG. 5B. . That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
  • the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
  • FIG. 6A is a circuit diagram showing a configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 6A includes a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2.
  • the first inductor L1 and the second inductor L2 are connected in series between the input part and the output part of the carrier-side output impedance matching circuit OMNC.
  • One end of the first capacitor C1 is commonly connected to the first inductor L1 and the second inductor L2, and the other end is grounded.
  • One end of the second capacitor C2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L2, and the other end is grounded.
  • the first and second inductors L1 and L2 are connected in series, and the first and second capacitors C1 and C2 are connected in parallel.
  • the Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L1 and L2 shown in FIG. 6A and the capacitance in each of the two capacitors C1 and C2. The inventor has confirmed this through simulation analysis and experiments.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 6B or FIG. 6C, for example.
  • FIG. 6B is a circuit diagram showing a configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 6B includes an inductor L3 and a capacitor C3.
  • the inductor L3 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP.
  • One end of the capacitor C3 is connected to the output portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded.
  • the inductor L3 is connected in series, and the capacitor C3 is connected in parallel.
  • FIG. 6C is a circuit diagram showing another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 6C includes a first inductor L4, a second inductor L5, a first capacitor C4, and a second capacitor C5. Is the same as that in the case of the carrier side output impedance matching circuit OMNC shown in FIG. 6A, and further detailed description is omitted.
  • FIG. 7A is a circuit diagram showing another configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 7A includes a first transmission line TL1, a second transmission line TL2, a first stub S1, and a second stub S2.
  • the first transmission line TL1 and the second transmission line TL2 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC.
  • the first stub S1 is commonly connected to the first transmission line TL1 and the second transmission line TL2.
  • the second stub S2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second transmission line TL2.
  • the first and second transmission lines TL1 and TL2 are connected in series, and the first and second stubs S1 and S2 are connected in parallel.
  • the Doherty amplifier circuit according to the present invention is normal.
  • the inventor has confirmed through experiments that it works.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 7B, for example.
  • FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 7B includes a transmission line TL3 and a stub S3.
  • the transmission line TL3 is connected between the input unit and the output unit of the peak side output impedance matching circuit OMNP.
  • the stub S3 is commonly connected to the output part of the peak-side output impedance matching circuit OMNP and the transmission line TL3.
  • the transmission line TL3 is connected in series, and the stub S3 is connected in parallel.
  • the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment may be configured using a lumped constant element or a distributed constant element. good. Furthermore, it goes without saying that a lumped constant element and a distributed constant element may be combined.
  • FIG. 8A is a block circuit diagram schematically showing a basic form of a series-connected load type Doherty amplifier circuit according to a second embodiment of the present invention.
  • the serial connection load type Doherty amplification circuit shown in FIG. 8A includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LS. And an aggregate OO.
  • These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
  • the output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC.
  • the output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP.
  • the aggregate OO includes a line TL (not shown) and a series connection load LS.
  • FIG. 8B is a block circuit diagram showing a configuration of a series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • a configuration example of the series-connected load-type Doherty amplifier circuit according to the second embodiment of the present invention will be described in more detail than FIG. 8A, using the block circuit diagram shown in FIG. 8B.
  • the serial connection load type Doherty amplifier circuit shown in FIG. 8B includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the input unit I shown in FIG. 8B includes a distribution circuit DC and a phase adjustment line PL.
  • the carrier amplification unit C shown in FIG. 8B includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC.
  • the peak amplifier P shown in FIG. 8B includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP.
  • the output unit O illustrated in FIG. 8B includes a transmission line TL and a balun B, and is connected to a series connection load LS.
  • the balun B is not particularly limited, and any of a transmission line balun, a transformer balun, a lumped constant balun, a phase inversion balun, and other baluns may be used.
  • One output section in the distribution circuit DC is connected to the input section of the carrier side input impedance matching circuit IMNC.
  • the output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC.
  • the drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC.
  • the source of the carrier transistor TC is grounded.
  • the output part of the carrier side output impedance matching circuit OMNC is connected to one end of the balanced port of the balun B. In the series connection load LS, one end is connected to one end of the unbalanced port of the balun B, and the other end is directly grounded. The other end of the unbalanced port of the balun B is grounded.
  • the other output section of the distribution circuit DC is connected to one end of the phase adjustment line PL.
  • the other end of the phase adjustment line PL is connected to the input part of the peak side input impedance matching circuit IMNP.
  • the output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP.
  • the drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP.
  • the source of the peak transistor TP is grounded.
  • the output part of the peak-side output impedance matching circuit OMNP is connected to the other end of the balanced port of the balun B via the transmission line TL.
  • the quarter wavelength line QW required in the parallel connection load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is converted into the series according to the second embodiment of the invention shown in FIG. 8B. Note that it is not used in a connected load Doherty amplifier.
  • FIG. 9A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • 9A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL that is not shown in FIG. 3B.
  • the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in cascade in this order.
  • FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the first impedance ZS1 shown in FIG. 9B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 9A when the intensity of the input signal is less than the threshold value of the peak amplifier.
  • the first impedance ZS1 is located in the lower half of the Smith chart shown in FIG. 9B, that is, is capacitive.
  • the second impedance ZS2 illustrated in FIG. 9B indicates the output impedance of the transmission line TL illustrated in FIG. 9A.
  • the second impedance ZS2 is located near the right end of the Smith chart shown in FIG. 9B, that is, an impedance close to a short circuit.
  • the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
  • FIG. 10A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • a carrier transistor TC a carrier-side output impedance matching circuit OMNC, and a load LS L are connected in cascade.
  • Z optL shown in FIG. 10A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents.
  • the load LS L is a load viewed from the carrier-side output impedance matching circuit OMNC.
  • FIG. 10B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the carrier transistor TC and a carrier-side output impedance matching circuit OMNC, and a load LS H, they are connected in cascade.
  • ZoptH shown in FIG. 10B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C being saturated. Represents impedance.
  • Load LS H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • the impedance of the load LS L in the low power amplification mode shown in FIG. 10A at twice the impedance of the load LS H in the high power amplification mode shown in FIG. 10B is there. That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
  • the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
  • FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit OMNC of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 11A includes a first inductor L6, a second inductor L7, a first capacitor C6, and a second capacitor C7.
  • the first inductor L6 and the second inductor L7 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC.
  • One end of the first capacitor C6 is commonly connected to the first inductor L6 and the second inductor L7, and the other end is grounded.
  • One end of the second capacitor C7 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L7, and the other end is grounded.
  • the first and second inductors L6 and L7 are connected in series, and the first and second capacitors C6 and C7 are connected in parallel.
  • the Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L6 and L7 shown in FIG. 11A and the capacitance in each of the two capacitors C6 and C7. The inventor has confirmed this through simulation analysis and experiments.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 11B, for example.
  • FIG. 11B is a circuit diagram showing a specific configuration example of the peak-side output impedance matching circuit OMNP of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 11B includes an inductor L8 and a capacitor C8.
  • the inductor L8 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP.
  • One end of the capacitor C8 is connected to the input portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded.
  • the inductor L8 is connected in series, and the capacitor C8 is connected in parallel.
  • the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment can be configured using lumped constant elements, but may be configured using distributed constant elements. Needless to say, a lumped constant element and a distributed constant element may be combined.

Abstract

L'invention porte sur un circuit amplificateur Doherty dans lequel le mode d'actionnement change entre le premier mode d'amplification et le second mode d'amplification en fonction de l'intensité du signal d'entrée. Ce circuit amplificateur Doherty comprend une unité d'entrée, un premier amplificateur, un second amplificateur, un premier circuit d'adaptation, une unité de sortie et un second circuit d'adaptation. L'unité d'entrée divise en deux le signal d'entrée. Le premier amplificateur amplifie l'un des signaux d'entrée dans le premier mode d'amplification, et est dans un état de sortie saturée dans le second mode d'amplification. Le second amplificateur est dans un état d'arrêt dans le premier mode d'amplification, et amplifie l'autre signal d'entrée dans le second mode d'amplification. Le premier circuit d'adaptation est connecté à l'étage qui suit le premier amplificateur. L'unité de sortie est connectée à l'étage qui suit le premier circuit d'adaptation. Le second circuit d'adaptation est connecté à l'étage qui suit le second amplificateur. L'unité de sortie est connectée à l'étage qui suit le second circuit d'adaptation, et est munie d'un fil qui est plus court qu'un quart de la longueur d'onde du signal d'entrée. Le premier circuit d'adaptation est doté d'au moins quatre paramètres indépendants ajustés en termes de conception de manière à satisfaire l'adaptation d'impédance de sortie, aussi bien dans le premier mode d'amplification que dans le second mode d'amplification.
PCT/JP2013/055857 2012-03-05 2013-03-04 Circuit amplificateur doherty WO2013133215A1 (fr)

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WO2015108492A1 (fr) * 2014-01-14 2015-07-23 Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi Amplificateur de doherty doté d'un combineur de puissance en phase à large bande
EP3264595A1 (fr) * 2016-06-30 2018-01-03 Nxp B.V. Amplificateurs de doherty
CN107547051A (zh) * 2017-08-28 2018-01-05 广东顺德中山大学卡内基梅隆大学国际联合研究院 基于分布式宽带阻抗变换结构的Doherty功率放大器
EP3396856A1 (fr) * 2017-04-24 2018-10-31 Gatesair Inc. Systèmes et procédés d'amplification push-pull
EP3570433A1 (fr) * 2015-01-09 2019-11-20 Kabushiki Kaisha Toshiba Amplificateur de doherty
EP3813253A1 (fr) * 2019-10-23 2021-04-28 Nxp B.V. Amplificateur de fréquence radio

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US10116266B2 (en) 2015-01-09 2018-10-30 Kabushiki Kaisha Toshiba Doherty amplifier
CN104579178A (zh) * 2015-01-19 2015-04-29 东南大学 一种基于宽带输入匹配的改进型多赫尔蒂功率放大器
CN112020826B (zh) * 2018-04-26 2023-08-15 三菱电机株式会社 放大器

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WO2015108492A1 (fr) * 2014-01-14 2015-07-23 Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi Amplificateur de doherty doté d'un combineur de puissance en phase à large bande
EP3570433A1 (fr) * 2015-01-09 2019-11-20 Kabushiki Kaisha Toshiba Amplificateur de doherty
EP3264595A1 (fr) * 2016-06-30 2018-01-03 Nxp B.V. Amplificateurs de doherty
CN107565909A (zh) * 2016-06-30 2018-01-09 恩智浦有限公司 多尔蒂放大器
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CN107565909B (zh) * 2016-06-30 2024-01-09 恩智浦有限公司 多尔蒂放大器
EP3396856A1 (fr) * 2017-04-24 2018-10-31 Gatesair Inc. Systèmes et procédés d'amplification push-pull
US10270396B2 (en) 2017-04-24 2019-04-23 Gatesair, Inc. Push-pull amplification systems and methods
CN107547051A (zh) * 2017-08-28 2018-01-05 广东顺德中山大学卡内基梅隆大学国际联合研究院 基于分布式宽带阻抗变换结构的Doherty功率放大器
CN107547051B (zh) * 2017-08-28 2020-10-23 广东顺德中山大学卡内基梅隆大学国际联合研究院 基于分布式宽带阻抗变换结构的Doherty功率放大器
EP3813253A1 (fr) * 2019-10-23 2021-04-28 Nxp B.V. Amplificateur de fréquence radio
US11482974B2 (en) 2019-10-23 2022-10-25 Nxp B.V. Radio-frequency amplifier

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