WO2013133215A1 - Doherty amplifier circuit - Google Patents

Doherty amplifier circuit Download PDF

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Publication number
WO2013133215A1
WO2013133215A1 PCT/JP2013/055857 JP2013055857W WO2013133215A1 WO 2013133215 A1 WO2013133215 A1 WO 2013133215A1 JP 2013055857 W JP2013055857 W JP 2013055857W WO 2013133215 A1 WO2013133215 A1 WO 2013133215A1
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WO
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Prior art keywords
doherty amplifier
circuit
matching circuit
amplifier circuit
peak
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PCT/JP2013/055857
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French (fr)
Japanese (ja)
Inventor
洋一郎 高山
本城　和彦
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国立大学法人 電気通信大学
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Publication of WO2013133215A1 publication Critical patent/WO2013133215A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/423—Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier

Definitions

  • the present invention relates to a Doherty amplifier circuit, and more particularly to a Doherty amplifier circuit whose operation mode is switched according to the strength of an input signal.
  • Doherty amplifiers are expected to be power amplifiers that meet these requirements, and their research and development are being conducted by many research institutions.
  • the characteristic of the Doherty amplifier is that the signal input level is relatively low and the state of saturation amplification is not reached, that is, the power efficiency in a state where a large back-off is taken is larger than amplifiers of other systems. Since such characteristics are extremely suitable as a power amplifier for the communication system described above, attention is focused on Doherty amplifiers.
  • the Doherty amplifier was conceived by Doherty in 1936 as described in Non-Patent Document 1.
  • Doherty has proposed a parallel connection load method and a series connection load method.
  • FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1A will be described.
  • the parallel connection load type Doherty amplifier circuit shown in FIG. 1A includes a first vacuum tube T1, a second vacuum tube T2, a parallel connection load LP, and an impedance inverting circuit IIN.
  • the connection relationship of the components of the parallel connection load type Doherty amplifier shown in FIG. 1A will be described.
  • the first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in parallel. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
  • FIG. 1B is a circuit diagram showing the configuration of a serial connection load type Doherty amplifier circuit according to the prior art. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1B will be described.
  • the serial connection load type Doherty amplifier circuit shown in FIG. 1B includes a first vacuum tube T1, a second vacuum tube T2, a serial connection load LS, and an impedance inverting circuit IIN.
  • the connection relationship of the components of the serial connection load type Doherty amplifier shown in FIG. 1B will be described.
  • the first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in series. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
  • FIG. 1C is a circuit diagram in a case where the parallel-connected load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power source assuming a transistor. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described.
  • the parallel connected load type Doherty amplifier circuit shown in FIG. 1C includes a first ideal current source I1, a second ideal current source I2, a parallel connected load LP, and a quarter wavelength line QW. Yes.
  • the connection relationship of the components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described.
  • the first ideal current source I1, the second ideal current source I2, and the parallel connection load LP are connected in parallel.
  • the quarter-wave line QW is connected in series between the first ideal current source I1 and the second ideal current source I2.
  • FIG. 1D is a circuit diagram in the case where the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power source assuming a transistor. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described. 1D includes a first ideal voltage source V1, a second ideal voltage source V2, a series connection load LS, and a quarter wavelength line QW. Yes.
  • the connection relationship of the components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described.
  • the first ideal voltage source V1, the second ideal voltage source V2, the series connection load LS, and the quarter wavelength line QW are connected in series.
  • the first vacuum tube T1 shown in FIGS. 1A and 1B, the first ideal current source I1 shown in FIG. 1C, and the first ideal voltage source V1 shown in FIG. 1D are all carriers.
  • the carrier amplifier is an amplifier having an operation corresponding to class AB to class B or equivalent to them, and amplifies the input signal if it is below a predetermined threshold, and saturates if it is above the predetermined threshold. It will be in the output state.
  • the second vacuum tube T2 shown in FIGS. 1A and 1B, the second ideal current source I2 shown in FIG. 1C, and the second ideal voltage source V2 shown in FIG. Functions as a peak amplifier.
  • the peak amplifier is an amplifier operating in the class B to class C or equivalent thereto, and is turned off when the intensity of the input signal is not more than a predetermined threshold, and if it is not less than the predetermined threshold, Is to amplify.
  • the threshold value of the peak amplifier is set to the same value as the threshold value of the carrier amplifier.
  • the quarter wavelength line QW shown in FIG. 1C and FIG. 1D is a transmission line having a length of almost a quarter of the wavelength of the input signal, and performs impedance conversion.
  • the impedance inverting circuit IIN shown in FIGS. 1A and 1B functions as the quarter wavelength line QW shown in FIGS. 1C and 1D.
  • the input signal is bisected by a distribution circuit, one being fed to the carrier amplifier and the other being fed to the peak amplifier via a line that is approximately a quarter wavelength of the input signal.
  • the Connected to the output section of the carrier amplifier is an impedance conversion circuit composed of a line having a quarter wavelength of the input signal.
  • the output signal of the carrier amplifier and the output signal of the peak amplifier output via the impedance conversion circuit and the output signal of the peak amplifier are directly coupled to obtain an amplified signal at the load.
  • the power of the input signal increases, and when the carrier amplifier reaches a state close to saturation output, the output of the peak amplifier rises. At this time, the power efficiency of the carrier amplifier is maximized, and this is ideally approximately 78% in an operation close to class B. As the power of the input signal further increases, the output power of both amplifiers is taken from the common load.
  • the carrier amplifier When increasing the power of the input signal, first, the carrier amplifier performs an amplification operation to dominate the amplification characteristic until the peak amplifier rises. The peak amplifier then rises at the input signal power at which the carrier amplifier reaches its maximum power efficiency. Furthermore, the output power and power efficiency are substantially maintained as the input signal increases.
  • FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FET field effect transistor
  • 2A and 2B each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier-side input impedance matching circuit IMNC.
  • the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases.
  • the output of the carrier transistor TC is supplied to the parallel connection load LP via the carrier side output impedance matching circuit OMNC.
  • the output of the peak transistor TP is also supplied to the parallel connection load LP via the peak side output impedance matching circuit OMNP and the transmission line TL.
  • the quarter wavelength line QW is arranged between the carrier side output impedance matching circuit OMNC and the parallel connection load LP in the normal type Doherty amplifier circuit of FIG. 2A, whereas the reverse type Doherty of FIG. In the amplifier circuit, it is arranged between the peak side output impedance matching circuit OMNP and the parallel connection load LP.
  • the phase adjustment line PL is also arranged between the distribution circuit DC and the peak transistor TP in the normal type Doherty amplification circuit of FIG. 2A, whereas the distribution circuit DC and the carrier are arranged in the reverse type Doherty amplification circuit of FIG. 2B. Arranged between the transistors TC.
  • FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FET field effect transistor
  • FIG. 2C and FIG. 2D each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier side input impedance matching circuit IMNC.
  • the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases.
  • the output of the carrier transistor TC is supplied to one end of the balanced port of the balun B through the carrier side output impedance matching circuit OMNC.
  • the output of the peak transistor TP is also supplied to the other end of the balanced port of the balun B via the peak side output impedance matching circuit OMNP and the transmission line TL.
  • the unbalanced port of the balun B is connected to the series connection load LS.
  • the transfer adjustment line PL is disposed between the distribution circuit DC and the peak transistor TP.
  • the quarter wavelength line QW is arranged between the balun B and the peak-side output impedance matching circuit OMNP in the normal type Doherty amplifier circuit of FIG. 2C, whereas the inverted Doherty amplifier circuit of FIG. Then, it is arranged between the balun B and the carrier side output impedance matching circuit OMNC.
  • a quarter-wave line functioning as an impedance conversion circuit is used as an important component.
  • the quarter-wave line occupies a large area in the Doherty amplifier circuit, and also causes a narrowing of the amplification frequency band and output power loss in terms of characteristics.
  • the quarter-wave line can also be constituted by a lumped element circuit.
  • An object of the present invention is to provide an ultra-high frequency Doherty power amplifier having a novel configuration that integrates a normal type and an inverted type without using a quarter-wave line as an impedance conversion circuit, eliminating the disadvantages of the prior art. It is in.
  • the operation mode is switched between the first amplification mode and the second amplification mode according to the strength of the input signal.
  • the Doherty amplifier circuit includes an input unit (I), a first amplifier (TC), a second amplifier (TP), a first matching circuit (OMNC), an output unit (O), and a second matching circuit ( OMNP) and a line (TL).
  • the input unit (I) distributes the input signal into two.
  • the first amplifier (TC) amplifies one of the input signals in the first amplification mode, and enters a saturated output state in the second amplification mode.
  • the second amplifier (TP) is turned off in the first amplification mode, and amplifies the other of the input signals in the second amplification mode.
  • the first matching circuit (OMNC) is connected to the subsequent stage of the first amplifier (TC).
  • the output unit (O) is connected to the subsequent stage of the first matching circuit (OMNC).
  • the second matching circuit (OMNP) is connected to the subsequent stage of the second amplifier (TP).
  • the line (TL) is connected between the output unit (O) and the output unit of the second matching circuit (OMNP).
  • the line (TL) has a length shorter than a quarter wavelength of the input signal.
  • the first matching circuit (OMNC) has four independent parameters. Here, the four independent parameters are designed and adjusted so as to satisfy the output impedance matching in both the first amplification mode and the second amplification mode.
  • the Doherty amplifier circuit according to the present invention does not have a quarter-wave line, its size can be greatly reduced.
  • FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art.
  • FIG. 1B is a circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the prior art.
  • FIG. 1C is a circuit diagram in the case where the parallel connection load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power supply.
  • FIG. 1D is a circuit diagram when the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power supply.
  • FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FET field effect transistor
  • FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type.
  • FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
  • FIG. 3A is a block circuit diagram schematically showing a basic form of the Doherty amplifier circuit according to the present invention.
  • FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 3C is a block circuit diagram showing a configuration of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4A is a block circuit diagram showing an output impedance in a peak amplifying unit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4A is a block circuit diagram showing an output impedance in a peak amplifying unit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the parallel connection load type Doherty amplifier
  • FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the low power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6A is a circuit diagram showing a configuration example of a carrier side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6B is a circuit diagram showing a configuration example of a peak-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 6C is a circuit diagram illustrating another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 7A is a circuit diagram showing another configuration example of the carrier-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • FIG. 8A is a block circuit diagram schematically showing a basic form of a serial connection load type Doherty amplifier circuit according to a second embodiment of the present invention.
  • FIG. 8B is a block circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 9A is a block circuit diagram showing an output impedance in a peak amplifying unit of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 10A is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the low power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 10B is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • FIG. 11B is a circuit diagram illustrating a specific configuration example of the peak-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the present invention provides a Doherty amplifier circuit that does not use a quarter-wave line as an impedance conversion circuit, which is provided as a basic constituent circuit element in a Doherty amplifier circuit according to the prior art.
  • the basic principle of the present invention is based on the following two points.
  • the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the output parallel coupling terminal.
  • the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the combined terminal of the output balun.
  • an ultra-high frequency power amplifier configured using transistors includes an input impedance matching circuit and an output impedance matching circuit.
  • FIG. 3A is a block circuit diagram schematically showing the basic form of the Doherty amplifier circuit according to the present invention.
  • the Doherty amplifier circuit illustrated in FIG. 3A includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the carrier amplification section C and the peak amplification section P are connected in parallel or in series at the input section I and the output section O.
  • the input unit I inputs an input signal and distributes it into two, supplies one to the carrier amplification unit C, and supplies the other to the peak amplification unit P.
  • the carrier amplifier C amplifies one of the distributed input signals, and is designed to be in a saturated output state when the intensity of the input signal is equal to or higher than a predetermined threshold. Further, the output part of the carrier amplifier C is designed so that impedance matching is achieved with respect to the output part O that is the connection destination.
  • the peak amplifying unit P amplifies the other one of the distributed input signals, and is designed to be turned off when the intensity of the input signal is a predetermined threshold value or less. Moreover, the output part of the peak amplification part P is designed so that impedance matching is taken with respect to the output part O which is a connection destination. Note that the threshold value related to the peak amplification unit P is preferably the same value as the threshold value related to the saturation output state of the carrier amplification unit C.
  • the output unit O is designed to synthesize the output of the carrier amplification unit C and the output of the peak amplification unit P in parallel or in series.
  • FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the parallel connection load type Doherty amplification circuit shown in FIG. 3B includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LP. And an aggregate OO.
  • These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
  • the output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC.
  • the output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP.
  • the aggregate OO includes a line TL (not shown) and a parallel connection load LP.
  • FIG. 3C is a block circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • a configuration example of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention will be described in more detail than FIG. 3B using the block circuit diagram shown in FIG. 3C.
  • the parallel-connected load type Doherty amplifier circuit illustrated in FIG. 3C includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the input section I shown in FIG. 3C includes a distribution circuit DC and a phase adjustment line PL.
  • the carrier amplifying unit C shown in FIG. 3C includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC.
  • the peak amplifier P shown in FIG. 3C includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP.
  • the output unit O illustrated in FIG. 3C includes a transmission line TL and is connected to a parallel connection load LP.
  • One output portion of the distribution circuit DC is connected to one end of the phase adjustment line PL.
  • the other end of the phase adjustment line PL is connected to the input part of the carrier side input impedance matching circuit IMNC.
  • the output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC.
  • the drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC.
  • the source of the carrier transistor TC is grounded.
  • the output part of the carrier side output impedance matching circuit OMNC is commonly connected to one end of the transmission line TL and one end of the parallel connection load LP.
  • the other end of the parallel connection load LP is grounded.
  • the other output section of the distribution circuit DC is connected to the input section of the peak side input impedance matching circuit IMNP.
  • the output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP.
  • the drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP.
  • the source of the peak transistor TP is grounded.
  • the output part of the peak side output impedance matching circuit OMNP is connected to the other end of the transmission line TL.
  • the quarter-wave line QW required in the parallel-connected load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is replaced by the parallel according to the first embodiment of the present invention shown in FIG. 3C. Note that it is not used in a connected load Doherty amplifier.
  • FIG. 4A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • 4A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL not shown in FIG. 3B.
  • the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in series in this order.
  • FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the first impedance ZP1 shown in FIG. 4B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 4A when the intensity of the input signal is less than the threshold value of the peak amplifier.
  • the first impedance ZP1 is located in the upper half of the Smith chart shown in FIG. 4B, that is, is inductive.
  • the second impedance ZP2 shown in FIG. 4B indicates the output impedance of the transmission line TL shown in FIG. 4A.
  • the second impedance ZP2 is located near the right end of the Smith chart shown in FIG. 4B, that is, an impedance close to opening.
  • the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
  • FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the block circuit diagram shown in FIG. 5A, the carrier transistor TC, and a carrier-side output impedance matching circuit OMNC, and the load LP L, are connected in cascade.
  • Z optL shown in FIG. 5A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents.
  • Load LP L is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier transistor TC and a carrier-side output impedance matching circuit OMNC, and the load LP H, they are connected in cascade.
  • ZoptH shown in FIG. 5B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C becoming saturated. Represents impedance.
  • Load LP H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • the impedance of the load LP L in the low power amplification mode shown in FIG. 5A is half of the impedance of the load LP H in the gradient power amplification mode shown in FIG. 5B. . That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
  • the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
  • FIG. 6A is a circuit diagram showing a configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 6A includes a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2.
  • the first inductor L1 and the second inductor L2 are connected in series between the input part and the output part of the carrier-side output impedance matching circuit OMNC.
  • One end of the first capacitor C1 is commonly connected to the first inductor L1 and the second inductor L2, and the other end is grounded.
  • One end of the second capacitor C2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L2, and the other end is grounded.
  • the first and second inductors L1 and L2 are connected in series, and the first and second capacitors C1 and C2 are connected in parallel.
  • the Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L1 and L2 shown in FIG. 6A and the capacitance in each of the two capacitors C1 and C2. The inventor has confirmed this through simulation analysis and experiments.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 6B or FIG. 6C, for example.
  • FIG. 6B is a circuit diagram showing a configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 6B includes an inductor L3 and a capacitor C3.
  • the inductor L3 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP.
  • One end of the capacitor C3 is connected to the output portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded.
  • the inductor L3 is connected in series, and the capacitor C3 is connected in parallel.
  • FIG. 6C is a circuit diagram showing another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 6C includes a first inductor L4, a second inductor L5, a first capacitor C4, and a second capacitor C5. Is the same as that in the case of the carrier side output impedance matching circuit OMNC shown in FIG. 6A, and further detailed description is omitted.
  • FIG. 7A is a circuit diagram showing another configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 7A includes a first transmission line TL1, a second transmission line TL2, a first stub S1, and a second stub S2.
  • the first transmission line TL1 and the second transmission line TL2 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC.
  • the first stub S1 is commonly connected to the first transmission line TL1 and the second transmission line TL2.
  • the second stub S2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second transmission line TL2.
  • the first and second transmission lines TL1 and TL2 are connected in series, and the first and second stubs S1 and S2 are connected in parallel.
  • the Doherty amplifier circuit according to the present invention is normal.
  • the inventor has confirmed through experiments that it works.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 7B, for example.
  • FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 7B includes a transmission line TL3 and a stub S3.
  • the transmission line TL3 is connected between the input unit and the output unit of the peak side output impedance matching circuit OMNP.
  • the stub S3 is commonly connected to the output part of the peak-side output impedance matching circuit OMNP and the transmission line TL3.
  • the transmission line TL3 is connected in series, and the stub S3 is connected in parallel.
  • the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment may be configured using a lumped constant element or a distributed constant element. good. Furthermore, it goes without saying that a lumped constant element and a distributed constant element may be combined.
  • FIG. 8A is a block circuit diagram schematically showing a basic form of a series-connected load type Doherty amplifier circuit according to a second embodiment of the present invention.
  • the serial connection load type Doherty amplification circuit shown in FIG. 8A includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LS. And an aggregate OO.
  • These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
  • the output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC.
  • the output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP.
  • the aggregate OO includes a line TL (not shown) and a series connection load LS.
  • FIG. 8B is a block circuit diagram showing a configuration of a series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • a configuration example of the series-connected load-type Doherty amplifier circuit according to the second embodiment of the present invention will be described in more detail than FIG. 8A, using the block circuit diagram shown in FIG. 8B.
  • the serial connection load type Doherty amplifier circuit shown in FIG. 8B includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
  • the input unit I shown in FIG. 8B includes a distribution circuit DC and a phase adjustment line PL.
  • the carrier amplification unit C shown in FIG. 8B includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC.
  • the peak amplifier P shown in FIG. 8B includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP.
  • the output unit O illustrated in FIG. 8B includes a transmission line TL and a balun B, and is connected to a series connection load LS.
  • the balun B is not particularly limited, and any of a transmission line balun, a transformer balun, a lumped constant balun, a phase inversion balun, and other baluns may be used.
  • One output section in the distribution circuit DC is connected to the input section of the carrier side input impedance matching circuit IMNC.
  • the output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC.
  • the drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC.
  • the source of the carrier transistor TC is grounded.
  • the output part of the carrier side output impedance matching circuit OMNC is connected to one end of the balanced port of the balun B. In the series connection load LS, one end is connected to one end of the unbalanced port of the balun B, and the other end is directly grounded. The other end of the unbalanced port of the balun B is grounded.
  • the other output section of the distribution circuit DC is connected to one end of the phase adjustment line PL.
  • the other end of the phase adjustment line PL is connected to the input part of the peak side input impedance matching circuit IMNP.
  • the output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP.
  • the drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP.
  • the source of the peak transistor TP is grounded.
  • the output part of the peak-side output impedance matching circuit OMNP is connected to the other end of the balanced port of the balun B via the transmission line TL.
  • the quarter wavelength line QW required in the parallel connection load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is converted into the series according to the second embodiment of the invention shown in FIG. 8B. Note that it is not used in a connected load Doherty amplifier.
  • FIG. 9A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • 9A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL that is not shown in FIG. 3B.
  • the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in cascade in this order.
  • FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the first impedance ZS1 shown in FIG. 9B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 9A when the intensity of the input signal is less than the threshold value of the peak amplifier.
  • the first impedance ZS1 is located in the lower half of the Smith chart shown in FIG. 9B, that is, is capacitive.
  • the second impedance ZS2 illustrated in FIG. 9B indicates the output impedance of the transmission line TL illustrated in FIG. 9A.
  • the second impedance ZS2 is located near the right end of the Smith chart shown in FIG. 9B, that is, an impedance close to a short circuit.
  • the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
  • FIG. 10A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • a carrier transistor TC a carrier-side output impedance matching circuit OMNC, and a load LS L are connected in cascade.
  • Z optL shown in FIG. 10A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents.
  • the load LS L is a load viewed from the carrier-side output impedance matching circuit OMNC.
  • FIG. 10B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the carrier transistor TC and a carrier-side output impedance matching circuit OMNC, and a load LS H, they are connected in cascade.
  • ZoptH shown in FIG. 10B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C being saturated. Represents impedance.
  • Load LS H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
  • the impedance of the load LS L in the low power amplification mode shown in FIG. 10A at twice the impedance of the load LS H in the high power amplification mode shown in FIG. 10B is there. That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
  • the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
  • FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit OMNC of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the carrier-side output impedance matching circuit OMNC illustrated in FIG. 11A includes a first inductor L6, a second inductor L7, a first capacitor C6, and a second capacitor C7.
  • the first inductor L6 and the second inductor L7 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC.
  • One end of the first capacitor C6 is commonly connected to the first inductor L6 and the second inductor L7, and the other end is grounded.
  • One end of the second capacitor C7 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L7, and the other end is grounded.
  • the first and second inductors L6 and L7 are connected in series, and the first and second capacitors C6 and C7 are connected in parallel.
  • the Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L6 and L7 shown in FIG. 11A and the capacitance in each of the two capacitors C6 and C7. The inventor has confirmed this through simulation analysis and experiments.
  • the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 11B, for example.
  • FIG. 11B is a circuit diagram showing a specific configuration example of the peak-side output impedance matching circuit OMNP of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
  • the peak-side output impedance matching circuit OMNP illustrated in FIG. 11B includes an inductor L8 and a capacitor C8.
  • the inductor L8 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP.
  • One end of the capacitor C8 is connected to the input portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded.
  • the inductor L8 is connected in series, and the capacitor C8 is connected in parallel.
  • the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment can be configured using lumped constant elements, but may be configured using distributed constant elements. Needless to say, a lumped constant element and a distributed constant element may be combined.

Abstract

In this Doherty amplifier circuit, the actuation mode switches between the first amplification mode and the second amplification mode according to the strength of the input signal. This Doherty amplifier circuit is provided with an input unit, a first amplifier, a second amplifier, a first matching circuit, an output unit, and a second matching circuit. The input unit divides the input signal into two. The first amplifier amplifies one of the input signals in the first amplification mode, and is in a saturated output state in the second amplification mode. The second amplifier is in an off state in the first amplification mode, and amplifies the other input signal in the second amplification mode. The first matching circuit is connected to the stage subsequent to the first amplifier. The output unit is connected to the stage subsequent to the first matching circuit. The second matching circuit is connected to the stage subsequent to the second amplifier. The output unit is connected to the stage subsequent to the second matching circuit, and provided with a wire that is shorter than a quarter of the wavelength of the input signal. The first matching circuit is provided with at least four independent parameters adjusted in terms of design so as to satisfy the output impedance matching, both in the first amplification mode and in the second amplification mode.

Description

ドハティ増幅回路Doherty amplifier circuit
　本発明は、ドハティ増幅回路に係り、特に、入力信号の強度に応じて動作モードが切り替わるドハティ増幅回路に係る。 The present invention relates to a Doherty amplifier circuit, and more particularly to a Doherty amplifier circuit whose operation mode is switched according to the strength of an input signal.
　無線通信システムの高度化に伴い、送信電力制御技術や、多値変調方式や、多チャンネル共通増幅技術のように、様々な新規技術が進展している。これらの技術のキーデバイスとして、送信電力増幅器が用いられており、その電力効率およびひずみ特性への要求は厳しさを増している。 With the advancement of wireless communication systems, various new technologies such as transmission power control technology, multi-level modulation method, and multi-channel common amplification technology have been developed. As a key device of these technologies, transmission power amplifiers are used, and demands for power efficiency and distortion characteristics are becoming stricter.
　ドハティ増幅器は、このような要求を満たす電力増幅器として期待されており、その研究開発が多くの研究機関で行われている。ドハティ増幅器の特徴は、信号入力レベルが比較的低く、飽和増幅の状態に達しない、すなわちバックオフを大きく取った状態での電力効率が、他の方式による増幅器と比べて大きいことにある。このような特性は、先に述べた通信方式の電力増幅器として極めて適しているため、ドハティ増幅器に注目が集まっている。 Doherty amplifiers are expected to be power amplifiers that meet these requirements, and their research and development are being conducted by many research institutions. The characteristic of the Doherty amplifier is that the signal input level is relatively low and the state of saturation amplification is not reached, that is, the power efficiency in a state where a large back-off is taken is larger than amplifiers of other systems. Since such characteristics are extremely suitable as a power amplifier for the communication system described above, attention is focused on Doherty amplifiers.
　ドハティ増幅器は、非特許文献１に記載されているように、１９３６年にドハティ（Ｄｏｈｅｒｔｙ）氏によって考案された。ここで、ドハティ氏は、並列接続負荷方式と、直列接続負荷方式とを提案している。 The Doherty amplifier was conceived by Doherty in 1936 as described in Non-Patent Document 1. Here, Doherty has proposed a parallel connection load method and a series connection load method.
　図１Ａは、従来技術による並列接続負荷型ドハティ増幅回路の構成を示す回路図である。図１Ａに示した並列接続負荷型ドハティ増幅回路の構成要素について説明する。図１Ａに示した並列接続負荷型ドハティ増幅回路は、第１の真空管Ｔ１と、第２の真空管Ｔ２と、並列接続負荷ＬＰと、インピーダンス反転回路ＩＩＮとを含んでいる。 FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1A will be described. The parallel connection load type Doherty amplifier circuit shown in FIG. 1A includes a first vacuum tube T1, a second vacuum tube T2, a parallel connection load LP, and an impedance inverting circuit IIN.
図１Ａに示した並列接続負荷型ドハティ増幅器の構成要素の接続関係について説明する。第１の真空管Ｔ１と、第２の真空管Ｔ２と、並列接続負荷ＬＰとは、並列に接続されている。また、第１の真空管Ｔ１と、第２の真空管Ｔ２との間には、インピーダンス反転回路ＩＩＮが接続されている。 The connection relationship of the components of the parallel connection load type Doherty amplifier shown in FIG. 1A will be described. The first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in parallel. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
　図１Ｂは、従来技術による直列接続負荷型ドハティ増幅回路の構成を示す回路図である。図１Ｂに示した直列接続負荷型ドハティ増幅回路の構成要素について説明する。図１Ｂに示した直列接続負荷型ドハティ増幅回路は、第１の真空管Ｔ１と、第２の真空管Ｔ２と、直列接続負荷ＬＳと、インピーダンス反転回路ＩＩＮとを含んでいる。 FIG. 1B is a circuit diagram showing the configuration of a serial connection load type Doherty amplifier circuit according to the prior art. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1B will be described. The serial connection load type Doherty amplifier circuit shown in FIG. 1B includes a first vacuum tube T1, a second vacuum tube T2, a serial connection load LS, and an impedance inverting circuit IIN.
図１Ｂに示した直列接続負荷型ドハティ増幅器の構成要素の接続関係について説明する。第１の真空管Ｔ１と、第２の真空管Ｔ２と、並列接続負荷ＬＰとは、直列に接続されている。また、第１の真空管Ｔ１と、第２の真空管Ｔ２との間には、インピーダンス反転回路ＩＩＮが接続されている。 The connection relationship of the components of the serial connection load type Doherty amplifier shown in FIG. 1B will be described. The first vacuum tube T1, the second vacuum tube T2, and the parallel connection load LP are connected in series. Further, an impedance inverting circuit IIN is connected between the first vacuum tube T1 and the second vacuum tube T2.
　図１Ｃは、図１Ａに示した並列接続負荷型ドハティ増幅回路を、トランジスタを想定して理想電源を用いて構成した場合の回路図である。図１Ｃに示した並列接続負荷型ドハティ増幅回路の構成要素について説明する。図１Ｃに示した並列接続負荷型ドハティ増幅回路は、第１の理想電流源Ｉ１と、第２の理想電流源Ｉ２と、並列接続負荷ＬＰと、４分の１波長線路ＱＷとを具備している。 FIG. 1C is a circuit diagram in a case where the parallel-connected load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power source assuming a transistor. The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described. The parallel connected load type Doherty amplifier circuit shown in FIG. 1C includes a first ideal current source I1, a second ideal current source I2, a parallel connected load LP, and a quarter wavelength line QW. Yes.
　図１Ｃに示した並列接続負荷型ドハティ増幅回路の構成要素の接続関係について説明する。第１の理想電流源Ｉ１と、第２の理想電流源Ｉ２と、並列接続負荷ＬＰとは、並列に接続されている。４分の１波長線路ＱＷは、第１の理想電流源Ｉ１と、第２の理想電流源Ｉ２との間に直列に接続されている。 The connection relationship of the components of the parallel connection load type Doherty amplifier circuit shown in FIG. 1C will be described. The first ideal current source I1, the second ideal current source I2, and the parallel connection load LP are connected in parallel. The quarter-wave line QW is connected in series between the first ideal current source I1 and the second ideal current source I2.
　図１Ｄは、図１Ｂに示した直列接続負荷型ドハティ増幅回路を、トランジスタを想定して理想電源を用いて構成した場合の回路図である。図１Ｄに示した直列接続負荷型ドハティ増幅回路の構成要素について説明する。図１Ｄに示した直列接続負荷型ドハティ増幅回路は、第１の理想電圧源Ｖ１と、第２の理想電圧源Ｖ２と、直列接続負荷ＬＳと、４分の１波長線路ＱＷとを具備している。 FIG. 1D is a circuit diagram in the case where the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power source assuming a transistor. The components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described. 1D includes a first ideal voltage source V1, a second ideal voltage source V2, a series connection load LS, and a quarter wavelength line QW. Yes.
　図１Ｄに示した直列接続負荷型ドハティ増幅回路の構成要素の接続関係について説明する。第１の理想電圧源Ｖ１と、第２の理想電圧源Ｖ２と、直列接続負荷ＬＳと、４分の１波長線路ＱＷとは、直列に接続されている。 The connection relationship of the components of the serial connection load type Doherty amplifier circuit shown in FIG. 1D will be described. The first ideal voltage source V1, the second ideal voltage source V2, the series connection load LS, and the quarter wavelength line QW are connected in series.
　図１Ａ～図１Ｄに示した各種ドハティ増幅回路の動作について説明する。まず、図１Ａおよび図１Ｂに示した第１の真空管Ｔ１と、図１Ｃに示した第１の理想電流源Ｉ１と、図１Ｄに示した第１の理想電圧源Ｖ１とは、いずれも、キャリア増幅器として機能する。ここで、キャリア増幅器とは、ＡＢ級乃至Ｂ級あるいはこれらに相当する動作の増幅器であって、入力信号の強度が所定の閾値以下であればこれを増幅し、所定の閾値以上であれば飽和出力状態になるものである。 The operation of various Doherty amplifier circuits shown in FIGS. 1A to 1D will be described. First, the first vacuum tube T1 shown in FIGS. 1A and 1B, the first ideal current source I1 shown in FIG. 1C, and the first ideal voltage source V1 shown in FIG. 1D are all carriers. Functions as an amplifier. Here, the carrier amplifier is an amplifier having an operation corresponding to class AB to class B or equivalent to them, and amplifies the input signal if it is below a predetermined threshold, and saturates if it is above the predetermined threshold. It will be in the output state.
　同様に、図１Ａおよび図１Ｂに示した第２の真空管Ｔ２と、図１Ｃに示した第２の理想電流源Ｉ２と、図１Ｄに示した第２の理想電圧源Ｖ２とは、いずれも、ピーク増幅器として機能する。ここで、ピーク増幅器とは、Ｂ級乃至Ｃ級あるいはこれらに相当する動作の増幅器であって、入力信号の強度が所定の閾値以下であればオフ状態になり、所定の閾値以上であればこれを増幅するものである。なお、ピーク増幅器の閾値は、キャリア増幅器の閾値と同じ値に設定されているものである。 Similarly, the second vacuum tube T2 shown in FIGS. 1A and 1B, the second ideal current source I2 shown in FIG. 1C, and the second ideal voltage source V2 shown in FIG. Functions as a peak amplifier. Here, the peak amplifier is an amplifier operating in the class B to class C or equivalent thereto, and is turned off when the intensity of the input signal is not more than a predetermined threshold, and if it is not less than the predetermined threshold, Is to amplify. The threshold value of the peak amplifier is set to the same value as the threshold value of the carrier amplifier.
　次に、図１Ｃおよび図１Ｄに示した４分の１波長線路ＱＷは、入力信号の波長のほぼ４分の１の長さを有する伝送線路であって、インピーダンスの変換を行うものである。図１Ａおよび図１Ｂに示したインピーダンス反転回路ＩＩＮは、図１Ｃおよび図１Ｄに示した４分の１波長線路ＱＷの機能を果たすものである。 Next, the quarter wavelength line QW shown in FIG. 1C and FIG. 1D is a transmission line having a length of almost a quarter of the wavelength of the input signal, and performs impedance conversion. The impedance inverting circuit IIN shown in FIGS. 1A and 1B functions as the quarter wavelength line QW shown in FIGS. 1C and 1D.
　典型的な並列負荷接続方式によるドハティ増幅器では、入力信号は分配回路によって二分され、一方はキャリア増幅器に供給され、他方は入力信号のほぼ４分の１波長の線路を介してピーク増幅器に供給される。キャリア増幅器の出力部には、入力信号のほぼ４分の１波長の線路からなるインピーダンス変換回路が接続されている。このインピーダンス変換回路を介して出力されるキャリア増幅器の出力信号と、ピーク増幅器の出力信号とは、直接結合されることで、負荷において増幅後の信号が得られる。 In a Doherty amplifier with a typical parallel load connection scheme, the input signal is bisected by a distribution circuit, one being fed to the carrier amplifier and the other being fed to the peak amplifier via a line that is approximately a quarter wavelength of the input signal. The Connected to the output section of the carrier amplifier is an impedance conversion circuit composed of a line having a quarter wavelength of the input signal. The output signal of the carrier amplifier and the output signal of the peak amplifier output via the impedance conversion circuit and the output signal of the peak amplifier are directly coupled to obtain an amplified signal at the load.
　典型的なドハティ増幅器では、入力信号の電力が増大し、キャリア増幅器がほぼ飽和出力に近い状態に達するとき、ピーク増幅器の出力が立ち上がる。このとき、キャリア増幅器の電力効率は最大になっており、これはＢ級に近い動作で理想的にはほぼ７８％となる。入力信号の電力がさらに増大すると、両増幅器の出力電力が共通負荷から取り出される。 In a typical Doherty amplifier, the power of the input signal increases, and when the carrier amplifier reaches a state close to saturation output, the output of the peak amplifier rises. At this time, the power efficiency of the carrier amplifier is maximized, and this is ideally approximately 78% in an operation close to class B. As the power of the input signal further increases, the output power of both amplifiers is taken from the common load.
　言い換えれば、ドハティ増幅器では、以下のような特性が実現する。入力信号の電力を増やしていくとき、まず、ピーク増幅器が立ち上がるまではキャリア増幅器が増幅動作を行って増幅特性を支配する。次に、キャリア増幅器がそのほぼ最大電力効率に達する入力信号電力においてピーク増幅器が立ち上がる。さらに、入力信号の増加とともに出力電力および電力効率がほぼ維持される。 In other words, the following characteristics are realized in the Doherty amplifier. When increasing the power of the input signal, first, the carrier amplifier performs an amplification operation to dominate the amplification characteristic until the peak amplifier rises. The peak amplifier then rises at the input signal power at which the carrier amplifier reaches its maximum power efficiency. Furthermore, the output power and power efficiency are substantially maintained as the input signal increases.
　ドハティ増幅器は、その後も様々な改善がなされている。２００１年には、特許文献１（米国特許第６２６２６２９号明細書）に記載されているように、逆（Ｉｎｖｅｒｔｅｄ）ドハティ増幅器が提案されている。この方式では、インピーダンス変換用の４分の１波長線路が、ピーク増幅器の出力部に挿入されている。 The Doherty amplifier has been improved since then. In 2001, an inverted Doherty amplifier has been proposed as described in US Pat. No. 6,262,629. In this method, a quarter wavelength line for impedance conversion is inserted in the output section of the peak amplifier.
　まず、従来技術による超高周波並列接続負荷型ドハティ増幅回路における、通常型および逆型の違いについて説明する。図２Ａは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波並列接続負荷型ドハティ増幅回路を通常型で形成した場合の構成を示す回路図である。図２Ｂは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波並列接続負荷型ドハティ増幅回路を逆型で形成した場合の構成を示す回路図である。 First, the difference between the normal type and the reverse type in the conventional super-high frequency parallel connection load type Doherty amplifier circuit will be described. FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type. FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
　図２Ａおよび図２Ｂに示した超高周波並列接続負荷型ドハティ増幅回路は、いずれも、分配回路ＤＣと、位相調整線路ＰＬと、キャリアトランジスタＴＣと、ピークトランジスタＴＰと、キャリア側入力インピーダンス整合回路ＩＭＮＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、ピーク側入力インピーダンス整合回路ＩＭＮＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、４分の１波長線路ＱＷと、伝送線路ＴＬとを有している。 2A and 2B each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier-side input impedance matching circuit IMNC. A carrier-side output impedance matching circuit OMNC, a peak-side input impedance matching circuit IMNP, a peak-side output impedance matching circuit OMNP, a quarter wavelength line QW, and a transmission line TL.
　また、図２Ａおよび図２Ｂに示した並列接続負荷型ドハティ増幅回路では、いずれの場合も、分配回路ＤＣが入力信号を入力してキャリアトランジスタＴＣおよびピークトランジスタＴＰに分配する。キャリアトランジスタＴＣの出力は、キャリア側出力インピーダンス整合回路ＯＭＮＣを介して、並列接続負荷ＬＰに供給される。ピークトランジスタＴＰの出力は、ピーク側出力インピーダンス整合回路ＯＭＮＰおよび伝送線路ＴＬを介して、やはり並列接続負荷ＬＰに供給される。 2A and 2B, in any case, the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases. The output of the carrier transistor TC is supplied to the parallel connection load LP via the carrier side output impedance matching circuit OMNC. The output of the peak transistor TP is also supplied to the parallel connection load LP via the peak side output impedance matching circuit OMNP and the transmission line TL.
　しかし、４分の１波長線路ＱＷが、図２Ａの通常型ドハティ増幅回路ではキャリア側出力インピーダンス整合回路ＯＭＮＣおよび並列接続負荷ＬＰの間に配置されているのに対して、図２Ｂの逆型ドハティ増幅回路ではピーク側出力インピーダンス整合回路ＯＭＮＰおよび並列接続負荷ＬＰの間に配置されている。また、位相調整線路ＰＬも、図２Ａの通常型ドハティ増幅回路では分配回路ＤＣおよびピークトランジスタＴＰの間に配置されているのに対して、図２Ｂの逆型ドハティ増幅回路では分配回路ＤＣおよびキャリアトランジスタＴＣの間に配置されている。 However, the quarter wavelength line QW is arranged between the carrier side output impedance matching circuit OMNC and the parallel connection load LP in the normal type Doherty amplifier circuit of FIG. 2A, whereas the reverse type Doherty of FIG. In the amplifier circuit, it is arranged between the peak side output impedance matching circuit OMNP and the parallel connection load LP. The phase adjustment line PL is also arranged between the distribution circuit DC and the peak transistor TP in the normal type Doherty amplification circuit of FIG. 2A, whereas the distribution circuit DC and the carrier are arranged in the reverse type Doherty amplification circuit of FIG. 2B. Arranged between the transistors TC.
　次に、従来技術による超高周波直列接続負荷型ドハティ増幅回路における、通常型および逆型の違いについて説明する。図２Ｃは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波直列接続負荷型ドハティ増幅回路を通常型で形成した場合の構成を示す回路図である。図２Ｄは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波直列接続負荷型ドハティ増幅回路を逆型で形成した場合の構成を示す回路図である。 Next, the difference between the normal type and the reverse type in the conventional super-high frequency series-connected load type Doherty amplifier circuit will be described. FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type. FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type.
　図２Ｃおよび図２Ｄに示した超高周波直列接続負荷型ドハティ増幅回路は、いずれも、分配回路ＤＣと、位相調整線路ＰＬと、キャリアトランジスタＴＣと、ピークトランジスタＴＰと、キャリア側入力インピーダンス整合回路ＩＭＮＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、ピーク側入力インピーダンス整合回路ＩＭＮＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、４分の１波長線路ＱＷと、伝送線路ＴＬと、バランＢとを有している。 2C and FIG. 2D each include a distribution circuit DC, a phase adjustment line PL, a carrier transistor TC, a peak transistor TP, and a carrier side input impedance matching circuit IMNC. A carrier side output impedance matching circuit OMNC, a peak side input impedance matching circuit IMNP, a peak side output impedance matching circuit OMNP, a quarter wavelength line QW, a transmission line TL, and a balun B. Yes.
　また、図２Ｃおよび図２Ｄに示した直列接続負荷型ドハティ増幅回路では、いずれの場合も、分配回路ＤＣが入力信号を入力してキャリアトランジスタＴＣおよびピークトランジスタＴＰに分配する。キャリアトランジスタＴＣの出力は、キャリア側出力インピーダンス整合回路ＯＭＮＣを介して、バランＢの平衡ポートの一方の端部に供給される。ピークトランジスタＴＰの出力は、ピーク側出力インピーダンス整合回路ＯＭＮＰおよび伝送線路ＴＬを介して、やはりバランＢの平衡ポートの他方の端部に供給される。バランＢの不平衡ポートは、直列接続負荷ＬＳに接続されている。移送調節線路ＰＬは、分配回路ＤＣおよびピークトランジスタＴＰの間に配置されている。 2C and FIG. 2D, in any case, the distribution circuit DC receives the input signal and distributes it to the carrier transistor TC and the peak transistor TP in both cases. The output of the carrier transistor TC is supplied to one end of the balanced port of the balun B through the carrier side output impedance matching circuit OMNC. The output of the peak transistor TP is also supplied to the other end of the balanced port of the balun B via the peak side output impedance matching circuit OMNP and the transmission line TL. The unbalanced port of the balun B is connected to the series connection load LS. The transfer adjustment line PL is disposed between the distribution circuit DC and the peak transistor TP.
　しかし、４分の１波長線路ＱＷが、図２Ｃの通常型ドハティ増幅回路ではバランＢおよびピーク側出力インピーダンス整合回路ＯＭＮＰの間に配置されているのに対して、図２Ｂの逆型ドハティ増幅回路ではバランＢおよびキャリア側出力インピーダンス整合回路ＯＭＮＣの間に配置されている。 However, the quarter wavelength line QW is arranged between the balun B and the peak-side output impedance matching circuit OMNP in the normal type Doherty amplifier circuit of FIG. 2C, whereas the inverted Doherty amplifier circuit of FIG. Then, it is arranged between the balun B and the carrier side output impedance matching circuit OMNC.
米国特許第６２６２６２９号明細書US Pat. No. 6,262,629
　このように、従来技術によるドハティ増幅回路では、インピーダンス変換回路として機能する４分の１波長線路が重要な構成要素として用いられている。しかし、４分の１波長線路はドハティ増幅回路の中でも大きな面積を占めており、また、特性面でも増幅周波数帯の狭帯域化および出力電力損失の要因となっている。なお、４分の一波長線路は集中素子回路により構成することも可能である。 Thus, in the Doherty amplifier circuit according to the prior art, a quarter-wave line functioning as an impedance conversion circuit is used as an important component. However, the quarter-wave line occupies a large area in the Doherty amplifier circuit, and also causes a narrowing of the amplification frequency band and output power loss in terms of characteristics. Note that the quarter-wave line can also be constituted by a lumped element circuit.
　本発明の目的は、従来技術の欠点を除去した、インピーダンス変換回路としての４分の１波長線路を用いない、通常型および逆型を統合した新規な構成による超高周波ドハティ電力増幅器を提供することにある。 An object of the present invention is to provide an ultra-high frequency Doherty power amplifier having a novel configuration that integrates a normal type and an inverted type without using a quarter-wave line as an impedance conversion circuit, eliminating the disadvantages of the prior art. It is in.
　以下に、（発明を実施するための形態）で使用される番号を用いて、課題を解決するための手段を説明する。これらの番号は、（特許請求の範囲）の記載と（発明を実施するための形態）との対応関係を明らかにするために付加されたものである。ただし、それらの番号を、（特許請求の範囲）に記載されている発明の技術的範囲の解釈に用いてはならない。 Hereinafter, means for solving the problem will be described using the numbers used in the (form for carrying out the invention). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).
　本発明によるドハティ増幅回路は、入力信号の強度に応じて動作モードが第１増幅モードおよび第２増幅モードの間で切り替わる。このドハティ増幅回路は、入力部（Ｉ）と、第１増幅器（ＴＣ）と、第２増幅器（ＴＰ）と、第１整合回路（ＯＭＮＣ）と、出力部（Ｏ）と、第２整合回路（ＯＭＮＰ）と、線路（ＴＬ）とを具備する。ここで、入力部（Ｉ）は、入力信号を２つに分配する。第１増幅器（ＴＣ）は、第１増幅モードにおいては入力信号の一方を増幅し、第２増幅モードにおいては飽和出力状態になる。第２増幅器（ＴＰ）は、第１増幅モードにおいてはオフ状態になり、第２増幅モードにおいては入力信号の他方を増幅する。第１整合回路（ＯＭＮＣ）は、第１増幅器（ＴＣ）の後段に接続されている。出力部（Ｏ）は、第１整合回路（ＯＭＮＣ）の後段に接続されている。第２整合回路（ＯＭＮＰ）は、第２増幅器（ＴＰ）の後段に接続されている。線路（ＴＬ）は、出力部（Ｏ）と、第２整合回路（ＯＭＮＰ）の出力部との間に接続されている。線路（ＴＬ）は、入力信号の四分の一波長より短い長さを具備する。第１整合回路（ＯＭＮＣ）は、４つの独立パラメータを具備する。ここで、４つの独立パラメータは、第１増幅モードにおいても、第２増幅モードにおいても、出力インピーダンス整合を満足するように設計調整されている。 In the Doherty amplifier circuit according to the present invention, the operation mode is switched between the first amplification mode and the second amplification mode according to the strength of the input signal. The Doherty amplifier circuit includes an input unit (I), a first amplifier (TC), a second amplifier (TP), a first matching circuit (OMNC), an output unit (O), and a second matching circuit ( OMNP) and a line (TL). Here, the input unit (I) distributes the input signal into two. The first amplifier (TC) amplifies one of the input signals in the first amplification mode, and enters a saturated output state in the second amplification mode. The second amplifier (TP) is turned off in the first amplification mode, and amplifies the other of the input signals in the second amplification mode. The first matching circuit (OMNC) is connected to the subsequent stage of the first amplifier (TC). The output unit (O) is connected to the subsequent stage of the first matching circuit (OMNC). The second matching circuit (OMNP) is connected to the subsequent stage of the second amplifier (TP). The line (TL) is connected between the output unit (O) and the output unit of the second matching circuit (OMNP). The line (TL) has a length shorter than a quarter wavelength of the input signal. The first matching circuit (OMNC) has four independent parameters. Here, the four independent parameters are designed and adjusted so as to satisfy the output impedance matching in both the first amplification mode and the second amplification mode.
　本発明によるドハティ増幅回路は、４分の１波長線路が無いので、そのサイズを大幅に縮小することが可能となっている。 Since the Doherty amplifier circuit according to the present invention does not have a quarter-wave line, its size can be greatly reduced.
図１Ａは、従来技術による並列接続負荷型ドハティ増幅回路の構成を示す回路図である。FIG. 1A is a circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the prior art. 図１Ｂは、従来技術による直列接続負荷型ドハティ増幅回路の構成を示す回路図である。FIG. 1B is a circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the prior art. 図１Ｃは、図１Ａに示した並列接続負荷型ドハティ増幅回路を、理想電源を用いて構成した場合の回路図である。FIG. 1C is a circuit diagram in the case where the parallel connection load type Doherty amplifier circuit shown in FIG. 1A is configured using an ideal power supply. 図１Ｄは、図１Ｂに示した直列接続負荷型ドハティ増幅回路を、理想電源を用いて構成した場合の回路図である。FIG. 1D is a circuit diagram when the series-connected load type Doherty amplifier circuit shown in FIG. 1B is configured using an ideal power supply. 図２Ａは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波並列接続負荷型ドハティ増幅回路を通常型で形成した場合の構成を示す回路図である。FIG. 2A is a circuit diagram showing a configuration in the case where a conventional super-high frequency parallel connection load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type. 図２Ｂは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波並列接続負荷型ドハティ増幅回路を逆型で形成した場合の構成を示す回路図である。FIG. 2B is a circuit diagram showing a configuration in the case where an ultra-high frequency parallel connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type. 図２Ｃは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波直列接続負荷型ドハティ増幅回路を通常型で形成した場合の構成を示す回路図である。FIG. 2C is a circuit diagram showing a configuration in the case where a conventional super-high frequency series-connected load type Doherty amplifier circuit using a field effect transistor (FET) is formed in a normal type. 図２Ｄは、電界効果トランジスタ（ＦＥＴ）による従来技術による超高周波直列接続負荷型ドハティ増幅回路を逆型で形成した場合の構成を示す回路図である。FIG. 2D is a circuit diagram showing a configuration in a case where an ultrahigh frequency series connection load type Doherty amplifier circuit according to the prior art using a field effect transistor (FET) is formed in an inverted type. 図３Ａは、本発明によるドハティ増幅回路の基本形を概略的に示すブロック回路図である。FIG. 3A is a block circuit diagram schematically showing a basic form of the Doherty amplifier circuit according to the present invention. 図３Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の基本形を概略的に示すブロック回路図である。FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図３Ｃは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の構成を示すブロック回路図である。FIG. 3C is a block circuit diagram showing a configuration of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図４Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路のピーク増幅部における出力インピーダンスを示すブロック回路図である。FIG. 4A is a block circuit diagram showing an output impedance in a peak amplifying unit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図４Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路でピーク増幅部に行うインピーダンス変換を示すスミスチャートである。FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図５Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、低電力増幅モードにおけるキャリア増幅部の入出力インピーダンス整合条件を示すブロック回路図である。FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the low power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention. 図５Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、高電力増幅モードにおけるキャリア増幅部の入出力インピーダンス整合条件を示すブロック回路図である。FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention. 図６Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路の構成例を示す回路図である。FIG. 6A is a circuit diagram showing a configuration example of a carrier side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図６Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路の構成例を示す回路図である。FIG. 6B is a circuit diagram showing a configuration example of a peak-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図６Ｃは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路の他の構成例を示す回路図である。FIG. 6C is a circuit diagram illustrating another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention. 図７Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路の他の構成例を示す回路図である。FIG. 7A is a circuit diagram showing another configuration example of the carrier-side output impedance matching circuit of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 図７Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路のさらに他の構成例を示す回路図である。FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention. 図８Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の基本形を概略的に示すブロック回路図である。FIG. 8A is a block circuit diagram schematically showing a basic form of a serial connection load type Doherty amplifier circuit according to a second embodiment of the present invention. 図８Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の構成を示すブロック回路図である。FIG. 8B is a block circuit diagram showing a configuration of a serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. 図９Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路のピーク増幅部における出力インピーダンスを示すブロック回路図である。FIG. 9A is a block circuit diagram showing an output impedance in a peak amplifying unit of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. 図９Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路でピーク増幅部に行うインピーダンス変換を示すスミスチャートである。FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. 図１０Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、低電力増幅モードにおけるキャリア増幅部の出力インピーダンス整合条件を示すブロック回路図である。FIG. 10A is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the low power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. 図１０Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、高電力増幅モードにおけるキャリア増幅部の出力インピーダンス整合条件を示すブロック回路図である。FIG. 10B is a block circuit diagram showing an output impedance matching condition of the carrier amplifier in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. 図１１Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路の具体的な構成例を示す回路図である。FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. 図１１Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路の具体的な構成例を示す回路図である。FIG. 11B is a circuit diagram illustrating a specific configuration example of the peak-side output impedance matching circuit of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention.
　添付図面を参照して、本発明によるドハティ増幅器を実施するための形態を以下に説明する。 Referring to the accompanying drawings, a mode for carrying out the Doherty amplifier according to the present invention will be described below.
　本発明では、従来技術によるドハティ増幅回路が基本構成回路要素として備えている、インピーダンス変換回路としての４分の１波長線路を用いないドハティ増幅回路を提供する。本発明の基本的な原理は、以下の２点による。 The present invention provides a Doherty amplifier circuit that does not use a quarter-wave line as an impedance conversion circuit, which is provided as a basic constituent circuit element in a Doherty amplifier circuit according to the prior art. The basic principle of the present invention is based on the following two points.
　第１の点として、入力信号の強度がピーク増幅器の閾値未満である際の出力インピーダンスが誘導性である場合は、並列接続負荷型の構成を用いる。反対に、出力インピーダンスが容量性である場合は、直列接続負荷型の構成を用いる。 First, if the output impedance is inductive when the intensity of the input signal is less than the threshold value of the peak amplifier, a parallel connection load type configuration is used. Conversely, when the output impedance is capacitive, a series connected load type configuration is used.
　第２の点として、並列接続負荷型の構成を用いる場合には、キャリア増幅器の出力インピーダンス整合回路を、出力並列結合端子に直接接続する負荷インピーダンスに最適化する。また、直列接続負荷型の構成を用いる場合には、キャリア増幅器の出力インピーダンス整合回路を、出力バランの合成端子に直接接続する負荷インピーダンスに最適化する。 Second, when a parallel connection load type configuration is used, the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the output parallel coupling terminal. Further, when a series connection load type configuration is used, the output impedance matching circuit of the carrier amplifier is optimized to a load impedance directly connected to the combined terminal of the output balun.
　なお、これらの原理は、トランジスタを用いて構成された超高周波電力増幅器が入力インピーダンス整合回路および出力インピーダンス整合回路を備えていることを利用している。 Note that these principles use the fact that an ultra-high frequency power amplifier configured using transistors includes an input impedance matching circuit and an output impedance matching circuit.
　図３Ａは、本発明によるドハティ増幅回路の基本形を概略的に示すブロック回路図である。図３Ａに示したドハティ増幅回路は、入力部Ｉと、キャリア増幅部Ｃと、ピーク増幅部Ｐと、出力部Ｏとを有している。キャリア増幅部Ｃと、ピーク増幅部Ｐとは、入力部Ｉと、出力部Ｏとにおいて、並列または直列に接続されている。 FIG. 3A is a block circuit diagram schematically showing the basic form of the Doherty amplifier circuit according to the present invention. The Doherty amplifier circuit illustrated in FIG. 3A includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O. The carrier amplification section C and the peak amplification section P are connected in parallel or in series at the input section I and the output section O.
　入力部Ｉは、入力信号を入力して２つに分配し、一方をキャリア増幅部Ｃに供給し、他方をピーク増幅部Ｐに供給する。 The input unit I inputs an input signal and distributes it into two, supplies one to the carrier amplification unit C, and supplies the other to the peak amplification unit P.
　キャリア増幅部Ｃは、分配された入力信号の一方を増幅するが、この入力信号の強度が所定の閾値以上の場合は飽和出力状態になるように設計されている。また、キャリア増幅部Ｃの出力部は、接続先である出力部Ｏに対して、インピーダンス整合が取れているように設計されている。 The carrier amplifier C amplifies one of the distributed input signals, and is designed to be in a saturated output state when the intensity of the input signal is equal to or higher than a predetermined threshold. Further, the output part of the carrier amplifier C is designed so that impedance matching is achieved with respect to the output part O that is the connection destination.
　ピーク増幅部Ｐは、分配された入力信号の他方を増幅するが、この入力信号の強度が所定の閾値以下の場合はオフ状態になるように設計されている。また、ピーク増幅部Ｐの出力部は、接続先である出力部Ｏに対して、インピーダンス整合が取れているように設計されている。なお、ピーク増幅部Ｐに関わる閾値は、キャリア増幅部Ｃの飽和出力状態に関わる閾値と同じ値であることが望ましい。 The peak amplifying unit P amplifies the other one of the distributed input signals, and is designed to be turned off when the intensity of the input signal is a predetermined threshold value or less. Moreover, the output part of the peak amplification part P is designed so that impedance matching is taken with respect to the output part O which is a connection destination. Note that the threshold value related to the peak amplification unit P is preferably the same value as the threshold value related to the saturation output state of the carrier amplification unit C.
　出力部Ｏは、キャリア増幅部Ｃの出力と、ピーク増幅部Ｐの出力とを並列あるいは直列に合成するように設計されている。 The output unit O is designed to synthesize the output of the carrier amplification unit C and the output of the peak amplification unit P in parallel or in series.
　（第１の実施形態）
　図３Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の基本形を概略的に示すブロック回路図である。図３Ｂに示した並列接続負荷型ドハティ増幅回路は、図示しない入力部Ｉと、キャリア増幅部Ｃの出力増幅部ＣＣと、ピーク増幅部Ｐの出力増幅部ＰＰと、出力部Ｏおよび負荷ＬＰの集合体ＯＯとを有している。これらの入力部Ｉ、キャリア増幅部Ｃ、ピーク増幅部Ｐおよび出力部Ｏは、図３Ａに示したものにそれぞれ対応する。 (First embodiment)
FIG. 3B is a block circuit diagram schematically showing a basic form of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The parallel connection load type Doherty amplification circuit shown in FIG. 3B includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LP. And an aggregate OO. These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
　キャリア増幅部Ｃの出力増幅部ＣＣは、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣとを含んでいる。ピーク増幅部Ｐの出力増幅部ＰＰは、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰとを含んでいる。集合体ＯＯは、図示しない線路ＴＬと、並列接続負荷ＬＰとを含んでいる。 The output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC. The output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP. The aggregate OO includes a line TL (not shown) and a parallel connection load LP.
　ここでは、並列接続負荷型の構成について、本発明の第１の実施形態として説明する。直列接続負荷型の構成については、本発明の第２の実施形態として後述する。 Here, a parallel connection load type configuration will be described as a first embodiment of the present invention. The configuration of the series connection load type will be described later as a second embodiment of the present invention.
　図３Ｃは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の構成を示すブロック回路図である。図３Ｃに示したブロック回路図を用いて、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の構成例を、図３Ｂよりも詳しく説明する。 FIG. 3C is a block circuit diagram showing a configuration of a parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. A configuration example of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention will be described in more detail than FIG. 3B using the block circuit diagram shown in FIG. 3C.
　図３Ｃに示した並列接続負荷型ドハティ増幅回路の構成要素について説明する。図３Ｃに示した並列接続負荷型ドハティ増幅回路は、入力部Ｉと、キャリア増幅部Ｃと、ピーク増幅部Ｐと、出力部Ｏとを含んでいる。 The components of the parallel connection load type Doherty amplifier circuit shown in FIG. 3C will be described. The parallel-connected load type Doherty amplifier circuit illustrated in FIG. 3C includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
　図３Ｃに示した入力部Ｉは、分配回路ＤＣと、位相調整線路ＰＬとを含んでいる。図３Ｃに示したキャリア増幅部Ｃは、キャリア側入力インピーダンス整合回路ＩＭＮＣと、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣとを含んでいる。図３Ｃに示したピーク増幅部Ｐは、ピーク側入力インピーダンス整合回路ＩＭＮＰと、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰとを含んでいる。図３Ｃに示した出力部Ｏは、伝送線路ＴＬを含んでおり、並列接続負荷ＬＰに接続されている。 The input section I shown in FIG. 3C includes a distribution circuit DC and a phase adjustment line PL. The carrier amplifying unit C shown in FIG. 3C includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC. The peak amplifier P shown in FIG. 3C includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP. The output unit O illustrated in FIG. 3C includes a transmission line TL and is connected to a parallel connection load LP.
　図３Ｃに示した並列接続負荷型ドハティ増幅回路の構成要素の接続関係について説明する。分配回路ＤＣにおける一方の出力部は、位相調整線路ＰＬの一端に接続されている。位相調整線路ＰＬの他端は、キャリア側入力インピーダンス整合回路ＩＭＮＣの入力部に接続されている。キャリア側入力インピーダンス整合回路ＩＭＣＮの出力部は、キャリアトランジスタＴＣのゲートに接続されている。キャリアトランジスタＴＣのドレインは、キャリア側出力インピーダンス整合回路ＯＭＮＣの入力部に接続されている。キャリアトランジスタＴＣのソースは、接地されている。キャリア側出力インピーダンス整合回路ＯＭＮＣの出力部は、伝送線路ＴＬの一端と、並列接続負荷ＬＰの一端とに共通接続されている。並列接続負荷ＬＰの他端は、接地されている。 The connection relationship of the components of the parallel connection load type Doherty amplifier circuit shown in FIG. 3C will be described. One output portion of the distribution circuit DC is connected to one end of the phase adjustment line PL. The other end of the phase adjustment line PL is connected to the input part of the carrier side input impedance matching circuit IMNC. The output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC. The drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC. The source of the carrier transistor TC is grounded. The output part of the carrier side output impedance matching circuit OMNC is commonly connected to one end of the transmission line TL and one end of the parallel connection load LP. The other end of the parallel connection load LP is grounded.
　分配回路ＤＣにおける他方の出力部は、ピーク側入力インピーダンス整合回路ＩＭＮＰの入力部に接続されている。ピーク側入力インピーダンス整合回路ＩＭＮＰの出力部は、ピークトランジスタＴＰのゲートに接続されている。ピークトランジスタＴＰのドレインは、ピーク側出力インピーダンス整合回路ＯＭＮＰの入力部に接続されている。ピークトランジスタＴＰのソースは、接地されている。ピーク側出力インピーダンス整合回路ＯＭＮＰの出力部は、伝送線路ＴＬの他端に接続されている。 The other output section of the distribution circuit DC is connected to the input section of the peak side input impedance matching circuit IMNP. The output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP. The drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP. The source of the peak transistor TP is grounded. The output part of the peak side output impedance matching circuit OMNP is connected to the other end of the transmission line TL.
　ここで、図２Ａおよび図２Ｂに示した従来技術による並列接続負荷型ドハティ増幅器では必要とされていた４分の１波長線路ＱＷが、図３Ｃに示した本発明の第１の実施形態による並列接続負荷型ドハティ増幅器には用いられていないことに注目されたい。 Here, the quarter-wave line QW required in the parallel-connected load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is replaced by the parallel according to the first embodiment of the present invention shown in FIG. 3C. Note that it is not used in a connected load Doherty amplifier.
　ピーク増幅器に関する上記第１の原理について説明する。図４Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路のピーク増幅部Ｐにおける出力インピーダンスを示すブロック回路図である。図４Ａに示したピーク増幅部Ｐは、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、図３Ｂでは図示を省略されていた伝送線路ＴＬとを有している。図４Ａに示したピーク増幅部Ｐにおいて、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、伝送線路ＴＬとは、この順番に直列に接続されている。 The first principle regarding the peak amplifier will be described. FIG. 4A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. 4A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL not shown in FIG. 3B. In the peak amplifier P shown in FIG. 4A, the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in series in this order.
　図４Ａに示したピーク増幅器の出力インピーダンスをＺＰと置く。この出力インピーダンスＺＰが誘導性である場合について説明する。 Suppose that the output impedance of the peak amplifier shown in FIG. 4A is ZP. A case where the output impedance ZP is inductive will be described.
　図４Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路でピーク増幅部Ｐに行うインピーダンス変換を示すスミスチャートである。図４Ｂに示した第１のインピーダンスＺＰ１は、入力信号の強度がピーク増幅器の閾値未満である場合の、図４Ａに示したピーク側出力インピーダンス整合回路ＯＭＮＰの出力インピーダンスを示している。第１のインピーダンスＺＰ１は、図４Ｂに示したスミスチャートの上半分に位置しており、すなわち誘導性である。 FIG. 4B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The first impedance ZP1 shown in FIG. 4B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 4A when the intensity of the input signal is less than the threshold value of the peak amplifier. The first impedance ZP1 is located in the upper half of the Smith chart shown in FIG. 4B, that is, is inductive.
　このピーク側出力インピーダンス整合回路ＯＭＮＰの後段に、伝送線路ＴＬを追加することで、出力インピーダンスを調整することが可能である。図４Ｂに示した第２のインピーダンスＺＰ２は、図４Ａに示した伝送線路ＴＬの出力インピーダンスを示している。第２のインピーダンスＺＰ２は、図４Ｂに示したスミスチャートの右端付近に位置しており、すなわち開放に近いインピーダンスである。 It is possible to adjust the output impedance by adding a transmission line TL after the peak side output impedance matching circuit OMNP. The second impedance ZP2 shown in FIG. 4B indicates the output impedance of the transmission line TL shown in FIG. 4A. The second impedance ZP2 is located near the right end of the Smith chart shown in FIG. 4B, that is, an impedance close to opening.
　なお、この範囲でインピーダンスを調整する伝送線路ＴＬの長さは、４分の１波長よりも短い。 Note that the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
　キャリア増幅器に関する上記第２の原理について説明する。図５Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、低電力増幅モードにおけるキャリア増幅部Ｃの入出力インピーダンス整合条件を示すブロック回路図である。図５Ａに示すブロック回路図では、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、負荷ＬＰＬとが、縦続に接続されている。 The second principle concerning the carrier amplifier will be described. FIG. 5A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The block circuit diagram shown in FIG. 5A, the carrier transistor TC, and a carrier-side output impedance matching circuit OMNC, and the load LP L, are connected in cascade.
　図５Ａに示したＺｏｐｔＬは、入力信号の強度がピーク増幅部Ｐの閾値に到達する近傍にあるときの、キャリア増幅部Ｃの出力電力効率あるいは出力電力が最大となるキャリアトランジスタＴＣの負荷インピーダンスを表す。負荷ＬＰＬは、このとき、キャリア側出力インピーダンス整合回路ＯＭＮＣから見た負荷である。 Z optL shown in FIG. 5A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents. Load LP L is then: load as viewed from the carrier side output impedance matching circuit OMNC.
　図５Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、高電力増幅モードにおけるキャリア増幅部Ｃの入出力インピーダンス整合条件を示すブロック回路図である。図５Ｂに示したブロック回路図では、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、負荷ＬＰＨとが、縦続に接続されている。 FIG. 5B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the parallel-connected load type Doherty amplifier circuit according to the first embodiment of the present invention. In block circuit diagram shown in Figure 5B, the carrier transistor TC, and a carrier-side output impedance matching circuit OMNC, and the load LP H, they are connected in cascade.
　図５Ｂに示したＺｏｐｔＨは、入力信号の強度が、キャリア増幅部Ｃが飽和状態になる近傍にあるときの、キャリア増幅部Ｃの出力電力効率あるいは出力電力が最大となるキャリアトランジスタＴＣの負荷インピーダンスを表す。負荷ＬＰＨは、このとき、キャリア側出力インピーダンス整合回路ＯＭＮＣから見た負荷である。 ZoptH shown in FIG. 5B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C becoming saturated. Represents impedance. Load LP H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
　ここで、典型的な並列接続負荷型ドハティ増幅器では、図５Ａに示した低電力増幅モードにおける負荷ＬＰＬのインピーダンスは、図５Ｂに示したこう電力増幅モードにおける負荷ＬＰＨのインピーダンスの半分である。すなわち、キャリア側出力インピーダンス整合回路ＯＭＮＣは、負荷ＬＰＬに対してＺｏｐｔＬのインピーダンスを、負荷ＬＰＨに対してＺｏｐｔＨのインピーダンスを満たす必要がある。 Here, in a typical parallel-connected load type Doherty amplifier, the impedance of the load LP L in the low power amplification mode shown in FIG. 5A is half of the impedance of the load LP H in the gradient power amplification mode shown in FIG. 5B. . That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
　各インピーダンスは複素数であるから前項の二条件を満たすには、キャリア側出力インピーダンス整合回路ＯＭＮＣが、独立に設計調整可能なパラメータを、最低でも４つ有することが必要である。その一例を以下に示す。 Since each impedance is a complex number, the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
　図６Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路ＯＭＮＣの構成例を示す回路図である。図６Ａに示したキャリア側出力インピーダンス整合回路ＯＭＮＣは、第１のインダクタＬ１と、第２のインダクタＬ２と、第１のキャパシタＣ１と、第２のキャパシタＣ２とを有している。ここで、第１のインダクタＬ１と、第２のインダクタＬ２とは、キャリア側出力インピーダンス整合回路ＯＭＮＣの入力部および出力部の間に直列に接続されている。第１のキャパシタＣ１は、その一端は第１のインダクタＬ１と、第２のインダクタＬ２とに共通接続されており、その他端は接地されている。第２のキャパシタＣ２は、その一端がキャリア側出力インピーダンス整合回路ＯＭＮＣの出力部と、第２のインダクタＬ２とに共通接続されており、その他端は接地されている。言い換えれば、第１、第２のインダクタＬ１、Ｌ２は直列に接続されており、第１、第２のキャパシタＣ１、Ｃ２は並列に接続されている。 FIG. 6A is a circuit diagram showing a configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The carrier-side output impedance matching circuit OMNC illustrated in FIG. 6A includes a first inductor L1, a second inductor L2, a first capacitor C1, and a second capacitor C2. Here, the first inductor L1 and the second inductor L2 are connected in series between the input part and the output part of the carrier-side output impedance matching circuit OMNC. One end of the first capacitor C1 is commonly connected to the first inductor L1 and the second inductor L2, and the other end is grounded. One end of the second capacitor C2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L2, and the other end is grounded. In other words, the first and second inductors L1 and L2 are connected in series, and the first and second capacitors C1 and C2 are connected in parallel.
　図６Ａに示した２つのインダクタＬ１およびＬ２のそれぞれにおけるインダクタンスと、同じく２つのキャパシタＣ１およびＣ２のそれぞれにおける容量とを、適宜に設計調整することで、本実施形態によるドハティ増幅回路が正常に機能することを、発明者はシミュレーション解析及び実験で確認した。 The Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L1 and L2 shown in FIG. 6A and the capacitance in each of the two capacitors C1 and C2. The inventor has confirmed this through simulation analysis and experiments.
　ここで、ピーク側出力インピーダンス整合回路ＯＭＮＰは、例えば、図６Ｂまたは図６Ｃのように構成してもよい。 Here, the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 6B or FIG. 6C, for example.
　図６Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路ＯＭＮＰの構成例を示す回路図である。図６Ｂに示したピーク側出力インピーダンス整合回路ＯＭＮＰは、インダクタＬ３と、キャパシタＣ３とを有している。インダクタＬ３は、ピーク側出力インピーダンス整合回路ＯＭＮＰの入力部および出力部の間に接続されている。キャパシタＣ３は、その一端がピーク側出力インピーダンス整合回路ＯＭＮＰの出力部に接続されており、その他端は接地されている。言い換えれば、インダクタＬ３は直列に接続されており、キャパシタＣ３は並列に接続されている。 FIG. 6B is a circuit diagram showing a configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The peak-side output impedance matching circuit OMNP illustrated in FIG. 6B includes an inductor L3 and a capacitor C3. The inductor L3 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP. One end of the capacitor C3 is connected to the output portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded. In other words, the inductor L3 is connected in series, and the capacitor C3 is connected in parallel.
　図６Ｃは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路ＯＭＮＰの他の構成例を示す回路図である。図６Ｃに示したピーク側出力インピーダンス整合回路ＯＭＮＰは、第１のインダクタＬ４と、第２のインダクタＬ５と、第１のキャパシタＣ４と、第２のキャパシタＣ５とを有しているが、その構成は図６Ａに示したキャリア側出力インピーダンス整合回路ＯＭＮＣの場合と同様であるので、更なる詳細な説明を省略する。 FIG. 6C is a circuit diagram showing another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The peak-side output impedance matching circuit OMNP illustrated in FIG. 6C includes a first inductor L4, a second inductor L5, a first capacitor C4, and a second capacitor C5. Is the same as that in the case of the carrier side output impedance matching circuit OMNC shown in FIG. 6A, and further detailed description is omitted.
　独立に設計調整可能なパラメータを４つ有するキャリア側出力インピーダンス整合回路ＯＭＮＣの他の構成例について説明する。 Another configuration example of the carrier-side output impedance matching circuit OMNC having four parameters that can be independently designed and adjusted will be described.
　図７Ａは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路ＯＭＮＣの他の構成例を示す回路図である。図７Ａに示したキャリア側出力インピーダンス整合回路ＯＭＮＣは、第１の伝送線路ＴＬ１と、第２の伝送線路ＴＬ２と、第１のスタブＳ１と、第２のスタブＳ２とを有している。第１の伝送線路ＴＬ１と、第２の伝送線路ＴＬ２とは、キャリア側出力インピーダンス整合回路ＯＭＮＣの入力部と、出力部との間に直列に接続されている。第１のスタブＳ１は、第１の伝送線路ＴＬ１と、第２の伝送線路ＴＬ２とに共通接続されている。第２のスタブＳ２は、キャリア側出力インピーダンス整合回路ＯＭＮＣの出力部と、第２の伝送線路ＴＬ２とに共通接続されている。言い換えれば、第１、第２の伝送線路ＴＬ１、ＴＬ２は、直列に接続されており、第１、第２のスタブＳ１、Ｓ２は並列に接続されている。 FIG. 7A is a circuit diagram showing another configuration example of the carrier side output impedance matching circuit OMNC of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The carrier-side output impedance matching circuit OMNC illustrated in FIG. 7A includes a first transmission line TL1, a second transmission line TL2, a first stub S1, and a second stub S2. The first transmission line TL1 and the second transmission line TL2 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC. The first stub S1 is commonly connected to the first transmission line TL1 and the second transmission line TL2. The second stub S2 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second transmission line TL2. In other words, the first and second transmission lines TL1 and TL2 are connected in series, and the first and second stubs S1 and S2 are connected in parallel.
　第１の伝送線路ＴＬ１と、第２の伝送線路ＴＬ２と、第１のスタブＳ１と、第２のスタブＳ２とのそれぞれのサイズを適宜に設計調整することで、本発明によるドハティ増幅回路が正常に機能することを、発明者は実験で確認した。 By appropriately designing and adjusting the sizes of the first transmission line TL1, the second transmission line TL2, the first stub S1, and the second stub S2, the Doherty amplifier circuit according to the present invention is normal. The inventor has confirmed through experiments that it works.
　ここで、ピーク側出力インピーダンス整合回路ＯＭＮＰは、例えば、図７Ｂのように構成してもよい。 Here, the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 7B, for example.
　図７Ｂは、本発明の第１の実施形態による並列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路ＯＭＮＰのさらに他の構成例を示す回路図である。図７Ｂに示したピーク側出力インピーダンス整合回路ＯＭＮＰは、伝送線路ＴＬ３と、スタブＳ３とを有している。伝送線路ＴＬ３は、ピーク側出力インピーダンス整合回路ＯＭＮＰの入力部と、出力部との間に接続されている。スタブＳ３は、ピーク側出力インピーダンス整合回路ＯＭＮＰの出力部と、伝送線路ＴＬ３とに共通接続されている。言い換えれば、伝送線路ＴＬ３は直列に接続されており、スタブＳ３は並列に接続されている。 FIG. 7B is a circuit diagram showing still another configuration example of the peak-side output impedance matching circuit OMNP of the parallel connection load type Doherty amplifier circuit according to the first embodiment of the present invention. The peak-side output impedance matching circuit OMNP illustrated in FIG. 7B includes a transmission line TL3 and a stub S3. The transmission line TL3 is connected between the input unit and the output unit of the peak side output impedance matching circuit OMNP. The stub S3 is commonly connected to the output part of the peak-side output impedance matching circuit OMNP and the transmission line TL3. In other words, the transmission line TL3 is connected in series, and the stub S3 is connected in parallel.
　このように、本実施形態によるキャリア側出力インピーダンス整合回路ＯＭＮＣと、ピーク側出力インピーダンス整合回路ＯＭＮＰとは、集中定数素子を用いて構成しても良いし、分布定数素子を用いて構成しても良い。さらには、集中定数素子と、分布定数素子とを組み合わせて構成しても良いことは言うまでも無い。 As described above, the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment may be configured using a lumped constant element or a distributed constant element. good. Furthermore, it goes without saying that a lumped constant element and a distributed constant element may be combined.
　（第２の実施形態）
　本発明の第２の実施形態として、直列接続負荷型ドハティ増幅回路について説明する。 (Second Embodiment)
As a second embodiment of the present invention, a series connected load type Doherty amplifier circuit will be described.
　図８Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の基本形を概略的に示すブロック回路図である。図８Ａに示した直列接続負荷型ドハティ増幅回路は、図示しない入力部Ｉと、キャリア増幅部Ｃの出力増幅部ＣＣと、ピーク増幅部Ｐの出力増幅部ＰＰと、出力部Ｏおよび負荷ＬＳの集合体ＯＯとを有している。これらの入力部Ｉ、キャリア増幅部Ｃ、ピーク増幅部Ｐおよび出力部Ｏは、図３Ａに示したものにそれぞれ対応する。 FIG. 8A is a block circuit diagram schematically showing a basic form of a series-connected load type Doherty amplifier circuit according to a second embodiment of the present invention. The serial connection load type Doherty amplification circuit shown in FIG. 8A includes an input unit I (not shown), an output amplification unit CC of the carrier amplification unit C, an output amplification unit PP of the peak amplification unit P, an output unit O, and a load LS. And an aggregate OO. These input unit I, carrier amplification unit C, peak amplification unit P, and output unit O correspond to those shown in FIG. 3A, respectively.
　キャリア増幅部Ｃの出力増幅部ＣＣは、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣとを含んでいる。ピーク増幅部Ｐの出力増幅部ＰＰは、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰとを含んでいる。集合体ＯＯは、図示しない線路ＴＬと、直列接続負荷ＬＳとを含んでいる。 The output amplifier CC of the carrier amplifier C includes a carrier transistor TC and a carrier side output impedance matching circuit OMNC. The output amplifier PP of the peak amplifier P includes a peak transistor TP and a peak side output impedance matching circuit OMNP. The aggregate OO includes a line TL (not shown) and a series connection load LS.
　図８Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の構成を示すブロック回路図である。図８Ｂに示したブロック回路図を用いて、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の構成例を、図８Ａよりも詳しく説明する。 FIG. 8B is a block circuit diagram showing a configuration of a series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. A configuration example of the series-connected load-type Doherty amplifier circuit according to the second embodiment of the present invention will be described in more detail than FIG. 8A, using the block circuit diagram shown in FIG. 8B.
　図８Ｂに示した直列接続負荷型ドハティ増幅回路の構成要素について説明する。図８Ｂに示した直列接続負荷型ドハティ増幅回路は、入力部Ｉと、キャリア増幅部Ｃと、ピーク増幅部Ｐと、出力部Ｏとを含んでいる。 Components of the serial connection load type Doherty amplifier circuit shown in FIG. 8B will be described. The serial connection load type Doherty amplifier circuit shown in FIG. 8B includes an input unit I, a carrier amplifier unit C, a peak amplifier unit P, and an output unit O.
　図８Ｂに示した入力部Ｉは、分配回路ＤＣと、位相調整線路ＰＬとを含んでいる。図８Ｂに示したキャリア増幅部Ｃは、キャリア側入力インピーダンス整合回路ＩＭＮＣと、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣとを含んでいる。図８Ｂに示したピーク増幅部Ｐは、ピーク側入力インピーダンス整合回路ＩＭＮＰと、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰとを含んでいる。図８Ｂに示した出力部Ｏは、伝送線路ＴＬと、バランＢとを含んでおり、直列接続負荷ＬＳに接続されている。ここで、バランＢには特に制限は無く、伝送線路バラン、変成器バラン、集中定数バラン、位相反転バラン、その他のバランのいずれを用いても構わない。 The input unit I shown in FIG. 8B includes a distribution circuit DC and a phase adjustment line PL. The carrier amplification unit C shown in FIG. 8B includes a carrier side input impedance matching circuit IMNC, a carrier transistor TC, and a carrier side output impedance matching circuit OMNC. The peak amplifier P shown in FIG. 8B includes a peak side input impedance matching circuit IMNP, a peak transistor TP, and a peak side output impedance matching circuit OMNP. The output unit O illustrated in FIG. 8B includes a transmission line TL and a balun B, and is connected to a series connection load LS. Here, the balun B is not particularly limited, and any of a transmission line balun, a transformer balun, a lumped constant balun, a phase inversion balun, and other baluns may be used.
　図８Ｂに示した直列接続負荷型ドハティ増幅回路の構成要素の接続関係について説明する。分配回路ＤＣにおける一方の出力部は、キャリア側入力インピーダンス整合回路ＩＭＮＣの入力部に接続されている。キャリア側入力インピーダンス整合回路ＩＭＣＮの出力部は、キャリアトランジスタＴＣのゲートに接続されている。キャリアトランジスタＴＣのドレインは、キャリア側出力インピーダンス整合回路ＯＭＮＣの入力部に接続されている。キャリアトランジスタＴＣのソースは、接地されている。キャリア側出力インピーダンス整合回路ＯＭＮＣの出力部は、バランＢの平衡ポートの一方の端部に接続されている。直列接続負荷ＬＳにおいて、一端はバランＢの不平衡ポートの一方の端部に接続されており、他端は直接接地されている。バランＢの不平衡ポートの他方の端部は、接地されている。 The connection relationship of the components of the serial connection load type Doherty amplifier circuit shown in FIG. 8B will be described. One output section in the distribution circuit DC is connected to the input section of the carrier side input impedance matching circuit IMNC. The output part of the carrier side input impedance matching circuit IMCN is connected to the gate of the carrier transistor TC. The drain of the carrier transistor TC is connected to the input part of the carrier side output impedance matching circuit OMNC. The source of the carrier transistor TC is grounded. The output part of the carrier side output impedance matching circuit OMNC is connected to one end of the balanced port of the balun B. In the series connection load LS, one end is connected to one end of the unbalanced port of the balun B, and the other end is directly grounded. The other end of the unbalanced port of the balun B is grounded.
　分配回路ＤＣにおける他方の出力部は、位相調整線路ＰＬの一端に接続されている。位相調整線路ＰＬの他端は、ピーク側入力インピーダンス整合回路ＩＭＮＰの入力部に接続されている。ピーク側入力インピーダンス整合回路ＩＭＮＰの出力部は、ピークトランジスタＴＰのゲートに接続されている。ピークトランジスタＴＰのドレインは、ピーク側出力インピーダンス整合回路ＯＭＮＰの入力部に接続されている。ピークトランジスタＴＰのソースは、接地されている。ピーク側出力インピーダンス整合回路ＯＭＮＰの出力部は、伝送線路ＴＬを介してバランＢの平衡ポートの他方の端部に接続されている。 The other output section of the distribution circuit DC is connected to one end of the phase adjustment line PL. The other end of the phase adjustment line PL is connected to the input part of the peak side input impedance matching circuit IMNP. The output part of the peak side input impedance matching circuit IMNP is connected to the gate of the peak transistor TP. The drain of the peak transistor TP is connected to the input part of the peak side output impedance matching circuit OMNP. The source of the peak transistor TP is grounded. The output part of the peak-side output impedance matching circuit OMNP is connected to the other end of the balanced port of the balun B via the transmission line TL.
　ここで、図２Ａおよび図２Ｂに示した従来技術による並列接続負荷型ドハティ増幅器では必要とされていた４分の１波長線路ＱＷが、図８Ｂに示した本発明の第２の実施形態による直列接続負荷型ドハティ増幅器にも用いられていないことに注目されたい。 Here, the quarter wavelength line QW required in the parallel connection load type Doherty amplifier according to the prior art shown in FIGS. 2A and 2B is converted into the series according to the second embodiment of the invention shown in FIG. 8B. Note that it is not used in a connected load Doherty amplifier.
　ピーク増幅器に関する上記第１の原理について説明する。図９Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路のピーク増幅部Ｐにおける出力インピーダンスを示すブロック回路図である。図９Ａに示したピーク増幅部Ｐは、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、図３Ｂでは図示を省略されていた伝送線路ＴＬとを有している。図９Ａに示したピーク増幅部Ｐにおいて、ピークトランジスタＴＰと、ピーク側出力インピーダンス整合回路ＯＭＮＰと、伝送線路ＴＬとは、この順番に縦続に接続されている。 The first principle regarding the peak amplifier will be described. FIG. 9A is a block circuit diagram showing an output impedance in the peak amplifying unit P of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. 9A includes a peak transistor TP, a peak-side output impedance matching circuit OMNP, and a transmission line TL that is not shown in FIG. 3B. In the peak amplifier P shown in FIG. 9A, the peak transistor TP, the peak-side output impedance matching circuit OMNP, and the transmission line TL are connected in cascade in this order.
　図ＰＡに示したピーク増幅器の出力インピーダンスをＺＳと置く。この出力インピーダンスＺＳが容量性である場合について説明する。 Suppose the output impedance of the peak amplifier shown in Fig. PA is ZS. A case where the output impedance ZS is capacitive will be described.
　図９Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路でピーク増幅部Ｐに行うインピーダンス変換を示すスミスチャートである。図９Ｂに示した第１のインピーダンスＺＳ１は、入力信号の強度がピーク増幅器の閾値未満である場合の、図９Ａに示したピーク側出力インピーダンス整合回路ＯＭＮＰの出力インピーダンスを示している。第１のインピーダンスＺＳ１は、図９Ｂに示したスミスチャートの下半分に位置しており、すなわち容量性である。 FIG. 9B is a Smith chart showing impedance conversion performed on the peak amplifying unit P in the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. The first impedance ZS1 shown in FIG. 9B indicates the output impedance of the peak-side output impedance matching circuit OMNP shown in FIG. 9A when the intensity of the input signal is less than the threshold value of the peak amplifier. The first impedance ZS1 is located in the lower half of the Smith chart shown in FIG. 9B, that is, is capacitive.
　このピーク側出力インピーダンス整合回路ＯＭＮＰの後段に、伝送線路ＴＬを追加することで、出力インピーダンスを調整することが可能である。図９Ｂに示した第２のインピーダンスＺＳ２は、図９Ａに示した伝送線路ＴＬの出力インピーダンスを示している。第２のインピーダンスＺＳ２は、図９Ｂに示したスミスチャートの右端付近に位置しており、すなわち短絡に近いインピーダンスである。 It is possible to adjust the output impedance by adding a transmission line TL after the peak side output impedance matching circuit OMNP. The second impedance ZS2 illustrated in FIG. 9B indicates the output impedance of the transmission line TL illustrated in FIG. 9A. The second impedance ZS2 is located near the right end of the Smith chart shown in FIG. 9B, that is, an impedance close to a short circuit.
　なお、この範囲でインピーダンスを調整する伝送線路ＴＬの長さは、４分の１波長よりも短い。 Note that the length of the transmission line TL for adjusting the impedance in this range is shorter than a quarter wavelength.
　キャリア増幅器に関する上記第２の原理について説明する。図１０Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、低電力増幅モードにおけるキャリア増幅部Ｃの入出力インピーダンス整合条件を示すブロック回路図である。図１０Ａに示すブロック回路図では、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、負荷ＬＳＬとが、縦続に接続されている。 The second principle concerning the carrier amplifier will be described. FIG. 10A is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the low power amplification mode of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. In the block circuit diagram shown in FIG. 10A, a carrier transistor TC, a carrier-side output impedance matching circuit OMNC, and a load LS L are connected in cascade.
　図１０Ａに示したＺｏｐｔＬは、入力信号の強度がピーク増幅部Ｐの閾値に到達する近傍にあるときの、キャリア増幅部Ｃの出力電力効率あるいは出力電力が最大となるキャリアトランジスタＴＣの負荷インピーダンスを表す。負荷ＬＳＬは、このとき、キャリア側出力インピーダンス整合回路ＯＭＮＣから見た負荷である。 Z optL shown in FIG. 10A is the load impedance of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the intensity of the input signal is in the vicinity of reaching the threshold of the peak amplifier P. Represents. At this time, the load LS L is a load viewed from the carrier-side output impedance matching circuit OMNC.
　図１０Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、高電力増幅モードにおけるキャリア増幅部Ｃの入出力インピーダンス整合条件を示すブロック回路図である。図５Ｂに示したブロック回路図では、キャリアトランジスタＴＣと、キャリア側出力インピーダンス整合回路ＯＭＮＣと、負荷ＬＳＨとが、縦続に接続されている。 FIG. 10B is a block circuit diagram showing input / output impedance matching conditions of the carrier amplifier C in the high power amplification mode of the serial connection load type Doherty amplifier circuit according to the second embodiment of the present invention. In block circuit diagram shown in Figure 5B, the carrier transistor TC, and a carrier-side output impedance matching circuit OMNC, and a load LS H, they are connected in cascade.
　図１０Ｂに示したＺｏｐｔＨは、入力信号の強度が、キャリア増幅部Ｃが飽和状態になる近傍にあるときの、キャリア増幅部Ｃの出力電力効率あるいは出力電力が最大となるキャリアトランジスタＴＣの負荷インピーダンスを表す。負荷ＬＳＨは、このとき、キャリア側出力インピーダンス整合回路ＯＭＮＣから見た負荷である。 ZoptH shown in FIG. 10B is the load of the carrier transistor TC that maximizes the output power efficiency or output power of the carrier amplifier C when the strength of the input signal is in the vicinity of the carrier amplifier C being saturated. Represents impedance. Load LS H is then: load as viewed from the carrier side output impedance matching circuit OMNC.
　ここで、典型的な直列接続負荷型ドハティ増幅器では、図１０Ａに示した低電力増幅モードにおける負荷ＬＳＬのインピーダンスは、図１０Ｂに示した高電力増幅モードにおける負荷ＬＳＨのインピーダンスの２倍である。すなわち、キャリア側出力インピーダンス整合回路ＯＭＮＣは、負荷ＬＰＬに対してＺｏｐｔＬのインピーダンスを、負荷ＬＰＨに対してＺｏｐｔＨのインピーダンスを満たす必要がある。 Here, in a typical series connection load type Doherty amplifier, the impedance of the load LS L in the low power amplification mode shown in FIG. 10A, at twice the impedance of the load LS H in the high power amplification mode shown in FIG. 10B is there. That is, the carrier-side output impedance matching circuit OMNC the impedance of ZoptL to the load LP L, it is necessary to satisfy the impedance Z OptH the load LP H.
　各インピーダンスは複素数であるから前項の二条件を満たすには、キャリア側出力インピーダンス整合回路ＯＭＮＣが、独立に設計調整可能なパラメータを、最低でも４つ有することが必要である。その一例を以下に示す。 Since each impedance is a complex number, the carrier side output impedance matching circuit OMNC needs to have at least four parameters that can be independently designed and adjusted in order to satisfy the above two conditions. An example is shown below.
　図１１Ａは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、キャリア側出力インピーダンス整合回路ＯＭＮＣの具体的な構成例を示す回路図である。図１１Ａに示したキャリア側出力インピーダンス整合回路ＯＭＮＣは、第１のインダクタＬ６と、第２のインダクタＬ７と、第１のキャパシタＣ６と、第２のキャパシタＣ７とを有している。ここで、第１のインダクタＬ６と、第２のインダクタＬ７とは、キャリア側出力インピーダンス整合回路ＯＭＮＣの入力部および出力部の間に直列に接続されている。第１のキャパシタＣ６は、その一端は第１のインダクタＬ６と、第２のインダクタＬ７とに共通接続されており、その他端は接地されている。第２のキャパシタＣ７は、その一端がキャリア側出力インピーダンス整合回路ＯＭＮＣの出力部と、第２のインダクタＬ７とに共通接続されており、その他端は接地されている。言い換えれば、第１、第２のインダクタＬ６、Ｌ７は直列に接続されており、第１、第２のキャパシタＣ６、Ｃ７は並列に接続されている。 FIG. 11A is a circuit diagram showing a specific configuration example of the carrier-side output impedance matching circuit OMNC of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. The carrier-side output impedance matching circuit OMNC illustrated in FIG. 11A includes a first inductor L6, a second inductor L7, a first capacitor C6, and a second capacitor C7. Here, the first inductor L6 and the second inductor L7 are connected in series between the input part and the output part of the carrier side output impedance matching circuit OMNC. One end of the first capacitor C6 is commonly connected to the first inductor L6 and the second inductor L7, and the other end is grounded. One end of the second capacitor C7 is commonly connected to the output part of the carrier-side output impedance matching circuit OMNC and the second inductor L7, and the other end is grounded. In other words, the first and second inductors L6 and L7 are connected in series, and the first and second capacitors C6 and C7 are connected in parallel.
　図１１Ａに示した２つのインダクタＬ６およびＬ７のそれぞれにおけるインダクタンスと、同じく２つのキャパシタＣ６およびＣ７のそれぞれにおける容量とを、適宜に設計調整することで、本実施形態によるドハティ増幅回路が正常に機能することを、発明者はシミュレーション解析及び実験で確認した。 The Doherty amplifier circuit according to the present embodiment functions normally by appropriately designing and adjusting the inductance in each of the two inductors L6 and L7 shown in FIG. 11A and the capacitance in each of the two capacitors C6 and C7. The inventor has confirmed this through simulation analysis and experiments.
　ここで、ピーク側出力インピーダンス整合回路ＯＭＮＰは、例えば、図１１Ｂのように構成してもよい。 Here, the peak-side output impedance matching circuit OMNP may be configured as shown in FIG. 11B, for example.
　図１１Ｂは、本発明の第２の実施形態による直列接続負荷型ドハティ増幅回路の、ピーク側出力インピーダンス整合回路ＯＭＮＰの具体的な構成例を示す回路図である。図１１Ｂに示したピーク側出力インピーダンス整合回路ＯＭＮＰは、インダクタＬ８と、キャパシタＣ８とを有している。インダクタＬ８は、ピーク側出力インピーダンス整合回路ＯＭＮＰの入力部および出力部の間に接続されている。キャパシタＣ８は、その一端がピーク側出力インピーダンス整合回路ＯＭＮＰの入力部に接続されており、その他端は接地されている。言い換えれば、インダクタＬ８は直列に接続されており、キャパシタＣ８は並列に接続されている。 FIG. 11B is a circuit diagram showing a specific configuration example of the peak-side output impedance matching circuit OMNP of the series-connected load type Doherty amplifier circuit according to the second embodiment of the present invention. The peak-side output impedance matching circuit OMNP illustrated in FIG. 11B includes an inductor L8 and a capacitor C8. The inductor L8 is connected between the input part and the output part of the peak side output impedance matching circuit OMNP. One end of the capacitor C8 is connected to the input portion of the peak-side output impedance matching circuit OMNP, and the other end is grounded. In other words, the inductor L8 is connected in series, and the capacitor C8 is connected in parallel.
　このように、本実施形態によるキャリア側出力インピーダンス整合回路ＯＭＮＣと、ピーク側出力インピーダンス整合回路ＯＭＮＰとは、集中定数素子を用いて構成することが出来るが、分布定数素子を用いて構成しても良いし、集中定数素子と、分布定数素子とを組み合わせて構成しても良いことは言うまでも無い。 As described above, the carrier-side output impedance matching circuit OMNC and the peak-side output impedance matching circuit OMNP according to the present embodiment can be configured using lumped constant elements, but may be configured using distributed constant elements. Needless to say, a lumped constant element and a distributed constant element may be combined.
　尚、この出願は、２０１２年３月５日に出願された日本特許出願２０１２－０４８４４８号を基礎とする優先権を主張し、その開示の全てを引用によりここに組み込む。 This application claims priority based on Japanese Patent Application No. 2012-048448 filed on March 5, 2012, the entire disclosure of which is incorporated herein by reference.

Claims (10)

  1. 　入力信号の強度に応じて動作モードが第１増幅モードおよび第２増幅モードの間で切り替わるドハティ増幅回路であって、
    　前記入力信号を２つに分配する入力部と、
    　前記第１増幅モードにおいては前記入力信号の一方を増幅し、前記第２増幅モードにおいては飽和出力状態になる第１増幅器と、
    　前記第１増幅モードにおいてはオフ状態になり、前記第２増幅モードにおいては前記入力信号の他方を増幅する第２増幅器と、
    　前記第１増幅器の後段に接続された第１整合回路と、
    　前記第１整合回路の後段に接続された出力部と、
    　前記第２増幅器の後段に接続された第２整合回路と
    を具備し、
    　前記出力部は、
    　前記第２整合回路の後段に接続されて、前記入力信号の四分の一波長より短い線路
    を具備し、
    　前記第１整合回路は、
    　前記第１増幅モードにおいても、前記第２増幅モードにおいても、出力インピーダンス整合を満足するように設計調整された少なくとも４つの独立パラメータ
    を具備する
    　ドハティ増幅回路。     A Doherty amplifier circuit in which an operation mode is switched between a first amplification mode and a second amplification mode according to the intensity of an input signal;
    An input unit for distributing the input signal into two;
    A first amplifier that amplifies one of the input signals in the first amplification mode and is in a saturated output state in the second amplification mode;
    A second amplifier that is off in the first amplification mode and amplifies the other of the input signals in the second amplification mode;
    A first matching circuit connected downstream of the first amplifier;
    An output connected to a subsequent stage of the first matching circuit;
    A second matching circuit connected downstream of the second amplifier,
    The output unit is
    Connected to a subsequent stage of the second matching circuit, comprising a line shorter than a quarter wavelength of the input signal;
    The first matching circuit includes:
    A Doherty amplifier circuit comprising at least four independent parameters that are designed and adjusted to satisfy output impedance matching in both the first amplification mode and the second amplification mode.
  2. 　請求項１に記載のドハティ増幅回路において、
    　前記線路は、
    　前記第２整合回路の出力インピーダンスが誘導性である場合には前記線路の出力インピーダンスが開放インピーダンスとして振舞うように調節され、前記第２整合回路の出力インピーダンスが容量性である場合には前記線路の出力インピーダンスが短絡インピーダンスとして振舞うように調節されたインピーダンス
    を具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to claim 1,
    The track is
    When the output impedance of the second matching circuit is inductive, the output impedance of the line is adjusted to behave as an open impedance, and when the output impedance of the second matching circuit is capacitive, A Doherty amplifier circuit having an impedance adjusted so that the output impedance behaves as a short-circuit impedance.
  3. 　請求項１または２に記載のドハティ増幅回路において、
    　前記第１整合回路の出力部と、前記線路の他方の端部とは、前記出力部の後段に配置される負荷に並列に共通接続されたものである
    　ドハティ増幅回路。     The Doherty amplifier circuit according to claim 1 or 2,
    The output unit of the first matching circuit and the other end of the line are commonly connected in parallel to a load arranged at a subsequent stage of the output unit.
  4. 　請求項１または２に記載のドハティ増幅回路において、
    　前記出力部は、
    　前記出力部の後段に配置される負荷に接続されたバラン
    をさらに具備し、
    　前記バランは、
    　前記第１整合回路の出力部と、前記線路との間に直列に接続された一方の回路と、
    　前記負荷に直列に接続された他方の回路と
    を具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to claim 1 or 2,
    The output unit is
    Further comprising a balun connected to a load disposed downstream of the output unit;
    The balun is
    One circuit connected in series between the output of the first matching circuit and the line;
    A Doherty amplifier circuit comprising: the other circuit connected in series to the load.
  5. 　請求項１～３のいずれかに記載のドハティ増幅回路において、
    　前記入力部は、
    　前記第１増幅器の前段に接続されて、前記入力信号の前記一方の位相を調整する位相調整線路
    をさらに具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to any one of claims 1 to 3,
    The input unit is
    A Doherty amplifier circuit further comprising a phase adjustment line that is connected to a preceding stage of the first amplifier and adjusts the one phase of the input signal.
  6. 　請求項１、２または４のいずれかに記載のドハティ増幅回路において、
    　前記入力部は、
    　前記第２増幅器の前段に接続されて、前記入力信号の前記他方の位相を調整する位相調整線路
    をさらに具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to any one of claims 1, 2, and 4,
    The input unit is
    A Doherty amplifier circuit further comprising a phase adjustment line that is connected to a preceding stage of the second amplifier and adjusts the other phase of the input signal.
  7. 　請求項１～６のいずれかに記載のドハティ増幅回路において、
    　前記第１整合回路は、
    　直列に接続された２つのインダクタと、
    　並列に接続された２つのキャパシタと
    を具備し、
    　前記４つのパラメータは、
    　前記２つのインダクタのそれぞれにおけるインダクタンスと、前記２つのキャパシタのそれぞれにおける容量と
    を具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to any one of claims 1 to 6,
    The first matching circuit includes:
    Two inductors connected in series;
    Two capacitors connected in parallel,
    The four parameters are:
    A Doherty amplifier circuit comprising an inductance in each of the two inductors and a capacitance in each of the two capacitors.
  8. 　請求項１～６のいずれかに記載のドハティ増幅回路において、
    　前記第１整合回路は、
    　直列に接続された２つの伝送線路と、
    　並列に接続された２つのスタブと
    を具備し、
    　前記４つのパラメータは、
    　前記２つの伝送線路のそれぞれにおけるサイズと、前記２つのスタブのそれぞれにおけるサイズと
    を具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to any one of claims 1 to 6,
    The first matching circuit includes:
    Two transmission lines connected in series;
    Two stubs connected in parallel,
    The four parameters are:
    A Doherty amplifier circuit comprising a size in each of the two transmission lines and a size in each of the two stubs.
  9. 　請求項１～８のいずれかに記載のドハティ増幅回路において、
    　前記第２整合回路は、
    　直列に接続されたインダクタと、
    　並列に接続されたキャパシタと
    を具備する
    　ドハティ増幅回路。     The Doherty amplifier circuit according to any one of claims 1 to 8,
    The second matching circuit includes:
    An inductor connected in series;
    A Doherty amplifier circuit comprising a capacitor connected in parallel.
  10. 　請求項１～８のいずれかに記載のドハティ増幅回路において、
    　前記第２整合回路は、
    　直列に接続された伝送線路と、
    　並列に接続されたスタブと
    を具備する
    　ドハティ増幅回路。
          The Doherty amplifier circuit according to any one of claims 1 to 8,
    The second matching circuit includes:
    A transmission line connected in series;
    A Doherty amplifier circuit comprising a stub connected in parallel.
PCT/JP2013/055857 2012-03-05 2013-03-04 Doherty amplifier circuit WO2013133215A1 (en)

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JP2012-048448 2012-03-05

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015108492A1 (en) * 2014-01-14 2015-07-23 Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi Doherty amplifier with a wideband in-phase power combiner
EP3264595A1 (en) * 2016-06-30 2018-01-03 Nxp B.V. Doherty amplifiers
CN107547051A (en) * 2017-08-28 2018-01-05 广东顺德中山大学卡内基梅隆大学国际联合研究院 Doherty power amplifier based on distributed broadband impedance mapped structure
EP3396856A1 (en) * 2017-04-24 2018-10-31 Gatesair Inc. Push-pull amplification systems and methods
EP3570433A1 (en) * 2015-01-09 2019-11-20 Kabushiki Kaisha Toshiba Doherty amplifier
EP3813253A1 (en) * 2019-10-23 2021-04-28 Nxp B.V. Radio-frequency amplifier

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10116266B2 (en) 2015-01-09 2018-10-30 Kabushiki Kaisha Toshiba Doherty amplifier
CN104579178A (en) * 2015-01-19 2015-04-29 东南大学 Broadband input matching based improved doherty power amplifier
WO2019207700A1 (en) * 2018-04-26 2019-10-31 三菱電機株式会社 Amplifier

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204131A (en) * 2000-10-23 2002-07-19 Matsushita Electric Ind Co Ltd Power amplifier
WO2008035396A1 (en) * 2006-09-19 2008-03-27 Panasonic Corporation Power amplifying apparatus
WO2009131138A1 (en) * 2008-04-24 2009-10-29 日本電気株式会社 Amplifier

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006005848A (en) * 2004-06-21 2006-01-05 Sharp Corp Power amplifier and high frequency communication device
JP2006157900A (en) * 2004-11-05 2006-06-15 Hitachi Kokusai Electric Inc Amplifier
JP2008113402A (en) * 2006-05-09 2008-05-15 Mitsubishi Electric Corp Amplifier
JP2009182635A (en) * 2008-01-30 2009-08-13 Toshiba Corp Doherty amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002204131A (en) * 2000-10-23 2002-07-19 Matsushita Electric Ind Co Ltd Power amplifier
WO2008035396A1 (en) * 2006-09-19 2008-03-27 Panasonic Corporation Power amplifying apparatus
WO2009131138A1 (en) * 2008-04-24 2009-10-29 日本電気株式会社 Amplifier

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015108492A1 (en) * 2014-01-14 2015-07-23 Aselsan Elektronik Sanayi Ve Ticaret Anonim Sirketi Doherty amplifier with a wideband in-phase power combiner
EP3570433A1 (en) * 2015-01-09 2019-11-20 Kabushiki Kaisha Toshiba Doherty amplifier
EP3264595A1 (en) * 2016-06-30 2018-01-03 Nxp B.V. Doherty amplifiers
CN107565909A (en) * 2016-06-30 2018-01-09 恩智浦有限公司 Doherty amplifier
US10090810B2 (en) 2016-06-30 2018-10-02 Nxp B.V. Doherty amplifiers
CN107565909B (en) * 2016-06-30 2024-01-09 恩智浦有限公司 Doherty amplifier
EP3396856A1 (en) * 2017-04-24 2018-10-31 Gatesair Inc. Push-pull amplification systems and methods
US10270396B2 (en) 2017-04-24 2019-04-23 Gatesair, Inc. Push-pull amplification systems and methods
CN107547051A (en) * 2017-08-28 2018-01-05 广东顺德中山大学卡内基梅隆大学国际联合研究院 Doherty power amplifier based on distributed broadband impedance mapped structure
CN107547051B (en) * 2017-08-28 2020-10-23 广东顺德中山大学卡内基梅隆大学国际联合研究院 Doherty power amplifier based on distributed broadband impedance transformation structure
EP3813253A1 (en) * 2019-10-23 2021-04-28 Nxp B.V. Radio-frequency amplifier
US11482974B2 (en) 2019-10-23 2022-10-25 Nxp B.V. Radio-frequency amplifier

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