WO2013125173A1 - ディジタルフィルタ回路、ディジタルフィルタ処理方法及びディジタルフィルタ処理プログラム記憶媒体 - Google Patents
ディジタルフィルタ回路、ディジタルフィルタ処理方法及びディジタルフィルタ処理プログラム記憶媒体 Download PDFInfo
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- WO2013125173A1 WO2013125173A1 PCT/JP2013/000754 JP2013000754W WO2013125173A1 WO 2013125173 A1 WO2013125173 A1 WO 2013125173A1 JP 2013000754 W JP2013000754 W JP 2013000754W WO 2013125173 A1 WO2013125173 A1 WO 2013125173A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0248—Filters characterised by a particular frequency response or filtering method
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0211—Frequency selective networks using specific transformation algorithms, e.g. WALSH functions, Fermat transforms, Mersenne transforms, polynomial transforms, Hilbert transforms
- H03H17/0213—Frequency domain filters using Fourier transforms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H2218/00—Indexing scheme relating to details of digital filters
- H03H2218/04—In-phase and quadrature [I/Q] signals
Definitions
- the present invention relates to arithmetic processing in digital signal processing, and more particularly to a digital filter circuit, a digital filter processing method, and a digital filter processing program storage medium.
- FIG. 9 is a configuration example of a digital filter circuit 100 using an FIR filter.
- the digital filter circuit 100 includes three FIR filters 101, 102, and 103.
- the FIR filter 101 is a real coefficient FIR filter with 5 taps that performs a filtering process by a real number operation on a real number real part signal r (n) that is a real number part of an input complex number signal x (n). is there.
- the five filter coefficients a0 to a4 of the FIR filter 101 are real numbers.
- the FIR filter 101 outputs the result of the filter processing as a real part signal r ′ (n).
- the FIR filter 102 is a FIR filter with a real number coefficient of 5 taps that performs a filtering process by a real number operation on a real imaginary part signal s (n) that is an imaginary part of an input complex signal.
- the five filter coefficients b0 to b4 of the FIR filter 102 are real numbers.
- the FIR filter 102 outputs the filter processing result as an imaginary part signal s ′ (n).
- This is a complex coefficient FIR filter with 5 taps, which performs filter processing on '(n) by complex number calculation.
- the five filter coefficients c0 to c4 of the FIR filter 103 are complex numbers.
- the FIR filter 103 outputs the result of the filter processing as a complex signal x ′′ (n).
- the complex signal is distinguished by being represented by a thicker line than the line indicating the real signal.
- lines indicating signals are similarly expressed.
- both the filter processing by the real number calculation using the real number filter coefficients and the filter processing by the complex number calculation using the complex number filter coefficients may be performed as in the digital filter circuit 100. .
- the minimum value of the number of taps of the FIR filter is determined by the impulse response length of the filter function to be realized. Therefore, when realizing a complicated filter function, a tap number of several hundred taps or more may be required.
- Such an LSI (Large Scale Integrated Circuit) on which an FIR filter with a large number of taps is mounted has a problem that the circuit scale and power consumption of the LSI become enormous.
- Patent Document 1 a technique for performing filter processing in the frequency domain is known (for example, Patent Document 1).
- signal data in the time domain is temporarily converted into signal data in the frequency domain by fast Fourier transform (FFT. Fast Transform).
- FFT fast Fourier transform
- IFFT fast inverse Fourier transform
- the circuit scale and power consumption necessary for realizing the filter processing can be reduced by performing the filter processing in the frequency domain. This is because the convolution operation in the time domain by the FIR filter can be converted into a simple multiplication in the frequency domain.
- the complex signal in the time domain is a complex signal
- the complex signal is converted into complex signal data in the frequency domain by a complex FFT.
- the complex FFT transform the real part and imaginary part of the complex signal in the time domain are combined and converted to complex signal data in the frequency domain. That is, both the real part and the imaginary part of the complex signal in the time domain are used to calculate the real part and the imaginary part of the complex signal data in the frequency domain. For this reason, when each of the real part and the imaginary part of the complex signal in the time domain is filtered independently, according to the technique of Patent Document 1, it is necessary to independently convert each into frequency domain signal data by a real FFT. There is.
- FIG. 10 shows a configuration example of the digital filter circuit 110 that performs filter processing in the frequency domain.
- the digital filter circuit 110 corresponds to the digital filter circuit 100 that performs filter processing in the time domain shown in FIG.
- the digital filter circuit 110 includes three frequency domain filter circuits 111, 112, and 113.
- the frequency domain filter 111 converts the real part signal r (n), which is the real part of the complex signal x (n) in the time domain, into complex signal data in the frequency domain by FFT. Then, the frequency domain filter 111 performs a filter operation by a complex number operation on the frequency domain to the complex number signal data on the frequency domain, and then reconverts the complex number signal data to the real part signal data r ′ (n) on the time domain by IFFT. To do.
- the real part signal r (n) is a real number signal, but even when the real number signal is Fourier transformed, the converted signal data is a complex number. Also, the filter coefficient is usually a complex number. Therefore, a complex number calculation is necessary for the filter calculation.
- the frequency domain filter 112 converts the real imaginary part signal s (n), which is the imaginary part of the complex signal x (n) in the time domain, into complex signal data in the frequency domain by FFT. .
- the frequency domain filter 112 performs a filter operation on the complex number signal data on the frequency domain by a complex number operation on the frequency domain, and then converts the complex number signal data s ′ (n) on the real number in the time domain by IFFT. Reconvert.
- the signal is converted into complex signal data in the frequency domain by FFT.
- the frequency domain filter 113 performs a filter operation by a complex number operation on the frequency domain on the complex number signal data on the frequency domain, and then converts the complex number signal data s ′′ (n) to a real number imaginary part signal data s ′′ (n) by the IFFT. Reconvert.
- Patent Document 3 discloses a technique for performing inverse Fourier transform after performing a predetermined operation using a complex signal generated by Fourier transform of an input signal and its complex conjugate value.
- the present invention is to solve the above-described problems, and a digital filter circuit, a digital filter processing method, and a digital filter capable of reducing the circuit scale and power consumption for performing digital filter processing in the frequency domain It is an object to provide a processing program storage medium.
- the digital filter circuit generates a second complex signal including conjugate complex numbers of all complex numbers constituting the first complex signal in the frequency domain generated by transforming the complex signal in the time domain by Fourier transform.
- a complex conjugate generator a filter coefficient generator that generates first and second frequency domain filter coefficients of complex numbers from the input first, second, and third input filter coefficients of complex numbers; Filtering a complex signal with a first frequency domain filter coefficient and outputting a third complex signal, and filtering the second complex signal with a second frequency domain filter coefficient
- the fifth complex signal is obtained by synthesizing the second filter unit that performs processing and outputs the fourth complex signal, the third complex signal, and the fourth complex signal.
- a complex conjugate synthesis unit to be generated characterized in that it comprises a.
- the second complex signal including the conjugate complex numbers of all the complex numbers constituting the first complex signal in the frequency domain generated by transforming the complex signal in the time domain by Fourier transform is obtained.
- the fifth complex signal is generated by synthesizing the complex signal and the fourth complex signal.
- the digital filter processing program storage medium of the present invention provides a computer provided in an arithmetic unit with the conjugates of all the complex numbers constituting the first complex signal in the frequency domain generated by transforming the complex signal in the time domain by Fourier transform.
- Complex first and second frequency domain filter coefficients are generated from complex conjugate generating means for generating a second complex signal including a complex number and first, second and third input filter coefficients of the complex number inputted Filter coefficient generation means for performing a filtering process on the first complex signal with the first frequency domain filter coefficient, and outputting a third complex signal, and a second complex signal.
- a second filter processing means for performing a filtering process on the second frequency domain filter coefficient and outputting a fourth complex signal; Storing a third complex signal, the program for functioning as a complex conjugate synthesis means for synthesizing the fourth complex signal to produce a fifth complex signal.
- the circuit scale and power consumption for performing digital filter processing in the frequency domain can be reduced.
- FIG. 1 is a block diagram showing a configuration of a digital filter circuit according to a first embodiment of the present invention.
- 2 is a block diagram showing a configuration of a complex conjugate generation circuit 15 according to the first exemplary embodiment of the present invention.
- FIG. It is a block diagram which shows the structure of the filter circuit 21 concerning the 1st Embodiment of this invention.
- 1 is a block diagram showing a configuration of a filter circuit 22 according to a first embodiment of the present invention.
- 2 is a block diagram showing a configuration of a complex conjugate synthesis circuit 16 according to the first exemplary embodiment of the present invention.
- FIG. FIG. 3 is a block diagram showing a configuration of a filter coefficient generation circuit 41 according to the first embodiment of the present invention.
- FIG. 1 is a block diagram showing a configuration of a digital filter circuit 10 according to the first embodiment of the present invention.
- the digital filter circuit 10 includes an FFT circuit 13, an IFFT circuit 14, a complex conjugate generation circuit 15, a complex conjugate synthesis circuit 16, a filter circuit 21, a filter circuit 22, and a filter coefficient generation circuit 41.
- n is an integer of 0 ⁇ n ⁇ N ⁇ 1 indicating a signal sample number in the time domain
- N is an integer of 0 ⁇ N indicating the number of FFT conversion samples
- k is a frequency number in the frequency domain 0 ⁇ k ⁇ N ⁇ 1.
- FFT is one method for performing Fourier transform at high speed.
- the processing form and processing speed of the Fourier transform are not essential problems for the present invention. Therefore, in place of the FFT circuit 13, a circuit that performs Fourier transform by a method other than FFT may be used. The same applies to IFFT described later.
- the complex conjugate generation circuit 15 inputs X (N ⁇ k) output from the FFT circuit 13 for each frequency number k of 0 ⁇ k ⁇ N ⁇ 1, and inputs the complex conjugate X * (X * (N ⁇ k).
- N ⁇ k) A (N ⁇ k) ⁇ jB (N ⁇ k) (4) Is generated.
- the complex conjugate generation circuit 15 outputs the input complex signal X (k) as a complex signal 32 and outputs the generated complex signal X * (N ⁇ k) as a complex signal 33.
- the filter coefficient generation circuit 41 calculates the complex coefficient C1 (from the input complex coefficients V (k), W (k), and H (k) for each frequency number k of 0 ⁇ k ⁇ N ⁇ 1.
- k) ⁇ V (k) + W (k) ⁇ ⁇ H (k) (5)
- complex coefficient C2 (k) ⁇ V (k) ⁇ V (k) ⁇ ⁇ H (k) (6) Is generated.
- V (k), W (k), and H (k) are coefficients in the frequency domain given from an upper circuit (not shown) of the digital filter circuit 10, and are obtained by real number calculation in the time domain. This corresponds to the real filter coefficient when filtering is performed. Details of V (k), W (k), and H (k) will be described later.
- the filter coefficient generation circuit 41 outputs the generated complex number coefficient C1 (k) as a complex number signal 45.
- the filter coefficient generation circuit 41 generates a complex signal C2 (N ⁇ k) from the complex signal C2 (k) (equation (6)) and outputs it as a complex signal 46.
- the filter circuit 21 outputs C1 (k) output from the filter coefficient generation circuit 41 to the complex signal 45 with respect to X (k) (formula (2)) output from the complex conjugate generation circuit 15 to the complex signal 32.
- complex number filter processing by complex number multiplication is performed.
- the filter circuit 22 outputs C * 2 that the filter coefficient generation circuit 41 outputs to the complex signal 46 in response to X * (N ⁇ k) (formula (4)) that the complex conjugate generation circuit 15 outputs to the complex signal 33.
- (N ⁇ k) formula (6)
- complex number filter processing by complex number multiplication is performed.
- C1 (k) and C2 (k) are divided into real part and imaginary part respectively.
- C1 (k) C1I (k) + jC1Q (k) (9)
- C2 (k) C2I (k) + jC2Q (k) (10) Can be written.
- the IFFT circuit 14 outputs X ′′ (k) (formula (11)) output from the complex conjugate synthesis circuit 16 to the complex signal 36 for each of the frequency numbers k satisfying 0 ⁇ k ⁇ N ⁇ 1. Generate and output a complex signal x ′′ (n) in time domain by IFFT.
- FIG. 2 is a block diagram showing details of the configuration of the complex conjugate generation circuit 15.
- X (k) and X * (N ⁇ k) are divided into a real part and an imaginary part respectively.
- X (k) XI (k) + jXQ (k) (12)
- X * (N ⁇ k) X * I (N ⁇ k) + jX * Q (N ⁇ k) (13) Can be written.
- FIG. 3 is a block diagram showing details of the configuration of the filter circuit 21.
- XI ′ (k) and XQ ′ (k) are the real part and the imaginary part of X ′ (k), respectively, and are given by the following equations.
- FIG. 4 is a block diagram showing details of the configuration of the filter circuit 22.
- X * I ′ (N ⁇ k) and X * Q ′ (N ⁇ k) are the real part and the imaginary part of X * ′ (N ⁇ k), respectively, and are given by the following equations.
- FIG. 5 is a block diagram showing details of the configuration of the complex conjugate synthesis circuit 16.
- XI "(k) and XQ" (k) are the real part and imaginary part of X "(k), respectively, and are given by the following equations.
- XI "(k) 1/2 ⁇ XI '(k) + X * I' (N-k) ⁇ (21)
- XQ "(k) 1/2 ⁇ XQ '(k) + X * Q' (N-k) ⁇ (22)
- XI ′ (k), XQ ′ (k), X * I ′ (N ⁇ k), and X * Q ′ (N ⁇ k) are represented by the equations (15), (16), (18), (19)
- the filter coefficient generation circuit 41 generates complex coefficient C1 (k) and C2 (k) used in the filter circuits 21 and 22.
- FIG. 6 is a block diagram showing details of the configuration of the filter coefficient generation circuit 41.
- the filter coefficient generation circuit 41 calculates V (k) from complex coefficient V (k) and W (k) input from a higher-order circuit (not shown) for each frequency number k of 0 ⁇ k ⁇ N ⁇ 1. Calculate + W (k) and V (k) -W (k).
- V (k) + W (k) VI (k) + WI (k) + jVQ (k) + jWQ (k) (23)
- V (k) -W (k) VI (k) -WI (k) + jVQ (k) -jWQ (k) (24) It is.
- VI (k) and VQ (k) are the real part and imaginary part of V (k), respectively, and WI (k) and WQ (k) are the real part and imaginary part of W (k), respectively.
- H (k) is also divided into a real part and an imaginary part.
- H (k) HI (k) + jHQ (k) (25) Can be written.
- the filter coefficient generation circuit 41 calculates and outputs complex coefficient C1 (k) and C2 (k) defined by the following equations.
- C1I (k) and C1Q (k) are the real part and imaginary part of C1 (k), respectively
- C2I (k) and C2Q (k) are the real part and imaginary part of C2 (k), respectively. It is.
- C1I (k) ⁇ VI (k) + WI (k) ⁇ ⁇ HI (k) ⁇ ⁇ VQ (k) + WQ (k) ⁇ ⁇ HQ (k) (29)
- C1Q (k) ⁇ VQ (k) + WQ (k) ⁇ ⁇ HI (k) + ⁇ VI (k) + WI (k) ⁇ ⁇ HQ (k) (30) It is.
- C2I (k) ⁇ VI (k) ⁇ WI (k) ⁇ ⁇ HI (k) ⁇ ⁇ VQ (k) ⁇ WQ (k) ⁇ ⁇ HQ (k) (32)
- C2Q (k) ⁇ VQ (k) ⁇ WQ (k) ⁇ ⁇ HI (k) + ⁇ VI (k) ⁇ WI (k) ⁇ ⁇ HQ (k) (33) It is.
- the digital filter circuit 10 performs FFT conversion on the time domain input signal to generate a frequency domain complex signal.
- the digital filter circuit 10 independently uses the two types of coefficients generated from V (k), W (k), and H (k) for the real part and the imaginary part of the complex signal in the frequency domain. Filtering is performed, and the result is converted into a signal in the time domain by IFFT. As described above, in the digital filter circuit 10, the FFT and IFFT are executed only once for the time domain input signal.
- the two types of coefficients used for the filtering process can minimize the number of FFT and IFFT.
- the physical meaning of V (k), W (k), H (k) and the filter processing using the coefficients C1 (k) and C2 (k) generated from these are used in the time domain. The principle that enables filter processing in the frequency domain equivalent to the desired filter processing will be described.
- the complex conjugate generation circuit 15 generates X * (N ⁇ k).
- R (k) is a frequency-domain complex signal obtained by transforming a real number real part signal r (n) in the time domain by a real number FFT
- S (k) is a real number imaginary part signal s (n in the time domain. ) Is a complex signal in the frequency domain transformed by a real number FFT.
- X * (N ⁇ k) R (k) ⁇ jS (k) (35)
- X * (N ⁇ k) is a complex conjugate of X (N ⁇ k).
- Equation (38) shows that the signal X ′′ (k) before IFFT is converted into filter coefficients V (k), W (k) and H (k), and R (k) and S in signal X (k) after FFT.
- R (k) is a frequency domain complex signal obtained by transforming a real number real part signal r (n) in the time domain by a real number FFT, and S (k) is represented by (k).
- the real number imaginary part signal s (n) in the time domain is a complex number signal in the frequency domain converted by the real number FFT, that is, the equation (38) is applied to the signal X (k) after the FFT.
- a complex filter coefficient in the frequency domain corresponding to the real filter coefficient when the real part signal r (n) is filtered by a real number operation in the time domain is assigned to V (k). .
- Filter processing with coefficient W (k) for S (k) the digital filter circuit 10 includes a frequency domain complex signal S (k) obtained by transforming an imaginary part signal s (n) in the time domain by a real FFT.
- the filter processing with the filter coefficient W (k) is performed. Therefore, W (k) is assigned a complex filter coefficient in the frequency domain corresponding to the real filter coefficient when filter processing by real number computation is performed on the imaginary part signal s (n) in the time domain.
- R (k) V (k) + jS (k) W (k) is a time composed of two signals obtained by independently filtering the real part signal r (n) and the imaginary part signal s (n) in the time domain. It is a complex signal in the frequency domain corresponding to the signal in the domain.
- the signals obtained by independently filtering the real part signal r (n) and the imaginary part signal s (n) correspond to r ′ (n) and s ′ (n) in FIGS.
- the time domain signal composed of r ′ (n) and s ′ (n) corresponds to x ′ (n) in FIGS.
- R (k) V (k) + jS (k) W (k) is a frequency domain signal corresponding to a time domain signal that is independently filtered in the real part and imaginary part in the time domain. It is.
- a coefficient may be used. That is, H (k) is assigned a complex filter coefficient in the frequency domain corresponding to the complex filter coefficient when filter processing by complex number computation is performed on the complex signal x (n) in the time domain. Good.
- a frequency domain coefficient H (k) corresponding to the filter coefficient is set.
- FFT and IFFT in the digital filter circuit 10 are normal conversions, respectively, and the processing unique to the present invention is not performed. Therefore, the FFT and IFFT may be processed by a circuit outside the digital filter circuit 10. That is, the digital filter circuit may receive only the signal from the external Fourier transform circuit, perform only the filter processing, and output the processing result to the external inverse Fourier transform circuit. Therefore, a block diagram of the digital filter circuit 110 having only the essential configuration of the filter circuit of the present embodiment is as shown in FIG. The block diagram of FIG. 7 is obtained by removing the FFT circuit 13 and the IFFT circuit 14 from the configuration of FIG.
- the digital filter circuit 110 includes a complex conjugate generation circuit 15, a complex conjugate synthesis circuit 16, a filter circuit 21, a filter circuit 22, and a filter coefficient generation circuit 41. Since the function of each block is the same as that of the digital filter circuit 10, description thereof is omitted.
- the filter processing in the frequency domain corresponding to the independent filter processing by the real number operation for each of the real part and the imaginary part of the complex signal in the time domain and the filter processing by the complex number operation for the complex signal in the time domain is performed. Therefore, a desired filter process can be realized by using only one FFT circuit that performs the FFT before the filter process and one IFFT circuit that performs the IFFT after the filter process. As a result, it is possible to reduce the circuit scale and power consumption for performing the filtering process.
- FFT, IFFT, conjugate complex number generation and synthesis, filter coefficient calculation, and filter processing are all processed by components such as individual circuits.
- Each processing of the present invention may be executed by software using a computer provided in a predetermined apparatus, for example, a DSP (Digital Signal Processor), instead of the form as in the first embodiment.
- DSP Digital Signal Processor
- FIGS. 8A and 8B are flowcharts showing an example of the processing procedure of the filter processing program according to the second embodiment of the present invention.
- Signal names such as X (k) and information names such as V (k) used in the following description are all the same as those used in the first embodiment.
- step S0 the DSP obtains C1 (k) and C2 (k) from V (k), W (k), and H (k) (step S0). Note that the process of step 0 only needs to be performed by the filter process (steps S3 and S4) described later, and is not necessarily executed first.
- the DSP performs Fourier transform on the input signal X (n) to generate X (k) and X (N-k) (step S1).
- the DSP obtains a conjugate complex number X * (Nk) of X (Nk) (step S2).
- step S3 the DSP filters X (k) using C1 (k) to generate X ′ (k) (step S3).
- the DSP also filters X * (Nk) using C2 (k) to generate X * ′ (Nk) (step S4).
- the processing order of step S3 and step S4 may be reverse to the above.
- the DSP combines X ′ (k) and X * ′ (Nk) to obtain X ′′ (k) (step S5).
- the DSP performs an inverse Fourier transform on X ′′ (k) to obtain x ′′ (n) (step S6).
- the content of the filter processing of the second embodiment is the same as that of the first embodiment. Therefore, the filtering process of the second embodiment has the same effect as that of the first embodiment.
- filter coefficients C1 (k) and C2 (k) may be calculated in advance by a separate program. In that case, since the process of step 0 is unnecessary, the flowchart showing the operation is as shown in FIG. 8B. Furthermore, individual processing such as FFT and IFFT may be processed by another processor.
- the above filter processing program may be stored in a non-transitory medium such as a ROM (Read Only Memory), a RAM (Random Access Memory), a semiconductor memory device such as a flash memory, an optical disk, a magnetic disk, or a magneto-optical disk. Good.
- a non-transitory medium such as a ROM (Read Only Memory), a RAM (Random Access Memory), a semiconductor memory device such as a flash memory, an optical disk, a magnetic disk, or a magneto-optical disk. Good.
- the first embodiment and the second embodiment may be combined. That is, some processes may be processed by hardware, and other processes may be processed by software.
- the FFT and IFFT may be processed using the FFT circuit 13 and the IFFT circuit 14, respectively, and other processing may be performed by software. Sharing of processing by hardware and processing by software is arbitrary.
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Abstract
Description
(発明の目的)
本発明は上記のような課題を解決するためのものであり、周波数領域におけるディジタルフィルタ処理を行うための回路規模や消費電力の低減を図ることができるディジタルフィルタ回路、ディジタルフィルタ処理方法及びディジタルフィルタ処理プログラム記憶媒体を提供することを目的とする。
(第1の実施形態)
図1は、本発明の第1の実施形態にかかるディジタルフィルタ回路10の構成を示すブロック図である。ディジタルフィルタ回路10は、FFT回路13、IFFT回路14、複素共役生成回路15、複素共役合成回路16、フィルタ回路21、フィルタ回路22、フィルタ係数生成回路41、を備える。
x(n)=r(n)+js(n) ・・・(1)
を入力する。
X(k)=A(k)+jB(k) ・・・(2)
に変換する。
X(N-k)=A(N-k)+jB(N-k) ・・・(3)
を生成して出力する。
X*(N-k)=A(N-k)-jB(N-k) ・・・(4)
を生成する。
C1(k)={V(k)+W(k)}×H(k) ・・・(5)
及び、複素数係数
C2(k)={V(k)-V(k)}×H(k) ・・・(6)
を生成する。
X'(k)=X(k)×C1(k) ・・・(7)
を計算して、複素数信号34として出力する。
X*'(N-k)=X*(N-k)×C2(N-k) ・・・(8)
を計算して、複素数信号35として出力する。
C1(k)=C1I(k)+jC1Q(k) ・・・(9)
C2(k)=C2I(k)+jC2Q(k) ・・・(10)
と書くことができる。
X"(k)=1/2×{X'(k)+X*'(N-k)} ・・・(11)
を計算して、複素数信号36として出力する。
X*(N-k)=A(N-k)-jB(N-k) ・・・(4)
を計算して出力する。
X(k)=XI(k)+jXQ(k) ・・・(12)
X*(N-k)=X*I(N-k)+jX*Q(N-k) ・・・(13)
と書くことができる。
X'(k)=XI'(k)+jXQ'(k)
=X(k)×C1(k) ・・・(14)
を計算して出力する。
XQ'(k)=XI(k)×C1Q(k)+XQ(k)×C1I(k) ・・・(16)
図4は、フィルタ回路22の構成の詳細を示すブロック図である。フィルタ回路22は、複素共役生成回路15が複素信号線33に出力するX*(N-k)(=X*I(N-k)+jX*Q(N-k)。式(13))と複素数係数C2(k)(=C2I(k)+jC2Q(k)。式(10))を入力して、
X*'(N-k)=X*I'(N-k)+jX*Q'(N-k)
=X*(N-k)×C2(N-k) ・・・(17)
を計算して出力する。
X*Q'(N-k)=X*I(N-k)×C2Q(N-k)+X*Q(N-k)×C2I(N-k)・・・(19)
図5は、複素共役合成回路16の構成の詳細を示すブロック図である。複素共役合成回路16は、0≦k≦N-1の周波数番号kのそれぞれについて、フィルタ回路21が複素数信号32に出力するX'(k)(=XI'(k)+jXQ'(k)。式(14))と、フィルタ回路22が複素数信号33に出力するX*'(N-k)(=X*I'(N-k)+jX*Q'(N-k)。式(17))とを入力して、
X"(k)=XI"(k)+jXQ"(k)
=1/2{X'(k)+X*'(N-k)} ・・・(20)
を計算して出力する。
XQ"(k)=1/2{XQ'(k)+X*Q'(N-k)} ・・・(22)
ここで、XI'(k)、XQ'(k)、X*I'(N-k)、X*Q'(N-k)は、それぞれ式(15)、(16)、(18)、(19)の通りである。
V(k)+W(k)=VI(k)+WI(k)+jVQ(k)+jWQ(k) ・・・(23)
V(k)-W(k)=VI(k)-WI(k)+jVQ(k)-jWQ(k) ・・・(24)
である。VI(k)及びVQ(k)は、それぞれV(k)の実数部と虚数部であり、WI(k)及びWQ(k)は、それぞれW(k)の実数部と虚数部である。
H(k)=HI(k)+jHQ(k) ・・・(25)
と書くことができる。
={V(k)+W(k)}×H(k) ・・・(26)
C2(k)=C2I(k)+jC2Q(k)
={V(k)-W(k)}×H(k) ・・・(27)
ここで、C1I(k)、C1Q(k)は、それぞれC1(k)の実数部と虚数部であり、C2I(k)、C2Q(k)は、それぞれC2(k)の実数部と虚数部である。
C1(k)={VI(k)+WI(k)+jVQ(k)+jWQ(k)}×{HI(k)+jHQ(k)}・・・(28)
である。
C1I(k)={VI(k)+WI(k)}×HI(k)-{VQ(k)+WQ(k)}×HQ(k)・・・(29)
C1Q(k)={VQ(k)+WQ(k)}×HI(k)+{VI(k)+WI(k)}×HQ(k)・・・(30)
である。
C2(k)=C2I(k)+jC2Q(k)
={V(k)-W(k)}×H(k)
={VI(k)-WI(k)+jVQ(k)-jWQ(k)}×{HI(k)+jHQ(k)}・・・(31)
である。
C2I(k)={VI(k)-WI(k)}×HI(k)-{VQ(k)-WQ(k)}×HQ(k)・・・(32)
C2Q(k)={VQ(k)-WQ(k)}×HI(k)+{VI(k)-WI(k)}×HQ(k)・・・(33)
である。
X(k)=R(k)+jS(k) ・・・(34)
から、複素共役生成回路15がX*(N-k)を生成する。
ここで、X*(N-k)は、X(N-k)の複素共役である。
X'(k)=X(k)×C1(k)
={R(k)+jS(k)}×{V(k)+W(k)}×H(k)
=R(k)V(k)H(k)+R(k)W(k)H(k)+jS(k)V(k)H(k)+jS(k) W(k)H(k)・・・(36)
となる。
X*'(N-k)=X*(N-k)×C2(N-k)
={R(k)-jS(k)}×{V(k)-W(k)}×H(k)
=R(k)V(k)H(k)-R(k)W(k)H(k)-jS(k)V(k)H(k)+jS(k)W(k)H(k) ・・・(37)
となる。
X"(k)=1/2×{X'(k)+X*'(N-k)}
=1/2×{2×R(k)V(k)H(k)+2×jS(k)W(k)H(k)}
=R(k)V(k)H(k)+jS(k)W(k)H(k)
={R(k)V(k)+jS(k)W(k)}×H(k) ・・・(38)
となる。
1)R(k)に対する係数V(k)によるフィルタ処理
まず、ディジタルフィルタ回路10は、時間領域における実数部信号r(n)が実数FFTにより変換された周波数領域の複素数信号R(k)に対して、フィルタ係数V(k)によるフィルタ処理を行う。従って、V(k)には、実数部信号r(n)に対して時間領域で実数演算によるフィルタ処理を行った場合の、実数フィルタ係数に対応する、周波数領域での複素数フィルタ係数が割り当てられる。
2)S(k)に対する係数W(k)によるフィルタ処理
同様に、ディジタルフィルタ回路10は、時間領域における虚数部信号s(n)が実数FFTにより変換された周波数領域の複素数信号S(k)に対して、フィルタ係数W(k)によるフィルタ処理を行う。従って、W(k)には、虚数部信号s(n)に対して時間領域で実数演算によるフィルタ処理を行った場合の、実数フィルタ係数に対応する、周波数領域での複素数フィルタ係数が割り当てられる。
3)1)、2)のフィルタ処理結果に対する係数H(k)によるフィルタ処理
次に、ディジタルフィルタ回路10は、それぞれ独立に処理された上記の2つのフィルタ処理後の、R(k)V(k)及びS(k)W(k)からなる複素数信号R(k)V(k)+jS(k)W(k)に対して、フィルタ係数H(k)によるフィルタ処理を行う。
(第1の実施形態の効果)
以上のように、本実施形態によれば、複素数信号の実数部及び虚数部のそれぞれに対する時間領域でのフィルタ係数に対応する、2種類の周波数領域のフィルタ係数と、複素信号に対する時間領域でのフィルタ係数に対応する周波数領域の係数を用いたフィルタ処理が行われる。すなわち、時間領域における複素数信号の実数部及び虚数部のそれぞれに対する実数演算による独立したフィルタ処理と、時間領域における複素数信号に対する複素数演算によるフィルタ処理と、に対応する周波数領域におけるフィルタ処理が行われる。従って、フィルタ処理前のFFTを行うFFT回路及びフィルタ処理後のIFFTを行うIFFT回路を、それぞれ1個のみを用いて、所望のフィルタ処理を実現することができる。その結果、フィルタ処理を行うための回路規模や消費電力の低減を図ることができるという効果がある。
(第2の実施形態)
第1の実施形態では、FFT、IFFT、共役複素数の生成及び合成、フィルタ係数の算出、フィルタ処理の各処理は、すべて個別の回路等の構成要素によって処理されることが想定されている。本発明の各処理は、第1の実施形態のような形態ではなく、所定の装置が備えるコンピュータ、例えば、DSP(Digital Signal Processor)等を用いたソフトウェアによって実行されてもよい。
13 FFT回路
14 IFFT回路
15 複素共役生成回路
16 複素共役合成回路
21 フィルタ回路
22 フィルタ回路
31~36 複素数信号
41 フィルタ係数生成回路
45、46 複素数信号
100 ディジタルフィルタ回路
101~103 FIRフィルタ
111~113 周波数領域フィルタ回路
Claims (8)
- フーリエ変換により時間領域の複素数信号が変換され生成された周波数領域の第1の複素数信号を構成するすべての複素数のそれぞれの共役複素数を含む第2の複素数信号を生成する複素共役生成部と、
入力された複素数の第1、第2及び第3の入力フィルタ係数から、複素数の第1及び第2の周波数領域フィルタ係数を生成するフィルタ係数生成部と、
前記第1の複素数信号に対して前記第1の周波数領域フィルタ係数によりフィルタ処理を行い、第3の複素数信号を出力する第1のフィルタ部と、
前記第2の複素数信号に対して前記第2の周波数領域フィルタ係数によりフィルタ処理を行い、第4の複素数信号を出力する第2のフィルタ部と、
前記第3の複素数信号と、前記第4の複素数信号とを合成して第5の複素数信号を生成する複素共役合成部と、
を備えることを特徴とするディジタルフィルタ回路。 - 入力された前記時間領域の複素数入力信号を前記フーリエ変換により前記第1の複素数信号に変換するフーリエ変換部と、
前記第5の複素数信号を、逆フーリエ変換により時間領域の信号に変換する逆フーリエ変換部と、
を備えることを特徴とする請求項1記載のディジタルフィルタ回路。 - 前記フーリエ変換の変換サンプル数をN(NはN>0の整数)とするとき、
前記複素共役生成部は、前記第1の複素数信号に含まれる周波数番号(N-k)の複素数信号の共役複素数を前記第2の複素数信号として生成する
ことを特徴とする請求項1又は2記載のディジタルフィルタ回路。 - 前記複素共役合成部は、0≦k≦N-1の範囲の周波数番号kのそれぞれについて、前記第3の複素数信号に含まれる周波数番号kの第1の複素数データと、前記第4の複素数信号に含まれる周波数番号(N-k)の第2の複素数データとを、複素加算して前記第5の複素数信号を生成する、
ことを特徴とする請求項3に記載のディジタルフィルタ回路。 - 前記フィルタ係数生成部は、
前記第1の周波数領域フィルタ係数を、前記第1の入力フィルタ係数に前記第2の入力フィルタ係数を複素加算したのち、さらに前記第3の入力フィルタ係数を複素乗算して生成し、
前記第2の周波数領域フィルタ係数を、前記第1の入力フィルタ係数から前記第2の入力フィルタ係数を複素減算したのち、さらに前記第3の入力フィルタ係数を複素乗算して生成する、
ことを特徴とする請求項1乃至4のいずれかに記載のディジタルフィルタ回路。 - 前記第1の周波数領域フィルタ係数は、前記複素入力信号に対する時間領域でのフィルタ処理である時間領域フィルタ処理における、前記複素入力信号の実数部に対するフィルタ係数に対応する、周波数領域での複素数フィルタ係数であり、
前記第2の周波数領域フィルタ係数は、前記時間領域フィルタ処理における、前記複素入力信号の虚数部に対するフィルタ係数に対応する、周波数領域での複素数フィルタ係数であり、
前記第3の周波数領域フィルタ係数は、前記時間領域フィルタ処理における、前記複素数入力信号に対するフィルタ係数に対応する、周波数領域での複素数フィルタ係数である
ことを特徴とする請求項1乃至5のいずれかに記載のディジタルフィルタ回路。 - フーリエ変換により時間領域の複素数信号が変換され生成された周波数領域の第1の複素数信号を構成するすべての複素数のそれぞれの共役複素数を含む第2の複素数信号を生成し、
入力された複素数の第1、第2及び第3の入力フィルタ係数から、複素数の第1及び第2の周波数領域フィルタ係数を生成し、
前記第1の複素数信号に対して前記第1の周波数領域フィルタ係数によりフィルタ処理を行い、第3の複素数信号を出力し、
前記第2の複素数信号に対して前記第2の周波数領域フィルタ係数によりフィルタ処理を行い、第4の複素数信号を出力し、
前記第3の複素数信号と、前記第4の複素数信号とを合成して第5の複素数信号を生成する
ことを特徴とするディジタルフィルタ処理方法。 - 演算装置が備えるコンピュータを、
フーリエ変換により時間領域の複素数信号が変換され生成された周波数領域の第1の複素数信号を構成するすべての複素数のそれぞれの共役複素数を含む第2の複素数信号を生成する複素共役生成手段と、
入力された複素数の第1、第2及び第3の入力フィルタ係数から、複素数の第1及び第2の周波数領域フィルタ係数を生成するフィルタ係数生成手段と、
前記第1の複素数信号に対して前記第1の周波数領域フィルタ係数によりフィルタ処理を行い、第3の複素数信号を出力する第1のフィルタ処理手段と、
前記第2の複素数信号に対して前記第2の周波数領域フィルタ係数によりフィルタ処理を行い、第4の複素数信号を出力する第2のフィルタ処理手段と、
前記第3の複素数信号と、前記第4の複素数信号とを合成して第5の複素数信号を生成する複素共役合成手段
として機能させるためのディジタルフィルタ処理プログラムを格納した非一時的な記憶媒体。
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