WO2013123803A1 - Substrat de réseau, procédé de fabrication associé et dispositif d'affichage - Google Patents

Substrat de réseau, procédé de fabrication associé et dispositif d'affichage Download PDF

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Publication number
WO2013123803A1
WO2013123803A1 PCT/CN2012/086854 CN2012086854W WO2013123803A1 WO 2013123803 A1 WO2013123803 A1 WO 2013123803A1 CN 2012086854 W CN2012086854 W CN 2012086854W WO 2013123803 A1 WO2013123803 A1 WO 2013123803A1
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WO
WIPO (PCT)
Prior art keywords
pixel electrode
gate line
forming
critical dimension
data line
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Application number
PCT/CN2012/086854
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English (en)
Chinese (zh)
Inventor
张锋
戴天明
姚琪
于航
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2013123803A1 publication Critical patent/WO2013123803A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and a display device. Background technique
  • the advanced super-dimensional field conversion technology converts the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal cell is narrow. All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .
  • the display device of the ADS mode is designed to increase the viewing angle and improve the display effect
  • the pattern of the second transparent electrode (for example, the pixel electrode) 8 is designed as a multi-domain oblique stripe as shown in FIG.
  • the angle between the generally inclined pixel electrode 8 and the gate line 2 is 7. ⁇ 15. between.
  • the CD measuring device automatically measures the CD value of the pattern perpendicular or parallel to the measuring abutment with high accuracy.
  • the pixel electrode is a slanted stripe, so that a large error is generated when the critical dimension of the pixel electrode is automatically measured, and even automatic measurement cannot be performed, and manual measurement is required manually.
  • a pixel electrode critical size monitoring pattern that is perpendicular or parallel to the measurement base is disposed at a position other than the pixel area.
  • such a pixel electrode critical dimension monitoring pattern and a pixel electrode of a pixel region have a certain difference in critical dimensions, and particularly when the liquid crystal panel has a large size, the difference also increases. Therefore, the pixel electrode critical dimension monitoring pattern located outside the pixel region cannot effectively monitor the critical size of the pixel electrode of the pixel region, and in particular, cannot effectively monitor the uniformity of the critical dimensions of the pixel electrode.
  • an array substrate includes: a substrate, a common electrode, a gate line, a data line, and a pixel electrode, wherein the common electrode is formed on the substrate, and the pixel electrode is formed with oblique stripes above the common electrode.
  • the pixel electrode in the pixel electrode critical dimension monitoring pattern has a key size equal to a critical dimension of the pixel electrode of the pixel electrode region, and the pixel electrode critical dimension monitoring pattern has a size smaller than a size of the void.
  • a method of fabricating an array substrate includes the steps of: forming a common electrode, a gate line, and a data line, wherein at least one void is formed on the gate line and/or the data line; and forming a pixel electrode and forming a pixel electrode key size over the gap Monitoring a pattern, wherein the pixel electrode critical dimension monitoring pattern is perpendicular or parallel to a corresponding gate line or data line and is used to measure a critical dimension of the pixel electrode, wherein a critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern is equal to a pixel A critical dimension of the pixel electrode of the electrode region, the pixel electrode monitoring pattern being formed over the void and having a size smaller than a size of the void.
  • a display device includes the above array substrate.
  • the gate line or/and the data line since a certain gap is reserved on the gate line or/and the data line, it is possible to avoid light due to the gate line or/and the data line when forming an exposure process of the pixel electrode critical size monitoring pattern.
  • the reflection affects the critical dimension of the pixel electrode monitoring pattern above the gate line or/and the data line such that the critical dimension of the pixel electrode monitoring pattern above the gate line or/and the data line is equivalent to the critical size of the pixel electrode within the pixel. Therefore, the key dimensions of the pixel electrodes in the pixel area and the uniformity of the critical dimensions can be measured more quickly and accurately, thereby providing a reference for the optimization design and production process of the liquid crystal panel.
  • FIG. 1 is a schematic structural view of an array substrate of a conventional ADS type display device
  • FIG. 2(a) - 2(f) shows an ADS type display device array substrate according to Example 1 of Embodiment 1 of the present invention.
  • FIG. 2(f) is a cross-sectional view taken along line AA of FIG. 2(e);
  • Figure 3 (a) is a view showing the structure of an array substrate of an ADS type display device prepared by the method of Example 2 of Embodiment 1 of the present invention
  • FIG. 3(b) is a cross-sectional view of the array substrate of FIG. 3(a) taken along line AA; and
  • FIG. 4 is an array of an ADS type display device prepared according to the method of Example 3 of Embodiment 1 of the present invention. Schematic diagram of the structure of the substrate. detailed description
  • This embodiment provides a method for manufacturing an array substrate, and the method includes the following steps.
  • the gate insulating layer, the semiconductor film and the doped semiconductor film, and the source/drain metal film are successively deposited, and the active film is formed by a patterning process.
  • At least one void 21 is formed in the gate line 2 and/or the data line 3.
  • the substrate 100 may be a glass substrate.
  • the semiconductor film may be an a-Si amorphous silicon film, and the doped semiconductor film may be an n + a _si amorphous silicon film.
  • the metal thin film may be an alloy of one or more of Mo, Al, Cu, AlNd.
  • a passivation layer film is deposited on the substrate 100 on which step S1 is completed, and a passivation layer via 71 is formed by a patterning process.
  • the passivation layer may be SiNx, Si0 2 or the like.
  • a transparent conductive film is deposited on the substrate 100 completing step S2, the pixel electrode 8 is formed by a patterning process, and a pixel electrode critical dimension monitoring pattern 81 is formed over the void 21.
  • the pixel electrode critical dimension monitoring pattern 81 is perpendicular or parallel to the corresponding gate line 2 or data line 3. Pixel electricity
  • the critical size of the pixel electrode in the extremely critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region, and the size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21.
  • the transparent conductive film may be ITO, tantalum, or ruthenium or the like.
  • the pixel electrode critical dimension monitoring pattern 81 is formed over at least one of the voids 21, and the pixel electrode critical dimension monitoring pattern 81 may be formed corresponding to each pixel, or may correspond to each pixel (1 ⁇
  • the gate line or the number of data lines is formed by a number of pixels, or is arbitrarily set corresponding to a designated pixel.
  • a pixel electrode critical dimension monitoring pattern 81 may be disposed on the gate line 2 and/or the data line 3 around each pixel, or may be provided in plurality.
  • the voids 21 can be rectangular, square, or other process-implementable graphics.
  • the critical size of the pixel electrode 8 within the pixel. In this way, the critical dimensions of the pixel electrodes in the pixel area and the uniformity of the critical dimensions can be measured more quickly and accurately, thereby providing a reference for the optimal design and production process of the display panel.
  • the pixel electrode critical dimension monitoring pattern 81 is formed over the gate line 2, and the method of fabricating the array substrate includes the following steps.
  • a transparent conductive film is deposited on the substrate 100, the common electrode 1 is formed by a patterning process, and at least one transparent conductive region is formed in a region where the gate line 2 is to be formed between the common electrodes 1.
  • a metal thin film is deposited on the substrate 100 completing the step S1.1, and a gate line 2, a gate electrode and a common electrode line (not shown) are formed by a patterning process, and the gate line 2 is formed.
  • a gate line 2 is formed by a patterning process, and the gate line 2 is formed.
  • S1.3 is as shown in FIG. 2(c), and a gate insulating layer (not shown), a semiconductor film, a doped semiconductor film, and a source/drain metal film are successively deposited on the substrate 100 on which the step S1.2 is completed, and passed through The patterning process forms the active layer 4, the source electrode 5, the drain electrode 6 and the data line 3;
  • a layer of passivation is deposited on the substrate 100 completing step S1.1-1.3.
  • a layer film (not shown), forming a passivation layer via 71 by a patterning process, the passivation layer may be SiNx, Si0 2 or the like;
  • a transparent conductive film is deposited on the substrate 100 completing step S2, and the pixel electrode 8 and the pixel electrode critical dimension monitoring pattern 81 parallel to the gate line 2 are formed by a patterning process, and the pixel electrode is formed.
  • a critical dimension monitoring pattern 81 is formed over the void 21.
  • the size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region.
  • Figure 2 (e) along A-A the cross section of the line is shown in Figure 2 (f).
  • reference numeral 7 denotes a passivation film
  • reference numeral 9 denotes a gate insulating layer.
  • the transparent conductive film region 11 and the common electrode 1 are simultaneously formed, and may be made of ITO,
  • the transparent conductive film region 11 can be rectangular, square, or other process-implementable pattern. By providing the transparent conductive film region 11 under the voids 21, the voids on the gate lines 2 can be repaired to prevent the gate wires 2 from being broken due to poor process.
  • the pixel electrode critical dimension monitoring pattern As shown in FIG. 3( a ) -3 ( b ), in this embodiment, the pixel electrode critical dimension monitoring pattern
  • the method of manufacturing the array substrate includes the following steps.
  • step S1.2 depositing a metal thin film on the substrate 100 completing the step S1.1, forming a gate line 2, a gate electrode and a common electrode line (not shown) by a patterning process;
  • step S1.3 continuously deposits a gate insulating layer 9, a semiconductor film, a doped semiconductor film, and a source/drain metal film on the substrate on which the step S1.2 is completed, and forms the active layer 4, the source electrode 5, and the drain electrode 6 by a patterning process. And the data line 3, at least one gap 21 is formed on the data line 3.
  • the deuterated layer may be SiNx, Si0 2, etc.
  • step S2 Depositing a transparent conductive film on the substrate 100 completing step S2, forming a pixel electrode 8 and a pixel electrode critical dimension monitoring pattern 81 parallel to the data line 3 by a patterning process, and a pixel electrode critical dimension monitoring pattern 81 is formed in the gap 21 Above.
  • the size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region.
  • the pixel electrode monitoring pattern 81 is formed over the gate line 2 and the data line 3, and the method of manufacturing the array substrate includes the following steps.
  • step S1.2 depositing a metal thin film on the substrate 100 completing step S1.1, forming a gate line 2, a gate electrode and a common electrode line by a patterning process, and forming at least one gap 21 on the gate line 2, the void 21 being located in the transparent conductive film region Above, and the size is smaller than the size of the transparent conductive film region;
  • step S1.3 continuously depositing a gate insulating layer (not shown), a semiconductor film, a doped semiconductor film, and a source/drain metal film on the substrate on which step S1.2 is completed, and forming an active layer 4 and a source electrode by a patterning process 5, the drain electrode 6 and the data line 3, forming at least one gap 21 on the data line 3;
  • the passivation layer may be SiNx, Si0 2 or the like;
  • step S3 depositing a transparent conductive film on the substrate 100 completing step S2, forming a pixel electrode 8 and a pixel electrode critical dimension monitoring pattern 81 parallel to the gate line 2 and the data line 3, respectively, by a patterning process, and the pixel electrode critical dimension monitoring pattern 81 is formed above the gap 21.
  • the size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region.
  • the array substrate includes: a substrate 100, a common electrode 1, a common electrode line (not shown), a gate (not shown), a gate line 2, and an active layer. 4.
  • other necessary components of the array substrate well known to those skilled in the art, such as a gate insulating layer and a passivation layer, etc., are not described herein.
  • the common electrode 1 is formed on the substrate 100, and the pixel electrode 8 is formed with oblique stripes above the common electrode 1.
  • At least one gap 21 is left on the gate line 2 and/or the data line 3 (shown in FIG. 2(e) -2(f) is a gap 21 on the gate line 2, but is not limited thereto), the gap 21
  • a pixel electrode critical dimension monitoring pattern 81 is formed above.
  • the pixel electrode critical dimension monitoring pattern 81 is perpendicular or parallel to the corresponding gate line or data line 3 for measuring the key dimension of the pixel electrode Inch.
  • the critical size of the pixel electrode in the pixel electrode critical size monitoring pattern 81 is equal to the critical size of the pixel electrode 8 of the pixel electrode region, and the size of the pixel electrode monitoring pattern 81 is smaller than the size of the gap 21.
  • a transparent conductive film region 11 (shown in FIG. 2) is disposed under the gap 21 of the gate line 2, the width of the transparent conductive film region 11 is not greater than the width of the corresponding gate line 2, and the size is larger than The size of the void 21.
  • the pixel electrode critical dimension monitoring pattern 81 is formed over at least one of the spaces 21, and the pixel electrode monitoring pattern 81 may be formed corresponding to each pixel, or may correspond to every N (1 ⁇ N ⁇ ).
  • the gate line or the number of data lines is formed by a number of pixels, or is arbitrarily set corresponding to a designated pixel.
  • a pixel electrode critical dimension monitoring pattern 81 may be disposed on the gate line 2 and/or the data line 3 around each pixel, or may be provided in plurality.
  • the voids 21 can be rectangular, square, or other process-implementable graphics.
  • the transparent conductive film region 11 can be rectangular, square, or other process-implementable pattern.
  • the transparent conductive film region 11 can be formed simultaneously with the common electrode 1.
  • This embodiment provides a display device including an array substrate.
  • the array substrate includes: a substrate, a common electrode, a gate line, a data line, and a pixel electrode.
  • the common electrode is formed on the substrate, and the pixel electrode is formed with oblique stripes above the common electrode.
  • the pixel electrode critical dimension monitoring The pattern is used to measure the critical dimensions of the pixel electrode.
  • the key dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern is equal to the critical dimension of the pixel electrode of the pixel electrode region, and the size of the pixel electrode critical dimension monitoring pattern is smaller than the size of the void.
  • a transparent conductive film region is formed under the gap of the gate line, the transparent conductive film region having a width not larger than a width of the gate line, and a size larger than a size of the gap.
  • the above display device may be a liquid crystal display device, an organic light emitting diode display device or other display device.

Abstract

La présente invention concerne un substrat de réseau, un procédé de fabrication associé et un dispositif d'affichage. Le substrat de réseau comprend : une base (100), des électrodes communes (1), des lignes de grille (2), des lignes de données (3) et des électrodes de pixels (8). Les électrodes communes (1) sont formées sur la base (100). Les électrodes de pixels (8) sont formées au-dessus des électrodes communes (1), en bandes inclinées. Au moins un espace (21) est formé sur les lignes de grille (2) et/ou sur les lignes de données (3). Un modèle (81) aux dimensions critiques surveillées pour les électrodes de pixels (8), perpendiculaires ou parallèles aux lignes de grille (2) ou aux lignes de données (3) correspondantes, est formé au-dessus de l'espace (21). Le modèle (81) aux dimensions critiques surveillées pour les électrodes de pixels (8) sert à mesurer les dimensions critiques des électrodes de pixels (8). Les dimensions critiques des électrodes de pixels (8) dans le modèle (81) aux dimensions critiques surveillées pour les électrodes de pixels (8) sont égales aux dimensions critiques des électrodes de pixels (8) dans la région des électrodes de pixels (8). Les dimensions dans le modèle (81) aux dimensions critiques surveillées pour les électrodes de pixels (8) sont inférieures à la dimension de l'espace (21).
PCT/CN2012/086854 2012-02-22 2012-12-18 Substrat de réseau, procédé de fabrication associé et dispositif d'affichage WO2013123803A1 (fr)

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CN201210042818.0A CN102629060B (zh) 2012-02-22 2012-02-22 阵列基板及其制造方法、显示装置
CN201210042818.0 2012-02-22

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Families Citing this family (7)

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CN102629060B (zh) * 2012-02-22 2014-04-02 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103576401B (zh) 2012-08-10 2018-05-08 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置
CN103337477B (zh) * 2013-05-27 2015-06-03 北京京东方光电科技有限公司 阵列基板的制备方法及阵列基板和显示装置
CN103323988B (zh) 2013-06-27 2016-08-31 京东方科技集团股份有限公司 透明电极、阵列基板和液晶显示装置
CN104914599B (zh) * 2015-06-03 2018-05-04 南京中电熊猫液晶显示科技有限公司 一种液晶阵列基板
CN105159486A (zh) 2015-07-14 2015-12-16 京东方科技集团股份有限公司 Ads阵列基板及其制作方法、显示器件
CN111665667B (zh) * 2020-06-17 2023-06-27 Tcl华星光电技术有限公司 阵列基板及显示面板

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