WO2013123803A1

WO2013123803A1 - Array substrate, method for fabricating same, and display device

Info

Publication number: WO2013123803A1
Application number: PCT/CN2012/086854
Authority: WO
Inventors: 张锋; 戴天明; 姚琪; 于航
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-02-22
Filing date: 2012-12-18
Publication date: 2013-08-29
Also published as: CN102629060A; CN102629060B

Abstract

An array substrate, a method for fabricating an array substrate, and a display device. The array substrate comprises: a base (100), common electrodes (1), grid lines (2), data lines (3), and pixel electrodes (8). The common electrodes (1) are formed on the base (100). The pixel electrodes (8) are formed above the common electrodes (1) in inclined stripes. At least one gap (21) is formed on the grid lines (2) and/or on the data lines (3). A critical dimension monitored pattern (81) for the pixel electrodes (8) perpendicular or parallel to the corresponding grid lines (2) or data lines (3) is formed above the gap (21). The critical dimension monitored pattern (81) for the pixel electrodes (8) is used to measure the critical dimensions of the pixel electrodes (8). The critical dimensions of the pixel electrodes (8) in the critical dimension monitored pattern (81) for the pixel electrodes (8) are equal to the critical dimensions of the pixel electrodes (8) in the region of the pixel electrodes (8), and the dimensions in the critical dimension monitored pattern (81) for the pixel electrodes (8) are smaller than the dimension of the gap (21).

Description

Array substrate, manufacturing method thereof, and display device

Embodiments of the present invention relate to an array substrate, a method of fabricating the array substrate, and a display device. Background technique

The advanced super-dimensional field conversion technology (ADS) converts the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal cell is narrow. All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency. Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura. .

Key dimensions of the pixel electrode on the array substrate in an ADS mode display device ( Critical

Dimension, CD) has a great influence on the display quality of the display device. If the critical dimension of the pixel electrode on the entire array substrate is not uniform, the electric field between the pixel electrode and the common electrode is not uniform, thereby affecting the final display effect. At present, the display device of the ADS mode is designed to increase the viewing angle and improve the display effect, and the pattern of the second transparent electrode (for example, the pixel electrode) 8 is designed as a multi-domain oblique stripe as shown in FIG. The angle between the generally inclined pixel electrode 8 and the gate line 2 is 7. ~15. between.

In the production process, the CD measuring device automatically measures the CD value of the pattern perpendicular or parallel to the measuring abutment with high accuracy. However, in the above case, the pixel electrode is a slanted stripe, so that a large error is generated when the critical dimension of the pixel electrode is automatically measured, and even automatic measurement cannot be performed, and manual measurement is required manually. At present, when designing an ADS type display device, a pixel electrode critical size monitoring pattern that is perpendicular or parallel to the measurement base is disposed at a position other than the pixel area. However, such a pixel electrode critical dimension monitoring pattern and a pixel electrode of a pixel region have a certain difference in critical dimensions, and particularly when the liquid crystal panel has a large size, the difference also increases. Therefore, the pixel electrode critical dimension monitoring pattern located outside the pixel region cannot effectively monitor the critical size of the pixel electrode of the pixel region, and in particular, cannot effectively monitor the uniformity of the critical dimensions of the pixel electrode. Summary of the invention

According to an embodiment of the invention, an array substrate is provided. The array substrate includes: a substrate, a common electrode, a gate line, a data line, and a pixel electrode, wherein the common electrode is formed on the substrate, and the pixel electrode is formed with oblique stripes above the common electrode. Forming at least one gap on the gate line and/or the data line, and forming a pixel electrode critical dimension monitoring pattern vertically or parallel to a corresponding gate line or data line above the gap, the pixel electrode key size monitoring The pattern is used to measure the critical dimensions of the pixel electrode. The pixel electrode in the pixel electrode critical dimension monitoring pattern has a key size equal to a critical dimension of the pixel electrode of the pixel electrode region, and the pixel electrode critical dimension monitoring pattern has a size smaller than a size of the void.

According to another embodiment of the present invention, a method of fabricating an array substrate is provided. The method includes the steps of: forming a common electrode, a gate line, and a data line, wherein at least one void is formed on the gate line and/or the data line; and forming a pixel electrode and forming a pixel electrode key size over the gap Monitoring a pattern, wherein the pixel electrode critical dimension monitoring pattern is perpendicular or parallel to a corresponding gate line or data line and is used to measure a critical dimension of the pixel electrode, wherein a critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern is equal to a pixel A critical dimension of the pixel electrode of the electrode region, the pixel electrode monitoring pattern being formed over the void and having a size smaller than a size of the void.

According to still another embodiment of the present invention, a display device is provided. The display device includes the above array substrate.

In the embodiment of the present invention, since a certain gap is reserved on the gate line or/and the data line, it is possible to avoid light due to the gate line or/and the data line when forming an exposure process of the pixel electrode critical size monitoring pattern. The reflection affects the critical dimension of the pixel electrode monitoring pattern above the gate line or/and the data line such that the critical dimension of the pixel electrode monitoring pattern above the gate line or/and the data line is equivalent to the critical size of the pixel electrode within the pixel. Therefore, the key dimensions of the pixel electrodes in the pixel area and the uniformity of the critical dimensions can be measured more quickly and accurately, thereby providing a reference for the optimization design and production process of the liquid crystal panel. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. . 1 is a schematic structural view of an array substrate of a conventional ADS type display device; FIG. 2(a) - 2(f) shows an ADS type display device array substrate according to Example 1 of Embodiment 1 of the present invention. Each step of the method, wherein FIG. 2(f) is a cross-sectional view taken along line AA of FIG. 2(e);

Figure 3 (a) is a view showing the structure of an array substrate of an ADS type display device prepared by the method of Example 2 of Embodiment 1 of the present invention;

3(b) is a cross-sectional view of the array substrate of FIG. 3(a) taken along line AA; and FIG. 4 is an array of an ADS type display device prepared according to the method of Example 3 of Embodiment 1 of the present invention. Schematic diagram of the structure of the substrate. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Example 1

This embodiment provides a method for manufacturing an array substrate, and the method includes the following steps.

51. After forming the common electrode 1, the common electrode line, and the gate and the gate line 2 on the substrate 100, the gate insulating layer, the semiconductor film and the doped semiconductor film, and the source/drain metal film are successively deposited, and the active film is formed by a patterning process. Layer 4, source electrode 5, drain electrode 6, and data line 3. At least one void 21 is formed in the gate line 2 and/or the data line 3.

The substrate 100 may be a glass substrate. The semiconductor film may be an a-Si amorphous silicon film, and the doped semiconductor film may be an _n + _a _si amorphous silicon film. The metal thin film may be an alloy of one or more of Mo, Al, Cu, AlNd.

52. A passivation layer film is deposited on the substrate 100 on which step S1 is completed, and a passivation layer via 71 is formed by a patterning process. The passivation layer may be SiNx, Si0 ₂ or the like.

53. A transparent conductive film is deposited on the substrate 100 completing step S2, the pixel electrode 8 is formed by a patterning process, and a pixel electrode critical dimension monitoring pattern 81 is formed over the void 21. The pixel electrode critical dimension monitoring pattern 81 is perpendicular or parallel to the corresponding gate line 2 or data line 3. Pixel electricity The critical size of the pixel electrode in the extremely critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region, and the size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21. The transparent conductive film may be ITO, tantalum, or ruthenium or the like.

In the method of the embodiment, the pixel electrode critical dimension monitoring pattern 81 is formed over at least one of the voids 21, and the pixel electrode critical dimension monitoring pattern 81 may be formed corresponding to each pixel, or may correspond to each pixel (1<Ν< The gate line or the number of data lines is formed by a number of pixels, or is arbitrarily set corresponding to a designated pixel. A pixel electrode critical dimension monitoring pattern 81 may be disposed on the gate line 2 and/or the data line 3 around each pixel, or may be provided in plurality. The voids 21 can be rectangular, square, or other process-implementable graphics.

In the method of the present embodiment, since at least one void 21 is formed on the gate line 2 or/and the data line 3, it is possible to avoid the gate line 2 or / at the time of forming the exposure process of the pixel electrode critical size monitoring pattern 81. And the reflection of light by the data line 2 affects the critical dimension of the pixel electrode monitoring pattern 81 above the gate line 2 or/and the data line 3, such that the critical dimension of the pixel electrode monitoring pattern above the gate line 2 or/and the data line 3 is equivalent The critical size of the pixel electrode 8 within the pixel. In this way, the critical dimensions of the pixel electrodes in the pixel area and the uniformity of the critical dimensions can be measured more quickly and accurately, thereby providing a reference for the optimal design and production process of the display panel.

Example 1

In the present embodiment, the pixel electrode critical dimension monitoring pattern 81 is formed over the gate line 2, and the method of fabricating the array substrate includes the following steps.

As shown in FIG. 2( a ), a transparent conductive film is deposited on the substrate 100, the common electrode 1 is formed by a patterning process, and at least one transparent conductive region is formed in a region where the gate line 2 is to be formed between the common electrodes 1. Film area 11;

S1.2, as shown in FIG. 2(b), a metal thin film is deposited on the substrate 100 completing the step S1.1, and a gate line 2, a gate electrode and a common electrode line (not shown) are formed by a patterning process, and the gate line 2 is formed. Forming at least one void 21 thereon, the void 21 being located above the transparent conductive film region 11 (not shown in FIG. 2(b)), and having a size smaller than the size of the transparent conductive film region 11;

S1.3 is as shown in FIG. 2(c), and a gate insulating layer (not shown), a semiconductor film, a doped semiconductor film, and a source/drain metal film are successively deposited on the substrate 100 on which the step S1.2 is completed, and passed through The patterning process forms the active layer 4, the source electrode 5, the drain electrode 6 and the data line 3;

S2. As shown in FIG. 2(d), a layer of passivation is deposited on the substrate 100 completing step S1.1-1.3. a layer film (not shown), forming a passivation layer via 71 by a patterning process, the passivation layer may be SiNx, Si0 ₂ or the like;

S3. As shown in FIG. 2(e), a transparent conductive film is deposited on the substrate 100 completing step S2, and the pixel electrode 8 and the pixel electrode critical dimension monitoring pattern 81 parallel to the gate line 2 are formed by a patterning process, and the pixel electrode is formed. A critical dimension monitoring pattern 81 is formed over the void 21. The size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region. Figure 2 (e) along A-A, the cross section of the line is shown in Figure 2 (f). In Fig. 2(f), reference numeral 7 denotes a passivation film, and reference numeral 9 denotes a gate insulating layer.

In the present example, the transparent conductive film region 11 and the common electrode 1 are simultaneously formed, and may be made of ITO,

Made of ΙΖΟ or ΑΖΟ. The transparent conductive film region 11 can be rectangular, square, or other process-implementable pattern. By providing the transparent conductive film region 11 under the voids 21, the voids on the gate lines 2 can be repaired to prevent the gate wires 2 from being broken due to poor process.

Example 2

As shown in FIG. 3( a ) -3 ( b ), in this embodiment, the pixel electrode critical dimension monitoring pattern

81 is formed over the data line 3, and the method of manufacturing the array substrate includes the following steps.

S1.1 depositing a transparent conductive film on the substrate 100 to form a common electrode by a patterning process

1 ;

S1.2 depositing a metal thin film on the substrate 100 completing the step S1.1, forming a gate line 2, a gate electrode and a common electrode line (not shown) by a patterning process;

S1.3 continuously deposits a gate insulating layer 9, a semiconductor film, a doped semiconductor film, and a source/drain metal film on the substrate on which the step S1.2 is completed, and forms the active layer 4, the source electrode 5, and the drain electrode 6 by a patterning process. And the data line 3, at least one gap 21 is formed on the data line 3.

52. Depositing a passivation layer film 7 on the substrate 100 of the step S1.1-1.3, forming a passivation layer via 71 by a patterning process, the deuterated layer may be SiNx, Si0 _2, etc.

53. Depositing a transparent conductive film on the substrate 100 completing step S2, forming a pixel electrode 8 and a pixel electrode critical dimension monitoring pattern 81 parallel to the data line 3 by a patterning process, and a pixel electrode critical dimension monitoring pattern 81 is formed in the gap 21 Above. The size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region. Example 3

As shown in FIG. 4, in the present embodiment, the pixel electrode monitoring pattern 81 is formed over the gate line 2 and the data line 3, and the method of manufacturing the array substrate includes the following steps.

S1.1 depositing a transparent conductive film on the substrate 100, forming a common electrode 1 by a patterning process, and forming at least one transparent conductive film region (not shown) between the common electrodes 1 to form a gate line 2;

S1.2 depositing a metal thin film on the substrate 100 completing step S1.1, forming a gate line 2, a gate electrode and a common electrode line by a patterning process, and forming at least one gap 21 on the gate line 2, the void 21 being located in the transparent conductive film region Above, and the size is smaller than the size of the transparent conductive film region;

S1.3 continuously depositing a gate insulating layer (not shown), a semiconductor film, a doped semiconductor film, and a source/drain metal film on the substrate on which step S1.2 is completed, and forming an active layer 4 and a source electrode by a patterning process 5, the drain electrode 6 and the data line 3, forming at least one gap 21 on the data line 3;

S2. depositing a deuterated layer film (not shown) on the substrate 100 completing the steps S1.1-1.3, forming a passivation layer via 71 by a patterning process, the passivation layer may be SiNx, Si0 ₂ or the like;

S3. depositing a transparent conductive film on the substrate 100 completing step S2, forming a pixel electrode 8 and a pixel electrode critical dimension monitoring pattern 81 parallel to the gate line 2 and the data line 3, respectively, by a patterning process, and the pixel electrode critical dimension monitoring pattern 81 is formed above the gap 21. The size of the pixel electrode critical dimension monitoring pattern 81 is smaller than the size of the void 21, and the critical dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern 81 is equal to the critical dimension of the pixel electrode 8 of the pixel electrode region.

Example 2

This embodiment provides an array substrate. As shown in FIG. 2(e) -2(f), the array substrate includes: a substrate 100, a common electrode 1, a common electrode line (not shown), a gate (not shown), a gate line 2, and an active layer. 4. The source electrode 5, the drain electrode 6, the data line 3, and the pixel electrode 8. It should be noted that, for the sake of brevity, other necessary components of the array substrate well known to those skilled in the art, such as a gate insulating layer and a passivation layer, etc., are not described herein.

In the array substrate of the present embodiment, the common electrode 1 is formed on the substrate 100, and the pixel electrode 8 is formed with oblique stripes above the common electrode 1. At least one gap 21 is left on the gate line 2 and/or the data line 3 (shown in FIG. 2(e) -2(f) is a gap 21 on the gate line 2, but is not limited thereto), the gap 21 A pixel electrode critical dimension monitoring pattern 81 is formed above. The pixel electrode critical dimension monitoring pattern 81 is perpendicular or parallel to the corresponding gate line or data line 3 for measuring the key dimension of the pixel electrode Inch. The critical size of the pixel electrode in the pixel electrode critical size monitoring pattern 81 is equal to the critical size of the pixel electrode 8 of the pixel electrode region, and the size of the pixel electrode monitoring pattern 81 is smaller than the size of the gap 21. Preferably, a transparent conductive film region 11 (shown in FIG. 2) is disposed under the gap 21 of the gate line 2, the width of the transparent conductive film region 11 is not greater than the width of the corresponding gate line 2, and the size is larger than The size of the void 21.

In the array substrate of the present embodiment, the pixel electrode critical dimension monitoring pattern 81 is formed over at least one of the spaces 21, and the pixel electrode monitoring pattern 81 may be formed corresponding to each pixel, or may correspond to every N (1<N<< The gate line or the number of data lines is formed by a number of pixels, or is arbitrarily set corresponding to a designated pixel. A pixel electrode critical dimension monitoring pattern 81 may be disposed on the gate line 2 and/or the data line 3 around each pixel, or may be provided in plurality. The voids 21 can be rectangular, square, or other process-implementable graphics. The transparent conductive film region 11 can be rectangular, square, or other process-implementable pattern. The transparent conductive film region 11 can be formed simultaneously with the common electrode 1.

Example 3

This embodiment provides a display device including an array substrate.

The array substrate includes: a substrate, a common electrode, a gate line, a data line, and a pixel electrode. The common electrode is formed on the substrate, and the pixel electrode is formed with oblique stripes above the common electrode. Having at least one void on the gate line and/or the data line, above which is formed a pixel electrode critical dimension monitoring pattern perpendicular or parallel to a corresponding gate line or data line, the pixel electrode critical dimension monitoring The pattern is used to measure the critical dimensions of the pixel electrode. The key dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern is equal to the critical dimension of the pixel electrode of the pixel electrode region, and the size of the pixel electrode critical dimension monitoring pattern is smaller than the size of the void.

Preferably, a transparent conductive film region is formed under the gap of the gate line, the transparent conductive film region having a width not larger than a width of the gate line, and a size larger than a size of the gap.

The above display device may be a liquid crystal display device, an organic light emitting diode display device or other display device.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

An array substrate, comprising: a substrate, a common electrode, a gate line, a data line, and a pixel electrode, wherein the common electrode is formed on the substrate, and the pixel electrode is formed by oblique stripes on the common Above the electrode, where:

Forming at least one gap on the gate line and/or the data line, above which is formed a pixel electrode critical dimension monitoring pattern perpendicular or parallel to a corresponding gate line or data line, the pixel electrode critical dimension monitoring The pattern is used to measure the critical dimensions of the pixel electrode;

The key dimension of the pixel electrode in the pixel electrode critical dimension monitoring pattern is equal to the critical dimension of the pixel electrode of the pixel electrode region, and the size of the pixel electrode critical dimension monitoring pattern is smaller than the size of the void.

The array substrate of claim 1, wherein the pixel electrode critical dimension monitoring pattern is formed over at least one of the voids.

3. The array substrate according to claim 1, wherein the void is rectangular or square.

4. The array substrate according to claim 1, wherein a transparent conductive film region is formed under the gap of the gate line, the transparent conductive film region having a width not greater than a width of the gate line, and a size larger than The size of the gap.

The array substrate according to claim 4, wherein the transparent conductive film region is disposed in the same layer as the common electrode, and the transparent conductive film region is rectangular or square.

6. The array substrate of claim 1, wherein the array substrate further comprises a gate insulating layer to cover the common electrode and the gate line.

The array substrate according to claim 1, wherein the array substrate further comprises a passivation layer to cover the data line, and the pixel electrode and the pixel electrode critical dimension monitoring pattern are formed on the passivation layer .

8. A method of fabricating an array substrate, wherein the method comprises the steps of:

Forming a common electrode, a gate line, and a data line, wherein at least one gap is formed on the gate line and/or the data line;

Forming a pixel electrode and forming a pixel electrode critical dimension monitoring pattern over the void, wherein the pixel electrode critical dimension monitoring pattern is perpendicular or parallel to a corresponding gate line or data line and is used to measure a critical dimension of the pixel electrode, The key of the pixel electrode in the pixel electrode critical dimension monitoring pattern A size equal to a critical size of the pixel electrode of the pixel electrode region, the pixel electrode monitoring pattern being formed over the void and having a size smaller than a size of the void.

9. The method of claim 8, wherein the steps of forming the common electrode, the gate line, and the data line comprise:

Forming a common electrode and forming at least one transparent conductive film region in a region where the gate line is to be formed between the common electrodes, the transparent conductive film region having a width not greater than a width of a gate line to be formed; forming a gate line and Forming at least one gap on the gate line, the gap being above the transparent conductive film region and having a size smaller than a size of the transparent conductive film region;

Form a data line.

10. The method of claim 8, wherein the steps of forming the common electrode, the gate line, and the data line comprise:

Forming a common electrode;

Forming a gate line;

A data line is formed and at least one void is formed on the data line.

11. The method of claim 8, wherein the steps of forming the common electrode, the gate line, and the data line comprise:

Forming a common electrode, and forming at least one transparent conductive film region in a region where the gate line is to be formed between the common electrodes, the transparent conductive film region having a width not greater than a width of a gate line to be formed; forming a gate line and being on the gate line Forming at least one void thereon, the void being located above the transparent conductive film region and having a size smaller than a size of the transparent conductive film region;

A data line is formed and at least one void is formed on the data line.

12. The method of any of claims 8-11, wherein the pixel electrode critical dimension monitoring pattern is formed over at least one of the voids.

13. The method of any of claims 8-11, wherein the void is rectangular or square.

14. The method of any of claims 8-11, wherein the method further comprises forming a gate insulating layer overlying the common electrode and the gate line.

The method according to any one of claims 8 to 11, wherein the method further comprises forming a passivation layer covering the data line, the pixel electrode and the pixel electrode critical dimension monitoring pattern Formed on the passivation layer.

The method according to claim 9 or 11, wherein said transparent conductive film region is rectangular Or square.

A display device comprising the array substrate of claim 1.