WO2013123630A1 - 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 - Google Patents

三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 Download PDF

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Publication number
WO2013123630A1
WO2013123630A1 PCT/CN2012/001557 CN2012001557W WO2013123630A1 WO 2013123630 A1 WO2013123630 A1 WO 2013123630A1 CN 2012001557 W CN2012001557 W CN 2012001557W WO 2013123630 A1 WO2013123630 A1 WO 2013123630A1
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substrate
intermetallic compound
layer
hole
interconnect structure
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PCT/CN2012/001557
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English (en)
French (fr)
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于大全
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江苏物联网研究发展中心
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Definitions

  • the invention relates to a vertical interconnect structure and a preparation method thereof, in particular to a vertical via interconnect structure filled with an intermetallic compound for three-dimensional packaging and a preparation method thereof, and belongs to the field of three-dimensional integration technology of microelectronic package.
  • SiP System-in-package
  • TSV through-silicon via
  • the main problem with TSV technology in application is still the complexity of the process and the high cost.
  • electroplating and filling holes there are the following types: (1), electroplating and filling holes; (2) chemical chemical deposition (CVD); (3) filling with liquid solder; (4), conductive adhesive filling.
  • the use of electroplating holes is mainly based on copper electroplating.
  • the advantage is that copper has good electrical conductivity.
  • electroplating requires good seed layer fabrication, long electroplating time, complicated electroplating process and high cost; Micron holes, electroplated holes are difficult to achieve.
  • the main material of chemical vapor deposition is tungsten, which can fill the small-aperture through-hole.
  • solder filling is the use of low melting point solder to fill micropores in a liquid state, which has the advantages of fastness and low cost.
  • solder has poor conductivity, and silicon
  • CTE Coefficient of Thermal Expansion
  • the CTE (Coefficient of Thermal Expansion) of the material has a large difference, which brings about stress problems, and the melting point of the solder is low, which causes many problems in the subsequent process.
  • Filling with conductive paste also simplifies the filling process, but the conductivity is poor and it is difficult to fill the holes with smaller diameters.
  • the object of the present invention is to overcome the deficiencies in the prior art, and provide a vertical via interconnect structure filled with an intermetallic compound for three-dimensional packaging and a preparation method thereof, which can effectively reduce the manufacturing cost, simplify the process steps, and improve the pass rate. Safe and reliable.
  • the vertical via interconnect structure filled with the intermetallic compound for three-dimensional encapsulation includes a substrate, and the substrate is provided with at least one through hole penetrating through the substrate vertically;
  • the through hole is filled with a vertically continuous intermetallic compound, the intermetallic compound layer and the substrate An adhesive layer is provided between them.
  • the substrate and the adhesion layer include an insulating layer, and the adhesion layer is adhered to the inner wall of the through hole through the insulating layer.
  • a residual metal layer is further interposed between the intermetallic compound layer and the adhesion layer, and the intermetallic compound layer is connected to the adhesion layer through the residual metal layer.
  • the intermetallic compound layer is formed by thermal diffusion of a high temperature metal layer filled in the through hole and a low melting point solder filler.
  • the high temperature metal layer is one or more of materials of Cu, Ni, Ag, Pd, Au or Fe; the low melting point filler is Sn, In, SnAg, Snln, SnBi, SnPb, SnAgCu, InAg, InSn One or several of the materials.
  • the intermetallic compound layer is one or more of Cu-Sn, Ni-Sn, Cn-In, Ni-In, Ag-Sn, Au-Sn, Ag-In, Au-In, and the like.
  • the intermetallic compound layer includes a high temperature metal phase, and the high temperature metal phase has a melting point higher than 300 degrees.
  • the material of the insulating layer is one or more of Si0 2 and SixN ⁇ .
  • a method for preparing a vertical via interconnect structure filled with an intermetallic compound in a three-dimensional package comprises the following steps:
  • a desired low melting point solder filler is formed in the through hole by inserting the substrate into a molten low melting solder bath or by filling the molten low melting solder in a vacuum environment.
  • the material of the substrate includes silicon, gallium arsenide, gallium nitride or glass.
  • the through hole includes a residual metal layer or a high temperature metal phase.
  • the high temperature metal phase has a melting point higher than 300 degrees, and the high temperature metal phase includes Ag 3 Sn, Cu 6 Sn 5 , a Pb-rich phase or a Bi-rich phase.
  • the substrate when the substrate is a conductor or a semiconductor substrate, an insulating layer is deposited on the surface of the substrate, the insulating layer covers the surface of the substrate and covers the inner wall surface of the through hole; when the substrate and the through hole are After the insulating layer is formed, the adhesion layer covers the surface of the substrate and the insulating layer inside the via.
  • the material of the insulating layer is one or more of sio 2 and sysi ⁇ .
  • the high temperature metal layer is one or more of materials of Cu, Ni, Ag, Pd, Au or Fe.
  • the low melting point solder filler is one or more of materials of Sn, In, SnAg, Snln, SnBi, SnPb, SnAgCu, InAg, and InSn.
  • the material of the adhesion layer is Ti, TiN or Ta.
  • the invention has the advantages that: at least one vertically penetrating through hole is arranged in the substrate, an insulating layer is grown on the inner wall of the through hole, and the intermetallic compound layer is filled in the through hole, and the intermetallic compound layer and the insulating layer are adhered
  • the electrical connection required in the three-dimensional stacking can be completed by the intermetallic compound layer, the entire forming process is convenient, the process complexity and the manufacturing cost are reduced; thus, the vertical interconnect structure can be fabricated on the integrated circuit, and the passive interconnect structure can also be passively
  • the adapter plate is made on the substrate to improve the pass rate and is safe and reliable.
  • Figure 1 is a schematic view of the structure of the present invention.
  • FIG. 2 is a schematic view showing the structure of a residual metal layer and a residual metal phase according to the present invention.
  • Fig. 3 is a view showing the state of use after the adapter plate is manufactured according to the present invention.
  • Fig. 4 is a cross-sectional view showing an insulating layer grown in a through hole.
  • Figure 5 is a cross-sectional view showing the adhesion layer formed in the via hole.
  • Fig. 6 is a cross-sectional view showing a high temperature metal layer obtained in the through hole.
  • Fig. 7 is a cross-sectional view showing a filling of a low melting point solder filler body in a through hole.
  • Figure 8 is a schematic view of the structure after flat polishing.
  • Fig. 9 is a cross-sectional view showing the formation of an intermetallic compound after thermal diffusion of a high temperature metal and a low melting point solder filler.
  • Figure 10 is a cross-sectional view showing a residual metal layer after thermal diffusion of a high temperature metal and a low melting point solder filler body.
  • the vertical interconnect structure in the present invention includes a substrate 10 made of silicon, gallium arsenide, gallium nitride or glass, and a substrate. There is provided at least one through hole 12 penetrating through the substrate 10 vertically.
  • an insulating layer 20 is grown on the inner wall of the via hole 12, and the insulating layer 20 is one or more of SiO 2 , Si x NL X .
  • the through hole 12 in which the insulating layer 20 is grown on the inner wall is filled with the intermetallic compound layer 40, and the adhesion layer 30 is provided between the intermetallic compound layer 40 and the insulating layer 20, and the intermetallic compound layer can be formed by the adhesion layer 30.
  • 40 can be effectively filled in the through hole 12 during the formation process, and the intermetallic compound layer 40 fills the entire through hole 12.
  • the material of the adhesion layer 30 is Ti, TiN or Ta. When the substrate 10 is an insulating material, the insulating layer 20 may not be disposed in the through hole 12, and the adhesion layer 30 may be directly disposed in the through hole 12.
  • the intermetallic compound layer 40 is formed after the high temperature metal layer 24 and the low melting point solder filler body 26 in the through hole 12 are subjected to the required heat diffusion; in the process of forming the intermetallic compound layer 40, due to the thickness of the high temperature metal layer 24 Otherwise, a residual metal layer 32 remains between the adhesion layer 30 and the intermetallic compound layer 40; due to the different arrangement of the low melting point solder filler 26, there may be a high temperature metal phase 36 in the intermetallic compound layer 40;
  • the high temperature metal layer 24 is Cu, and the low melting point solder filler body 26 is made of SnBi.
  • the high temperature metal layer 24 is one or more of Cu, Ni, Ag, Pd, Au or Fe.
  • the low melting point solder filler body 26 is one or more of Sn, In, SnAg, Snln, SnBi, SnPb, SnAgCu, InAg, and InSn.
  • the intermetallic compound layer 40 is one or more of Cu—Sn, Ni—Sn, Cn—In, Ni—In, Ag—Sn, Au—Sn, Ag—In, and Au—In.
  • the high temperature metal phase 36 includes Ag 3 Sn, Cu 6 Sn 5 , a Pb-rich phase, or a Bi-rich phase.
  • the above vertical interconnection structure can be realized by the following specific process steps, specifically:
  • a substrate 10 is provided, and a through hole 12 penetrating through the substrate 10 is formed in the substrate 10.
  • the substrate 10 is selected from an 8-inch silicon wafer, and the silicon crystal is selected. The thickness of the circle is reduced to
  • a through hole 12 is formed in the silicon wafer by a conventional process, and the through hole 12 has a hole diameter of generally 30 ⁇ m;
  • an insulating layer 20 is deposited on the surface of the substrate 10, and the insulating layer 20 covers the surface of the substrate 10 and covers the inner wall surface of the through hole 12;
  • the adhesion layer 30 covers the surface of the substrate 10 and the insulating layer 20 in the via 12;
  • the oxide layer is thermally oxidized on the surface of the silicon wafer to obtain a surface on the substrate 10.
  • the thickness of the Ti layer is between several tens and hundreds of micrometers, and can be set as needed, thereby being used as a paste.
  • the layer 30 and the barrier layer; during the deposition of Ti, will cover the corresponding insulating layer 20 in the through hole 12;
  • the high temperature metal layer 24 may be formed by depositing metal on the adhesion layer 30 and then plating or electroless plating to a desired thickness.
  • the high temperature metal layer 24 is made of Cu. First, the physical vapor deposition of Cu, and then electroplating to 6 microns; when the via 12 has an insulating layer 20 ⁇ , the high temperature metal layer 24 is insulated from the substrate 10 by the insulating layer 24;
  • the substrate 10 when the low-melting solder is filled in the through hole 12, the substrate 10 can be inserted into the molten low-melting solder bath, or the molten low-melting solder can be potted under vacuum; due to surface tension In a short time, the filling can be completed; in the specific implementation of the present invention, the low melting point solder is Sn, the temperature during filling is higher than the melting point of Sn, for example, can be 260 degrees;
  • the bumps of the lower:) f point solder filler body 26 are formed with bumps.
  • the height is higher than the surface of the substrate 10; therefore, the bumps and some material layers on the surface of the substrate 10 are removed by a planarization polishing operation; the planarization is performed by mechanical chemical polishing (CMP) or other planarization process; f.
  • CMP mechanical chemical polishing
  • the low-melting-point solder filler body 26 and the high-temperature metal layer 24 are thermally diffused at a desired temperature until the low-melting-point solder filler body 26 is completely melted, and the intermetallic compound layer 40 is formed with the high-temperature metal layer 24.
  • the intermetallic compound layer 40 In order to form the desired intermetallic compound layer 40, it is necessary to carry out thermal diffusion treatment at a desired temperature; the heat diffusion treatment is performed for the time when the low melting point solder filler body 26 can be diffused and melted; In the case of the material, the intermetallic compound layer 40 is a mixture of Cu 6 Sn 5 , Cu 3 Sn, Cu 6 Sn 5 , and Cu 3 Sn. When the high temperature metal layer 24 exceeds a certain thickness, there is a residue after thermal diffusion, such as the residual metal layer 32 in FIGS. 2 and 10.
  • FIG 3 is a schematic view showing the structure of an adapter plate after forming the vertical interconnection structure of the present invention.
  • the package can be completed by the adapter board.
  • At least one vertically penetrating through hole 12 is provided in the substrate 10 of the present invention, and is filled in the through hole 12 by a vertically continuous intermetallic compound layer 40, and the intermetallic compound layer 40 and the substrate 10 have an adhesion layer 30 therebetween.
  • the intermetallic compound layer 40 Through the intermetallic compound layer 40, the electrical connection required in the three-dimensional stacking can be completed, the entire forming process is convenient, the process complexity and the manufacturing cost are reduced; thereby, the vertical interconnect structure can be fabricated on the integrated circuit, and the passive interconnect structure can also be passively
  • the adapter plate is made on the substrate to improve the pass rate and is safe and reliable.

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Abstract

提供一种三维封装用金属间化合物填充的垂直通孔互连结构及其制备方法，包括衬底（10），其内设有至少一个垂直贯通穿透衬底的通孔，通孔的内壁生长有绝缘层（20），并在生长有绝缘层的通孔内填充有金属间化合物层（40），金属间化合物层（40）与绝缘层（20）间设有粘附层（30），通过金属间化合物层（40）完成三维堆叠中所需的电连接。该结构可以用于集成电路上制作垂直互连结构，也可以在无源基板上制作转接板。其降低了工艺复杂度，提高了合格率，降低了成本。

Description

三维封装用金属间化合物填充的垂直通孔互连结构及制备方法 技术领域
本发明涉及一种垂直互连结构及制备方法， 尤其是一种三维封装用金属间 化合物填充的垂直通孔互连结构及制备方法， 属于微电子封装三维集成技术领 域。
背景技术
系统级封装 （SiP) 是微电子关键技术之一， 满足了电子器件的高频高速、 多功能、 高性能、 小体积和高可靠性的要求， 是电子技术发展的方向。 随着集 成电路特征尺寸达到纳米级， 晶体管向更高密度、 更高的时钟频率发展， 封装 也向更高密度的方向发展， 集成电路产品也从二维向三维发展。
硅通孔（TSV) 的三维集成技术是实现 3D-SiP的关键技术之一， 是具有极 大影响的新核心技术， 具有极其广阔的应用前景； 因此受到各工业国家、 重要 企业和学术界的极大关注， 现在已经并持续投入大量资源进行研发。 硅通孔技 术具有很多技术挑战， 特别是其工艺制程复杂， 包括硅孔刻蚀、 绝缘层 /阻挡层 / 种子层沉积、 通孔填充、 化学机械研磨、 晶圆键合、 拆键合、 晶圆减薄、 金属 再布线制作、 凸点制备等。
TSV技术在应用方面存在的主要问题仍是工艺复杂， 成本高。 对于硅通孔 的填充材料和方式，大致有如下几种：（1 )、电镀填孔；（2)、化学气象沉积 (CVD); (3)、液态钎料填充； （4)、 导电胶填充。利用电镀填孔， 主要是以铜电镀为主， 其优点是铜具有良好的导电性， 缺点是电镀需要良好的种子层制作， 电镀时间 较长， 电镀工艺复杂， 成本高； 而且对于孔径小于 5微米的孔， 电镀填孔难以 实现。 化学气相沉积的主要材料是钨， 可以实现小孔径通孔的填充， 主要问题 是工艺复杂， 填充时间长， 成本高， 导电性稍差。 钎料填充， 是利用低熔点钎 料在液态下填充微孔，具有快速，低成本等优点。（参考文献 Ko Y.-K.， Fujii H. T.， Sato Y. S.， Lee C,W.， and Yoo S. Microelectron Eng 2012; 89: 62-64.)但^点是钎 料导电性较差， 与硅材料的 CTE (Coefficient of thermal expansion, 热膨胀系 数）相差较大， 带来应力问题， 而且钎料熔点低， 在后续工艺制程过程中会带 来很多问题。 利用导电胶填充， 也可以简化填充工艺， 但导电性很差， 难以填 充直径较小的孔。
发明内容
本发明的目的是克服现有技术中存在的不足， 提供一种三维封装用金属间 化合物填充的垂直通孔互连结构及制备方法， 其能有效降低制作成本， 简化工 艺步骤， 提高合格率， 安全可靠。
按照本发明提供的技术方案， 所述三维封装用金属间化合物填充的垂直通 孔互连结构， 包括衬底， 所述衬底内设有至少一个垂直贯通穿透衬底的通孔； 所述通孔内由垂直方向连续的金属间化合物填充， 所述金属间化合物层与衬底 间设有粘附层。
所述衬底与粘附层包括绝缘层， 粘附层通过绝缘层粘附于通孔的内壁上。 所述金属间化合物层与粘附层间还包括残余金属层， 金属间化合物层通过 残余金属层与粘附层相连。
所述金属间化合物层通过填充在通孔内的高温金属层与低熔点钎料填充体 热扩散形成。
所述高温金属层为 Cu、 Ni、 Ag、 Pd、 Au或 Fe中材料的一种或几种； 低熔 点钎料填充体为 Sn、 In、 SnAg、 Snln、 SnBi、 SnPb、 SnAgCu、 InAg、 InSn中 材料的一种或几种。
所述金属间化合物层为 Cu-Sn、 Ni-Sn、 Cn-In、 Ni-In、 Ag-Sn、 Au-Sn、 Ag-In、 Au-In等中的一种或几种。
所述金属间化合物层内包括高温金属相， 高温金属相的熔点高于 300度。 所述绝缘层的材料为 Si02， SixN^中的一种或几种。
一种三维封装用金属间化合物填充的垂直通孔互连结构制备方法， 所述垂 直互连结构制备方法包括如下步骤：
a、 提供衬底， 并在衬底内形成所需垂直贯通穿透衬底的通孔；
b、 在上述衬底的表面上淀积粘附层， 所述粘附层覆盖于衬底的表面并覆盖 于通孔的内壁表面；
c、 在上述衬底的表面设置与衬底绝缘的高温金属层， 所述高温金属层覆盖 衬底的表面并覆盖于通孔内对应粘附层的表面；
d、 在上述通孔内填充低熔点钎料， 以在通孔内形成低熔点钎料填充体； e、对上述形成低熔点钎料填充体的衬底表面平整化，抛光衬底对应的表面， 以使得通孔内的低熔点钎料填充体与抛光后衬底的表面平齐；
f、 在所需的温度下， 对低熔点钎料填充体及高温金属层进行热扩散处理， 直至低熔点钎料填充体全部融化后与高温金属层形成金属间化合物层。
所述步骤 d 中， 通过将衬底插入熔融的低熔点钎料熔池或在真空环境下灌 封熔融的低熔点钎料， 以在通孔内形成所需的低熔点钎料填充体。
所述衬底的材料包括硅、 砷化镓， 氮化镓或玻璃。
所述步骤 f中， 通孔内包括残余金属层或高温金属相，
所述高温金属相的熔点高于 300度， 高温金属相包括 Ag3Sn、 Cu6Sn5、 富 Pb相或富 Bi相。
所述步骤 b 中， 衬底为导体或半导体衬底时， 在衬底表面淀积绝缘层， 所 述绝缘层覆盖于衬底的表面并覆盖通孔的内壁表面； 当衬底及通孔内形成绝缘 层后， 粘附层覆盖衬底及通孔内绝缘层的表面。
所述绝缘层的材料为 sio2， sysi^中的一种或几种。
所述高温金属层为 Cu、 Ni、 Ag、 Pd、 Au或 Fe中材料的一种或几种。
低熔点钎料填充体为 Sn、 In、 SnAg、 Snln、 SnBi、 SnPb、 SnAgCu、 InAg、 InSn中材料的一种或几种。
所述粘附层的材料为 Ti、 TiN或 Ta。 本发明的优点： 衬底内设有至少一个垂直贯通的通孔， 通孔的内壁上生长 有绝缘层， 并在通孔内填充金属间化合物层， 金属间化合物层与绝缘层间具有 粘附层； 通过金属间化合物层能够完成三维堆叠中所需的电连接， 整个形成制 作过程方便， 降低了工艺复杂度及制作成本； 从而能够在集成电路上制作垂直 互连结构， 也能够在无源基板上制作转接板， 提高合格率， 安全可靠。
附图说明
图 1为本发明的结构示意图。
图 2为本发明具有残留金属层与残留金属相的结构示意图。
图 3为本发明制作转接板后的使用状态图。
图 4〜图 10为本发明的具体工艺步骤剖视图， 其中：
图 4为在通孔内生长得到绝缘层后的剖视图。
图 5为在通孔内淀积得到粘附层后的剖视图。
图 6为在通孔内得到高温金属层后的剖视图。
图 7为在通孔内填充得到低熔点钎料填充体后的剖视图。
图 8为平整抛光后的结构示意图。
图 9为高温金属与低熔点钎料填充体热扩散后形成金属间化合物后的剖视 图。
图 10 为高温金属与低熔点钎料填充体热扩散后具有残余金属层后的剖视 图。
附图标记说明： 10-衬底、 12-通孔、 20-绝缘层、 24-高温金属层、 26-低熔点 钎料填充体、 30-粘附层、 32-残余金属层、 36-高温金属相及 40-金属间化合物层。 具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图 1、 图 2、 图 9和图 10所示： 本发明中的垂直互连结构包括衬底 10， 所述衬底 10的材料为硅、 砷化镓， 氮化镓或玻璃， 衬底 10内设有至少一个垂 直贯通穿透衬底 10的通孔 12。 为了实现互连封装， 当衬底 10为导体或半导体 材料时，通孔 12的内壁上生长有绝缘层 20，所述绝缘层 20为 Si02, SixNLX中的 一种或几种。 在内壁生长有绝缘层 20的通孔 12内填充有金属间化合物层 40， 所述金属间化合物层 40与绝缘层 20间设有粘附层 30，通过粘附层 30能够使得 金属间化合物层 40在形成过程中能有效填充在通孔 12内， 金属间化合物层 40 填充满整个通孔 12。 粘附层 30的材料为 Ti、 TiN或 Ta。 当衬底 10为绝缘材料 时， 通孔 12内可以不设置绝缘层 20， 在通孔 12内直接设置粘附层 30。
金属间化合物层 40为通孔 12内的高温金属层 24与低熔点钎料填充体 26 在经过所需的热扩散后形成； 形成金属间化合物层 40的过程中， 由于高温金属 层 24的厚度等不同， 在粘附层 30与金属间化合物层 40间还残留有残余金属层 32； 由于低熔点钎料填充体 26的设置不同， 在金属间化合物层 40内可能有高 温金属相 36; 例如高温金属层 24为 Cu， 低熔点钎料填充体 26采用 SnBi, 当 Sn与 Cu扩散反应， Sn耗尽后富 Bi相会剩余下来， 即在金属间化合物层 40内 得到富 Bi相。 所述高温金属层 24为 Cu、 Ni、 Ag、 Pd、 Au或 Fe中的一种或几 种；低熔点钎料填充体 26为 Sn、 In、 SnAg、 Snln、 SnBi、 SnPb、 SnAgCu、 InAg、 InSn中的一种或几种。 所述金属间化合物层 40为 Cu-Sn、 Ni-Sn、 Cn-In、 Ni-In、 Ag-Sn、 Au-Sn、 Ag-In、 Au-In中的一种或几种。所述高温金属相 36包括 Ag3Sn、 Cu6Sn5、 富 Pb相或富 Bi相。
如图 4〜图 10所示： 上述垂直的互连结构可以通过下述具体工艺步骤实现， 具体地为：
a、 提供衬底 10， 并在衬底 10内形成所需垂直贯通穿透衬底 10的通孔 12; 本发明实施例中， 衬底 10选择 8寸硅晶圆， 并将所述硅晶圆的厚度减薄至
300微米； 通过常规工艺在硅晶圆内形成通孔 12， 所述通孔 12的孔径一般为 30 微米；
b、 在上述衬底 10的表面上淀积粘附层 30， 所述粘附层 30覆盖于衬底 10 的表面并覆盖于通孔 12的内壁表面；
如图 4所示衬底 10为导体或半导体衬底时，在衬底 10表面淀积绝缘层 20， 所述绝缘层 20覆盖于衬底 10的表面并覆盖通孔 12的内壁表面； 当衬底 10及 通孔 12内形成绝缘层 20后， 粘附层 30覆盖衬底 10及通孔 12内绝缘层 20的 表面； 在硅晶圆的表面热氧化生长氧化层， 得到位于衬底 10表面及通孔 12内 壁上的绝缘层 20;
如图 5所示： 本发明实施例中， 通过在衬底 10表面上淀积 Ti， 所述 Ti层 的厚度在几十到几百微米之间， 可以根据需要进行设定， 以此作为粘附层 30和 阻挡层； 淀积 Ti的过程中， 会同时覆盖通孔 12内对应绝缘层 20;
c、在上述衬底 10的表面设置与衬底 10绝缘隔离的高温金属层 24， 所述高 温金属层 24覆盖衬底 10的表面并覆盖于通孔 12内对应粘附层 30的表面； 如图 6所示： 所述高温金属层 24的形成过程可以先在上述粘附层 30上沉 积金属， 然后在电镀或化学镀至所需的厚度； 本发明具体实施时， 高温金属层 24采用 Cu， 先通过物理气相沉积 Cu， 然后在电镀至 6微米； 当通孔 12内有绝 缘层 20吋， 高温金属层 24通过绝缘层 24与衬底 10相绝缘隔离；
d、 在上述通孔 12内填充低熔点钎料， 以在通孔 12内形成低熔点钎料填充 体 26;
如图 7所示： 在通孔 12内填充低熔点钎料时， 可以将衬底 10插入熔融的 低熔点钎料熔池内， 或者在真空环境下灌封熔融低熔点钎料； 由于表面张力的 作用， 在短时间内， 就可以完成填充； 本发明的具体实施中， 低熔点钎料为 Sn， 填充过程中的温度高于 Sn的熔点， 比如可以在 260度；
e、 对上述形成低熔点钎料填充体 26的衬底 10表面平整化， 抛光衬底 10 对应的表面， 以使得通孔 12内的低熔点钎料填充体 26与抛光后衬底 10的表面 平齐；
如罔 8所示： 在通孔 12 内通过填充低熔点钎料形成低熔点钎料填充体 26 后， 低:) f点钎料填充体 26的两端会形成凸点， 所述凸点的高度高于衬底 10的 表面； 因此通过平整化抛光操作将凸点及衬底 10表面的一些材料层去除； 所述 平整化^以采用机械化学抛光 （CMP) 或其他平整化工艺； f、 在所需的温度下， 对低熔点钎料填充体 26及高温金属层 24进行热扩散 处理， 直至低熔点钎料填充体 26全部融化后与高温金属层 24形成金属间化合 物层 40。
为了形成所需的金属间化合物层 40，需要在所需的温度下进行热扩散处理; 热扩散处理的时间以能够使低熔点钎料填充体 26扩散融化完为止； 当采用那个 本发明中前述的材料时，金属间化合物层 40为 Cu6Sn5、 Cu3Sn或 Cu6Sn5、 Cu3Sn 两者的混合。 当高温金属层 24超过一定厚度， 在热扩散后就会有残余， 如图 2 和图 10中的残余金属层 32。
图 3 为当形成本发明的垂直互连结构后制作转接板的结构示意图。 在转接 板的正面具有两层布线以及微凸点， 在背面具有一层布线及微凸点， 通过转接 板能够完成集成电路的封装。
本发明衬底 10内设有至少一个垂直贯通的通孔 12， 在通孔 12内由垂直方 向上连续的金属间化合物层 40填充， 金属间化合物层 40与衬底 10间具有粘附 层 30;通过金属间化合物层 40能够完成三维堆叠中所需的电连接，整个形成制 作过程方便， 降低了工艺复杂度及制作成本； 从而能够在集成电路上制作垂直 互连结构， 也能够在无源基板上制作转接板， 提高合格率， 安全可靠。
以上所述仅为本发明的具体实施例， 并不用以限制本发明， 本实施例中所 用材料和工艺条件仅限于本实施例， 凡在本发明的精神和原则之内， 所作的任 何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权 利 要 求 书
1、一种三维封装用金属间化合物填充的垂直通孔互连结构，包括衬底（10)， 所述衬底 （10) 内设有至少一个垂直贯通穿透衬底 （10) 的通孔（12); 其特征 是： 所述通孔 （12) 内由垂直方向连续的金属间化合物 （40) 填充， 所述金属 间化合物层 （40) 与衬底 （10) 间设有粘附层 （30)。
2、 根据权利要求 1所述的三维封装用金属间化合物填充的垂直通孔互连结 构， 其特征是： 所述衬底（10)与粘附层（30)包括绝缘层（20)， 粘附层（30) 通过绝缘层 （20)粘附于通孔 （12) 的内壁上。
3、根据权利要求 1或 2所述的三维封装用金属间化合物填充的垂直通孔互 连结构， 其特征是： 所述金属间化合物层 （40) 与粘附层 （30) 间还包括残余 金属层 （32)， 金属间化合物层 （40)通过残余金属层 （32)与粘附层 （30)相 连。
4、根据权利要求 1或 2所述的三维封装用金属间化合物填充的垂直通孔互 连结构， 其特征是： 所述金属间化合物层 （40) 通过填充在通孔 （12) 内的高 温金属层 （24) 与低熔点钎料填充体 （26) 热扩散形成。
5、 根据权利要求 4所述的三维封装用金属间化合物填充的垂直通孔互连结 构， 其特征是： 所述高温金属层 （24)为 Cu、 Ni、 Ag、 Pd、 Au或 Fe中材料的 一种或几种； 低熔点钎料填充体 (26) 为 Sn、 In、 SnAg、 Snln、 SnBi、 SnPb、 SnAgCu、 InAg、 InSn中材料的一种或几种。
6、根据权利要求 1或 2所述的三维封装用金属间化合物填充的垂直通孔互 连结构， 其特征是： 所述金属间化合物层（40)为 Cu-Sn、 Ni-Sn、 Cn-In、 Ni-In、 Ag-Sn、 Au-Sn、 Ag-In、 Au-In等中的一种或几种。
7、根据权利要求 1或 2所述的三维封装用金属间化合物填充的垂直通孔互 连结构， 其特征是： 所述金属间化合物层 （40) 内包括高温金属相 （36)， 高温 金属相 (36) 的熔点高于 300度。
8、根据权利要求 2所述的三维封装用金属间化合物填充的垂直通孔互连结 构， 其特征是： 所述绝缘层 （20) 的材料为 SiC^ SixN^中的一种或几种。
9、 一种三维封装用金属间化合物填充的垂直通孔互连结构制备方法， 其特 征是， 所述垂直互连结构制备方法包括如下步骤：
(a)、提供衬底（10)， 并在衬底（10) 内形成所需垂直贯通穿透衬底（10) 的通孔 （12);
(b)、 在上述衬底 （10) 的表面上淀积粘附层 （30)， 所述粘附层 （30)覆 盖于衬底 （10) 的表面并覆盖于通孔 （12) 的内壁表面；
(c)、 在上述衬底（10) 的表面设置与衬底（10)绝缘的高温金属层（24)， 所述高温金属层 （24) 覆盖衬底 （10) 的表面并覆盖于通孔 （12) 内对应粘附 层 (30) 的表面；
(d)、 在上述通孔 （12) 内填充低熔点钎料， 以在通孔 （12) 内形成低熔 点钎料填充体 （26);
(e)、 对上述形成低熔点钎料填充体 （26) 的衬底 （10) 表面平整化， 抛 光衬底 （10) 对应的表面， 以使得通孔 （12) 内的低熔点钎料填充体 （26) 与 抛光后衬底 （10) 的表面平齐；
(f)、 在所需的温度下， 对低熔点钎料填充体（26)及高温金属层（24)进 行热扩散处理， 直至低熔点钎料填充体 （26) 全部融化后与高温金属层 （24) 形成金属间化合物层 （40)。
10、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述步骤（d) 中， 通过将衬底 （10)插入熔融的低 熔点钎料熔池或在真空环境下灌封熔融的低熔点钎料， 以在通孔 （12) 内形成 所需的低熔点钎料填充体 （26)。
11、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述衬底 （10) 的材料包括硅、 砷化镓， 氮化镓或 玻璃。
12、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是：所述步骤（0中，通孔（12)内包括残余金属层（32) 或高温金属相 （36)，
13、 根据权利要求 12所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述高温金属相 （36) 的熔点高于 300度， 高温金 属相 (36) 包括 Ag3Sn、 Cu6Sn5、 富 Pb相或富 Bi相。
14、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述步骤（b) 中， 衬底 （10) 为导体或半导体衬底 时， 在衬底 （10)表面淀积绝缘层 （20)， 所述绝缘层 （20) 覆盖于衬底 （10) 的表面并覆盖通孔 （12) 的内壁表面； 当衬底 （10) 及通孔 （12) 内形成绝缘 层 （20) 后， 粘附层 （30) 覆盖衬底 （10) 及通孔 （12) 内绝缘层 （20) 的表 面。
15、 根据权利要求 14所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述绝缘层 （20) 的材料为 SiC^ SixN^中的一种或 几种。
16、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述高温金属层 （24) 为 Cu、 Ni、 Ag、 Pd、 Au或 Fe中材料的一种或几种。
17、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 低熔点钎料填充体 （26) 为 Sn、 In、 SnAg、 Snln、 SnBi、 SnPb、 SnAgCu、 InAg、 InSn中材料的一种或几种。
18、 根据权利要求 9所述的三维封装用金属间化合物填充的垂直通孔互连 结构制备方法， 其特征是： 所述粘附层 （30) 的材料为 Ti、 TiN或 Ta。
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