Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
  • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
  • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
  • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
  • H10F30/221—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PN homojunction
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/026—Wafer-level processing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/10—Integrated devices
  • H10F39/12—Image sensors
  • H10F39/199—Back-illuminated image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/139—Manufacture or treatment of devices covered by this subclass using temporary substrates
  • H10F71/1395—Manufacture or treatment of devices covered by this subclass using temporary substrates for thin-film devices
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy

Definitions

• Image sensors receive light and convert the energy into electrical signals based on the amount of light received.
• Image sensors generally include a silicon light-sensitive layer and electrical circuitry, such as an integrated chip, for processing the electrical signals. It is desirable to increase the pixel density on a chip to improve resolution. However, increasing pixel density creates issues such as crosstalk and denser circuitry wiring,
• FSI frontside-illummated
• BSI backside-illuminated
• BSI sensors require thinner silicon in order for the light to pass through and reach the photoactive layer and therefore have not been as cost-effective to manufacture as FSI sensors.
• BSI sensors also require precision uniformity in thickness across the chip, which can be difficult to accomplish.
• One approach for manufacturing thin semiconductor wafers is utilizing epitaxial silicon, in which layers of silicon are grown on a bulk silicon substrate.
• the silicon substrate is a very thin sheet of typically less than 1.5 microns.
• Another approach is using a thicker silicon wafer and grinding it down to the desired thinness after the circuitry and interconnect layers have been formed. Because it is difficult to achieve the necessary precision uniformity in thickness with grinding, BSI processing often requires both wafer level grinding and die level polishing. This creates throughput issues, increases cost, and can cause contamination.
• Other factors in fabricating BSI sensors include differences in processing temperatures at the various stages of manufacturing, which greatly affects the materials and sequence of manufacturing steps, and the ability to handle thin films during fabrication.
• a method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. An electrical connection is formed to the doped region, A temporar carrier is contacted to the back surface of the semiconductor and later removed, A backside- illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the provided semiconductor lamina remains substantially unchanged during the fabrication.
• a method for fabricating a backside-illuminated sensor includes providing a semiconductor donor body having a first conductivity. A doped region of a second conductivity is formed at a first surface of the donor body and within the donor body. Ions are implanted into the first surface to define a cleave plane, and a semiconductor lamina is cleaved from the donor body. The doped region is included in the lamina, and an electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication.
• FIG. 1 depicts a cross-sectional view of a conventional frontside- illuminated sensor.
• FIG. 2 depicts a cross-sectional view of a conventional backside- illuminated sensor.
• FIGs, 3A-3C are cross-sectional views of an embodiment of a backside-illuminated sensor in various stages of manufacturing.
• FIG. 4 is a flowchart of an exemplary method of the present invention.
• FIGs. 5A-5C show exemplary cross-sectional views of another embodiment of a backside-illumi ted sensor in various stages of manufacturing.
• FIG. 6 is a flowchart of another exemplary method of the present invention.
• a backside-illuminated sensor is fabricated using a lamina having a thickness substantially equivalent to the desired thickness for the finished sensor device.
• the lamina may be provided as a free-standing lamina, in which doped regions are formed within and at a front surface of the lamina.
• doped regions are formed in a first surface of a semiconductor donor body and a lamina is cleaved from the donor body, where the doped regions are within and at the front surface of the lamina.
• FIG. 1 shows a simplified view of a conventional FSI sensor 100 which includes lenses 1 10, color filter 120, integrated circuit 130, metal interconnect layer 140, doped regions 150 and semiconductor substrate 160.
• the semiconductor substrate 160 has a first conductivity and may be, for example, silicon.
• the doped regions 150 are doped to a different conductivity than the semiconductor substrate 160.
• the semiconductor substrate 160 may be a p-type conductor while the doped regions 150 may be n-type.
• a depletion zone forms at the p-n junction, creating an electric field.
• the p-n junction between the doped regions 150 and semiconductor substrate 160 forms a photodiode.
• metal interconnect layer 140 may include wiring or interconnects 142 and dielectric 144.
• integrated circuit 130 also includes wiring 132.
• Light 170 enters the "front side" of the of the FSI sensor 100, where some fight rays are blocked or reflected by wiring 132 and wiring 142. Light energy that reaches the doped regions 150 is then converted to electrical signals that are processed by integrated circuit 130.
• FIG. 2 is a simplified diagram of a conventional BSI sensor 200.
• a BSI sensor is essentially an inverted FSI, so that light enters the back side, through the semiconductor substrate.
• incident light indicated by arrows 270, enters lens 210 and passes through color filter 2.20, and then proceeds through semiconductor substrate 260 to diode regions 250, unhindered by waring in metal interconnect layer 240 and integrated circuit 230.
• the efficiency of capturing photons is greatly increased for BSI sensors compared to FSI sensors.
• the semiconductor substrate 260 thin enough to allow light to reach doped regions 250 can be very difficult, as the substrate 260 also requires high precision unifonnitv in thickness and avoiding damage to the thin film semiconductor during processing. Grinding is typically used to thin a silicon wafer; however, wafer level grinding commonly results in thickness variation across the wafer. Therefore, additional die level polishing is often performed. The need for multiple material removal steps creates various issues such as lower throughput, higher cost, increased risk of surface contamination, and potential for damage to the semiconductor substrate due to increased handling.
• FIGs. 3A-3C depict cross-sectional views of an embodiment of the present disclosure, in which a BSI sensor is fabricated utilizing a thin film semiconductor lamina that already possesses a thickness substantially equivalent to the desired thickness required for the finished sensor assembly.
• the lamina may be less than 50 microns ( ⁇ ) thick, such as between 1 and 20 ⁇ or between 1 and 10 ⁇ thick.
• the thickness of the provided lamina remains substantially unchanged, for example within at least 80% of its initially provided thickness, during processing steps for fabrication of the BSI sensor.
• a thin film semiconductor lamina 360 is provided, where semiconductor lamina 360 has a front surface 362, a back surface 364, and a first conductivity.
• the lamina 360 has a thickness measured between the front surface 362 and the back surface 364.
• Semiconductor lamina 360 may be contacted by a temporary support 380 at back surface 364 to aid in handling the thin film.
• Temporary support 380 may be contacted to lamina 360 by any type of separable force or adherence such as a vacuum, electrostatic or chemical force.
• semiconductor lamina 360 may be a doped n-type or p-type monocrystalline silicon.
• the doping concentration may be, for example, between about 1 x 10° and about 1 x 10 18 dopant atoms/cm 3 , or for example, about 1 x 10 1 ' dopant atoms/cm .
• One or more doped regions 350 are formed within semiconductor lamina 360 at front surface 362, where the doped regions 350 have a different conductivity than that of the semiconductor.
• doped regions may be formed on any lamina of any thickness, such as less than 50 ⁇ thick.
• Another aspect of this invention is that imperfections in the lamina that may have been generated by an exfoliation process may be repaired before the fabrication of doped diode regions.
• the doped regions 350 in FIG. 3A may be formed by methods known in the art, including diffusion doping.
• a doped glass layer 390 may be formed on the front surface 362 by any method such as atmospheric pressure chemical vapor deposition (PCVD).
• PCVD atmospheric pressure chemical vapor deposition
• the doped glass layer 390 may be, for example, horosilicaie glass (BSC) doped with boron.
• the source gas may be any suitable gas that will provide boron, for example, ⁇ 3 ⁇ 4 B23 ⁇ 4, or BCI3.
• an appropriate gas such as POCI 3 may be flowed at about 880 °C for about 30 minutes 011 front surface 362, forming phosphosiiicate glass (PSG).
• a dopant-providing material may be spun onto the front surface 362 and baked.
• the doped glass may be grown thermally, by flowing O2 over a solid source such as BN.
• the doped glass layer 390 may have a thickness between, for example, about 500 and about 1500 angstroms, for example, about 1000 angstroms.
• doped glass 390 is removed in selected areas, for example by screen printing etchant paste, leaving glass regions 392 (shown as shaded areas) where the doped regions 350 are to be formed.
• doped regions 350 may be formed on front surface 362 by the deposition of amorphous silicon comprising an n-type dopant.
• an intrinsic (undoped) layer of amorphous silicon may be interposed between the doped amorphous silicon layer and front surface 362.
• a layer of S13N4 may be deposited on the front surface 362.
• a screen print etchant paste is applied to etch the SijiNU, to mask any locations on front surface 362 in which doped regions 350 are not to be formed.
• conventional photolithographic techniques could be used to define these masked regions.
• Diffusion doping using a source of phosphorus e.g., POCI 3
• a boron-containing ambient e.g., BBr-,
• Any remaining S13N4 may be etched off at this time using known methods such as hydrofluoric acid (HF).
• HF hydrofluoric acid
• An anneal for example between about 850 and about 1000 °C, is performed in a furnace from between about 30 and about 90 minutes, and diffuses dopants from glass regions 392 into semiconductor lamina 360 at front surface 362, This diffusion forms either doped p-type (from, e.g., BSG) or n-type (from, e.g., PSG) regions 350.
• a conventional wet etch for example an HF dip, removes the BSG or PSG, leaving doped regions 350 exposed at front surface 362. Boron and phosphorus are the most commonly used p-type and n-type dopants, respectively, but other dopants may be used.
• electrical connections may be formed as shown in FIG. 3B, In some embodiments, the electrical connection may include one or more sub-layers in metallization layer 340.
• the metallization layer 340 may be formed by, for example, sputter deposition using physical vapor deposition.
• the metallization layers 340 may comprise, for example, titanium, titanium-tungsten, or copper. Photolithography methods known in the art may be used to mask and etch the desired wiring patterns in
• CMOS complementary metal-oxide semiconductor
• a completed BSI sensor may be fabricaied by adding, for example, coatings, color filters, and micro-lenses to back surface 364 (e.g., FIG. 2).
• the thickness of initially provided thin film semiconductor lamin 360 remains substantially unchanged during fabrication of the backside illuminated sensor, thus reducing issues created by grinding,
• Flowchart 400 of FIG. 4 illustrates the embodiments FTGs. 3A-3C.
• the exemplary method of flowchart 400 begins with providing a thin film semiconductor lamina in step 410.
• a temporary carrier or support may be contacted to the back surface of the lamina, to support handling of the fragile lamina during processing.
• One or more doped regions are formed at the front surface of the lamina in step 430, where the doped regions have a conductivity opposite of the conductivity of the thin film semiconductor.
• one or more electrical connections are formed to the doped region.
• the electrical connections may include, for example, metallization layers, solder bumps and thermo-compression interfaces.
• the temporary carrier is removed in step 450, after which a finished backside-illuminated sensor may be fabricated in step 460 by performing any additional manufacturing steps as desired on the back surface of the lamina.
• finishing steps may include, for example, adding coatings, color filters and micro-lenses.
• the coatings may include layers that passivate the back surface of the lamina. These passivation layers may include a 10 A - 300 A layer of hydrogenated amorphous silicon, deposited by plasma-enhanced chemical vapor deposition at a temperature of ⁇ 450 C.
• the finishing steps may also include etching some material from the back surface of the lamina, to remove damage incurred during the cleaving implant process.
• FIGs. 5A- 5C Another embodiment of the present disclosure is shown in FIGs. 5A- 5C.
• doped regions 550 of FIG. 5A are formed in a semiconductor donor body 500, and then a lamina is cleaved from the semiconductor donor body 500, where the lamina includes the doped regions 550.
• the donor body 500 is an appropriate semiconductor material such as a monocrystalline silicon wafer of any practical thickness, for example from about 200 to about 1000 microns thick. In alternative embodiments, the donor wafer may be thicker; maximum thickness is iimiied only by practicalities of wafer handling. Alternatively, wafers or ingots of other semiconductors materials, including germanium, silicon germanium, or III-V or II- VI semiconductor compounds such as GaAs, InP, etc may be used.
• the process of forming monocry stalline silicon generally results in circular wafers, but the donor body can have other shapes as well. Cylindrical monocrystalline ingots are often machined to an octagonal cross section prior to cutting wafers. Multicrystailine wafers are often square. Square wafers have the advantage that, unlike circular or hexagonal wafers, they can be aligned edge-to-edge with minimal unused gaps between them. The dia meter or width of the wafer may be any standard or custom size. For simplicity this disclosure will describe the use of a monociystalline silicon % r afer as the semiconductor donor body, but it will be understood that donor bodies of other types and materials can be used.
• Exfoliation of a lamina comprising the doped regions 550 may occur by any means, including an ion induced cleavage reaction.
• the implanted ions define a cleave plane, such as cleave plane 501 of FIG. 5 A, within the semiconductor donor wafer 500.
• Semiconductor donor wafer 500 also referred to as a donor body in this disclosure, has a first surface 562, which will become the front surface 562 of the later-exfoliated lamina.
• the gas ions are implanted (indicated by arrows 503) through first surface 562, to create cleave plane 501.
• the cost of this hydrogen or helium implant may reduced by methods described in Parrill et al, U.S. Patent Application No. 12/122108, "Ion Implanter for Photovoltaic Cell Fabrication," filed May 16, 2008, owned by the assignee of the present invention and hereby incorporated by reference.
• the overall depth of cleave plane 501, as measured from first surface 562, is determined by several factors including implant energy.
• the depth of cleave plane 501 can be between about 0.2 and about 100 ⁇ from first surface 562, for example between about 0.5 and about 20 ⁇ ; or between about 0.5 and about 50 um, for example between about 1 and about 25 ⁇ or between about 8 microns and about 20 ⁇ .
• the depth of the cleave plane 501 will determine the thickness of cleaved lamina.
• the thickness of cleaved lamina is chosen to be substantially equivalent to the desired thickness of a semiconductor substrate in the completed BSI sensor.
• a semiconductor substrate for a BSI according to embodiments of this invention may advantageously be produced with a specifically desired thickness and with a highly precise uniformity in thickness.
• an anneal reaction causes lamina 560 to cleave from donor wafer 500 at cleave plane 501 , where the cleave plane 501 creates back surface 564 of lamina 560.
• the first surface 562 of the semiconductor donor body 500 becomes front surface 562 of the lamina 560.
• Donor wafer 500 is affixed at first surface 562 to a temporary support element 585, which may be used to lift the lamina 560 from the semiconductor donor body 500.
• semiconductor lamina 560 may be between about 0.2 and about 100 ⁇ , ⁇ thick, for example between about 0.2 and about 50 ⁇ , for example between about 1 and about 25 ⁇ thick, in some embodiments between about 5 and about 20 um thick, though any thickness within the named range is possible.
• photovoltaic cells are formed of thin semiconductor laminae rather than being formed from sliced wafers, without wasting silicon through excessive kerf loss or by fabrication of an unnecessarily thick cell, thus reducing cost.
• the same donor wafer can be reused to form multiple laminae, further reducing cost, and may be resold after exfoliation of multiple laminae for some other use.
• a thin, free standing lamina may be formed and separated from a donor body without adhesive or permanent bonding to a support element and without requiring debonding or cleaning steps prior to fabricating a device from the lamina, beneficially providing for any number of processing steps to the front or back surface of the lamina.
• the first surface of the donor body 500 - which will be the front surface of an exfoliated lamina - may be placed adjacent to support element 585 and an anneal step may be performed that exfoliates a lamina from the first surface of the donor body before or after the surface is treated with a processing step.
• the cleaved plane creates the back surface of the lamina, and once again, any number of processing steps may then occur on either side of the exfoliated lamina.
• a second surface 502 of semiconductor donor body 500 of the present invention may be separably contacted to a temporary support element 586, such as a susceptor assembly.
• the contact between the donor body 500 and the support element 586 may comprise any type of separable force or adherence such as a vacuum, electrostatic or chemical force.
• the inieracting force between the donor body 500 and the susceptor 586 during exfoliation of a lamina is solely the weight of the donor body 500 on the susceptor 586.
• the exfoliation equipment has a configuration which is inverted vertically from that shown in FIG.
• the interacting force is solely the weight of the susceptor assembly 586 on the donor body.
• heat or other force may be applied to the donor body 500 to cleave lamina 560 from the donor body 500 at the cleave plane 501.
• Exfoliation conditions may be optimized to cleave the lamina from the donor body in order to minimize physical defects in a lamina exfoliated in the absence of a permanently adhered support element. Exfoliation may be performed at temperatures between, for example, about 350 and about 650 degrees C. In general, exfoliation proceeds more rapidly at higher temperature.
• a back surface 564 which is opposite of the front surface 562 on lamina 560 is created, as shown in FIG. 5C.
• Doped regions 550 are located at front surface 562 and within lamina 560.
• the lamina 560 may be annealed to remove any damage caused by the ion implantation.
• the free-standing lamina 560 may be temporarily contacted at either the front surface 562 or back surface 564 with a temporary support element. For example, support element 580 in FIG. 5C may contact back surface 564 during further
• Flowchart 600 of FIG. 6 illustrates an exemplary embodiment of the methods of FIGs. 5A-5C.
• a semiconductor donor body is provided.
• One or more doped regions which will serve as photodiodes of a finished BSI sensor assembly. are formed in the donor body in step 620.
• the doped regions are formed at a first surface of the donor body and ha v e a conductivity that is different from the conductivity of the donor body. Tons are implanted into the semiconductor donor body to form a cleave plane in step 630, and then a semiconductor lamina is cleaved from the donor body in step 640.
• the first surface of the semiconductor body serves as the front surface of the lamina, and the cleave plane creates the back surface of the lamina. Furthermore, the doped regions are included at a front surface of the exfoliated lamina.
• a temporary carrier or support is contacted to the back surface of the semiconductor lamina. Electrical connections, such as the metallization layers described above, are coupled to the doped regions on the front side of the lamina in step 660.
• the temporary carrier is removed in step 670.
• a finished backside-illuminated sensor may be fabricated in step 680 by performing any additional manufacturing steps desired on back surface of the lamina, such as those described in relation to step 460 of FIG. 4,
• the embodiments of the present invention provide method of providing a lamina that does not require further thinning to achieve the desired thickness for a BSI sensor, thus reducing cost and improving and manufacturabiliiy.
• the thickness of the provided lamina remains substantially unchanged - such as being modified by not more than 20% of its initial thickness as a result of, for example, etching - during processing of the lamina and fabrication of the backside-illuminated sensor.
• Embodiments of the methods also involv e doping the diode regions - processes which typically require high temperatures - early in the manufacturing process, consequently allowing for use of lower temperature materials and processes in subsequent fabrication steps.
• a temporary support may also be contacted to the front surface.
• temporary supports contacting either or both of the front and back surfaces may be used to transfer the lamina through the various steps involved with fabricating a finished BSI sensor assembly.
• etching or other surface preparation processes may be performed.
• An etch step may serve to remove damage at the back surface of the lamina.
• This etch step may be performed, for example, by a wet or plasma treatment. The plasma treatment may occur, for example, in an SFg ambient. The amount etched may be ⁇ 20% of the total lamina thickness.

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