WO2024038303A1

WO2024038303A1 - Back illuminated image sensor with implanted boron for ultraviolet response

Info

Publication number: WO2024038303A1
Application number: PCT/IB2022/057671
Authority: WO
Inventors: Nixon O; Gary ALLAN
Original assignee: Teledyne Digital Imaging, Inc.
Priority date: 2022-08-16
Filing date: 2022-08-16
Publication date: 2024-02-22

Abstract

A method of fabricating a back-side illuminated (BSI) silicon image sensor may include providing an image sensor, in which a silicon substrate of the image sensor silicon layer is thinned to expose a silicon layer including device circuitry and forming an optical entrance surface, doping a portion of the optical entrance with a boron implant to create a dopant implanted region, annealing and activating the dopant region with laser energy, removing an oxide layer formed on the optical entrance, growing a new oxide layer on the optical entrance, and depositing a dielectric layer over the new oxide layer. The dielectric layer includes a negative fixed oxide charge layer at a dielectric/new oxide interface. The fixed charge layer has an oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV^-1 cm^-2. A BSI silicon image sensor may be fabricated according to this method.

Description

TITLE

BACK ILLUMINATED IMAGE SENSOR WITH IMPLANTED BORON FOR ULTRAVIOLET RESPONSE

TECHNICAL FIELD

[0001] The present disclosure is directed to an image sensor. More particularly, the present disclosure is directed to a back-side illuminated (BSI) silicon image sensor for detection of high intensity ultraviolet (UV) illumination, in the spectral range 190nm to 370nm.

BACKGROUND

[0002] The present disclosure is directed to UV detectors for imaging technology. Detection of UV light with silicon detectors, specifically charge coupled devices (CCD) or complementary metal oxide semiconductor (CMOS) image sensors, entails significant technical challenges that result from excitation of electrons into and out of the dielectric overlayers that form the Si/SiO2 interface and other layers/interfaces at the optical detection surface.

[0003] It is well known and established that back-side illuminated (BSI) silicon detectors require some form of surface treatment at the optical entrance surface, even for visible or near infra-red detection, to counteract the low energy electron states at the interface of silicon to SiO2, which serve to form a potential well at the back surface and reduce detection efficiency. Several methods to achieve back surface passivation, such as implantation of Boron or negative charging of a deposited dielectric layer, are effective and have proven technological success for many imaging applications. However, the high photon energy of UV illumination presents difficulties for these methods, in particular for wavelengths shorter than 220nm, because electrons can be excited through virtual band-to-band transitions to energy levels that allow positive charging of the SiO2 layer. Even at longer UV wavelengths oxide charging can occur through excitation mechanisms involving impurity, interface, and defect states.

[0004] Electrons excited into or out of the oxide layer generate an electro-static field that will affect the charge distribution of mobile carriers (majority carriers typically) in the detection volume of silicon. The case that leads to the most difficult problem for conventional p-type silicon substrate imaging devices, is trapping of hole charges in the oxide layer adjacent to the Si/SiO2 interface , and it is well known this can occur under UV illumination. The effect of trapped holes in the SiO2 layer is to lower the free energy of electrons at and near the silicon surface, with the result that a potential well is formed at the optical detection surface (back surface). Photo-excited electrons generated near the surface in silicon may not escape the potential well at the surface and therefore not contribute to detected signal. Hole trapping sites with very deep energies (i.e. at a large energy above the valence band of SiO2) present the most difficult condition because these sites are typically very long lived and therefore can accumulate to a significant charge density. Technological approaches to reduce the density of trapping sites in oxide or at interface have made excellent progress. The nature and physical attributes of these trapping sites is not the focus of this disclosure. However, UV illumination can generate trapping sites in oxide and therefore the inspection conditions themselves at wavelengths of 190nm to 370nm can present inherent instabilities. Design approaches to limit the impact of oxide charge on the detection volume of silicon, such as providing a high density of mobile carriers to screen the field of trapped charge, have shown the most promise.

[0005] Charging of oxide is a very low probability event, and so requires extended periods of near continuous illumination to accumulate sufficient oxide charge to cause measureable effects. Many high-speed UV inspection applications, particularly those of the semiconductor fabrication industry for wafer, mask, or reticle inspection, use high intensity UV illumination and operate in nearly continuous use. Therefore, these applications suffer from response degradation as usage time accumulates. Many silicon imaging detectors essentially have a memory effect of total accumulated exposure, which is undesired.

[0006] Surface passivation of image sensors for UV detection requires a very shallow depth and a very high concentration of the implanted dopant because of the very short absorption depth of silicon at UV wavelengths. Though shallow Boron implants and annealing methods have been developed for small length scales in BSI detectors, electrostatic effects within a few nanometers of the detection surface can cause measureable response degradation.

[0007] Known UV image sensors have eliminated or reduced the memory effect by means of very strong back side passivation conditions. Known is a device that employed growth of a SiO2 layer at sufficiently high temperature to achieve very high quality (i.e., low trap density) oxide. Also known is a method involving growth of a boron doped silicon layer by molecular- beam epitaxy (MBE) to achieve sufficiently high boron density to form a thin screening layer of mobile holes at the silicon surface. Also known is a method involving deposition of a pure boron layer onto silicon surface. Also known is the deposition and annealing of pure boron onto silicon. MBE capability is not common in typical silicon wafer fabrication foundries due to equipment complexity. Conditions required for pure boron deposition and annealing may not be compatible with image sensor wafers that have completed full device processing, including metal layers which have strict temperature limitations, necessitating a complicated partial backside fabrication process prior to completion of full device circuitry layers. In yet another alternative method, PECVD (plasma enhanced chemical vapor deposition) has been used to create thin highly doped layers over the back-thinned silicon surface.

[0008] MBE-based approaches have the ability to fabricate boron-rich layers that are very thin at only a few atoms thick. One such approach has been described as “delta doping.” While delta doping aims for maximum boron concentration at the Si/oxide interface, the amount of boron is not sufficient to achieve the required level of UV stability in high-dose UV imaging applications. It is known that there is a need for surface passivation technologies with improved stability and robustness.” Is has been considered that this deficiency may due, in part, to surface artefacts for example the deactivation of boron by atmospheric hydrogen. Alternatively, the main contributor to surface artefacts may be due, instead, to the UV- induced increase in the interface trap charges and positive fixed oxide charge in the dielectric layer, including in an AR coating above the silicon layer in the backside thinned surface. One solution to the surface artefacts may be to increase the amount of boron by depositing a thicker highly doped layer. The use of a thicker boron layer may reduce the deep UV quantum efficiency of the imager, as more photogenerated electrons recombine before they exit the highly doped layer.

[0009] The “pure boron” is another approach to passivating the back surface. In some instances, the “pure boron” approach may be considered “the poor man’s delta doping,” although the process differs from delta doping. Pure boron is deposited using chemical vapor deposition instead of MBE. The original process requires processing temperatures that exceed 400 deg C, which makes the process incompatible with CMOS wafer processing. A pure boron process at 400 deg C may compromise the film quality. Pure boron has the same quantum efficiency vs. stability trade-offs as MBE-based approaches.

[0010] Accordingly, there exists a need for an image sensor device that has improved or eliminated response degradation as usage time under UV illumination accumulates, and is fabricated through conventional BSI silicon image sensor fabrication methods.

SUMMARY

[0011] In one aspect, the present disclosure provides a method of fabricating a back-side illuminated (BSI) silicon image sensor. The method includes providing an image sensor comprising a silicon wafer bonded face-to-face to a handle wafer, in which a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface, doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region, annealing and activating the dopant implanted region with laser energy, removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface, removing a native oxide layer formed on the optical entrance surface after thinning the image sensor wafer and exposing the silicon surface, growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region, and depositing a dielectric layer over the new oxide layer, in which the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface and in which the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

[0012] In another aspect of the method, depositing a dielectric layer over the new oxide layer comprises depositing a dielectric layer using atomic layer deposition at a temperature between 150°C and 250°C.

[0013] In another aspect, the method further comprising annealing the deposited dielectric layer at a temperature between 300°C and 400°C.

[0014] In another aspect of the method, annealing the deposited dielectric layer at a temperature between 300°C and 400°C comprises annealing the deposited dielectric layer at a temperature between 300°C and 400°C under a dry nitrogen environment without breaking vacuum.

[0015] In another aspect of the method, depositing a dielectric layer over the new oxide layer comprises depositing a layer of AI2O3 over the new oxide layer.

[0016] In another aspect of the method, doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a near surface region of the silicon layer with a boron-11 isotope at a concentration between 1 E20cnr³ and 5E21cnr³, and having a nominal thickness of approximately 5nm to 30 nm.

[0017] In another aspect of the method, doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a surface of the image sensor silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, thereby obtaining a dopant concentration profile between 1 E20cnr³ and 5E21cnr³ extending over a depth between 5nm and 30nm.

[0018] In another aspect of the method, annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern.

[0019] In another aspect, the method further comprises applying the laser energy at an energy density per pulse to produce activation for a limited portion of the dopant and to produce a minimum profile change of a dopant concentration, when compared to a preannealed dopant concentration profile.

[0020] In another aspect of the method, annealing and activating the dopant implanted region with laser energy comprises applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region.

[0021] In another aspect of the method, annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with laser energy at a laser wavelength between 190nm and 370nm.

[0022] In another aspect of the method, removing a native oxide layer formed on the optical entrance surface comprises removing the native oxide layer by chemical etching.

[0023] In another aspect of the method, growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture.

[0024] In another aspect of the method, growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours.

[0025] In another aspect of the method, depositing a dielectric layer over the new oxide layer comprises depositing one or more layers of any combination of AI2O3, SiO2, HfO2, or AlHfOx by atomic layer deposition (ALD).

[0026] In another aspect of the method, depositing a dielectric layer over the new oxide layer comprises depositing the dielectric layer by ALD to a thickness between 10nm and 100nm.

[0027] In another aspect, the method further comprises heating the BSI silicon image sensor to a temperature between 300°C and 400°C.

[0028] In another aspect, the method further comprises removing the silicon substrate and a portion of dielectric material of the silicon wafer of the image sensor in predefined regions by a photolithography process.

[0029] In another aspect of the method, removing the silicon and the portion of dielectric material of the image sensor silicon wafer comprises removing the silicon and the portion of dielectric materials of the image sensor silicon wafer in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds. [0030] In one aspect, a back-side illuminated (BSI) silicon image sensor fabricated according to the methods above.

[0031] In one aspect, a method of fabricating a back-side illuminated (BSI) silicon image sensor is disclosed. The method comprises providing an image sensor comprising a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface, doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region, annealing and activating the dopant implanted region with laser energy, removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface, and depositing a dielectric layer over the image sensor silicon layer. In one aspect, the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface, and the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

[0032] In one aspect, a back-side illuminated (BSI) silicon image sensor is fabricated according to the method above.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various features of the embodiments described herein, together with advantages thereof, may be understood in accordance with the following description taken in conjunction with the accompanying drawings as follows.

[0034] FIGS. 1 A-1 F illustrate a series of cross sectional views of a process of fabricating a BSI silicon image sensor according to at least one aspect of the present disclosure, where:

[0035] FIG. 1 A is a cross sectional view of a BSI silicon image sensor after wafer bonding and thinning of the device wafer, with an oxide layer formed natively after thinning the silicon layer, and prior to implanting a boron dopant in the silicon layer;

[0036] FIG. 1 B is a cross sectional view of a BSI silicon image sensor shown in FIG. 1 A comprising a dopant implanted region formed in the device silicon layer of the BSI silicon image sensor;

[0037] FIG. 1C is a cross sectional view of a BSI silicon image sensor shown in FIG. 1B after annealing and activating the dopant implanted region with laser energy applied in a predetermined pattern; [0038] FIG. 1 D is a cross sectional view of a BSI silicon image sensor shown in FIG. 1C after removing the native oxide layer and exposing the surface of the annealed dopant implanted region;

[0039] FIG. 1 E is a cross sectional view of a BSI silicon image sensor shown in FIG. 1 D with a new oxide layer grown on the surface of the annealed dopant implanted region; and

[0040] FIG.1 F is a cross sectional view of a BSI silicon image sensor shown in FIG. 1E with an atomic layer deposition (ALD) formed over the new oxide layer.

[0041] FIG. 2 is a cross sectional view of specific layers of the silicon layer of the BSI silicon image sensor shown in FIGS. 1A-1F according to at least one aspect of the present disclosure.

[0042] FIG. 3 is a method of fabricating a BSI silicon image sensor shown in FIGS. 1A-1 F according to at least one aspect of the present disclosure.

[0043] Corresponding reference characters indicate corresponding parts throughout the several views. The exemplifications set out herein illustrate various embodiments of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.

DESCRIPTION

[0044] Applicant of the present application owns International Patent Application Serial Number PCT/IB2021/051348, titled BACK ILLUMINATED IMAGE SENSOR WITH IMPLANTED BORON FOR ULTRAVIOLET RESPONSE, and International Patent Application Serial Number PCT/IB2021/051347, titled BACK ILLUMINATED IMAGE SENSOR WITH A DIELECTRIC LAYER THAT NEUTRALIZES EFFECTS OF ILLUMINATION INDUCED OXIDE CHARGE IN ULTRAVIOLET IMAGING CONDITIONS, both filed February 17, 2021 , the disclosures of which are herein incorporated by reference in their respective entireties.

[0045] In one general aspect, the present disclosure provides a method of fabricating a boron-implanted BSI silicon image sensor (CCD or CMOS), in silicon wafer form, with dopant activation and crystal annealing achieved by UV laser exposure such that strong surface accumulation is achieved while also maintaining both dopant activation and crystal annealing at a low enough magnitude that carrier lifetime is limited in the near surface region. Silicon oxide removal and regrowth processes are executed after dopant annealing and are a critical aspect of the general method to achieve the desired functionality of stable response under UV illumination. Subsequent deposition of one or more layers of AI2O3, SiO2, HfO2, or AlHfOx by atomic layer deposition (ALD) may be made over the regrown silicon oxide layer thereby resulting in negative fixed oxide charges formed at the interface. The present disclosure provides a boron-implanted BSI silicon image sensor (CCD or CMOS) produced according to the fabrication process disclosed herein.

[0046] In one general aspect, the present disclosure provides a method of fabricating a silicon photo-detection surface and associated dielectric layers suitable for operation as an image sensor in a BSI geometry, such that collection efficiency into charge readout circuitry of photo-excited carriers in silicon is not sensitive to electro-static effects of photo-excited carriers that become trapped in the SiO2 layer (or other dielectric layer) at or near the surface of silicon. Oxide charging during illumination has a strong effect on mobile hole density in silicon due to electrostatic effects. Hole density at and near the silicon surface is reduced from as-fabricated condition due to the presence of trapped hole charges in oxide. The potential profile in silicon is changed as a result of changes in the hole density, since the fixed dopant density does not change. The potential profile changes to create a potential barrier for electron transport in the direction toward the (front-side) charge readout circuitry. This effect typically results in a reduced UV response, which is undesirable.

[0047] The previously applied methods of boron doping (see Background, above) disclose alternative methods of generating the thin highly-doped layer at the Si side of the Si/oxide interface. For imagers based on these alternative methods, the key to the ability to withstand the highest possible UV/EIIV dose without exhibiting degradation signatures associated with the accumulated damage from high energy photons is not to let the UV/EUV-induced positive charges in the oxide or the silicon/SiO2 interface deplete the silicon at the silicon/SiO2 interface. Such imagers rely on achieving the highest possible boron dopant density at the silicon/SiO2 interface to prevent this surface from being depleted. The segregation of boron atoms at the interface decreases the highest possible dopant density at the interface (see below). Higher interface dopant density is also often achieved at the expense of increasing the layer thickness. Under these conditions, more signal electrons may be lost to recombination.

[0048] In one aspect, the present disclosure arranges the depth profiles of three factors in such a way that the electro-static effects of trapped oxide charge do not cause a reduction of response. The three factors are (i) dopant density, (ii) activated dopant density, and (iii) crystal damage due to implant. Inactivated dopants and un-annealed crystal damage serve to provide electron recombination centers in sufficient density, and in addition to interface defect recombination centers, such that minority carrier (electron) lifetime is very low in the near-surface region which experiences potential profile changes. With a very low lifetime, even in the presence of a favorable potential profile to support electron transport to charge readout circuitry as would be expected to be the case as fabricated prior to accumulation of UV illumination, the probability that photo-excited electrons in this near-surface region will drift or diffuse far enough to be collected before recombination occurs can be very low. In this way, the region of silicon that will experience electro-static influence from oxide charging is configured to have very low response and contribute essentially no carriers to the detected signal. In one aspect, one implementation of the present disclosure is to configure the insensitive region to be only as thick as necessary to achieve stable response, as any larger thickness would result in lower UV response with little impact on stability. Any reduction in the density of potential hole trapping sites in the oxide or interface layers would provide benefit, of course. In one aspect, oxide removal and regrowth steps are included to provide for an oxide layer with lower trap density than would be present with native oxide that had been damaged through implant.

[0049] In one general aspect, the present disclosure provides a method of fabricating a BSI silicon image sensor (CCD or CMOS), in wafer form and thinned by chemical etching and/or chemical-mechanical polishing (CMP) to reveal the epitaxial layer of the device. The thin silicon back surface is subsequently doped with a shallow high-dose boron implant. Damage to the crystal structure incurred during the implant process is annealed and the dopant is partially activated by exposing the silicon surface to multiple UV laser illumination exposures at sub-melt threshold energy density. The poor quality native SiO2 layer (formed after the thinning process and degraded by implant process) is removed by chemical etching. An oxidation process is used to regrow an oxide layer of minimal thickness with better quality than the native oxide layer.

[0050] In one aspect, a dielectric layer, or a stack of more than one dielectric layer, may be deposited directly onto the grown SiO2 layer, which may result in a fixed negative charge outside of the silicon to improve the surface passivation condition of the silicon surface (see below). In other aspects, the dielectric layer may also serve to obtain satisfactory antireflection properties and surface protection. In practice, the additional dielectric layer(s) can be AI2O3, SiO2, HfO2, or AlHfOx deposited by ALD. In some aspects, a thin ALD SiO2 layer may be required as an interface between the deposition surface and the ALD AI2O3, HfO2, or AlHfOx layer(s). According to the technical literature, RuO2 appears be able to achieve similar electrical properties as AI2O3, SiO2, HfO2. However, RuO2 is not transparent in the UV, so may not be useful for the present device. Further, the toxicity of RuO2 will also likely prevent it from being a viable alternative to AI2O3, HfO2, and AlHfOx. A layer stack of one or more than one layer of AI2O3, SiO2, HfO2, or AlHfOx is deposited by ALD over the regrown silicon oxide layer thereby resulting in negative fixed oxide charges formed at the interface. In another example, the ALD layer may be deposited over the silicon layer to the same effect. However, it may be recognized that a layer of silicon oxide may grow naturally between the ALD layer and the silicon. A post fabrication temperature bake can be executed to populate low energy electron states at defect sites in the dielectric stack of the surface protection layer, if comprised of either AI2O3, HfO2 or AlHfOx. This may result in a layer of fixed negative charge outside of the silicon to improve the surface passivation condition of the silicon surface (see below). SiO2 deposited by ALD is not known to provide for negative dielectric charging through a temperature bake process.

[0051] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which examples of the present disclosure are shown. The present disclosure, however, can be embodied in many different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided for thoroughness and completeness, and will fully convey the scope of the present disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0052] Turning now to the figures where FIGS. 1A-1 F illustrate a series of cross sectional views of a BSI silicon image sensor at various points in the fabrication process according to at least one aspect of the present disclosure. The BSI silicon image sensor may be fabricated as a CCD or CMOS device. The BSI silicon image sensor comprises an optical detection layer of silicon, which is a boron implanted region at the surface of a thinned device silicon layer, and image detector readout circuitry at the opposite surface of the same layer of silicon. One aspect of a fabrication process of the boron-implanted BSI silicon image sensor is described below in connection with FIGS. 1A-1F.

[0053] Turning first to FIG. 1A, there is shown a cross sectional view of a BSI silicon image sensor 100 (CCD or CMOS) in silicon wafer form after thinning and prior to implanting a boron dopant into the exposed face of silicon layer 104. The BSI silicon image sensor 100 comprises a thinned silicon device wafer, including silicon layer 104 and device circuitry layers, bonded to a silicon handle wafer (silicon substrate 102). The silicon substrate 102 can be a standard blank silicon wafer having a nominal thickness of 675 microns for mechanical support purpose.

[0054] The silicon layer 104 contains the electronic components for implementing a CCD or CMOS BSI silicon image sensor device. Various layers of the silicon layer 104 are shown in FIG. 2 and described with more specificity with reference thereto. Generally, the silicon layer 104 is fabricated on a silicon wafer substrate with epitaxial layer doped to 150 Ohm-cm resistivity and with various device related implants (both n-type and p-type) to form a CCD charge collection and readout circuitry. The silicon layer 104 has been formed into a thinned layer of silicon, having a nominal thickness of approximately 11 microns, through a substrate removal process after being bonded to a handle wafer for mechanical support. The silicon layer 104 constitutes the normal electronic device layers of a silicon image detector, except for having the ground plane of the conductive silicon substrate removed. In other aspects, the thickness of the silicon layer 104 may vary and is not critical to the functionality of the BSI silicon image sensor 100 for detection of UV illumination. It will be appreciated that in a CMOS device implementation the silicon layer 104 is thinner than a comparable silicon layer in a CCD device implementation. In BSI configuration, the silicon layer 104 operates as an electronic circuit layer on one face, and an optical interaction layer on the opposite face.

[0055] Returning to FIG. 1A, a silicon layer 104 is shown, which was prepared as a high quality optical interface surface using several steps of grinding, polishing, etching, and/or chemical-mechanical-polishing to reach a condition where silicon layer 104 has a thickness of approximately 11 microns. After thinning, a native oxide will form naturally on the surface 108 of the silicon layer 104, and is shown as layer 112. The silicon layer 104 is ready for implantation of a dopant as described below in connection with FIG. 1B.

[0056] FIG. 1 B is a cross sectional view of a BSI silicon image sensor 200 shown in FIG. 1A comprising a dopant implanted region 110 formed in the thinned silicon layer 104 of the BSI silicon image sensor 200. In various aspects, the surface 108 of the thinned silicon layer 104 is doped with a shallow high density boron or boron-11 isotope by implantation process to form the dopant implanted region 110 defining a surface 116.

[0057] In one aspect, the dopant implanted region 110 is doped with a boron-11 isotope implanted to a concentration greater than about 1E20crrr³. In some alternative aspects, the boron-11 isotope may be implanted to a concentration greater than about 5E21 cm^-3. In some aspects, the higher boron dopant concentration may be used in anticipation that the laser annealing process (see below) may not activate all of the implanted boron. In one nonlimiting aspect, a nominal depth of the implanted region may range from about 5 nm to about 20 nm. The thickness of the dopant implanted region 110 is determined by the implant energy and will be influenced by the laser annealing energy, described below.

[0058] FIG. 1C is a cross sectional view of a BSI silicon image sensor 300 shown in FIG. 1B after annealing and activating the dopant implanted region 110 with laser energy applied in a predetermined pattern. The crystal structure damage caused by the implantation process is annealed by a laser to form an annealed dopant implanted region 120 (FIG. 1C). As shown in FIG. 1 C, the boron-11 isotope dopant implanted region 110 is annealed with laser energy applied in a predetermined pattern sufficient to anneal and activate the dopant to the extent that surface passivation effects are achieved, but not to the extent that significant dopant diffusion occurs. In one aspect, the dopant implanted region 110 is activated by exposing the surface 108 of the silicon layer 104 to UV laser light at a sub-melt threshold energy density with multiple laser spot exposures. The sub-melt regime of annealing has much lower dopant diffusion rate than the melt regime, and is effective to maintain the dopant profile at the as-implanted profile, for example at a dopant layer thickness less than about 5 nm to about 20 nm. In one aspect, the laser is a 248nm krypton fluoride (KrF) excimer laser configured to apply energy with a pulse duration of approximately 10ns and an energy density below the melt threshold energy of implanted silicon. The laser annealing energy is optimized so that dopant activation is maximized while minimizing dopant diffusion into the substrate. In one alternative aspect, the annealing process may use microwave energy instead of laser energy for dopant activation. The laser energy is applied in a predetermined pattern comprising a laser spot raster pattern of a series of partially overlapping exposures to cover the surface 116 of the dopant implanted region 110 and create as uniform a total applied laser energy density condition as possible.

[0059] FIG. 1 D is a cross sectional view of a BSI silicon image sensor 400 shown in FIG. 1C after removing the native oxide layer 112 and exposing the surface 116 of the annealed dopant implanted region 120. The native oxide layer is removed by chemical etching, with either a buffered oxide etch or a dilute hydrofluoric acid solution.

[0060] FIG. 1 E is a cross sectional view of a BSI silicon image sensor 500 shown in FIG. 1D with a new oxide layer 124 grown on the surface 116 of the annealed dopant implanted region 120. After removing the native oxide layer 112 a better quality new oxide layer 124 is regrown at a minimal thickness, and therefore will cause a small reduction in thickness of the annealed dopant layer. Ideally the new oxide layer would be free of any defect sites that serve to trap positive charges, though this cannot be achieved in practical methods of implementation. The new oxide layer 124 may be a SiO2 layer grown on the surface 116 of the annealed dopant implanted region 120 to a nominal thickness of approximately 3nm as determined by the growth process. The new oxide layer 124 can be grown either by chemical oxide growth in a SC-1 (standard clean process) mixture, or thermal oxide growth in dry oxygen at a temperature below the upper limits of all materials in the device structure for more than 24 hours. When the new oxide layer 124 is deposited or grown on the surface 116 of the oxide layer at the Si/SiO2 interface, boron segregation may result in a reduction of the dopant density in the silicon side of this interface and an equivalent increase in boron density in the SiO2 side of this interface (that is, at the annealed dopant implanted region 120). The reduction of boron concentration at the Si side of the Si/SiO2 interface can make the Si side of the interface non-degenerate. This may, in turn, result in a potential trap for electrons at the interface, an undesirable result.

[0061] The BSI silicon image sensor 500 according to one aspect of the present disclosure limits the depth of electro-statically induced changes of the potential profile in silicon layer 104 resulting from accumulation of positive charges trapped in the new oxide layer 124 near the Si/SiO2 interface defined at the surface 116 of the silicon layer 104.

[0062] FIG.1 F is a cross sectional view of a BSI silicon image sensor 600 with an atomic deposition layer 128 formed over the new oxide layer 124. UV light enters the surface 130 of the atomic deposition layer 128 on the illumination side 132. In some aspects, the atomic deposition layer 128 may result in a layer of negative fixed oxide charge trapped at the interface. Atomic deposition layers can comprise one or more dielectric materials in a multiple layer stack. Ideally the atomic deposition layer 128 is comprised of dielectric materials with bandgap greater than the photon energy of illumination. For 193nm illumination, there are few such material choices compatible with silicon wafer process techniques. In one aspect intended for detection of illumination in the range 190 to 370nm, the atomic deposition layer 128 is formed on the surface 126 of the new oxide layer 124 by depositing a single layer of AI2O3, SiO2, HfO2, or AlHfOx in an ALD process to a thickness of about 10 nm to about 100nm. It may be understood that the ALD layer may be deposited directly on the silicon layer after the native oxide layer has been removed. However, it is recognized that a thin silicon oxide layer may form naturally over the exposed silicon layer during the ALD process. In another aspect intended for detection of illumination in the range 190nm to 370nm, the atomic deposition layer 128 is formed on the surface 126 of the new oxide layer 124 by depositing a layer of AI2O3 and subsequently a layer of SiO2 in an ALD process. In an additional aspect, the atomic deposition layer thicknesses may be chosen to further create an optimal anti-reflective coating at the illumination wavelength. The thickness of the atomic deposition layer 128, however, is not critical to the functionality of the BSI silicon image sensor 600 and the thickness may be selected for, among other properties, its optical anti-reflection properties. In one aspect intended for detection of 193nm illumination, the AI2O3 material may be deposited by an ALD process at 200°C using tetramethylammonium (TMA) and water (H2O) precursors to a thickness of about 10nm to about 40nm. In an alternative aspect, the AI2O3 annealing process may use ozone instead of water.

[0063] As noted above, when the new oxide layer 124 is deposited or grown on the surface 116 of the oxide layer at the Si/SiO2 interface, boron segregation may result in a reduction of the dopant density in the silicon side of this interface. The reduction of boron concentration at the Si side of the Si/SiO2 interface can make the Si side of the interface non-degenerate. This may, in turn, result in a potential trap for electrons at the interface, an undesirable result. To counter this effect, the ALD layers may be deposited and annealed in a fashion to result in levels of negative fixed oxide charge at the silicon/oxide interface (surface 116) with a magnitude that is greater than about 2E12 cm'² and an interface defect state density that is ideally less than 5E11 eV'¹ COT² (see below). In some aspects, after the atomic deposition layer 128 is deposited, the device may be annealed without breaking vacuum in dry nitrogen for about 30 minutes. The fixed negative charge at the oxide side of the silicon/oxide interface (surface 116) may attract a corresponding layer of holes to the Si side of the Si/SiO2 interface (surface 116), preventing the Si side of the Si/SiO2 interface from being depleted. The layer of holes will only be a few atoms thick, thin enough that most electrons photogenerated in the Si side of the Si/SiO2 interface will have drifted towards the charge collection area before they can recombine with the holes at the Si interface.

[0064] Many alternative passivation materials for c-Si have been reported to have strongly negatively charged oxide/nitride charges. These may include HfO2, Ta2O5, Ga2O3, TiO2, Nb2O5, and AIN. However, not all of these are suitable replacements for ALD AI2O3 in this application because of fundamental material constraints, such as that the spectral limits that are determined by the band structure of the material. There are also technological limits that determine parameters such as spatial uniformity, reproducibility, and the presence of nonideal behavior such as hysteresis.

[0065] The ALD layer can comprise a stack of different dielectrics. These multiple ALD layers can allow the optical and electric properties of the ALD film to be optimized more effectively.

[0066] The electrical properties of the ALD oxides depend critically on a number of variables, including the type of ALD precursors used (for example H2O or 03), the deposition temperature, the gas in the post-deposition anneal environment, the postdeposition anneal temperature, the surface properties of the layer on which the ALD oxide is deposited (whether it is hydrophobic or hydrophilic), and the post-deposition thermal budget that the ALD layer is exposed to. In some non-limiting aspects, the deposition temperature may range between about 150°C and about 250°C. In some non-limiting aspects, the postdeposition anneal temperature may range between about 300°C and about 400°C.

[0067] While it is possible to generate negative oxide charges by using precursors that leave impurities such as chlorine in ALD AI2O3, it may not be good practice depend on the presence of components that are considered undesirable and that the producers intend to eliminate. Further, the impurity level may not be consistent across fabrications. Instead, negative fixed oxide charge may arise from the intrinsic localized defect states which do not need external doping or removal of oxygen to create vacancies. AI2O3 can have two bonding environments for the Al atoms: coordinated tetrahedral (charge -3) and octahedral (charge +3) Al. Octahedral coordination is preferred in bulk AI2O3. The tetrahedral sites determine the number of easy-to-be-filled charges in the excitonic defect states around the Fermi level EF. These are the most sensitive defects concerning the electrical properties. In some aspects, it is believed that the negative fixed charge originates from the material properties of the ALD AI2O3 itself.

[0068] Even when ALD AI2O3 is deposited over Si directly, with no native SiO2, a thin AlSiOx layer forms between AI2O3 and Si. In the aluminum silicate interface layer, Al atoms exist as tetrahedral AIOx. In general, tetrahedrally coordinated cation is dominant in silica. The aluminum silicate interface increases the proportion of tetrahedrally coordinated Al near the AI2O31 Si interface. In some aspects, it is proposed that the tetrahedrally coordinated cation may further result in an enrichment of interstitial oxygen atoms at the oxygen-rich interfacial AIOx or AlSiOx at the Si/SiO interface. In this manner, a layer of negative fixed oxide charge may form on the ALD AIOx to SiOx interface. In some aspects, the level of negative fixed oxide charge at the negative fixed oxide charge layer may have a surface charge magnitude that is greater than about 2E12 cm^-2 and an interface defect state density that is ideally less than 5E11 eV'¹ cm^-2. Such charge magnitudes and interface defect state densities may result from the ALD deposition temperature ranging between about 150°C and about 250°C and the post-deposition anneal temperature ranging between about 300°C and about 400°C. As discussed above, after the atomic deposition layer 128 is deposited, the device may be annealed without breaking vacuum in dry nitrogen for about 30 minutes.

[0069] The fact that the negative fixed oxide charges of ALD AI2O3 is physically located at the aluminum silicate interface is important because the ALD layer also serve as the antireflection coating for the imager. When the negative charges are located at the ALD AI2O31 SiO2 interface, this permits the use of very thin ALD AI2O3 having a range in thickness between about 10 nm and about 100 nm. while maintaining nearly the same magnitude of negative charge as a thicker layer. Shorter wavelength UV require thinner AR coating for maximum photon absorption in silicon. In extreme UV (EUV) imaging, the ALD oxide absorbs EUV photons. Any EUV photon absorbed in the ALD oxide is one less photon that can be absorbed in silicon. To maximize the quantum efficiency of the EUV detector (e.g. for 13.5 nm photons used in semiconductor wafer lithography), the ALD oxide may be as thin as possible, for example having a thickness ranging between about 5 nm and about 10 nm. Hence, the location of the negative charges at the ALD oxide I SiO2 interface is an advantage. The addition of the negative fixed oxide charge layer at the ALD AIOx to SiOx interface may attract a layer of holes to the Si side of the Si/SiO2 interface, preventing the Si side of the Si/SiO2 interface from being depleted. The layer of holes will only be a few atoms thick, thin enough that most electrons photogenerated in the Si side of the Si/SiO2 interface will have drifted towards the charge collection area before they can recombine with the holes at the Si interface. [0070] Post fabrication, the BSI silicon image sensor 600 may be baked at a predetermined temperature to populate low energy electron states at defect sites in the AI2O3, HfO2, or AlHfOx atomic deposition layer 128 and achieve a fixed negative charge outside of silicon to improve surface passivation condition of the silicon surface. In one aspect, the post fabrication temperature bake may include heating the BSI silicon image sensor 600 at a temperature in the range 300°C to 400°C to enable charge activation of the atomic deposition layer 128.

[0071] Following the fabrication process described in connection with FIGS. 1A-1 F, the BSI silicon image sensor 600 will undergo additional processing to complete the boron implanted BSI silicon image sensor. The additional processing may include a photolithography process using photoresist to form a patterned metallic light shield layer. The additional processing may also include a photolithography process using photoresist to form open regions in the AI2O3, SiO2, HfO2, or AlHfOx dielectric atomic deposition layer 128 by wet chemical etching to remove the atomic deposition layer 128 in certain areas. A photolithography process also may be employed to form open regions in the device silicon layer and other device circuitry layers, such as oxide insulation layers, to create features such as bond pads, and scribe lanes, by reactive ion etching to fully remove the silicon, and chemical etch to remove oxide layers in certain areas.

[0072] In some alternative aspects, a light shield or light blocking material may be used to cover areas of the BSI surface in which illumination is to be excluded. In some aspects, the light blocking material may comprise tungsten titanium (TiW) or titanium nitride (TiN). The light blocking layer may be deposited across the entire imaging surface and then removed where they are not needed, thus exposing that portion of the BSI surface to light. A photo lithographic step may be used to define the areas with and without the light shield. Additional processes may also include etching to remove thin layers of titanium and titanium nitride (Ti/TiN), which are used in the CCD fabrication process as barrier metal layer but present difficulty in implementing electrical contact through wire bonds. The aluminum metal layer may then be exposed in defined regions and is compatible with common techniques to make electrical contact through wire bonds.

[0073] Additional processes include assembling the BSI silicon image sensor 600. These processes may include, for example, wafer probing, wafer dicing, die bonding in chip carriers, wire bonding, windowing, and completion of device assembly.

[0074] FIG. 2 is a cross sectional view of the specific layers of the silicon layer 104 of the BSI silicon image sensor 100 shown in FIG. 1A according to at least one aspect of the present disclosure. The silicon layer 104 is fabricated prior to providing the wafer for wafer- wafer bonding and other processes described in connection with FIGS. 1A-1F. The silicon layer 104 is formed as one part of a conventional silicon device wafer comprised of a thin “device” layer, typically epitaxially grown doped silicon, on top of a high conductivity silicon substrate through a typical fabrication process to form a “conventional” CCD image sensor. One minor modification from the typical CCD fabrication process used to form front illuminated image sensors that was implemented for the process to form the BSI image sensor 600 is the exclusion of the steps to open bond pads to the front side. This leaves the wafer front surface topology as flat as possible, which is beneficial for wafer bonding, but precludes any electrical device test even though the sensor circuits are fully fabricated at this stage and able to be tested to monitor fabrication success. Additional steps include preparation of the image sensor wafer for wafer-wafer bonding by deposition of a thick silicon oxide layer. Wafer-to-wafer bonding can be accomplished by several methods. Application of an adhesive material to one or both wafers, and curing of the adhesive at an appropriate temperature is a common method. Another method avoids use of adhesive material by achieving strong covalent molecular bonds between oxygen atoms on the faces of two wafers brought into intimate contact, such method referred to as oxide-oxide molecular bond process. The device wafer is edge trimmed in outer periphery region to remove all device wafer in a region of potential weaker bond.

[0075] Still with reference to FIG. 2, the layers of the silicon layer 104 are formed during a CCD wafer fabrication process in the order from the top layers (176 and 174) first and the bottom layers (154, 152) last, prior to wafer-wafer bonding. Wafer bonding can be achieved by use of a wafer bonding material layer 150 that bonds the silicon layer 104 to the silicon substrate 102 (FIG. 1A), which is needed for mechanical support once the device wafer is thinned.

[0076] FIG. 3 is a method 700 of fabricating the BSI silicon image sensor of FIGS. 1 A-1 F according to at least one aspect of the present disclosure. With reference now to FIGS. 1 A- 1F and 2, to initiate the method 700, a silicon image sensor in silicon wafer form is provided 702. The silicon image sensor wafer is bonded to a silicon handle wafer for support. The substrate of the silicon image sensor wafer is removed to expose the surface of silicon layer 104. The surface 108 of the silicon layer 104 is doped 706 with a shallow high density boron implant to form a dopant implanted region 110.

[0077] After implanting the surface 108 of the silicon layer 104 with a boron-11 isotope to form the dopant implanted region 110, the crystal structure of the dopant implanted region 110 is annealed 708 with a laser in a predetermined pattern to anneal and activate the dopant. [0078] The annealed dopant implanted region 120 is activated by exposing the surface 108 of the silicon layer 104 to UV laser light at sub-melt threshold energy density with multiple laser spot exposures. The laser energy is applied in a predetermined pattern comprising a laser spot raster pattern of a series of exposures to cover the surface 116 of the dopant implanted region 110 with a uniform total energy density condition. The laser annealing energy may be optimized so that dopant activation is maximized while minimizing dopant diffusion into the substrate. In one non-limiting alternative approach, microwave energy may be used instead of laser energy for dopant activation.

[0079] After annealing and activating 708 the dopant implanted region 110, the native oxide layer 112 is removed 710 by chemical etching, for example, either by buffered oxide etch or a diluted hydrofluoric acid solution. A new oxide layer 124 is grown 712 on the surface 116 of the activated dopant implanted region 120. The new oxide layer 124 may be grown 712 by either chemical oxide growth by immersion in SC-1 mixture or thermal oxide growth at in dry oxygen at a temperature below the upper limits of all materials in the device structure.

[0080] An atomic deposition layer 128 is deposited 714 on the surface 126 of the new oxide layer 124. As disclosed above, the atomic deposition layer 128 may be deposited directly on the etched silicon, although a thin oxide layer will naturally grow between the silicon and the atomic deposition layer 128. In one aspect, the atomic deposition layer 128 is formed by depositing 714 AI2O3 by ALD at 200°C using tetramethylammonium (TMA) and water (H₂O) precursors to a thickness of 15nm. In one aspect, a post fabrication temperature bake may include heating the BSI silicon image sensor 600 at a temperature of 350°C to enable charge activation of the 15nm thick atomic deposition layer 128 to capture electron charge (negative) into the AI2O3, dielectric atomic deposition layer 128. In some aspects, the atomic deposition layer 128 may be annealed without breaking vacuum in dry nitrogen for about 30 minutes.

[0081] Additional processing may include photolithography to form 716 open regions in the atomic deposition layer 128, new oxide layer 124, and the device silicon layer to form bond pads, and scribe lanes, in certain areas. The open regions extend from the top surface through to the first metal layer of the device circuitry layers to create wire bond pads.

[0082] Additional processing includes titanium nitride etching to remove a thin layer of Ti/TiN that is adjacent to the first metal layer. The aluminum metal layer is exposed in defined regions to enable electrical contact through wire bonds. [0083] Additional processing includes assembling the BSI silicon image sensor 600. These processes may include, for example, wafer probing, wafer dicing, die bonding in chip carriers, wire bonding, windowing, and completion of device assembly.

EXAMPLES

[0084] Various aspects of the subject matter described herein are set out in the following examples.

[0085] Example 1. providing an image sensor comprising a silicon wafer bonded face-to- face to a handle wafer, wherein a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface; growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region; and depositing a dielectric layer over the new oxide layer, wherein the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface, wherein the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

[0086] Example 2. The method of Example 1, wherein depositing a dielectric layer over the new oxide layer comprises depositing a dielectric layer using atomic layer deposition at a temperature between 150°C and 250°C.

[0087] Example 3. The method of Example 2, further comprising annealing the deposited dielectric layer at a temperature between 300°C and 400°C.

[0088] Example 4. The method of Example 3, wherein annealing the deposited dielectric layer at a temperature between 300°C and 400°C comprises annealing the deposited dielectric layer at a temperature between 300°C and 400°C under a dry nitrogen environment without breaking vacuum.

[0089] Example 5. The method of Example 3, wherein depositing a dielectric layer over the new oxide layer comprises depositing a layer of AI2O3 over the new oxide layer.

[0090] Example 6. The method of Example 1, wherein doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a near surface region of the silicon layer with a boron-11 isotope at a concentration between 1 E20cnr³ and 5E21cnr³, and having a nominal thickness of approximately 5nm to 30 nm. [0091] Example 7. The method of Example 1, wherein doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a surface of the image sensor silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, thereby obtaining a dopant concentration profile between 1 E20crrr³ and 5E21cnr³ extending over a depth between 5nm and 30nm.

[0092] Example 8. The method of Example 1, wherein annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern.

[0093] Example 9. The method of Example 8, further comprising applying the laser energy at an energy density per pulse to produce activation for a limited portion of the dopant and to produce a minimum profile change of a dopant concentration, when compared to a preannealed dopant concentration profile.

[0094] Example 10. The method of Example 8, wherein annealing and activating the dopant implanted region with laser energy comprises applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region.

[0095] Example 11. The method of Example 8, wherein annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with laser energy at a laser wavelength between 190nm and 370nm.

[0096] Example 12. The method of Example 1 , wherein removing a native oxide layer formed on the optical entrance surface comprises removing the native oxide layer by chemical etching.

[0097] Example 13. The method of Example 1 , wherein growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture.

[0098] Example 14. The method of Example 1 , wherein growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours.

[0099] Example 15. The method of Example 1 , wherein depositing a dielectric layer over the new oxide layer comprises depositing one or more layers of any combination of AI2O3, SiO2, HfO2, or AlHfOx by atomic layer deposition (ALD).

[0100] Example 16. The method of Example 15, wherein depositing a dielectric layer over the new oxide layer comprises depositing the dielectric layer by ALD to a thickness between 10nm and 100nm. [0101] Example 17. The method of Example 1 , further comprising heating the BSI silicon image sensor to a temperature between 300°C and 400°C.

[0102] Example 18. The method of Example 1 , further comprising removing the silicon substrate and a portion of dielectric material of the silicon wafer of the image sensor in predefined regions by a photolithography process.

[0103] Example 19. The method of Example 18, wherein removing the silicon and the portion of dielectric material of the image sensor silicon wafer comprises removing the silicon and the portion of dielectric materials of the image sensor silicon wafer in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds.

[0104] Example 20. A back-side illuminated (BSI) silicon image sensor fabricated according to the method of Examples 1-19.

[0105] Example 21. A method of fabricating a back-side illuminated (BSI) silicon image sensor, the method comprising: providing an image sensor comprising a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface; and depositing a dielectric layer over the image sensor silicon layer, wherein the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface, wherein the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

[0106] Example 22. A back-side illuminated (BSI) silicon image sensor fabricated according to the method of Example 21.

[0107] While specific aspects of the present disclosure have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of which is to be given the full breadth of the claims appended and any and all equivalents thereof. [0108] Those skilled in the art will recognize that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to claims containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.

[0109] In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that typically a disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms unless context dictates otherwise. For example, the phrase “A or B” will be typically understood to include the possibilities of “A” or “B” or “A and B.” [0110] With respect to the appended claims, those skilled in the art will appreciate that recited operations therein may generally be performed in any order. Also, although various operational flow diagrams are presented in a sequence(s), it should be understood that the various operations may be performed in other orders than those which are illustrated, or may be performed concurrently. Examples of such alternate orderings may include overlapping, interleaved, interrupted, reordered, incremental, preparatory, supplemental, simultaneous, reverse, or other variant orderings, unless context dictates otherwise. Furthermore, terms like “responsive to,” “related to,” or other past-tense adjectives are generally not intended to exclude such variants, unless context dictates otherwise.

[0111] It is worthy to note that any reference to “one aspect,” “an aspect,” “an exemplification,” “one exemplification,” and the like means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, appearances of the phrases “in one aspect,” “in an aspect,” “in an exemplification,” and “in one exemplification” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more aspects.

[0112] Any patent application, patent, non-patent publication, or other disclosure material referred to in this specification and/or listed in any Application Data Sheet is incorporated by reference herein, to the extent that the incorporated materials is not inconsistent herewith.

As such, and to the extent necessary, the disclosure as explicitly set forth herein supersedes any conflicting material incorporated herein by reference. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material set forth herein will only be incorporated to the extent that no conflict arises between that incorporated material and the existing disclosure material.

[0113] The terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including") and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. As a result, a system that "comprises," "has," "includes" or "contains" one or more elements possesses those one or more elements, but is not limited to possessing only those one or more elements. Likewise, an element of a system, device, or apparatus that "comprises," "has," "includes" or "contains" one or more features possesses those one or more features, but is not limited to possessing only those one or more features. [0114] In summary, numerous benefits have been described which result from employing the concepts described herein. The foregoing description of the one or more forms has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The one or more forms were chosen and described in order to illustrate principles and practical application to thereby enable one of ordinary skill in the art to utilize the various forms and with various modifications as are suited to the particular use contemplated. It is intended that the claims submitted herewith define the overall scope.

Claims

1. A method of fabricating a back-side illuminated (BSI) silicon image sensor, the method comprising: providing an image sensor comprising a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface; growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region; and depositing a dielectric layer over the new oxide layer, wherein the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface, wherein the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

2. The method of claim 1 , wherein depositing a dielectric layer over the new oxide layer comprises depositing a dielectric layer using atomic layer deposition at a temperature between 150°C and 250°C.

3. The method of claim 2, further comprising annealing the deposited dielectric layer at a temperature between 300°C and 400°C.

4. The method of claim 3, wherein annealing the deposited dielectric layer at a temperature between 300°C and 400°C comprises annealing the deposited dielectric layer at a temperature between 300°C and 400°C under a dry nitrogen environment without breaking vacuum.

5. The method of claim 3, wherein depositing a dielectric layer over the new oxide layer comprises depositing a layer of AI2O3 over the new oxide layer.

6. The method of claim 1 , wherein doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a near surface region of the silicon layer with a boron-11 isotope at a concentration between 1 E20crrr³ and 5E21crrr³, and having a nominal thickness of approximately 5nm to 30 nm.

7. The method of claim 1, wherein doping a portion of the optical entrance surface of the image sensor with a boron implant comprises doping a surface of the image sensor silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, thereby obtaining a dopant concentration profile between 1 E20cm^-3 and 5E21cm^-3 extending over a depth between 5nm and 30nm.

8. The method of claim 1, wherein annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern.

9. The method of claim 8, further comprising applying the laser energy at an energy density per pulse to produce activation for a limited portion of the dopant and to produce a minimum profile change of a dopant concentration, when compared to a pre-annealed dopant concentration profile.

10. The method of claim 8, wherein annealing and activating the dopant implanted region with laser energy comprises applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region.

11. The method of claim 8, wherein annealing and activating the dopant implanted region with laser energy comprises annealing and activating the dopant implanted region with laser energy at a laser wavelength between 190nm and 370nm.

12. The method of claim 1, wherein removing a native oxide layer formed on the optical entrance surface comprises removing the native oxide layer by chemical etching.

13. The method of claim 1, wherein growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture.

14. The method of claim 1, wherein growing a new oxide layer on the optical entrance surface comprises growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours.

15. The method of claim 1 , wherein depositing a dielectric layer over the new oxide layer comprises depositing one or more layers of any combination of AI2O3, SiO2, HfO2, or AlHfOx by atomic layer deposition (ALD).

16. The method of claim 15, wherein depositing a dielectric layer over the new oxide layer comprises depositing the dielectric layer by ALD to a thickness between 10nm and 100nm.

17. The method of claim 1, further comprising heating the BSI silicon image sensor to a temperature between 300°C and 400°C.

18. The method of claim 1, further comprising removing the silicon substrate and a portion of dielectric material of the silicon wafer of the image sensor in predefined regions by a photolithography process.

19. The method of claim 18, wherein removing the silicon substrate and a portion of dielectric material of the silicon wafer of the image sensor comprises removing the silicon substrate and a portion of dielectric material of the silicon wafer of the image sensor in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds.

20. A back-side illuminated (BSI) silicon image sensor fabricated according to the method of claims 1-19.

21. A method of fabricating a back-side illuminated (BSI) silicon image sensor, the method comprising: providing an image sensor comprising a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the silicon wafer of the image sensor is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the optical entrance surface of the image sensor with a boron implant to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the silicon substrate of the silicon wafer and exposing the silicon surface; and depositing a dielectric layer over the image sensor silicon layer, wherein the dielectric layer comprises a negative fixed oxide charge layer at a dielectric/new oxide interface, wherein the negative fixed oxide charge layer has a fixed oxide charge magnitude greater than 2E12 cm^-2, and an interface defect state density less than 5E11 eV'¹ cm^-2.

22. A back-side illuminated (BSI) silicon image sensor fabricated according to the method of claim 21.