JPS6155791B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photodiode, and more particularly to a photodiode.
The present invention relates to a method of manufacturing an n ⁺ -P-π-P ⁺ silicon avalanche photodiode.

With the advent of lasers and their promise as carrier sources for optical communications, there has been great interest in developing photodetectors that are sensitive to weak signals and respond quickly to optical intensity modulation. Optical receivers usually include a photodetector and its output amplifier, and are used in the Journal of Luminescence, Vol. 7, pp. 390-414.
(1973)) by H. Melchior (H.
The following general performance criteria based on "Sensitivity High Speed Photodetector for Visible Light and Near-Infrared Light Demodulation" by John Melchior) should be met. (1) high responsivity at the incident optical signal wavelength (quantum efficiency), (2) sufficient electrical bandwidth (i.e., response speed) to accommodate the information bandwidth, and (3) introduction by the detection and amplification process. minimal excess noise.

A common type of photodetector is a photodiode that essentially contains a depleted semiconductor region with a high electric field that serves to separate photoexcited electron-hole pairs via band-to-band excitation. A high speed photodiode is usually connected to a relatively low impedance and allows a photoexcitation carrier to induce a photocurrent in its load circuit while the carrier moves through the high field region. Photodiodes that detect visible and near-infrared radiation are normally operated with relatively large reverse bias voltages to reduce carrier drift time and lower their diode capacitance without producing significantly large dark currents (Melchior's The above report
397 pages). In a reverse biased p-i-n photodiode, for example, when radiation is incident on its p-layer, the radiation that is not reflected at the surface will penetrate the photodiode material some distance before being absorbed and giving rise to light carriers. Electrons and holes generated in the high field region of the junction (i-layer) and minority carriers that diffuse from the p and n layers into the junction before recombination are collected across the high field region and emit light. Contributes to current.

The effective quantum efficiency and photodiode response speed are significantly affected by the wavelength used and the photodiode response speed are significantly influenced by the wavelength used and the diode material and design. For example, silicon photodiodes are preferred for near ultraviolet and infrared radiation below about 1 micron. However, due to the significant variability in their light transmission depth, silicon photodiodes must be optimized for each wavelength of interest (Melchior, supra, p. 400). The response speed decreases with increasing wavelength because the width of the high electric field region increases.

Dark current in a photodiode limits its sensitivity to weak optical signals and can originate from its solid interior or from its surface. Surface leakage current is an inherent problem with high resistance silicon photodiodes, but it can be eliminated by special surface treatments and various guard ring structures. However, bulk leakage current in silicon photodiodes is mainly due to carrier generation within the space charge layer. Low dark currents of 10 ^-6 to 10 ^-8 A/mm ³ of depletion volume have been achieved in carefully treated silicon diodes (Melchior, supra, p. 405).

A particularly useful form of photodiode is the avalanche photodiode (APD).
, which combines optical signal detection with internal amplification of the photocurrent. The internal current gain is determined by the carrier passing through the high electric field region of the high reverse bias junction and gaining sufficient energy by emitting new electron-hole pairs via an impact ionization mechanism.
Occurs during APD. The current gain of the APD varies depending on the statistical nature of the carrier increase. Even in the sterically uniform avalanche region, statistical gain variations result in a noise rise above the multiple shot noise, and this variation is usually expressed in terms of excess noise figure, usually given by:

F(M)=<i _M ² >/<i _p h ² >×M ² (1) In the above equation, <i _M ² > is the mean square noise current of the APD output, which is equal to the primary photocurrent. Mean square noise <i
_p h ² >, and the latter is multiplied by the average gain M squared. The ionization rate α of electrons in silicon APDs is much larger than the ionization rate β for holes (e.g. β/α = 0.2~,2), so F(M) is more sensitive to hole injection than electron injection. increases much faster (Melchior's paper, p. 409). This consideration suggests that silicon n ⁺ -p-π-p ⁺ APDs are back-illuminated (i.e., light is injected in the p ⁺ layer away from the junction and electrons are injected into the increasing region) and front-illuminated ( That is, it suggests that the light is not incident at the n ⁺ layer near the junction and the holes are also injected into the increased region). n ⁺
―p―π―p ⁺ The application of this principle in the design of silicon APDs is the
Transactions on Electron Devices, Vol.ED―
14, No. 5, pp. 239-251 (1967), "On Optimal Avalanche Photodiodes" by H. W. Ruegg. In this type of APD, which is particularly useful for fast sensing of GaAs laser wavelengths, the carrier increase is bound to a narrow n ⁺ -p region and a broad π region serves primarily as a collector, with the carrier gain being absorbed by the light incident on the p ⁺ layer. It acts on the photoexcited electrons that are generated. As Roog points out (page 247, column 1): "Optimized devices require an illuminated surface (p ⁺ layer) opposite the p-n ⁺ junction to ensure pure electron injection into the augmented region." Therefore, he said, "The total element thickness in this case must be of the order of the depth of penetration of the detected light."
(20-30 μm for GaAs laser wavelength). He adds, "Wafers of this thickness cannot be handled, so the only obvious solution is to etch a local cavity (at the location of the device) into a fairly thick silicon wafer." Unfortunately, the requirement to etch cavities of uniform thickness or to equivalently thin the substrate by wrapping substantially increases the cost of manufacturing such APDs. The increased cost is due to thinner wafers that are more difficult to handle, tend to be more fragile and bend, making mask alignment difficult, and packaging difficult. .

Therefore, the solution is to form the structure in a thick p ⁺ layer and use front illumination through the n ⁺ layer,
And the wafer must not be made thin. However, as previously discussed, mixed hole and electron injection occurs with a concomitant increase in noise. Prior art front-illuminated n ⁺ -p-π-p ⁺ silicon APDs (e.g., U.S. Pat. No. 3,886,579, 1975
patent dated May 27, 2013, Ouch et al., the structure was not optimized to reduce excessive noise, provide low leakage current, and be reliable over long periods of time. Therefore, the problem is that such receiver sensitivity is typically -55 dBm (e.g.
At a wavelength of 825 μm and a data rate of 44.7 Mbit/s), the device is useful in optical communications systems. Therefore, reducing the noise adverse conditions and dark current during relying on APD without using overly complex processing and front illumination
It would be desirable to develop general lower cost and handling advantages for APDs.

Therefore, ^the main purpose of the present invention is to
The purpose is to manufacture p ⁺ type APD silicon photodiodes.

Another object of the present invention is to develop an APD that allows front illumination without incurring excessive noise pollution.
is to manufacture.

Yet another object of the present invention is to produce a front-illuminated APD that is relatively easy to handle during manufacture and relatively inexpensive to manufacture.

Another object of the invention is to produce such an APD with low excess noise.

Yet another object of the present invention is high quantum efficiency,
The objective is to manufacture an APD that also has short-time response, low dark current, and high reliability.

These and other objects can be achieved by the present invention - a method for manufacturing front-illuminated silicon photodiodes, which includes (1) epitaxially forming a highly resistive π-type silicon layer on a low dislocation density, highly conductive P-type silicon substrate; (2) Form an n-type guard ring in the π layer by phosphorus diffusion, (3) Form a P-type channel stop around the guard ring in the π layer by boron diffusion, (4) Introducing phosphorus into the backside of the substrate to get defects and/or impurities and ramping the furnace temperature during steps (5)(2), (3) and (4). (by gradually changing the temperature) to suppress crystal defects and (6)
(7) forming an antireflection/passivation coating on at least the n ⁺ layer and the region between the guard ring and ^the channel stop; and (8) forming an antireflection/passivation coating on the substrate, the guard ring, and the channel stop. The process consists of forming an electrical contact to the channel stop so that the guard ring contact overlaps the π-n metallurgical bond surface, and the channel stop overlaps the π-p metallurgical bond surface. ing.

The next example is a high quantum efficiency (GaAs-AGaAs
>90 at laser wavelength, e.g. 0.80-0.90μm
%), short-time response (e.g. 1ns), high gain (e.g. M
= 100), low excess noise figure (e.g. F at M = 100)
(M) = 4~6), front illumination with low dark current (e.g. 10 ^-11 A) and high reliability n ⁺ - p - π - p ⁺
It concerns the manufacture of silicon APDs. In this specific example, the method of the invention provides (1) a highly resistive (>300 Ω-cm) π on a highly conductive p ⁺ type silicon substrate;
The mold silicon layer is epitaxially grown to a thickness of approximately 30-60 μm, and the epitaxial growth procedure used makes the method suitable for batch processing of large diameter wafers (e.g., 3 inches (76 mm) in diameter). )
(3) early deposition and diffusion of boron forms a p-type channel stop around the guard ring; (4) the dose is approximately 4-6. ×10 ¹² cm ^-2 from 30
Graft 150 KeV boron ions into the π layer, (5) drive the implanted boron ions by heating to about 1150-1250°C for 2-8 hours in a suitable atmosphere, and reduce the p-layer thickness to about 2-12μ. (6) mask the p layer and
POC ₃ by heating to about 1000-1100℃ for 30-60 minutes
or introducing phosphorus into the backside (P substrate) from any other suitable source, thereby gettering defects and/or impurities, step (7)(2) or (6)
During the process, the furnace temperature is ramped to suppress crystal defects, (8) a thin n ⁺ layer with a thickness of about 0.1 to 1.0μ is formed in the p layer, and (9) a thin SiO layer is formed on the n ⁺ layer. Form an anti _- reflection and passivation coating consisting of a 1/4 wavelength thick _Si3N4 layer on top of ₂ , (10) after _{the SiO2} formation and before the _Si3N4 formation. Approximately 850-950℃ for 30 minutes
(11) form a highly conductive p ⁺⁺ contact layer on the backside of the p ⁺ substrate, (12) form electrical contacts to the substrate, guard ring, and channel stop, and the guard ring contact The process consists of overlapping the π-n metallurgical joint surface and causing the channel stop contact to overlap the π-p metallurgical joint surface.

In addition, a feature of this APD fabrication method is that the n ⁺ layer is made extremely thin and suppresses excess noise caused by hole injection and radiation incident on the layer. Although this layer is extremely thin, edge droop is prevented even at reverse biases of 250-400V due to the unique guard ring structure used.

Another feature of this APD manufacturing method is that the ion implantation step (4), the drive-in step (5), and the subsequent steps including heating are alternated with each other, and the electric field distribution in the multiplication region (P layer) is substantially It is an upper triangle. This distribution provides a balance between the competing effects of field-dependent ionization rate and optical carrier mixed injection in the high field region, approaching the low-noise performance of pure electron injection over a wide range of diffusion depths.

Another feature of this n ⁺ -p-π-p ⁺ APD manufacturing method is that it mainly involves the HC getter step (10) and the P
By combining the getter step (6) with the channel stop formed in step (3), the dark current is reduced by two to three orders of magnitude compared to the prior art.

These and other objects of the invention, together with its various features and advantages, will be readily understood from the following more detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is an isometric view of an n ⁺ -p-π-p ⁺ silicon APD manufactured in accordance with an embodiment of the present invention.

FIG. 2 is a graph of the electric field and multiplication distribution calculated for a theoretical APD of the type shown in FIG.

n ⁺ ―p―π―p ⁺ APD Referring to the drawings, FIG.
The structure of APD is then described, followed by its operation and manufacturing method.

The APD, shown in cross-section in FIG. 1, is made by epitaxially growing a highly resistive π-type silicon layer 12 on a p ⁺ silicon substrate 10. A P layer 14 is formed over most of the upper surface of the π layer 12 and a thin n ⁺ layer 1 is formed.
6 is formed in the P layer. Part of this structure allows the fundamental n ⁺ −p−π, where the P layer is the multiplication region
―p ⁺ APD is determined. However, in actual devices, the shape is modified to match the conditions of the system in which the APD functions. Specifically, an n-type guard ring 18 is formed in the π layer 12 and surrounds the P layer 14 and the n ⁺ layer 16. n ⁺ layer 16 is P layer 14
It extends laterally beyond the guard ring and overlaps the guard ring to prevent edge drooping of the n ⁺ -P junction under normal operating conditions. This n ⁺ layer also includes a ring metal contact and a field plate 20 (e.g. PtSi) to which the positive terminal of a bias voltage source (not shown) is connected.
-Ti-Pt-Au or acts as a contact layer for A).

Next, the P-type channel stop 22 is attached to the π layer 1.
Form in 2. Although in a distant relationship,
The channel stop surrounding the guard ring 18 acts to prevent an inversion layer at the surface of the highly resistive π layer 12. A ring metal contact and field plate 24 (for example Ptsi-Ti-Pt-Au or A) are made in the P-type channel stop 22 and thereby in the P ⁺ substrate 10. Contact with the substrate 10 is also made through a metal layer 26 (eg Ti-Au) formed on the bottom surface of the substrate. Another metal layer 30 (for example Au) is formed on the ceramic block 32. Conductive epoxy layer 28
or bond the APD to block 32 using other suitable means (eg, a solder preform). The negative terminal of the bias voltage source is connected to metal layer 30 and optionally also to channel stop field plate 24. Channel stop field plate 24 overlaps junction 34 to suppress ion accumulation in or with respect to the surface of dielectric layer 35 above surface 34 of the p-π metallurgical junction, thereby reducing noise and leakage currents. Both improve presser foot and reliability. For the same reason, the guard ring field plate 20 is
- overlapping the surface portion 36 of the π metallurgical joint;

In order to reduce the reflection of the radiation 38 to be detected, the n ⁺ layer is made of a thin _SiO2 layer 40 with a thickness of 1/4 wavelength.
Cover with an anti-reflection coating made of ₄ layers of Si ₃ N. These layers also serve to passivate the surface. _{A 4-} layer layer of SiO ₂ and Si ₃ N - the latter designated as layer 35 - is also formed between the guard ring and the channel stop, and the SiO ₂ layer is thick there as it remains from the previous step described below. Please note that.

In operation, the contacts provide the reverse bias (typically a few hundred volts) necessary to fully deplete the π layer 12 and the P layer (laterally down to about line 13 and vertically down to substrate 10). 2
0 and 30, and the radiation 38 enters the active area of the device, a circular zone 44 in the center of the guard ring. This radiation first generates photoexcited carriers in the π layer. These carriers are multiplied in the high field P layer 14. Electrons are collected in the n ⁺ layer and holes are collected in the P ⁺ substrate 10. The resulting photocurrent flows into a load (not shown) connected across contacts 20 and 30. Since this device is front illuminated, mixed carrier injection occurs. That is, the radiation incident on the n ⁺ layer 16 creates holes, the holes are injected into the P layer and are increased there, and the radiation that enters the P and π layers generates electrons, which are increased. Injected into the double area. To approach the low noise properties of pure electron injection (ie, of back-illuminated APD), the n ⁺ layer is made very thin and the electric field (E) distribution is formed as shown in FIG.
That is, the electric field, which is almost zero in the n ⁺ layer, rises very rapidly near the n ⁺ -p junction and forms a substantially triangular shape in the p layer. Due to this triangular distribution, p−π
Multiplication of extremely low noise of electrons entering near the interface (X ₂ ) and relatively low noise (compared to rectangular electric field distribution) of mixed holes and electron injection in the P layer resulting from front illumination. (multiplication)
degree (M).

The thinness of the n ⁺ layer also helps to reduce light absorption into this layer, thereby maintaining high quantum efficiency. If this were not the case, a large number of minority carriers generated in the n ⁺ layer would recombine before reaching the high electric field P layer.

Although the graph in FIG. 2 merely shows theoretically calculated values, we will demonstrate the realization of its essential features with respect to the n ⁺ -p-π-p ⁺ silicon APD manufactured based on a detailed embodiment of this invention. made possible as follows.

(1) Low dislocation density, P-type silicon substrate 10 doped with boron at approximately 5×10 ¹⁷ to 1.2×10 ¹⁸ cm ^-3
High resistance (>300Ω−
cm) An epitaxial silicon layer 12 was grown. In order to collect at least 95% of the photoexcited carrier with about 0.825μ radiation, this epitaxial layer is preferably 35μ thick or more. The epitaxial layer is grown in a reactor using dichlorosilane (SiH ₂ C ₂ ) as the silicon source. In detail, the growth rate is approximately the attachment temperature.
It is 3.5μ/min at 1100-1200℃. Using diborane as the doping source, the HC etch was carried out at 1160°C before the growth reached 1 micron.
I went there. Since these high resistance layers are grown on a heavily doped substrate, care should be taken to suppress autodoping from this substrate.

(2) A SiO ₂ layer was then formed on top of this epitaxial layer, which was _e.g.
Silicon was oxidized at 1050°C for 2 hours. An opening was formed in the oxide for the formation of guard ring 18 by standard photolithographic techniques.

(3) Phosphorus was then diffused into this opening. A layer of phosphor glass was predeposited thereon using POC ₃ as a source at 900-950°C for 15-30 minutes. The phosphor glass layer is removed and the phosphor is converted into an epitaxial layer by heating at 1100-1200°C for 30-60 minutes (non-critical) in an atmosphere of _N2 + 0.1% _O2 . 12 was diffused into the underlying portion. In order to reduce some crystal defects formed in this layer, this intermediate device structure (wafer) is placed in a furnace maintained at a temperature of approximately 900°C, and then the temperature is gradually increased.
Raised to 1100-1200℃ (e.g. 4-8℃/
minutes). For the same reason, the temperature was gradually lowered to 900° C. after diffusion for the aforementioned time. Through this diffusion process, an n-type guard ring 18 was formed.

(4) The oxidation and masking step (2) was repeated to create an opening in the channel stop.

(5) Boron was then diffused into the opening, but at 950
BN as a source for 1-2 hours at ~975 °C
This was done by pre-depositing a layer of boron glass within the opening. The boron glass layer is transferred and the boron is then removed in an atmosphere of substantially 100% _O2 .
It was diffused into the underlying portion of epitaxial layer 12 by heating at 1100-1200° C. for 30-60 minutes (non-critical). As described in step (3), the furnace temperature was set at 900°C and gradually changed between temperatures. A P-type channel stop 22 was formed by this diffusion process.

(6) The oxidation and masking step (2) was repeated again to form an opening adjacent to and partially overlapping the guard ring 18. Boron ions were then implanted into the top surface of epitaxial layer 12.
Energy and dose are 30-50KeV and 4 respectively
-6×10 ¹² cm ^-2 . It is especially important to adjust the dose to within ±5% for a given device design. If this dose is too high, the entire heating cycle (e.g. the time and temperature of all subsequent steps including heating) may be modified to longer times and/or higher temperatures, if possible. There must be. Conversely, if the initial dose is low, the device will have very little gain and high voltage drop.

(7) After injection (implantation), approximately 1150 ~
At 1250℃ for 2-8 hours in nitrogen or argon.
Boron ions were driven into the epitaxial layer by heating in an O ₂ 0.1-1.0% atmosphere. 1200
℃ for 4 hours.
A P layer 14 of μ was formed. However, this layer is 2-12μ thick for a given operating range and 5μ for an APD with M=100 at 300V.
~7μ is desirable. The furnace temperature was ramped between 900°C and the drive temperature as in steps (3) and (5).

(8) All wafers were then reoxidized at approximately 1050° C. for 1 hour. The oxidation was removed only from the back side of the substrate 10.

(9) A phosphor glass layer was then formed on the backside of the substrate 10 using POC ₃ as a source. Other phosphorus sources, such as PBr ₃ , are also suitable in this pre-deposition as well as in the phosphorus pre-deposition described above. substantially
30-60 at 1000-1100℃ in _N2 + 0.1% _O2 atmosphere
The phosphorus was diffused onto the backside by heating for 1 minute. The strain and/or maladaptive dislocations introduced by the phosphorus atoms are effective in getting impurities (particularly rapidly diffusing metal impurities) and other defect nucleation sites. This process played a significant role in reducing dark current in the APD of this invention. Step (3) and
As in (5), gradually raise the furnace temperature between 900℃ and the diffusion temperature.

(10) The phosphor glass layer on the back side was then removed and the wafer was reoxidized at about 900 °C for 10 minutes. Standard photolithography techniques were used to mask the oxide and create openings in the n ⁺ layer 16.

(11) The n ⁺ layer 16 is deposited using phosphorous predeposition (i.e., deposition of a phosphorous glass layer by POC ₃ ) and then
It was formed by heating at 930° C. for 20-30 minutes in an atmosphere of substantially N ₂ +0.1% O ₂ . This glass layer was then removed. This process results in a thickness of approximately 0.3μ.
An n ⁺ layer was obtained. In the subsequent heating step, 0.1-1.0
The thickness was increased to approximately 0.4μ, where μ is suitable but particularly preferred. Alternatively, by arsenic pre-deposition or arsenic ion implantation and drive-in
It is also possible to form an n ⁺ layer. This step supplements the previous boron implant and thereby p−n ⁺
Determine the depth of the joint. Time and temperature are critical to its deeper diffusion, reducing the total change in the P layer and increasing the breakdown voltage. And injection-
This step in conjunction with drive steps (6) and (7) creates the desired triangular electric field distribution.

(12) At this intermediate stage, the device was tested and its current-voltage characteristics and leakage current were measured. Those diodes that met specifications were subjected to subsequent operations. Those that were overdoped in critical P layer 14 that did not meet specifications were carefully heated to specifications. Testing and reheating can be repeated until the device meets specifications.

(13) Devices meeting specifications are coated with a thin layer 40 of SiO ₂ (approximately 100-200 angstroms) using well-known dry oxidation techniques.

(14) This SiO ₂ layer was then annealed at approximately 850–950 °C for 10–30 min in an atmosphere of 1–5% HC in N ₂ . This process is carried out in oxides.
This is important for effectively getting or trapping mobile ions such as Na ions to reduce leakage current.

(15) After capture, a quarter-wave layer 42 of Si ₃ N ₄ (approximately 1000
angstrom) using chemical vapor deposition
Deposit on the SiO ₂ layer 40. Layers 40 and 42 serve to passivate the device against external impurities and act as an antireflection coating in the active area surrounded by guard ring 18.

(16) Contact windows were then opened in layers 40 and 42 for the field plates 20 and 24 of the guard ring and channel stop.

(17) Next, the substrate (initially about 500 mm thick)
Etch or wrap the back side of μ) and approximately 75
μ is removed, thereby removing the phosphorus layer formed in the diffusion step (for example gettering step (9)). To lower the contact resistance, boron ions are added at a dose of 2 to 4
Inject into the back side at approximately 30-50 KeV for ×10 ¹⁵ cm ^-2 . Then boron ions are added to the nitrogen atmosphere.
Activate by heating at 750-800℃ for 30-60 minutes.

(18) Using appropriate masking, PtSi―Ti―Pt
- The field plates 20 and 24 of the guard ring and channel stop were formed by depositing metal using the Au metallization method. π-p and π-
To avoid ion accumulation on the n-junction surfaces 34 and 36, these field plates overlap each metallurgical junction. This oxide-
Since the nitride layers are thinner than these layers and a higher reverse bias voltage is applied, without this overlap configuration, impulse noise is generated by surface microplasma and/or leakage currents.

(19) The device was then annealed at 300-320° C. for about 16-24 hours in an atmosphere of N ₂ +8-15% H ₂ .
This is to reduce the surface state density and anneal the Au in the contact layer to improve adhesion.

(20) Finally, a Ti--Au alloy layer 26 was deposited on the substrate 10. A conductive epoxy layer 28 was used to bond the APD to the Au layer of the ceramic mounting block 32.

By the above procedure, we fabricated n ⁺ -p-π-p ⁺ silicon APDs. Here, for example, the P ⁺ substrate 10 is 500μ thick and the epitaxial π layer 12 is 50μ thick and has a resistance of 300Ω-cm.
or more, the ion-implanted P layer 14 is about 6μ thick and has a substantially triangular electric field distribution, and n ⁺
Layer 16 was approximately 0.4μ thick. The diameter of the active area 44 is approximately 100μ, the inner and outer diameters of the guard ring 18 are 180μ and 290μ, respectively, and those of the channel stop 22 are approximately 100μ.
They were 350μ and 480μ.

CW operation at room temperature double heterostructure GaAs-A
Radiation from GaAs bonding laser (λ=0.825μ)
was connected to the active area of this APD via a fiber.

The APD was operated with P layer 14 and π layer 12 fully depleted at 100V and a breakdown voltage of 375V.
Current gains of 5 to several hundred were achieved over this voltage range. At a gain of 100 the excess noise figure was only 4-6, exceeding the shot noise limit. The total dark current was only about 10 ^-11 A and the final increased portion was about 10 ^-13 A. The quantum efficiency was over 95% and the response speed was about 1 ns. When incorporated into an optical receiver, the sensitivity is 0.825μ and
It was -55 dBm at 44.7 Mbit/s. From a reliability standpoint, the mean time to failure was about 10 ³ to 10 ⁴ hours according to a bias stress aging test at 200°C. The specified values for the more important parameters used in the manufacture of this APD are as follows.

In step (3), phosphorus was diffused at 1200°C for 1 hour.

In step (5), boron was diffused at 1150°C for 1 hour.

In step (6), the dose of boron is 5.5×10 ¹² cm ^-2 ±5
% was implanted at a voltage of 150 KeV.

In step (7), boron ions were driven at 1200°C for 4 hours.

In step (9), the phosphor glass layer on the back side was heated at 1100°C for 1 hour.

In step (11), the phosphor glass layer of the P layer is heated at 925℃.
Heat for 30 minutes.

In step (14), the SiO ₂ layer is heated with N ₂ +5% HC.
Annealed at 900°C for 10 minutes.

[Brief explanation of the drawing]

Figure 1 shows n ⁺ -p manufactured according to the present invention.
-π-p ⁺ It is a perspective view of a silicon APD. FIG. 2 is a graph of electric field and increase factor distribution. [Explanation of symbols of main parts] 10...P ⁺ substrate, 12...π silicon layer, 14...P
Layer, 16...n ⁺ layer, 18... Guard ring, 2
2...Channel stop.

Claims (1)

[Claims] 1. A method for manufacturing a front-illuminated n-p-π-p ⁺ silicon avalanche photodiode, comprising: (a) on a low dislocation density, highly conductive p-type silicon substrate; A highly resistive π-type silicon layer is grown epitaxially, (b) an n-type guard ring is formed in the π layer by phosphorus diffusion, and (c) a p-type guard ring is formed in the π layer and around the guard ring by boron diffusion. (d) gradually changing the diffusion temperature between steps (b) and (c) to reduce crystal defects; (e) forming a channel stop in the surface portion of the π layer within the guard ring; implanting boron ions, (f) driving the implanted boron ions by heating to form a p layer, (g) forming an n ⁺ layer in the p layer, (h) at least above the n ⁺ layer; an anti-reflective coating and a passivating coating in the area between the guard ring and the channel stop; and (i) providing an electrical contact to the substrate, the guard ring and the channel stop, the guard ring contact being (j) the implantation step (e); Drive process (f) and forming process
(g) in combination with subsequent steps including heating to make them mutually compatible, so that the resulting electric field distribution in the p-layer is substantially triangular and of the desired magnitude. 2. The manufacturing method according to claim 1, characterized in that (k) the step of introducing phosphorus to the back surface of the substrate, and the temperature changing step (d) in the step (k). 3. In the manufacturing method according to claim 1 or 2, forming an antireflection coating and a passivation coating during the (h) process includes (1) forming _two thin SiO layers, (2) HCl A manufacturing method characterized in that: (3) annealing of the SiO ₂ layer at a high temperature in a containing atmosphere; and forming ₄ Si ₃ N layers about 1/4 wavelength thick on the SiO ₂ layer. 4. A method according to claim 1 or 2 or 3, in which step (a) the epitaxial layer is grown to a thickness of at least 30 μm and a resistivity of at least 300 Ω-cm; (f) driving the boron ions to form a p-layer with a thickness of about 2-12μ; and (g) forming the n ⁺ layer with a thickness of about 0.1-1.0μ; Characterized by a wavelength of approximately 0.8μ
A method of manufacturing a diode suitable for detecting radiation of ~0.9μ. 5. In the manufacturing method according to claim 1 or 4, in step (e), 30 to 150 KeV boron ions are implanted at a dose of about 4 to 6 x 10 ¹² cm ^-2 , and in step (f) The boron ions are substantially reduced to N ₂ +0.1 to 1.0%.
A manufacturing method characterized by heating and drive-in at approximately 1150-1250°C for 2-8 hours in an O ₂ atmosphere. 6. In the manufacturing method according to claim 1, 4, or 5, in step (d) the temperature is gradually changed between the diffusion temperature and a lower high temperature, and in step (k) Phosphorus adheres the phosphor glass layer and 30~
In step (h) (2), the SiO ₂ layer is heated to about 850 °C for 10 to 30 minutes in an atmosphere containing about 1 to 5% HC. A manufacturing method characterized by annealing at ~950℃. 7. In the manufacturing method according to claim 2 or 3 or 4 or 5 or 6, in step (k) depositing the phosphor glass layer using POC ₃ as a source. A manufacturing method characterized by 8. In the manufacturing method according to claim 1, in step (i) of forming electrical contacts on the substrate, (1) the back surface of the substrate is sufficiently removed to remove the phosphorus-doped layer formed in the previous step. (2) Voltage approximately 30 to 50 KeV, dose approximately 2 to 4 × 10 ¹² cm ^-2
A manufacturing method characterized by implanting boron ions into the back surface thereof, and (3) heating at approximately 750 to 800°C for 30 to 60 minutes in a nitrogen atmosphere. 9. The manufacturing method according to claim 1, including the step of annealing after step (i) at a temperature of 300 to 320° C. for 16 to 24 hours in a substantially N ₂ + 8 to 15% H ₂ atmosphere. A manufacturing method characterized by 10 In the manufacturing method according to claim 1 or 4 or 5 or 6 or 7, in the step (b), the temperature is first about 900 to 950°C, 15 to
Deposit the phosphor glass layer for 30 hours, then reduce the furnace temperature.
Devices manufactured at 900°C are heated to virtually N ₂ +
placed in the furnace with 0.1% O ₂ atmosphere, then gradually increase the temperature to about 1100-1200 °C and then keep the temperature constant for about 30-60 minutes to obtain the desired phosphorus diffusion; Next, a guard ring is formed by gradually lowering the temperature to 900°C and taking out the device from the furnace, and in step (c), the boron glass layer is first heated at about 950-975°C.
The glass layer was deposited in 1 to 2 hours, and after removing the glass layer, the temperature of the furnace was lowered to about 900℃, and the glass layer was completely coated.
Place the device to be fabricated into a furnace with _O2 atmosphere, and then gradually increase the temperature in the furnace to about 1100-1200 °C and then keep the temperature for about 30-60 minutes to obtain the desired boron diffusion. The channel stop is formed by keeping the temperature constant and then gradually lowering the temperature to 900°C and then taking out the manufactured device from the furnace. As in step c), the temperature of the furnace is gradually changed between approximately 900℃ and the drive-in temperature of boron ions, and in step (k), the temperature of the furnace is increased.
A manufacturing method characterized by gradually changing the heating temperature between 900°C and the heating temperature for phosphorus introduction, similar to step (b) or step (c).