CN114975672A - Structure and preparation method of back-incident near-infrared enhanced silicon avalanche photodetector - Google Patents
Structure and preparation method of back-incident near-infrared enhanced silicon avalanche photodetector Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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Abstract
A structure and a preparation method of a back incidence near infrared enhanced silicon avalanche photodetector comprise the following steps: substrate, pi-type layer, p-type layer, n + A layer, a channel-type protective groove penetrating the p-type layer, a silicon dioxide insulating layer and a first electrode; a substrate undercut region, a silicon pillar region and a second electrode are also included below the structure. According to the invention, by arranging the silicon column region and the channel type protection groove, the response of different wavelengths of the photoelectric detector under a near-infrared band is enhanced, the distribution of a fringe electric field is regulated and controlled, the breakdown characteristic of a device is effectively regulated, and the excessive noise is reduced; in addition, the invention adopts micron-scale process in the preparation process, has lower precision requirement and higher process fault tolerance rate compared with the nanometer-scale process, and achieves the aim of reducingThe preparation cost is beneficial.
Description
Technical Field
The invention relates to photoelectric detection research and an avalanche photodetector structure, in particular to a structure of a back-incident near-infrared enhanced silicon avalanche photodetector and a preparation method thereof.
Background
With the continuous development of leading-edge technologies such as automatic driving and the like, the performance requirements of devices, namely photoelectric detectors, of a detection receiving end are higher and higher, and meanwhile, the photoelectric detectors are used in an optical fiber communication system, a radar imaging system, a laser ranging system and the like. Avalanche photodetectors, particularly silicon-based avalanche photodetectors, stand out of the detector family due to their advantages of small size, high internal gain, easy integration, etc.
The main incidence modes of the current avalanche photodetector are front incidence, back incidence and side incidence, wherein the front incidence needs n + The zone layer thickness is low to reduce the excess noise of photo-generated holes introduced by the multiplication zone as much as possible. When the guard ring is adopted to inhibit edge breakdown, although the depth of the guard ring can be accurately controlled by ion implantation, lateral diffusion can be generated and internal crystal lattices are damaged; due to the light absorption coefficient of the silicon material, the light responsivity to the near infrared band is very low, the infrared absorption can be enhanced by utilizing the technologies such as nano imprinting and the like, but the cost of introducing the nano microstructure is too high, and meanwhile, the different wavelength enhanced responses under the near infrared are difficult to accurately design.
Disclosure of Invention
It is therefore an objective of the claimed invention to provide a structure and a manufacturing method of a back-incident near-infrared enhanced silicon avalanche photodetector, which at least partially solve at least one of the above-mentioned problems.
To achieve the above object, as one aspect of the present invention, there is provided a structure of a back-incident near-infrared enhanced silicon avalanche photodetector, including:
a substrate;
a pi-type layer disposed on the upper surface of the substrate for absorbing incident light;
a p-type layer disposed on the pi-type layer;
n + a layer disposed on the p-type layer, wherein the p-type layer is coupled to the n-type layer + The layers together form an avalanche region;
the channel type protective groove penetrates through the p-type layer and is used for improving the breakdown voltage;
the upper surface of the p-type layer is divided into a middle circular part and a peripheral circular part by the channel-type protective groove; wherein n is + The layer is located on the middle circular part of the p-type layer;
a silicon dioxide insulating layer covering n + The layer, the channel type protective groove and the peripheral circular part of the p-type layer are used as surface passivation layers;
a first electrode covering n + A silicon dioxide insulating layer above the layer for forming an ohmic contact anode;
the substrate hollowed-out region is arranged on the lower surface of the substrate and is used for reducing the optical loss of incident light outside the absorption region and reducing the transit time of carriers;
the silicon column region is arranged at the bottom of the groove in the substrate hollowed area and used for enhancing the absorption of near-infrared band light;
and the second electrode covers the bottom of the substrate, is positioned at the periphery of the hollowed-out region of the substrate and is used for forming an ohmic contact cathode.
As another aspect of the present invention, a method for preparing a back-incident near-infrared enhanced silicon avalanche photodetector is also disclosed, which comprises:
preparing a pi-type layer on the upper surface of the substrate;
preparing a p-type layer on the pi-type layer;
preparing a silicon dioxide layer on the p-type layer;
etching the silicon dioxide layer to form an ion implantation window;
preparation of n at ion implantation window + A layer;
etching the p-type layer and part of the n + A layer forming a channel-type protection groove; the p-type layer is divided into a middle circular part and a peripheral circular part by a channel-type protection groove;
in p-type layer, channel-type protective groove and n + Preparing a silicon dioxide insulating layer on the layer;
at n + Preparing a first electrode on the silicon dioxide insulating layer above the layer;
etching a groove on the lower surface of the substrate to prepare a substrate hollowed-out area;
preparing a second electrode on the lower surface of the substrate and at the periphery of the hollowed-out area of the substrate;
and preparing a silicon column region at the bottom of the groove in the substrate hollowed region to finish the preparation of the novel back-incident near-infrared enhanced silicon avalanche photodetector.
Based on the technical scheme, the structure and the preparation method of the back-incidence near-infrared enhanced silicon avalanche photodetector have at least one of the following advantages compared with the prior art:
1. according to the invention, the inductive coupling plasma etching method is adopted to etch the micron-sized silicon column, and the nano-scale process is not adopted in the preparation process, so that the preparation method has the advantages of low precision requirement, high process fault tolerance, low preparation cost and good repeatability compared with the nano-scale process, and meanwhile, the response enhancement to the near-infrared band is still kept, so that the realization of the near-infrared band high-responsiveness avalanche photodetector under low precision becomes possible;
2. according to the invention, by designing different silicon column diameters and silicon column intervals and etching silicon column regions with different depths, the response of different wavelengths in a near-infrared band can be enhanced, and the quantum efficiency can be adjusted;
3. according to the invention, the distribution of the fringe electric field can be regulated and controlled by etching the channel type protection Ring (Guard-Ring), namely the channel type protection groove, so that the breakdown of the fringe electric field of the active area is effectively inhibited, and meanwhile, the breakdown characteristic of a device can be effectively regulated by designing different etching depths, so that the device has the characteristic of regulating and controlling the electric field of the channel under the low-precision process;
4. the invention adopts a back incidence mode, improves the near-infrared band response, reduces the excess noise, and simultaneously can accurately regulate and control the fringe electric field through the precise design of the channel protection ring area, thereby achieving the effect of simultaneously improving three characteristics (namely edge breakdown inhibition, low noise and near-infrared band response) of the avalanche photodetector.
Drawings
FIG. 1 is a schematic cross-sectional view of a back-incident near-infrared enhanced silicon avalanche photodetector in an embodiment of the present invention;
FIG. 2 is a schematic top plan view of a back-incident NIR-enhanced silicon avalanche photodetector in accordance with an embodiment of the present invention;
FIG. 3 is a bottom plan view of a back-incident NIR enhancing silicon avalanche photodetector in accordance with an embodiment of the present invention;
fig. 4 is a graph of the relationship between the depth of the trench protection trench and the breakdown voltage in the embodiment of the present invention.
Description of the reference numerals:
1-a substrate;
2-substrate undercut area;
a 3-silicon column region;
4-channel type protection groove;
a 5-pi type layer;
a 6-p type layer;
7-n + a layer;
8-a silicon dioxide insulating layer;
9-a first electrode;
10-second electrode.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
The invention mainly aims to provide a structure and a preparation method of a back-incident near-infrared enhanced silicon avalanche photodetector, aiming at regulating and controlling the distribution of a fringe electric field by utilizing a channel etching type protection ring, and further etching a micron-sized silicon column after a back substrate is hollowed by a certain thickness, so that the back-incident near-infrared enhanced silicon avalanche photodetector has the characteristics of regulating and controlling the response of the near-infrared wave band by utilizing a channel regulating and controlling electric field and the back silicon column under a low-precision process.
The invention discloses a structure of a back incidence near-infrared enhanced silicon avalanche photodetector, which comprises the following components:
a substrate 1;
a pi-type layer 5 disposed on the upper surface of the substrate 1 for absorbing incident light;
a p-type layer 6 disposed on the pi-type layer 5;
n + a layer 7 disposed on the p-type layer 6, wherein the p-type layer 6 is in contact with the n + The layers 7 together form an avalanche region;
a channel-type protective groove 4 penetrating the p-type layer 6 for increasing breakdown voltage;
the upper surface of the p-type layer 6 is divided into a middle circular part and a peripheral circular part by the channel-type protective groove 4; wherein n is + Layer 7 is located on the central circular portion of p-type layer 6;
a silicon dioxide insulating layer 8 covering n + The layer 7, the channel type protective groove 4 and the peripheral circular part of the p-type layer 6 are used as surface passivation layers;
a first electrode 9 covering n + On the silicon dioxide insulating layer 8 above the layer 7, for forming an ohmic contact anode;
the substrate hollowed area 2 is arranged on the lower surface of the substrate 1 and is used for reducing the optical loss of incident light outside an absorption area and reducing the transit time of a carrier;
the silicon column region 3 is arranged at the bottom of the groove of the substrate hollowed-out region 2 and used for enhancing the absorption of near-infrared band light;
and a second electrode 10 covering the bottom of the substrate 1 and located at the periphery of the substrate hollow region 2 for forming an ohmic contact cathode.
In some embodiments of the present invention, the substrate 1 has a thickness of 70 to 150 μm.
In some embodiments of the present invention, the depth of the undercut region 2 is 30 to 60 μm, for example, may be 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm;
in some embodiments of the present invention, the undercut region 2 is in the shape of a cylindrical recess.
In some embodiments of the present invention, the silicon pillar region 3 comprises at least 2 silicon pillars;
in some embodiments of the invention, the shape of the silicon pillar comprises a cylinder;
in some embodiments of the invention, the height of the silicon pillars is 8 to 15 μm, for example, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm;
in some embodiments of the present invention, the silicon pillars have a spacing period of 5 to 10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm;
in some embodiments of the present invention, when the silicon pillar is shaped as a cylinder, the diameter of the bottom of the silicon pillar is 3 to 8 μm, and may be, for example, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm.
In some embodiments of the present invention, the thickness of the pi-type layer 5 is 30 to 70 μm;
in some embodiments of the invention, the doping concentration of the pi-type layer 5 is 1 × 10 14 To 5X 10 14 cm -3 。
In some embodiments of the present invention, the p-type layer 6 has a thickness of 4 to 10 μm, and may be, for example, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm;
in some embodiments of the invention, the p-type layer 6 has a doping concentration of 1 × 10 15 cm -3 To 3X 10 15 cm -3 ；
In some embodiments of the invention, said n + The thickness of the layer 7 is 0.1 to 0.5. mu.m, and may be, for example, 0.1. mu.m, 0.2. mu.m, 0.3. mu.m, 0.4. mu.m, or 0.5. mu.m.
In some embodiments of the present invention, the shape of the channel-type protection groove 4 includes an annular groove;
in some embodiments of the present invention, the channel-type protection groove 4 has a width of 1 to 6 μm, and may be, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm;
in some embodiments of the present invention, the depth of the channel-type protection groove 4 is greater than the thickness of the p-type layer 6 and less than the sum of the thickness of the p-type layer 6 and the thickness of the pi-type layer 5.
In some embodiments of the present invention, the material used for the first electrode 9 includes aluminum, gold, titanium gold or titanium platinum alloy;
in some embodiments of the invention, the thickness of the first electrode 9 is 300 to 600 nm.
In some embodiments of the present invention, the material used for the second electrode 10 includes aluminum, gold, titanium gold or titanium platinum alloy;
in some embodiments of the present invention, the thickness of the second electrode 10 is 300 to 600 nm.
The invention also discloses a preparation method of the back incidence near-infrared enhanced silicon avalanche photodetector, which comprises the following steps:
preparing a pi-type layer 5 on the upper surface of the substrate 1;
preparing a p-type layer 6 on the pi-type layer 5;
preparing a silicon dioxide layer on the p-type layer 6;
etching the silicon dioxide layer to form an ion implantation window;
preparation of n at ion implantation window + A layer 7;
etching the p-type layer 6 and part of the n + A layer 7 forming a channel-type protective groove 4; the p-type layer 6 is divided into a middle circular part and a peripheral circular part by a channel-type protective groove 4;
in the p-type layer 6, the channel-type protective groove 4 and n + Preparing a silicon dioxide insulating layer 8 on the layer 7;
at n + A first electrode 9 is prepared on the silicon dioxide insulating layer 8 above the layer 7;
etching a groove on the lower surface of the substrate 1 to prepare a substrate hollowed-out area 2;
preparing a second electrode 10 on the lower surface of the substrate 1 and at the periphery of the substrate hollowed-out region 2;
and preparing a silicon column region 3 at the bottom of the groove in the substrate hollowed-out region 2 to finish the preparation of the novel back-incident near-infrared enhanced silicon avalanche photodetector.
In some embodiments of the present invention, the n is etched when the channel-type protective groove 4 is prepared + The layer 7 has a width of 2 to 4 μm.
In order to further understand the summary, features and advantages of the present invention, the following description is further provided with several preferred embodiments. The materials used in the following examples are either commercially available or prepared by themselves by methods reported in the literature. The following examples are intended to illustrate the present invention and are not intended to limit the present invention.
In one embodiment of the present invention, a novel back-incident near-infrared enhanced silicon avalanche photodetector is disclosed, as shown in fig. 1, 2 and 3, including: thinned p + A type substrate (i.e. a substrate 1), a region hollowed out to a certain depth (i.e. a substrate hollowed-out region 2), an epitaxial pi-type layer (i.e. a pi-type layer 5) positioned above the substrate 1, an epitaxial p-type layer 6 positioned above the pi-type layer 5, and an n-type layer adjacent to the p-type layer 6 + Layer 7 at n + Channel-type protective grooves 4 on both sides of the layer 7, middle micron-sized silicon pillar regions (i.e., silicon pillar regions 3) directly below the light-absorbing pi-type layer (i.e., pi-type layer 5), and lower electrodes (i.e., second electrodes 10) and n below the substrate 1 + An upper electrode 9 (i.e., a first electrode 9) over the layer 7.
The depth of the substrate hollowed-out area 2 is 30-60 mu m, so that an etching space for the next step of silicon column etching is reserved.
P after thinning + The type substrate (i.e. substrate 1) is p + High doping concentration of 1 × 10 to form ohmic contact with the lower electrode (i.e., the second electrode 10) 19 cm -3 ～1×10 21 cm -3 。
The middle silicon column region (namely the silicon column region 3) etched on the back is obtained by inductively coupled plasma etching, the diameter of the silicon columns is 3-8 mu m, the height of the silicon columns is 8-15 mu m, the silicon column interval is 5-10 mu m, and the silicon column interval is distributed at equal intervals.
The pi-type layer 5 is p after thinning + The substrate (i.e. substrate 1) is obtained by epitaxial growth, the thickness is 30-70 μm, and the doping concentration is 1 × 10 14 cm -3 ～5×10 14 cm -3 。
The p-type layer 6 is obtained by epitaxial growth on the pi-type layer 5, the thickness of the p-type layer is 4-10 mu m, and the doping concentration of the p-type layer is 1 multiplied by 10 15 cm -3 ～3×10 15 cm -3 。
N is said + The layer 7 is obtained after the p-type layer 6 is subjected to two times of ion implantation of phosphorus ions, and the dosage of the first time of phosphorus ion implantation is 3 multiplied by 10 15 cm -3 ～5×10 14 cm -3 The injection energy is 50 keV-200 keV, the annealing advancing temperature is 850-1050 ℃, and the annealing advancing time is 50-80 s; the dosage of the second phosphorus ion implantation is 1 × 10 14 cm -3 ～5×10 15 cm -3 The implantation energy is 30 keV-60 keV, the annealing temperature is 850-950 ℃, and the annealing time is 50-80 s.
The channel-type protective groove 4 is formed by etching inductively coupled plasma and is positioned at the n + Both sides of layer 7 but etched areas are again in contact with the above-mentioned n + The layer 7 is partially overlapped, the width of the channel protection grooves 4 on the two sides is 2-6 mu m, the etching depth is 0-6 mu m, and the channel protection grooves are not etched until the avalanche region is etched (the instant etching depth is less than the sum of the thickness of the p-type layer 6 and the thickness of the pi-type layer 5), and n + The width of the overlapping portion of the layers 7 is 2 to 4 μm.
The first electrode 9 and the second electrode 10 are metal film electrodes, the thickness of the electrodes is 300-600 nm, and the metal material can be aluminum Al, gold Au, titanium-gold alloy Ti/Au or titanium-platinum-gold alloy Ti/Pt/Au.
When the device works, light radiation or various reflected lasers excited by a detected substance are absorbed by a photosensitive surface (silicon-containing column region 3) and a pi-type layer 5 of the novel back-incidence near-infrared enhanced silicon avalanche photodetector to generate photon-generated carriers, wherein the photon-generated electrons drift to an avalanche region, namely a p-type layer 6 and an n-type layer 5 + The interface region of the layer 7 is multiplied, and the original photo-generated charges and the avalanche multiplied charges respectively continue to drift towards the electrodes at the two ends, so that photocurrent is generated.
The preparation method of the novel back-incident near-infrared enhanced silicon avalanche photodetector comprises the following steps:
step 1: preparing a surface-cleaned and dried p-type highly-doped silicon single-crystal-wafer substrate material (namely a substrate 1) with a crystal orientation of (111);
step 2: a layer of pi-type layer 5 with a doping concentration of 1 x 10 is grown on a silicon single crystal wafer (i.e. substrate 1) by vapor phase epitaxy 14 cm -3 ～5×10 14 cm -3 The thickness of the film is 30-70 mu m, and the film is used for absorbing incident light;
and step 3: on the pi-type layer 5 obtained by the vapor phase epitaxial growth, furtherA p-type layer 6 with a doping concentration of 1 × 10 is epitaxially grown in vapor phase 15 cm -3 ～3×10 15 cm -3 The thickness is 4-10 μm; wherein the p-type layer (6) and the n + layer (7) form an avalanche region together;
so far, the epitaxial growth of the epitaxial wafer used for the subsequent flow wafer is finished.
And 4, step 4: growing a layer of silicon dioxide on the silicon epitaxial wafer by adopting magnetron sputtering or PECVD, wherein the thickness of the silicon dioxide is about 0.2-0.5 mu m;
and 5: in SiO 2 Spin coating a layer of photoresist on the surface of the film layer, and patterning the photoresist by using a mask pattern to form a SiO film 2 Photoetching an ion injection area to-be-etched silicon dioxide in the film layer;
step 6: etching the patterned area with silicon dioxide to remove unprotected SiO 2 Forming a phosphorus ion implantation window on the film layer;
and 7: removing the residual photoresist in the step 5, and implanting phosphorus ions with the silicon dioxide mask layer in the step 6, wherein the implantation dosage is 3 multiplied by 10 15 cm -3 ～5×10 16 cm -3 The injection energy is 50 keV-200 keV;
and 8: carrying out rapid thermal annealing in an annealing furnace, wherein the annealing temperature is 850-1050 ℃, and the annealing time is 50-80 s;
and step 9: and (5) carrying out phosphorus ion implantation again by using the silicon dioxide mask layer in the step (6), wherein the implantation dosage is 1 multiplied by 10 14 cm -3 ～5×10 15 cm -3 The injection energy is 30 keV-60 keV;
step 10: annealing again, wherein the rapid thermal annealing is adopted at the time, the annealing temperature is 850-950 ℃, and the annealing time is 50-80 s;
wherein, to increase n + The surface layer of the layer 7 is doped with concentration, ohmic contact is formed between the layer and the electrode, and n is formed by three times of ion implantation + A layer 7;
step 11: spin-coating a layer of photoresist on the front surface of the silicon epitaxial wafer (the thickness of the photoresist needs to be ensured to be larger than 1 μm at this time), patterning the photoresist by using a mask pattern again, and photoetching a channel type protection groove region to be etched;
step 12: etching a protective ring channel (namely a channel type protective groove 4) at two sides by using the residual photoresist in the step 11 as a mask for improving breakdown voltage; the width of the two-sided channel-type protection groove 4 is 2-6 μm, the etching depth is 0-6 μm (from etching to etching through the avalanche region), and n + The width of the overlapping portion of the layers 7 is 2 to 4 μm.
Step 13: depositing a layer of silicon dioxide on the front surface of the silicon epitaxial wafer by adopting PECVD (plasma enhanced chemical vapor deposition), wherein the thickness is 100-500 nm, and forming a silicon dioxide insulating layer 8;
step 14: and removing all the residual photoresist in the previous step, continuously depositing a metal film layer (Ti/Au) on the front surface of the epitaxial wafer, and etching a metal electrode pattern to form an upper end electrode (namely the first electrode 9).
At this point, the processing of the front side portion of the device is completed.
Step 15: grinding and polishing a silicon epitaxial wafer substrate (namely, the substrate 1) to a thickness of 100-150 μm;
step 16: spin-coating a layer of photoresist on a silicon epitaxial wafer substrate (namely a substrate 1), patterning the photoresist by using a mask pattern, and photoetching a substrate hollowed-out region on the photoresist to be etched;
and step 17: taking the residual photoresist in the step 16 as a mask, and carrying out back silicon etching with the etching depth of 30-60 mu m to form a substrate hollowed-out area 2;
step 18: removing the photoresist generated in the front, depositing a metal film layer (Ti/Au) on the back of the silicon epitaxial wafer, etching a metal electrode pattern to form a lower end electrode (namely a second electrode 10);
step 19: spin-coating a layer of photoresist (the thickness of the photoresist is about 1 mu m) on the silicon epitaxial wafer substrate again, patterning the photoresist by using a mask pattern, and photoetching a silicon column pattern region on the photoresist to be etched;
step 20: etching the silicon at the unprotected part by taking the photoresist patterned in the step 23 as a mask, wherein the etching depth is 8-15 mu m, and forming a silicon column region 3;
step 21: and removing all the residual photoresist in the previous step to finish the preparation of the design of the back-incident near-infrared enhanced silicon avalanche photodetector.
As shown in fig. 4, as the etching depth of the channel protection groove 4 increases, the breakdown voltage of the back-incident near-infrared enhanced silicon avalanche photodetector shows an overall upward trend, and when the depth of the channel protection groove 4 is 0, the breakdown voltage of the back-incident near-infrared enhanced silicon avalanche photodetector is 72V; and when the depth of the channel protection groove 4 is 3 μm, the breakdown voltage of the back incidence near infrared enhanced silicon avalanche photodetector is 87V, and the breakdown voltage is increased by 20.8%. Therefore, the device breakdown voltage can be effectively improved and the breakdown characteristic of the device can be inhibited by etching the channel protection groove 4, so that the back-incident near-infrared enhanced silicon avalanche photodetector has the characteristic of channel regulation and control of an electric field under a low-precision process.
The novel micron-sized silicon column back-incident near-infrared enhanced silicon avalanche photodetector prepared by the embodiment improves the response of a near-infrared band, reduces the excessive noise, and can accurately regulate and control the fringe field through the precise design of a channel protection ring region, thereby achieving the effect of simultaneously improving three characteristics (inhibiting fringe breakdown, low noise and near-infrared band response) of the avalanche photodetector.
Another embodiment of the present invention provides a method for preparing a novel back-incident near-infrared enhanced silicon avalanche photodetector, which comprises the following steps:
step 1: preparing a surface-cleaned and dried p-type highly-doped silicon single-crystal-wafer substrate material (namely a substrate 1) with a crystal orientation of (111);
step 2: a layer of pi-type layer 5 is grown on a silicon single crystal wafer (i.e. substrate 1) by vapor phase epitaxy with a doping concentration of 5 x 10 14 cm -3 The thickness is 50 mu m;
and step 3: on the pi-type layer 5 obtained by the vapor phase epitaxial growth, a p-type layer 6 with a doping concentration of 3 × 10 is further vapor phase epitaxially grown 15 cm -3 The thickness is 7 mu m;
so far, the epitaxial growth of the epitaxial wafer used for the subsequent flow wafer is finished.
And 4, step 4: growing a layer of silicon dioxide on the silicon epitaxial wafer by adopting magnetron sputtering, wherein the thickness of the silicon dioxide is 0.5 mu m;
and 5: in SiO 2 Spin coating a layer of photoresist on the surface of the film layer, and patterning the photoresist by using a mask pattern to form a SiO film 2 Photoetching an ion injection area to-be-etched silicon dioxide in the film layer;
step 6: etching the patterned area with silicon dioxide to remove unprotected SiO 2 Forming a phosphorus ion implantation window on the film layer;
and 7: removing the residual photoresist in the step 5, and implanting phosphorus ions with the silicon dioxide mask layer in the step 6, wherein the implantation dosage is 3 multiplied by 10 15 cm -3 The implantation energy is 150 keV;
and 8: carrying out rapid thermal annealing in an annealing furnace, wherein the annealing temperature is 1000 ℃, and the annealing advancing time is 80 s;
and step 9: and (5) carrying out phosphorus ion implantation again by using the silicon dioxide mask layer in the step (6), wherein the implantation dosage is 3 multiplied by 10 14 cm -3 The implantation energy is 30 keV;
step 10: performing rapid thermal annealing again, wherein the annealing temperature is 850 ℃ and the annealing time is 50 s;
Step 11: a layer of photoresist is coated on the front surface of the silicon epitaxial wafer in a rotating way (the thickness of the photoresist needs to be ensured at this time)
Larger than 1 μm), patterning the photoresist by using the mask pattern again, and photoetching to form a channel type protection groove region to be etched;
step 12: etching to obtain two-side protection ring trenches (i.e. trench-type protection grooves 4) by using the remaining photoresist of step 11 as a mask, wherein the width of the two-side trench protection grooves 4 is 5 μm, the etching depth is 0-6 μm (from etching to etching of an avalanche region), and n + The width of the overlapped part of the layer 7 is 2-4 μm;
step 13: depositing a layer of silicon dioxide on the front surface of the silicon epitaxial wafer by adopting PECVD (plasma enhanced chemical vapor deposition), wherein the thickness is 100-500 nm, and forming a silicon dioxide insulating layer 8;
step 14: and removing all the residual photoresist in the previous step, continuously depositing a metal film layer (Ti/Au) on the front surface of the epitaxial wafer, and etching a metal electrode pattern to form a first electrode 9.
At this point, the processing of the front side portion of the device is completed.
Step 15: grinding and polishing a silicon epitaxial wafer substrate (namely, a substrate 1) to a thickness of 120 mu m;
step 16: spin-coating a layer of photoresist on a silicon epitaxial wafer substrate (namely a substrate 1), patterning the photoresist by using a mask pattern, and photoetching a substrate hollowed-out region on the photoresist to be etched;
and step 17: taking the residual photoresist in the step 16 as a mask, and carrying out back silicon etching with the etching depth of 40 μm to form a substrate hollowed-out region 2;
step 18: and removing the photoresist generated in the front, depositing a metal film layer (Ti/Au) on the back of the silicon epitaxial wafer, and etching a metal electrode pattern to form a second electrode 10.
Step 23: spin-coating a layer of photoresist (the thickness of the photoresist is about 1 mu m) on the silicon epitaxial wafer substrate again, patterning the photoresist by using a mask pattern, and photoetching a silicon column pattern region on the photoresist to be etched;
step 24: etching the silicon at the unprotected part by taking the photoresist patterned in the step 23 as a mask, wherein the etching depth is 10 mu m, and forming a silicon column region 3;
step 25: and removing all the photoresist remained in the previous step to finish the preparation of the design of the back incidence near infrared enhanced silicon avalanche photodetector.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A structure of a back-incident near-infrared enhanced silicon avalanche photodetector, comprising:
a substrate (1);
a pi-type layer (5) disposed on the upper surface of the substrate (1) for absorbing incident light;
a p-type layer (6) disposed on the pi-type layer (5);
n + a layer (7) arranged on the p-type layer (6), wherein the p-type layer (6) and the n-type layer + The layers (7) together form an avalanche region;
a channel-type protective groove (4) penetrating the p-type layer (6) for increasing the breakdown voltage;
the upper surface of the p-type layer (6) is divided into a middle circular part and a peripheral circular part by the channel-type protective groove (4); wherein n is + The layer (7) is located on the central circular portion of the p-type layer (6);
a silicon dioxide insulating layer (8) covering n + The layer (7), the channel type protective groove (4) and the peripheral circular part of the p-type layer (6) are used as surface passivation layers;
a first electrode (9) covering n + On the insulating layer (8) of silicon dioxide above the layer (7) for forming an ohmic contact anode;
the substrate hollowed-out region (2) is arranged on the lower surface of the substrate (1) and is used for reducing the optical loss of incident light outside the absorption region and reducing the transit time of carriers;
the silicon column region (3) is arranged at the bottom of the groove of the substrate hollowed-out region (2) and used for enhancing the absorption of near-infrared band light;
and the second electrode (10) covers the bottom of the substrate (1), is positioned at the periphery of the substrate hollow area (2) and is used for forming an ohmic contact cathode.
2. The structure of claim 1,
the thickness of the substrate (1) is 70 to 150 [ mu ] m.
3. The structure of claim 1,
the depth of the substrate hollowed-out region (2) is 30-60 mu m;
the substrate hollowed-out area (2) is in the shape of a cylindrical groove.
4. The structure of claim 1,
the silicon pillar region (3) comprises at least 2 silicon pillars;
the shape of the silicon pillar comprises a cylinder;
the height of the silicon column is 8-15 μm;
the interval period of the silicon columns is 5-10 mu m;
when the silicon pillar is in the shape of a cylinder, the diameter of the bottom of the silicon pillar is 3 to 8 μm.
5. The structure of claim 1,
the thickness of the pi-type layer (5) is 30-70 mu m;
the doping concentration of the pi-type layer (5) is 1 x 10 14 To 5X 10 14 cm -3 ；
The thickness of the p-type layer (6) is 4 to 10 μm;
the doping concentration of the p-type layer (6) is 1 x 10 15 cm -3 To 3X 10 15 cm -3 ；
N is + The thickness of the layer (7) is 0.1 to 0.5. mu.m.
6. The structure of claim 1,
the shape of the channel-type protective groove (4) comprises an annular groove;
the width of the channel-type protective groove (4) is 1 to 6 μm;
the depth of the channel type protective groove (4) is larger than the thickness of the p-type layer (6) and smaller than the sum of the thickness of the p-type layer (6) and the thickness of the pi-type layer (5).
7. The structure of claim 1,
the first electrode (9) is made of aluminum, gold, titanium gold or titanium-platinum-gold alloy;
the thickness of the first electrode (9) is 300 to 600 nm.
8. The structure of claim 1,
the second electrode (10) is made of aluminum, gold, titanium gold or titanium-platinum-gold alloy;
the thickness of the second electrode (10) is 300 to 600 nm.
9. A preparation method of a back incidence near-infrared enhanced silicon avalanche photodetector is characterized by comprising the following steps:
preparing a pi-type layer (5) on the upper surface of the substrate (1);
preparing a p-type layer (6) on the pi-type layer (5);
preparing a silicon dioxide layer on the p-type layer (6);
etching the silicon dioxide layer to form an ion implantation window;
preparation of n at ion implantation window + A layer (7);
etching the p-type layer (6) and part of the n + A layer (7) forming a channel-type protective groove (4); the p-type layer (6) is divided into a middle circular part and a peripheral circular part by a channel-type protective groove (4);
in the p-type layer (6), the channel-type protection groove (4) and n + Preparing a silicon dioxide insulating layer (8) on the layer (7);
at n + Preparing a first electrode (9) on the silicon dioxide insulating layer (8) above the layer (7);
etching a groove on the lower surface of the substrate (1) to prepare a substrate hollowed-out area (2);
preparing a second electrode (10) on the lower surface of the substrate (1) and at the periphery of the substrate hollowed-out region (2);
and preparing a silicon column region (3) at the bottom of the groove of the substrate hollowed-out region (2) to finish the preparation of the novel back-incident near-infrared enhanced silicon avalanche photodetector.
10. The production method according to claim 9,
etching the n-type protective groove (4) during the preparation thereof + The width of the layer (7) is 2 to 4 mum。
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