JPH02253666A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPH02253666A
JPH02253666A JP1073913A JP7391389A JPH02253666A JP H02253666 A JPH02253666 A JP H02253666A JP 1073913 A JP1073913 A JP 1073913A JP 7391389 A JP7391389 A JP 7391389A JP H02253666 A JPH02253666 A JP H02253666A
Authority
JP
Japan
Prior art keywords
junction
layer
semiconductor
carrier concentration
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1073913A
Other languages
Japanese (ja)
Inventor
Haruhiko Okazaki
治彦 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1073913A priority Critical patent/JPH02253666A/en
Publication of JPH02253666A publication Critical patent/JPH02253666A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent edge breakdown and assure high speed response by providing a second semiconductor region in a first semiconductor layer, said second semiconductor region having carrier concentration decreasing from a substrate side to a surface, and providing a large curvature portion of a first PN junction as an optical detection region in said second semiconductor layer. CONSTITUTION:A portion of a PN junction 12 without any curved portion which forms an optical detection region and a multiplication layer 5 having higher carrier concentration are contiguous with each other. Accordingly, avalanche building-up time can be reduced. Further, a large curvature portion of the PN junction 12 is formed in a region 6 where carrier concentration decreases from a semiconductor substrate 1 side to a surface. Accordingly, the curvature of the PN junction 12 can be reduced and a graded junction can be realized. Hereby, edge breakdown can be prevented at the large curvature PN junction 12 portion around the optical detection section, so that an effective guard ring can be formed together with a high speed response.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、ガードリングを備えた、アバランシェ増倍現
象を利用したブレーナ型半導体受光素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a Brehner-type semiconductor light-receiving element that is equipped with a guard ring and utilizes an avalanche multiplication phenomenon.

(従来の技術) 現在、遠距離・高速光通信用受光素子として、光ファイ
バの伝送損失の低い1〜1.6μm帯の波長帯で感度を
有するI n G a A s / I n P系のア
バランシェフォトダイオード(A P D)の開発が進
められている。
(Prior art) At present, InGaAs/InP-based light receiving elements for long-distance and high-speed optical communications are used, which have sensitivity in the wavelength band of 1 to 1.6 μm, where the transmission loss of optical fibers is low. The development of avalanche photodiodes (APDs) is progressing.

この様なAPDとして、例えば第5図に示す構造が知ら
れている。即ち、n  −1nP基板1上に、n−1n
Pバッファ層2、n  −1nGaAS光吸収層3、n
  −1nGaAsP中間層4、n”−1nP増倍層5
、n−−1nPウィンドウ層6を順次エピタキシャル成
長し、Cd等を選択拡散法によりP −受光部7を、ま
たBe等のイオン注入の後高温アニールを行なってP−
ガードリング部8をそれぞれ設け、更にP側電極10、
N側電極11を設けたものである。なお、図中9は反射
防止膜、12および13はそれぞれPN接合である。
As such an APD, for example, the structure shown in FIG. 5 is known. That is, n-1n on the n-1nP substrate 1
P buffer layer 2, n −1nGaAS light absorption layer 3, n
-1nGaAsP intermediate layer 4, n''-1nP multiplication layer 5
, n--1nP window layer 6 are sequentially grown epitaxially, Cd or the like is selectively diffused to form the P- light receiving part 7, and Be or the like is implanted and then high-temperature annealing is performed to form the P-
A guard ring portion 8 is provided, and a P side electrode 10,
An N-side electrode 11 is provided. In the figure, 9 is an antireflection film, and 12 and 13 are PN junctions, respectively.

光の吸収・増倍をl nGaAsW内で行なうln G
 a A s −A P Dの場合、高電界をかけると
、トンネル電流により暗電流が急激に増加する。このた
め、通常InGaAs光吸収層3を低キャリア濃度とし
て高電界がかからないようにし、さらにバンドギャップ
が広くトンネル電流の生じにくいInP層5をアバラン
シェ領域とする、光の吸収を行なう領域と増倍を行なう
領域とを分離させた上述の構造がとられる。
lnG absorbs and multiplies light in lnGaAsW
In the case of a As - A P D, when a high electric field is applied, the dark current rapidly increases due to tunnel current. For this reason, the InGaAs light absorption layer 3 is usually made with a low carrier concentration to prevent high electric fields from being applied, and the InP layer 5, which has a wide band gap and is difficult to generate a tunnel current, is used as an avalanche region, which is a region for light absorption and multiplication. The above-mentioned structure is adopted in which the area where the image processing is performed is separated.

しかし、InGaAs層3とInP層5はへテロ構造と
なり、光吸収により発生した正孔がへテロ界面に存在す
る価電子帯の障壁に蓄積され、高速応答特性が得られな
い。このため、I nGaAS層3とInP層5の間に
エネルギーギャップが両者の中間となる組成のInGa
AsP中間層4を挿入している。
However, the InGaAs layer 3 and the InP layer 5 have a heterostructure, and holes generated by light absorption are accumulated in the barrier of the valence band existing at the hetero interface, making it impossible to obtain high-speed response characteristics. For this reason, an InGaAs layer 3 and an InP layer 5 having a composition with an energy gap between the two are formed.
An AsP intermediate layer 4 is inserted.

また、低電流、高増倍率の、特性の良いAPDを実現す
るためには、受光面全体に渡り均一なアバランシェ増倍
が行われ、受光部以外の領域では、電圧降伏の発生しな
いことが必要である。特に、PN接合が選択的に形成さ
れた受光部周辺の曲率を有する部分(第5図中の14)
は、電界が集中し、局部的な電圧降伏(エッヂブレーク
ダウン)が生じ易い。局所的電圧降伏が発生した場合、
受光部のPN接合12にかかる逆方向電圧が増加しない
ため、アバランシェ増倍が発生しない。この様な、局所
的な電圧降伏を防止するため、受光部周辺にガードリン
グを設けている。
In addition, in order to realize an APD with low current, high multiplication factor, and good characteristics, it is necessary that uniform avalanche multiplication be performed over the entire light-receiving area, and that voltage breakdown should not occur in areas other than the light-receiving area. It is. Particularly, the part with curvature around the light receiving part where the PN junction is selectively formed (14 in Fig. 5)
, the electric field concentrates and local voltage breakdown (edge breakdown) tends to occur. If a local voltage breakdown occurs,
Since the reverse voltage applied to the PN junction 12 of the light receiving section does not increase, avalanche multiplication does not occur. In order to prevent such local voltage breakdown, a guard ring is provided around the light receiving section.

一般に、半導体受光素子の降伏電圧は、半導体層のキャ
リア濃度が低く、またバンドギャップが広い程、高いこ
とが知られている。またPN接合面の曲率の大なる部分
における降伏電圧については、曲率が小さい程、またP
N接合近傍における不純物濃度が階段的に変化している
階段型接合より、線形に変化している傾斜接合の方が高
い。
Generally, it is known that the breakdown voltage of a semiconductor light-receiving element increases as the carrier concentration of the semiconductor layer decreases and the band gap widens. Also, regarding the breakdown voltage at a portion with a large curvature of the PN junction surface, the smaller the curvature, the more
The impurity concentration near the N junction is higher in a graded junction where it changes linearly than in a stepped junction where it changes stepwise.

このため、ガードリングを設けたAPDでは、受光部の
PN接合12を階段型接合とし、PN接合の曲率の大な
る部分における曲率を小さくし、またガードリング部の
PN接合13を傾斜接合とし、受光部よりガードリング
部での降伏電圧を高くしている。
For this reason, in an APD provided with a guard ring, the PN junction 12 in the light receiving part is a stepped junction, the curvature of the PN junction where the curvature is large is made small, and the PN junction 13 in the guard ring part is a sloped junction. The breakdown voltage at the guard ring part is higher than that at the light receiving part.

(発明が解決しようとする課題) 一般に、階段型接合を形成するためには高キャリア濃度
のInF’層内にPN接合を形成し、また傾斜型接合を
形成するためには低キヤリア濃度のInP層内にPN接
合を形成することが望ましい。
(Problems to be Solved by the Invention) Generally, to form a stepped junction, a PN junction is formed in an InF' layer with a high carrier concentration, and to form a graded junction, a PN junction is formed in an InF' layer with a low carrier concentration. It is desirable to form a PN junction within the layer.

しかし、上述のAPDでは、ガードリング効果を得るた
めには、受光部のPN接合12の曲率の大なる部分より
深い位置まで、ガードリング部のPN接合13を形成す
る必要がある。即ち、十分なガードリング効果を得るた
めには、受光部となるPN接合12面は、ガードリング
部のPN接合13面より浅くなるように、且つn  −
1nPウィンドウ層6内のn  −1nP層倍層5にで
きるだけ近い部分に形成せざるを得えない。従って、低
キヤリア濃度のn  −1nPウィンドウ層6内に受光
部のPN接合12を形成するため、アバランシェビルト
アップタイムが太き(なり、高速応答特性を得ることは
難しい。
However, in the above-mentioned APD, in order to obtain the guard ring effect, it is necessary to form the PN junction 13 of the guard ring part to a position deeper than the portion where the curvature of the PN junction 12 of the light receiving part is large. That is, in order to obtain a sufficient guard ring effect, the 12th surface of the PN junction, which becomes the light receiving section, should be shallower than the 13th surface of the PN junction, which is the guard ring section, and should be n -
The n-1nP layer in the 1nP window layer 6 must be formed as close as possible to the double layer 5. Therefore, since the PN junction 12 of the light receiving section is formed in the n -1nP window layer 6 with a low carrier concentration, the avalanche built up time is long (and it is difficult to obtain high-speed response characteristics).

また、n  −1nP増倍層5の層厚は結晶成長の制御
性および均一性で決まり、n−−1nPウィンドウ層6
内に形成するPN接合12の深さは拡散の制御性で決ま
るため、ガードリング効果が十分有り、しかも高速応答
特性が得られるAPDを実現するためには、両方の制御
性が重要となり、製作が容易ではなく歩留まりが低くな
るという製作上の問題があった。
The layer thickness of the n-1nP multiplication layer 5 is determined by the controllability and uniformity of crystal growth, and the thickness of the n-1nP multiplication layer 5 is determined by the controllability and uniformity of crystal growth.
The depth of the PN junction 12 formed within the PN junction 12 is determined by the controllability of diffusion, so in order to realize an APD that has a sufficient guard ring effect and high-speed response characteristics, controllability of both is important. There was a manufacturing problem in that it was not easy and the yield was low.

本発明は、上記の欠点を解決するもので、エッヂブレー
クダウンを防止し、且つ高速応答特性が得られ、製作が
容易で歩留まりの良い半導体受光素子を提供することを
目的とする。
The present invention solves the above-mentioned drawbacks, and aims to provide a semiconductor light-receiving element that prevents edge breakdown, provides high-speed response characteristics, is easy to manufacture, and has a high yield.

[発明の構成] (課題を解決するための手段) 本発明の半導体受光素子は、半導体内にPN接合を有す
る受光領域が選択的に形成され、この受光領域の周辺に
ガードリングを備えた半導体受光素子において、第1の
半導体層内にキャリア濃度が基板側から表面にかけて減
少している第2の半導体領域を有し、受光領域である第
1のPN接合の曲率の大なる部分が第2の牛導体層内に
設けられていることを特徴とする半導体受光素子である
[Structure of the Invention] (Means for Solving the Problems) The semiconductor light receiving element of the present invention is a semiconductor in which a light receiving region having a PN junction is selectively formed in a semiconductor, and a guard ring is provided around the light receiving region. The light-receiving element has a second semiconductor region in which the carrier concentration decreases from the substrate side to the surface in the first semiconductor layer, and the portion of the first PN junction that is the light-receiving region has a large curvature. A semiconductor light-receiving element characterized in that it is provided within a conductor layer of the semiconductor light-receiving element.

(作 用) 本発明によれば、受光領域を形成するPN接合の曲がり
のない部分とキャリア濃度の高い増倍層が接しているた
め、アバランシェビルドアップタイムを小さくでき、高
速応答特性に優れる。
(Function) According to the present invention, since the uncurved portion of the PN junction forming the light receiving region is in contact with the multiplication layer with high carrier concentration, avalanche build-up time can be reduced and excellent high-speed response characteristics can be achieved.

また本発明によれば、PN接合の曲率の大なる部分は、
半導体基板側から表面にかけてキャリア濃度が減少して
いる領域に形成されるため、PN接合の曲率を小さくで
き、且つ傾斜型接合が実現できる。このため、受光部周
辺のPN接合の曲率の大なる部分では、エッヂブレーク
ダウンを防止することが可能で、効果的なガードリング
を形成できる。
Further, according to the present invention, a large portion of the curvature of the PN junction is
Since it is formed in a region where the carrier concentration decreases from the semiconductor substrate side to the surface, the curvature of the PN junction can be reduced and a sloped junction can be realized. Therefore, edge breakdown can be prevented in a portion of the PN junction with a large curvature around the light receiving portion, and an effective guard ring can be formed.

更に、増倍層の膜厚制御は拡散プロセス時に行なわれ、
エピタキシャル成長時に行なうものに比べ膜厚制御に自
由度が大きく、制御が容易で、製作の歩留まりの高い半
導体受光素子を実現できる。
Furthermore, the thickness of the multiplication layer is controlled during the diffusion process.
Compared to epitaxial growth, there is a greater degree of freedom in film thickness control, and it is possible to realize a semiconductor light-receiving element that is easy to control and has a high production yield.

(実施例) 第1図は本発明の半導体受光素子の一実施例の構成を示
す。
(Embodiment) FIG. 1 shows the structure of an embodiment of the semiconductor light receiving element of the present invention.

n”−1nP基板1上に、n−1nPバッファ層2、n
  −1nGaAs光吸収層3、n  −InGaAs
P中間層4、n”−1nP増倍層5ζ順次エピタキシャ
ル成長し、n  −1nP増倍層5の一部をドーナツ状
に除去し、更にS 102等をマスクとして、基板から
表面方向にキャリア濃度が減少するようにn−1nP層
6を選択成長する。受光部7となるp中層を増倍層5か
らn−1nP層6にかけて選択拡散法で形成し、曲率の
大なる部分はn−1nP層6内に形成し、更に反射防止
膜9、n側電極10、N側電極11を設けたものである
。図中12はPN接合を示す。
On the n''-1nP substrate 1, an n-1nP buffer layer 2, n
-1nGaAs light absorption layer 3, n-InGaAs
The P intermediate layer 4 and the n''-1nP multiplication layer 5ζ are sequentially epitaxially grown, a part of the n-1nP multiplication layer 5 is removed in a donut shape, and the carrier concentration is increased from the substrate to the surface using S102 etc. as a mask. The n-1nP layer 6 is selectively grown so that the light-receiving portion 7 is formed by the selective diffusion method from the multiplication layer 5 to the n-1nP layer 6. 6, and further provided with an antireflection film 9, an n-side electrode 10, and an n-side electrode 11. In the figure, 12 indicates a PN junction.

次に、上記の半導体受光素子の製造方法について説明す
る。
Next, a method for manufacturing the above semiconductor light receiving element will be explained.

まず、n”−1nP基板1上に、n−1nPバッファ層
2、n  −InGaAs光吸収層3、n  −InG
aAsP中間層4、n”−1nP増倍層5を、順次気相
成長法(VPE等)によりエピタキシャル成長を行なう
。次に、S iO2等を堆積し、フォトエツチング技術
によりドーナツ状にエツチング除去する。次にn”−1
nP増倍層5の一部をB r  CH30H等によりエ
ツチング除去する。n  −1nP増倍層5のサイドエ
ツチングにより生じるS iO2の庇は、さらに5i0
2をオーバエツチングし除去する。続いて、VPE法に
より、エツチング除去したn”−InP増倍層5の部分
に基板表面からウェハ表面方向に対してキャリア濃度が
連続的、或いは階段的に減少するように、n−−1nP
層6を選択成長する。この後、S i O2マスクを除
去する。
First, on an n''-1nP substrate 1, an n-1nP buffer layer 2, an n-InGaAs light absorption layer 3, an n-InG
The aAsP intermediate layer 4 and the n''-1nP multiplication layer 5 are sequentially epitaxially grown by vapor phase epitaxy (VPE, etc.).Next, SiO2, etc. are deposited and removed by photoetching in a donut shape. Then n”-1
A part of the nP multiplication layer 5 is removed by etching with B r CH30H or the like. The SiO2 eaves created by side etching of the n-1nP multiplication layer 5 are further 5i0
2 is overetched and removed. Next, by the VPE method, n-1nP is applied to the etched portion of the n''-InP multiplication layer 5 so that the carrier concentration decreases continuously or stepwise from the substrate surface to the wafer surface.
Layer 6 is selectively grown. After this, the S i O2 mask is removed.

次に、P−CVD法等によりSiN  選択拡散マスク
を堆積し、n  −1nP層6を含むようにフォトエツ
チング技術により、円形にパターニングする。そしてケ
ミカルドライエツチング法(CDE法)等によりSiN
  膜を円形にエツチングする。このSiN  膜等を
マスクとして、封管法等によりカドミウム(Cd)等の
p型不純物を選択拡散し、PN接合12を形成する。
Next, a SiN selective diffusion mask is deposited by P-CVD or the like, and patterned into a circular shape by photoetching so as to include the n-1nP layer 6. Then, by chemical dry etching method (CDE method) etc., SiN is
Etch the membrane in a circular shape. Using this SiN film or the like as a mask, a p-type impurity such as cadmium (Cd) is selectively diffused by a sealed tube method or the like to form a PN junction 12.

受光部のPN接合12の曲率の大なる部分にガードリン
グ効果を持たせるため、SiN  膜を除去後、フォス
フイン雰囲気中(1010000pp、7500Cで、
60分間のアニールを行ない、n  −In2層6に押
し込み拡散を行なう。
In order to create a guard ring effect in a large part of the curvature of the PN junction 12 in the light receiving part, after removing the SiN film, it was heated in a phosphine atmosphere (1010000pp, 7500C,
Annealing is performed for 60 minutes, and the n-In2 layer 6 is injected and diffused.

その後、反射防止膜形成のためSiN  膜9を堆積し
た後、p側電極取出し部分のSiN  膜9を除去する
。真空蒸着技術により電極金属を蒸着し、フォトエツチ
ング技術によりパターニング、不要な電極金属を除去し
、p側電極を形成する。
After that, a SiN 2 film 9 is deposited to form an antireflection film, and then the SiN 2 film 9 at the p-side electrode extraction portion is removed. Electrode metal is deposited using vacuum evaporation technology, patterned using photoetching technology, and unnecessary electrode metal is removed to form a p-side electrode.

次に、InP基板1の裏面を研磨後、真空蒸着により、
n側電極11を形成する。最後に、オーミック電極とす
るため、熱処理をおこなって半導体受光素子が完成する
Next, after polishing the back surface of the InP substrate 1, by vacuum evaporation,
An n-side electrode 11 is formed. Finally, heat treatment is performed to form an ohmic electrode, and the semiconductor light-receiving element is completed.

本実施例におけるキャリア濃度と層厚および拡散プロフ
ァイルの関係を第2図および第3図に示す。受光部(第
1図A)のPN接合は、第2図に示すように、階段型接
合である。またガードリング部(第1図B)のPN接合
は、第3図に示すように、傾斜型接合である。
The relationship between carrier concentration, layer thickness, and diffusion profile in this example is shown in FIGS. 2 and 3. The PN junction of the light receiving section (FIG. 1A) is a stepped junction, as shown in FIG. 2. Further, the PN junction of the guard ring portion (FIG. 1B) is an inclined type junction, as shown in FIG. 3.

上記実施例では、InGaAsP、InP系の化合物半
導体について説明したが、AIGaAsSb、GaAs
等においても実現可能である。また導電型については、
実施例とは逆の構造のものも可能である。
In the above embodiment, InGaAsP and InP-based compound semiconductors were explained, but AIGaAsSb, GaAs
It is also possible to realize this in Regarding conductivity type,
A structure opposite to that of the embodiment is also possible.

第4図に本発明の他の実施例を示す。第1図の例では、
受光部を形成するPN接合12を選択拡散法で形成後、
熱処理を加え、押し込み拡散を行なうことによりガード
リングを形成したが、この実施例は、特に更にガードリ
ングをイオン注入法で形成し、ガードリングをより効果
的したものである。
FIG. 4 shows another embodiment of the invention. In the example in Figure 1,
After forming the PN junction 12 that forms the light receiving part by selective diffusion method,
Although the guard ring was formed by applying heat treatment and performing intrusion diffusion, in this example, the guard ring was further formed by an ion implantation method to make the guard ring more effective.

[発明の効果] 本発明によれば、高速応答特性を有し、またエッヂブレ
ークダンが生じ難く、且つ製作が容易で歩留まりの半導
体受光素子が得られる。
[Effects of the Invention] According to the present invention, it is possible to obtain a semiconductor light-receiving element that has high-speed response characteristics, is hard to cause edge break-down, is easy to manufacture, and has a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の半導体受光素子の断面図、
第2図は本発明の受光部のキャリア濃度のプロファイル
、第3図は本発明のガードリング部のキャリア濃度のプ
ロファイル、第4図は本発明の他の実施例の断面図、第
5図は従来の半導体受光素子の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor photodetector according to an embodiment of the present invention;
FIG. 2 is a carrier concentration profile of the light receiving part of the present invention, FIG. 3 is a carrier concentration profile of the guard ring part of the present invention, FIG. 4 is a cross-sectional view of another embodiment of the present invention, and FIG. FIG. 2 is a cross-sectional view of a conventional semiconductor light receiving element.

Claims (1)

【特許請求の範囲】[Claims] 半導体内にPN接合を有する受光領域が選択的に形成さ
れ、この受光領域の周辺にガードリングを備えた半導体
受光素子において、第1の半導体層内にキャリア濃度が
基板側から表面にかけて減少している第2の半導体領域
を有し、受光領域である第1のPN接合の曲率の大なる
部分が前記第2の半導体層内に設けられていることを特
徴とする半導体受光素子。
In a semiconductor light-receiving element in which a light-receiving region having a PN junction is selectively formed in a semiconductor and a guard ring is provided around the light-receiving region, the carrier concentration in the first semiconductor layer decreases from the substrate side to the surface. 1. A semiconductor light-receiving element having a second semiconductor region having a second semiconductor layer, wherein a portion of a first PN junction which is a light-receiving region has a large curvature is provided in the second semiconductor layer.
JP1073913A 1989-03-28 1989-03-28 Semiconductor photodetector Pending JPH02253666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1073913A JPH02253666A (en) 1989-03-28 1989-03-28 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1073913A JPH02253666A (en) 1989-03-28 1989-03-28 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPH02253666A true JPH02253666A (en) 1990-10-12

Family

ID=13531887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1073913A Pending JPH02253666A (en) 1989-03-28 1989-03-28 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH02253666A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438217A (en) * 1994-04-29 1995-08-01 General Electric Company Planar avalanche photodiode array with sidewall segment
US5670383A (en) * 1994-04-04 1997-09-23 General Electric Company Method for fabrication of deep-diffused avalanche photodiode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670383A (en) * 1994-04-04 1997-09-23 General Electric Company Method for fabrication of deep-diffused avalanche photodiode
US5438217A (en) * 1994-04-29 1995-08-01 General Electric Company Planar avalanche photodiode array with sidewall segment
US5500376A (en) * 1994-04-29 1996-03-19 General Electric Company Method for fabricating planar avalanche photodiode array

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