WO2022175713A1

WO2022175713A1 - Back illuminated image sensor with implanted boron for ultraviolet response

Info

Publication number: WO2022175713A1
Application number: PCT/IB2021/051348
Authority: WO
Inventors: Gary ALLAN
Original assignee: Teledyne Digital Imaging, Inc.
Priority date: 2021-02-17
Filing date: 2021-02-17
Publication date: 2022-08-25

Abstract

A method of fabricating a back-side illuminated (BSI) silicon image sensor is disclosed. An image sensor is provided in silicon wafer form having a silicon substrate, an epitaxial silicon device layer formed over the substrate, and circuitry layers formed over the silicon device layer bonded to a supporting handle wafer. The substrate is removed by polishing to expose the epitaxial silicon device layer, defining an illumination detection surface, doping the epitaxial silicon layer surface with a boron implant creating a dopant implanted region, annealing and activating the dopant implanted region with laser energy, removing a native oxide layer formed after exposing the surface of the epitaxial silicon layer, growing a new oxide layer over the annealed dopant implanted region, and depositing a surface protection layer over the new oxide layer. Disclosed is a BSI silicon image sensor fabricated according to this method.

Description

TITLE BACK ILLUMINATED IMAGE SENSOR WITH IMPLANTED BORON FOR ULTRAVIOLET RESPONSE TECHNICAL FIELD [0001] The present disclosure is directed to an image sensor. More particularly, the present disclosure is directed to a back-side illuminated (BSI) silicon image sensor for detection of high intensity ultraviolet (UV) illumination, in the spectral range 190nm to 370nm. BACKGROUND [0002] The present disclosure is directed to UV detectors for imaging technology. Detection of UV light with silicon detectors, specifically charge coupled devices (CCD) or complementary metal oxide semiconductor (CMOS) image sensors, entails significant technical challenges that result from excitation of electrons into and out of the dielectric over- layers that form the Si/SiO2 interface and other layers/interfaces at the optical detection surface. [0003] It is well known and established that back-side illuminated (BSI) silicon detectors require some form of surface treatment at the optical entrance surface, even for visible or near infra-red detection, to counteract the low energy electron states at the interface of silicon to SiO2, which serve to form a potential well at the back surface and reduce detection efficiency. Several methods to achieve back surface passivation, such as implantation of Boron or negative charging of a deposited dielectric layer, are effective and have proven technological success for many imaging applications. However, the high photon energy of UV illumination presents difficulties for these methods, in particular for wavelengths shorter than 220nm, because electrons can be excited through virtual band-to-band transitions to energy levels that allow positive charging of the SiO2 layer. Even at longer UV wavelengths oxide charging can occur through excitation mechanisms involving impurity, interface, and defect states. [0004] Electrons excited into or out of the oxide layer generate an electro-static field that will affect the charge distribution of mobile carriers (majority carriers typically) in the detection volume of silicon. The case that leads to the most difficult problem for conventional p-type silicon substrate imaging devices, is trapping of hole charges in the oxide layer adjacent to the Si/SiO2 interface , and it is well known this can occur under UV illumination. The effect of trapped holes in the SiO2 layer is to lower the free energy of electrons at and near the silicon surface, with the result that a potential well is formed at the optical detection surface (back surface). Photo-excited electrons generated near the surface in silicon may not escape the potential well at the surface and therefore not contribute to detected signal. Hole trapping sites with very deep energies (i.e. at a large energy above the valence band of SiO2) present the most difficult condition because these sites are typically very long lived and therefore can accumulate to a significant charge density. Technological approaches to reduce the density of trapping sites in oxide or at interface have made excellent progress. The nature and physical attributes of these trapping sites is not the focus of this disclosure. However, UV illumination can generate trapping sites in oxide and therefore the inspection conditions themselves at wavelengths of 190nm to 370nm can present inherent instabilities. Design approaches to limit the impact of oxide charge on the detection volume of silicon, such as providing a high density of mobile carriers to screen the field of trapped charge, have shown the most promise. [0005] Charging of oxide is a very low probability event, and so requires extended periods of near continuous illumination to accumulate sufficient oxide charge to cause measureable effects. Many high-speed UV inspection applications, particularly those of the semiconductor fabrication industry for wafer, mask, or reticle inspection, use high intensity UV illumination and operate in nearly continuous use. Therefore, these applications suffer from response degradation as usage time accumulates. Many silicon imaging detectors essentially have a memory effect of total accumulated exposure, which is undesired. [0006] Surface passivation of image sensors for UV detection requires a very shallow depth and a very high concentration of the implanted dopant because of the very short absorption depth of silicon at UV wavelengths. Though shallow Boron implants and annealing methods have been developed for small length scales in BSI detectors, electro- static effects within a few nanometers of the detection surface can cause measureable response degradation. [0007] Known UV image sensors have eliminated or reduced the memory effect by means of very strong back side passivation conditions. Known is a device that employed growth of a SiO2 layer at sufficiently high temperature to achieve very high quality (i.e., low trap density) oxide. Also known is a method involving growth of a boron doped silicon layer by molecular- beam epitaxy (MBE) to achieve sufficiently high boron density to form a thin screening layer of mobile holes at the silicon surface. Also known is a method involving deposition of a pure boron layer onto silicon surface. Also known is the deposition and annealing of pure boron onto silicon. MBE capability is not common in typical silicon wafer fabrication foundries due to equipment complexity. Conditions required for pure boron deposition and anneal may not be compatible with image sensor wafers that have completed full device processing, including metal layers which have strict temperature limitations, necessitating a complicated partial backside fabrication process prior to completion of full device circuitry layers. [0008] Accordingly, there exists an opportunity for an image sensor device that has improved or eliminated response degradation as usage time under UV illumination accumulates, and is fabricated through conventional BSI silicon image sensor fabrication methods. SUMMARY [0009] In one aspect, the present disclosure provides a method of fabricating a back-side illuminated (BSI) silicon image sensor. The method comprises providing an image sensor in the form of a silicon wafer bonded face-to-face to a handle wafer. The silicon substrate of the image sensor silicon wafer is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface. The method further comprises doping a portion of the image sensor silicon layer with a boron implant to the optical entrance surface to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the image sensor wafer and exposing the silicon surface; growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region; and depositing a dielectric layer over the new oxide layer. [0010] In another aspect, the boron implant is a shallow high dose boron implant. [0011] In another aspect, the boron implant is a boron-11 implant. In yet another aspect, the method comprises doping the near surface region of the silicon layer with a boron-11 isotope at a concentration in the range 1E20cm^-3 - 5E21cm^-3, having a nominal thickness of approximately 5nm to 30 nm. [0012] In another aspect, the method comprises doping the surface of the silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, to obtain the dopant concentration profile in the range 1E20cm^-3 - 5E21cm^-3 extending over a depth in the range 5nm to 30nm. [0013] In another aspect, the method comprises annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern. In yet another aspect, the method comprises applying the laser energy at an energy density per pulse sufficient to produce activation for a limited portion of the dopant and to produce a minimum profile change of the dopant concentration, as compared to pre-annealed profile. In yet another aspect, the method comprises applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region. In yet another aspect, the laser has a wavelength of operation in the range 190nm to 370nm. [0014] In another aspect, the method comprises removing the native oxide layer by chemical etching. [0015] In another aspect, the method comprises growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture. [0016] In another aspect, the method comprises growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours. [0017] In another aspect, the method comprises depositing a surface protection layer over the new oxide layer. In yet another aspect, the surface protection layer comprises one or more layers of any combination of Al2O3, SiO2, or HfO2 deposited by atomic layer deposition (ALD). In yet another aspect, the surface protection layer is deposited by ALD to a thickness in a range of approximately 10nm to 40nm. In yet another aspect, the method comprises heating the BSI silicon image sensor to a temperature in the range 300°C to 400°C. [0018] In another aspect, the method comprises removing the silicon and the portion of dielectric material of the image sensor silicon wafer in predefined regions by a photolithography process. [0019] In another aspect, the method comprises removing silicon and a portion of dielectric materials of the image sensor silicon wafer in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds [0020] In another aspect, the present disclosure provides a back-side illuminated (BSI) silicon image sensor fabricated according to the above method. BRIEF DESCRIPTION OF THE DRAWINGS [0021] Various features of the embodiments described herein, together with advantages thereof, may be understood in accordance with the following description taken in conjunction with the accompanying drawings as follows. [0022] FIGS.1A-1F illustrate a series of cross sectional views of a process of fabricating a BSI silicon image sensor according to at least one aspect of the present disclosure, where: [0023] FIG.1A is a cross sectional view of a BSI silicon image sensor after wafer bonding and thinning of the device wafer, with an oxide layer formed natively after thinning the silicon layer, and prior to implanting a boron dopant in the silicon layer; [0024] FIG.1B is a cross sectional view of a BSI silicon image sensor shown in FIG.1A comprising a dopant implanted region formed in the device silicon layer of the BSI silicon image sensor; [0025] FIG.1C is a cross sectional view of a BSI silicon image sensor shown in FIG.1B after annealing and activating the dopant implanted region with laser energy applied in a predetermined pattern; [0026] FIG.1D is a cross sectional view of a BSI silicon image sensor shown in FIG.1C after removing the native oxide layer and exposing the surface of the annealed dopant implanted region; [0027] FIG.1E is a cross sectional view of a BSI silicon image sensor shown in FIG.1D with a new oxide layer grown on the surface of the annealed dopant implanted region; and [0028] FIG.1F is a cross sectional view of a BSI silicon image sensor shown in FIG.1E with a surface protection layer formed over the new oxide layer. [0029] FIG.2 is a cross sectional view of specific layers of the silicon device layer of the BSI silicon image sensor shown in FIGS.1A-1F according to at least one aspect of the present disclosure. [0030] FIG.3 is a method of fabricating a BSI silicon image sensor shown in FIGS.1A-1F according to at least one aspect of the present disclosure. [0031] Corresponding reference characters indicate corresponding parts throughout the several views. The exemplifications set out herein illustrate various embodiments of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner. DESCRIPTION [0032] Applicant of the present application owns U.S. Patent Application Docket No.410P- 2020-003PCT / 200914PCT, titled BACK ILLUMINATED IMAGE SENSOR WITH A DIELECTRIC LAYER THAT NEUTRALIZES EFFECTS OF ILLUMINATION INDUCED OXIDE CHARGE IN ULTRAVIOLET IMAGING CONDITIONS, filed on even date, the disclosure of which is herein incorporated by reference in its respective entirety. [0033] In one general aspect, the present disclosure provides a method of fabricating a boron-implanted BSI silicon image sensor (CCD or CMOS), in silicon wafer form, with dopant activation and crystal annealing achieved by UV laser exposure such that strong surface accumulation is achieved while also maintaining both dopant activation and crystal annealing at a low enough magnitude that carrier lifetime is limited in the near surface region. Silicon oxide removal and regrowth processes are executed after dopant annealing and are a critical aspect of the general method to achieve the desired functionality of stable response under UV illumination. Subsequent deposition of one or more layers of Al2O3, SiO2, or HfO2 by atomic layer deposition (ALD) forms a surface protection layer and exhibits anti-reflection properties. The present disclosure provides a boron-implanted BSI silicon image sensor (CCD or CMOS) produced according to the fabrication process disclosed herein. [0034] In one general aspect, the present disclosure provides a method of fabricating a silicon photo-detection surface and associated dielectric layers suitable for operation as an image sensor in a BSI geometry, such that collection efficiency into charge readout circuitry of photo-excited carriers in silicon is not sensitive to electro-static effects of photo-excited carriers that become trapped in the SiO2 layer (or other dielectric layer) at or near the surface of silicon. Oxide charging during illumination has a strong effect on mobile hole density in silicon due to electrostatic effects. Hole density at and near the silicon surface is reduced from as-fabricated condition due to the presence of trapped hole charges in oxide. The potential profile in silicon is changed as a result of changes in the hole density, since the fixed dopant density does not change. The potential profile changes to create a potential barrier for electron transport in the direction toward the (front-side) charge readout circuitry. This effect typically results in a reduced UV response, which is undesirable. [0035] In one aspect, the present disclosure arranges the depth profiles of three factors in such a way that the electro-static effects of trapped oxide charge do not cause a reduction of response. The three factors are (i) dopant density, (ii) activated dopant density, and (iii) crystal damage due to implant. Inactivated dopants and un-annealed crystal damage serve to provide electron recombination centers in sufficient density, and in addition to interface defect recombination centers, such that minority carrier (electron) lifetime is very low in the near-surface region which experiences potential profile changes. With a very low lifetime, even in the presence of a favorable potential profile to support electron transport to charge readout circuitry as would be expected to be the case as fabricated prior to accumulation of UV illumination, the probability that photo-excited electrons in this near-surface region will drift or diffuse far enough to be collected before recombination occurs can be very low. In this way, the region of silicon that will experience electro-static influence from oxide charging is configured to have very low response and contribute essentially no carriers to the detected signal. In one aspect, one implementation of the present disclosure is to configure the insensitive region to be only as thick as necessary to achieve stable response, as any larger thickness would result in lower UV response with little impact on stability. Any reduction in the density of potential hole trapping sites in the oxide or interface layers would provide benefit, of course. In one aspect, oxide removal and regrowth steps are included to provide for an oxide layer with lower trap density than would be present with native oxide that had been damaged through implant. [0036] In one general aspect, the present disclosure provides a method of fabricating a BSI silicon image sensor (CCD or CMOS), in wafer form and thinned by chemical etching and/or chemical-mechanical polishing (CMP) to reveal the epitaxial layer of the device. The thin silicon back surface is subsequently doped with a shallow high-dose boron implant. Damage to the crystal structure incurred during the implant process is annealed and the dopant is partially activated by exposing the silicon surface to multiple UV laser illumination exposures at sub-melt threshold energy density. The poor quality native SiO2 layer (formed after the thinning process and degraded by implant process) is removed by chemical etching. An oxidation process is used to regrow an oxide layer of minimal thickness with better quality than the native oxide layer. [0037] A dielectric layer, or a stack of more than one dielectric layer, which is deposited directly onto the grown SiO2 layer, is necessary to obtain satisfactory anti-reflection properties, surface protection, and possibly additional surface passivation. In practice, the additional dielectric layer(s) can be Al2O3, SiO2, or HfO2 deposited by ALD. A layer stack of one or more than one layer of Al2O3, SiO2, or HfO2 is deposited by ALD to form a surface protection layer and exhibit anti-reflection property. A post fabrication temperature bake can be executed to populate low energy electron states at defect sites in the dielectric stack of the surface protection layer, if comprised of either Al2O3, or HfO2, and achieve a fixed negative charge outside of the silicon to improve the surface passivation condition of the silicon surface. SiO2 deposited by ALD is not known to provide for negative dielectric charging through a temperature bake process. Although this additional surface passivation condition is not necessary to satisfy the intended conditions required to achieve stable UV response, it is contemplated to be a possible extension of the implementation. [0038] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which examples of the present disclosure are shown. The present disclosure, however, can be embodied in many different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided for thoroughness and completeness, and will fully convey the scope of the present disclosure to those skilled in the art. Like numbers refer to like elements throughout. [0039] Turning now to the figures where FIGS.1A-1F illustrate a series of cross sectional views of a BSI silicon image sensor at various points in the fabrication process according to at least one aspect of the present disclosure. The BSI silicon image sensor may be fabricated as a CCD or CMOS device. The BSI silicon image sensor comprises an optical detection layer of silicon, which is a boron implanted region at the surface of a thinned device silicon layer, and image detector readout circuitry at the opposite surface of the same layer of silicon. One aspect of a fabrication process of the boron-implanted BSI silicon image sensor is described below in connection with FIGS.1A-1F. [0040] Turning first to FIG.1A, there is shown a cross sectional view of a BSI silicon image sensor 100 (CCD or CMOS) in silicon wafer form after thinning and prior to implanting a boron dopant into the exposed face of silicon device layer 104. The BSI silicon image sensor 100 comprises a thinned silicon device wafer, including epitaxial silicon layer 104 and device circuitry layers, bonded to a silicon handle wafer (substrate 102). The silicon substrate 102 can be a standard blank silicon wafer having a nominal thickness of 675 microns for mechanical support purpose. [0041] The silicon device layer 104 contains the electronic components for implementing a CCD or CMOS BSI silicon image sensor device. Various layers of the silicon device layer 104 are shown in FIG.2 and described with more specificity with reference thereto. Generally, the silicon device layer 104 is fabricated on a silicon wafer substrate with epitaxial layer doped to 150 Ohm-cm resistivity and with various device related implants (both n-type and p-type) to form a CCD charge collection and readout circuitry. The device layer 104 has been formed into a thinned layer of silicon, having a nominal thickness of approximately 11 microns, through a substrate removal process after being bonded to a handle wafer for mechanical support. The silicon device layer 104 constitutes the normal electronic device layers of a silicon image detector, except for having the ground plane of the conductive silicon substrate removed. In other aspects, the thickness of the silicon layer 104 may vary and is not critical to the functionality of the BSI silicon image sensor 100 for detection of UV illumination. It will be appreciated that in a CMOS device implementation the silicon layer 104 is thinner than a comparable silicon layer in a CCD device implementation. In BSI configuration, the silicon device layer 104 operates as an electronic circuit layer on one face, and an optical interaction layer on the opposite face. [0042] Returning to FIG.1A, a silicon layer 104 is shown, which was prepared as a high quality optical interface surface using several steps of grinding, polishing, etching, and/or chemical-mechanical-polishing to reach a condition where silicon layer 104 has a thickness of approximately 11 microns. After thinning, a native oxide will form naturally on the surface 108 of the silicon layer 104, and is shown as layer 112. The layer 104 is ready for implantation of a dopant as described below in connection with FIG.1B. [0043] FIG.1B is a cross sectional view of a BSI silicon image sensor 200 shown in FIG. 1A comprising a dopant implanted region 110 formed in the thinned silicon layer 104 of the BSI silicon image sensor 200. In various aspects, the surface 108 of the thinned silicon layer 104 is doped with a shallow high density boron or boron-11 isotope by implantation process to form the dopant implanted region 110 defining a surface 116. [0044] In one aspect, the dopant implanted region 110 is doped with a boron-11 isotope implanted to a concentration greater than 5E20cm^-3 and to a nominal depth of 5 to 30nm. The thickness of the dopant implanted region 110 is determined by the implant energy and will be influenced by the laser annealing energy, described below. [0045] FIG.1C is a cross sectional view of a BSI silicon image sensor 300 shown in FIG. 1B after annealing and activating the dopant implanted region 110 with laser energy applied in a predetermined pattern. The crystal structure damage caused by the implantation process is annealed by a laser to form an annealed dopant implanted region 120 (FIG.1C). As shown in FIG.1C, the boron-11 isotope dopant implanted region 110 is annealed with laser energy applied in a predetermined pattern sufficient to anneal and activate the dopant to the extent that surface passivation effects are achieved, but not to the extent that significant dopant diffusion occurs. In one aspect, the boron-11 isotope dopant implanted region 110 is activated by exposing the surface 108 of the silicon layer 104 to UV laser light at a sub-melt threshold energy density with multiple laser spot exposures. The sub-melt regime of annealing has much lower dopant diffusion rate than the melt regime, and is effective to maintain the dopant profile at the as-implanted profile. In one aspect, the laser is a 248nm krypton fluoride (KrF) excimer laser configured to apply energy with a pulse duration of approximately 10ns and an energy density below the melt threshold energy of implanted silicon. The laser energy is applied in a predetermined pattern comprising a laser spot raster pattern of a series of partially overlapping exposures to cover the surface 116 of the dopant implanted region 110 and create as uniform a total applied laser energy density condition as possible. [0046] FIG.1D is a cross sectional view of a BSI silicon image sensor 400 shown in FIG. 1C after removing the native oxide layer 112 and exposing the surface 116 of the annealed dopant implanted region 120. The native oxide layer is removed by chemical etching, with either a buffered oxide etch or a dilute hydrofluoric acid solution. [0047] FIG.1E is a cross sectional view of a BSI silicon image sensor 500 shown in FIG. 1D with a new oxide layer 124 grown on the surface 116 of the annealed dopant implanted region 120. After removing the native oxide layer 112 a better quality new oxide layer 124 is regrown at a minimal thickness, and therefore will cause a small reduction in thickness of the annealed dopant layer. Ideally the new oxide layer would be free of any defect sites that serve to trap positive charges, though this cannot be achieved in practical methods of implementation. The new oxide layer 124 may be a SiO2 layer grown on the surface 116 of the annealed dopant implanted region 120 to a nominal thickness of approximately 3nm as determined by the growth process. The new oxide layer 124 can be grown either by chemical oxide growth in a SC-1 (standard clean process) mixture, or thermal oxide growth in dry oxygen at a temperature below the upper limits of all materials in the device structure for more than 24 hours. [0048] The BSI silicon image sensor 500 according to one aspect of the present disclosure limits the depth of electro-statically induced changes of the potential profile in silicon layer 104 resulting from accumulation of positive charges trapped in the oxide layer 124 near the Si/SiO2 interface defined at the surface 116 of the silicon layer 104. [0049] FIG.1F is a cross sectional view of a BSI silicon image sensor 600 with a surface protection layer 128 formed over the new oxide layer 124. UV light enters the surface 130 of the surface protection layer 128 on the illumination side 132. The surface protection layer 128 forms an anti-reflection coating (ARC) that exhibits anti-reflection properties according to at least one aspect of the present disclosure. ARC layers can be comprised of one or more dielectric materials in a multiple layer stack. Ideally the new layer 128 is comprised of dielectric materials with bandgap greater than the photon energy of illumination. For 193nm illumination, there are few such material choices compatible with silicon wafer process techniques. In one aspect intended for detection of illumination in the range 190 to 370nm, the surface protection layer 128 is formed on the surface 126 of the new oxide layer 124 by depositing a single layer of Al2O3, SiO2 or HfO2 in an ALD process to a thickness of 10 to 100nm, where the thickness is chosen to be optimal for the anti-reflection condition at the illumination wavelength. In another aspect intended for detection of illumination in the range 190nm to 370nm, the surface protection layer 128 is formed on the surface 126 of the new oxide layer 124 by depositing a layer of Al2O3 and subsequently a layer of SiO2 in an ALD process with layer thicknesses chosen to create an optimal ARC at the illumination wavelength. The thickness of the surface protection layer 128, however, is not critical to the functionality of the BSI silicon image sensor 600 and the thickness may be selected for its optical anti-reflection properties, for example. In one aspect intended for detection of 193nm illumination, the Al2O3 material may be deposited by an ALD process at 200°C using tetramethylammonium (TMA) and water (H₂O) precursors to a thickness of 10nm to 40nm. [0050] Post fabrication, the BSI silicon image sensor 600 may be baked at a predetermined temperature to populate low energy electron states at defect sites in the Al2O3, or HfO2 surface protection layer 128 and achieve a fixed negative charge outside of silicon to improve surface passivation condition of the silicon surface. This condition is not necessary to satisfy the intended condition, but is contemplated to be a possible extension of the implementation. In one aspect, the post fabrication temperature bake may include heating the BSI silicon image sensor 600 at a temperature in the range 300°C to 400°C to enable charge activation of the surface protection layer 128. [0051] Following the fabrication process described in connection with FIGS.1A-1F, the BSI silicon image sensor 600 will undergo additional processing to complete the boron implanted BSI silicon image sensor. The additional processing may include a photolithography process using photoresist to form a patterned metallic light shield layer. The additional processing may also include a photolithography process using photoresist to form open regions in the Al2O3, SiO2, or HfO2 dielectric surface protection layer 128 by wet chemical etching to remove the surface protection layer 128 in certain areas. A photolithography process also may be employed to form open regions in the device silicon layer and other device circuitry layers, such as oxide insulation layers, to create features such as bond pads, and scribe lanes, by reactive ion etching to fully remove the silicon, and chemical etch to remove oxide layers in certain areas. [0052] Additional processes include etching to remove thin layers of titanium and titanium nitride (Ti/TiN), which are used in the CCD fabrication process as barrier metal layer but present difficulty in implementing electrical contact through wire bonds. The aluminum metal layer is exposed in defined regions and is compatible with common techniques to make electrical contact through wire bonds. [0053] Additional processes include assembling the BSI silicon image sensor 600. These processes may include, for example, wafer probing, wafer dicing, die bonding in chip carriers, wire bonding, windowing, and completion of device assembly. [0054] FIG.2 is a cross sectional view of the specific layers of the silicon device layer 104 of the BSI silicon image sensor 100 shown in FIG.1A according to at least one aspect of the present disclosure. The silicon device layer 104 is fabricated prior to providing the wafer for wafer-wafer bonding and other processes described in connection with FIGS.1A-1F. The silicon device layer 104 is formed as one part of a conventional silicon device wafer comprised of a thin “device” layer, typically epitaxially grown doped silicon, on top of a high conductivity silicon substrate through a typical fabrication process to form a “conventional” CCD image sensor 100. One minor modification from the typical CCD fabrication process used to form front illuminated image sensors that was implemented for the process to form the BSI image sensor 600 is the exclusion of the steps to open bond pads to the front side. This leaves the wafer front surface topology as flat as possible, which is beneficial for wafer bonding, but precludes any electrical device test even though the sensor circuits are fully fabricated at this stage and able to be tested to monitor fabrication success. Additional steps include preparation of the image sensor wafer for wafer-wafer bonding by deposition of a thick silicon oxide layer. Wafer-to-wafer bonding can be accomplished by several methods. Application of an adhesive material to one or both wafers, and curing of the adhesive at an appropriate temperature is a common method. Another method avoids use of adhesive material by achieving strong covalent molecular bonds between oxygen atoms on the faces of two wafers brought into intimate contact, such method referred to as oxide-oxide molecular bond process. The device wafer is edge trimmed in outer periphery region to remove all device wafer in a region of potential weaker bond. [0055] Still with reference to FIG.2, the layers of the silicon device layer 104 are formed during a CCD wafer fabrication process in the order from the top layers (176 and 174) first and the bottom layers (154, 152) last, prior to wafer-wafer bonding. Wafer bonding can be achieved by use of a wafer bonding material layer 150 that bonds the silicon device layer 104 to the silicon substrate 102 (FIG.1A), which is needed for mechanical support once the device wafer is thinned. [0056] FIG.3 is a method 700 of fabricating the BSI silicon image sensor of FIGS.1A-1F according to at least one aspect of the present disclosure. With reference now to FIGS.1A- 1F and 2, to initiate the method 700, a silicon image sensor in silicon wafer form is provided 702. The silicon image sensor wafer is bonded to a silicon handle wafer for support. The substrate of the silicon image sensor wafer is removed to expose the surface of silicon device layer 104. The surface 108 of the silicon layer 104 is doped 706 with a shallow high density boron implant to form a dopant implanted region 110. [0057] After implanting the surface 108 of the silicon layer 104 with a boron-11 isotope to form the dopant implanted region 110, the crystal structure of the boron-11 isotope dopant implanted region 110 is annealed 708 with a laser in a predetermined pattern to anneal and activate the dopant. [0058] The annealed dopant implanted region 120 is activated by exposing the surface 108 of the silicon layer 104 to UV laser light at sub-melt threshold energy density with multiple laser spot exposures. The laser energy is applied in a predetermined pattern comprising a laser spot raster pattern of a series of exposures to cover the surface 116 of the dopant implanted region 110 with a uniform total energy density condition. [0059] After annealing and activating 708 the dopant implanted region 110, the native oxide layer 112 is removed 710 by chemical etching, for example, either by buffered oxide etch or a diluted hydrofluoric acid solution. A new oxide layer 124 is grown 712 on the surface 116 of the activated dopant implanted region 120. The new oxide layer 124 may be grown 712 by either chemical oxide growth by immersion in SC-1 mixture or thermal oxide growth at in dry oxygen at a temperature below the upper limits of all materials in the device structure. [0060] A surface protection layer 128 is deposited 714 on the surface 126 of the new oxide layer 124. In one aspect, the surface protection layer 128 is formed by depositing 714 Al2O3 by ALD at 200°C using tetramethylammonium (TMA) and water (H₂O) precursors to a thickness of 15nm. In one aspect, a post fabrication temperature bake may include heating the BSI silicon image sensor 600 at a temperature of 350°C to enable charge activation of the 15nm thick surface protection layer 128 to capture electron charge (negative) into the Al2O3, dielectric surface protection layer 128. [0061] Additional processing may include photolithography to form 716 open regions in the surface protection layer 128, oxide layer 124, and the device silicon layer to form bond pads, and scribe lanes, in certain areas. The open regions extend from the top surface through to the first metal layer of the device circuitry layers to create wire bond pads. [0062] Additional processing includes titanium nitride etching to remove a thin layer of Ti/TiN that is adjacent to the first metal layer. The aluminum metal layer is exposed in defined regions to enable electrical contact through wire bonds. [0063] Additional processing includes assembling the BSI silicon image sensor 600. These processes may include, for example, wafer probing, wafer dicing, die bonding in chip carriers, wire bonding, windowing, and completion of device assembly. EXAMPLES [0064] Various aspects of the subject matter described herein are set out in the following examples. [0065] Example 1. A method of fabricating a back-side illuminated (BSI) silicon image sensor, the method comprising: providing an image sensor in the form of a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the image sensor silicon wafer is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the image sensor silicon layer with a boron implant to the optical entrance surface to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the image sensor wafer and exposing the silicon surface; growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region; and depositing a dielectric layer over the new oxide layer. [0066] Example 2. The method of Example 1, wherein the boron implant is a shallow high dose boron implant. [0067] Example 3. The method of any one or more of Examples 1-2, wherein the boron implant is a boron-11 implant. [0068] Example 4. The method of Example 3, comprising doping the near surface region of the silicon layer with a boron-11 isotope at a concentration in the range 1E20cm^-3 - 5E21cm^-3, having a nominal thickness of approximately 5nm to 30 nm. [0069] Example 5. The method of any one or more of Examples 1-4, comprising doping the surface of the silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, to obtain the dopant concentration profile in the range 1E20cm^-3 - 5E21cm^-3 extending over a depth in the range 5nm to 30nm. [0070] Example 6. The method of any one or more of Examples 1-5, comprising annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern. [0071] Example 7. The method of Example 6, comprising applying the laser energy at an energy density per pulse sufficient to produce activation for a limited portion of the dopant and to produce a minimum profile change of the dopant concentration, as compared to pre- annealed profile. [0072] Example 8. The method of Example 7, comprising applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region. [0073] Example 9. The method of any one or more of Examples 7-8, wherein the laser has a wavelength of operation in the range 190nm to 370nm. [0074] Example 10. The method of any one or more of Examples 1-9, comprising removing the native oxide layer by chemical etching. [0075] Example 11. The method of any one or more of Examples 1-10, comprising growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture. [0076] Example 12. The method of any one or more of Examples 1-11, comprising growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours. [0077] Example 13. The method of any one or more of Examples 1-12, comprising depositing the surface protection layer over the new oxide layer. [0078] Example 14. The method of Example 13, wherein the surface protection layer comprises one or more layers of any combination of Al2O3, HfO2, or SiO2 deposited by atomic layer deposition (ALD) [0079] Example 15. The method of Example 14, wherein the surface protection layer is deposited by ALD to a thickness in the range 10nm to 40nm.. [0080] Example16. The method of Example 13, comprising heating the BSI silicon image sensor with surface protection layer deposited at a temperature in the range 300°C to 400°C. [0081] Example17. The method of any one or more of Examples 1-16, comprising removing the silicon and the portion of dielectric material of the image sensor silicon wafer in predefined regions by a photolithography process. [0082] Example 18. The method of any one or more of Examples 1-17, comprising removing silicon and a portion of dielectric materials of the image sensor silicon wafer in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds. [0083] Example19. A back-side illuminated silicon image sensor fabricated according to the method of any one or more of Examples 1-18. [0084] While specific aspects of the present disclosure have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of which is to be given the full breadth of the claims appended and any and all equivalents thereof. [0085] Those skilled in the art will recognize that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to claims containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should typically be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. [0086] In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, typically means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). In those instances where a convention analogous to “at least one of A, B, or C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “a system having at least one of A, B, or C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B, and C together, etc.). It will be further understood by those within the art that typically a disjunctive word and/or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms unless context dictates otherwise. For example, the phrase “A or B” will be typically understood to include the possibilities of “A” or “B” or “A and B.” [0087] With respect to the appended claims, those skilled in the art will appreciate that recited operations therein may generally be performed in any order. Also, although various operational flow diagrams are presented in a sequence(s), it should be understood that the various operations may be performed in other orders than those which are illustrated, or may be performed concurrently. Examples of such alternate orderings may include overlapping, interleaved, interrupted, reordered, incremental, preparatory, supplemental, simultaneous, reverse, or other variant orderings, unless context dictates otherwise. Furthermore, terms like “responsive to,” “related to,” or other past-tense adjectives are generally not intended to exclude such variants, unless context dictates otherwise. [0088] It is worthy to note that any reference to “one aspect,” “an aspect,” “an exemplification,” “one exemplification,” and the like means that a particular feature, structure, or characteristic described in connection with the aspect is included in at least one aspect. Thus, appearances of the phrases “in one aspect,” “in an aspect,” “in an exemplification,” and “in one exemplification” in various places throughout the specification are not necessarily all referring to the same aspect. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more aspects. [0089] Any patent application, patent, non-patent publication, or other disclosure material referred to in this specification and/or listed in any Application Data Sheet is incorporated by reference herein, to the extent that the incorporated materials is not inconsistent herewith. As such, and to the extent necessary, the disclosure as explicitly set forth herein supersedes any conflicting material incorporated herein by reference. Any material, or portion thereof, that is said to be incorporated by reference herein, but which conflicts with existing definitions, statements, or other disclosure material set forth herein will only be incorporated to the extent that no conflict arises between that incorporated material and the existing disclosure material. [0090] The terms "comprise" (and any form of comprise, such as "comprises" and "comprising"), "have" (and any form of have, such as "has" and "having"), "include" (and any form of include, such as "includes" and "including") and "contain" (and any form of contain, such as "contains" and "containing") are open-ended linking verbs. As a result, a system that "comprises," "has," "includes" or "contains" one or more elements possesses those one or more elements, but is not limited to possessing only those one or more elements. Likewise, an element of a system, device, or apparatus that "comprises," "has," "includes" or "contains" one or more features possesses those one or more features, but is not limited to possessing only those one or more features. [0091] In summary, numerous benefits have been described which result from employing the concepts described herein. The foregoing description of the one or more forms has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise form disclosed. Modifications or variations are possible in light of the above teachings. The one or more forms were chosen and described in order to illustrate principles and practical application to thereby enable one of ordinary skill in the art to utilize the various forms and with various modifications as are suited to the particular use contemplated. It is intended that the claims submitted herewith define the overall scope.

Claims

CLAIMS 1. A method of fabricating a back-side illuminated (BSI) silicon image sensor, the method comprising: providing an image sensor in the form of a silicon wafer bonded face-to-face to a handle wafer, wherein a silicon substrate of the image sensor silicon wafer is thinned to expose a silicon layer comprising device circuitry of the image sensor and forming an optical entrance surface; doping a portion of the image sensor silicon layer with a boron implant to the optical entrance surface to create a dopant implanted region; annealing and activating the dopant implanted region with laser energy; removing a native oxide layer formed on the optical entrance surface after thinning the image sensor wafer and exposing the silicon surface; growing a new oxide layer on the optical entrance surface over the annealed dopant implanted region; and depositing a dielectric layer over the new oxide layer.

2. The method of claim 1, wherein the boron implant is a shallow high dose boron implant.

3. The method of claim 1, wherein the boron implant is a boron-11 implant.

4. The method of claim 3, comprising doping the near surface region of the silicon layer with a boron-11 isotope at a concentration in the range 1E20cm^-3 - 5E21cm^-3, having a nominal thickness of approximately 5nm to 30 nm.

5. The method of claim 1, comprising doping the surface of the silicon layer by implanting the boron implant at a predetermined energy, twist, and total dose, to obtain the dopant concentration profile in the range 1E20cm^-3 - 5E21cm^-3 extending over a depth in the range 5nm to 30nm.

6. The method of claim 1, comprising annealing and activating the dopant implanted region with the laser energy applied in a predetermined pattern.

7. The method of claim 6, comprising applying the laser energy at an energy density per pulse sufficient to produce activation for a limited portion of the dopant and to produce a minimum profile change of the dopant concentration, as compared to pre-annealed profile.

8. The method of claim 7, comprising applying a laser spot raster pattern of a series of partially overlapping exposures to cover the surface of the dopant implanted region.

9. The method of claim 7, wherein the laser has a wavelength of operation in the range 190nm to 370nm.

10. The method of claim 1, comprising removing the native oxide layer by chemical etching.

11. The method of claim 1, comprising growing the new oxide layer by chemical oxide growth to a nominal thickness of 3nm by immersion in a standard clean process 1 (SC-1) mixture.

12. The method of claim 1, comprising growing the new oxide layer by thermal oxide growth at temperature between 200°C and 300°C in dry oxygen for more than 24 hours.

13. The method of claim 1, comprising depositing a surface protection layer over the new oxide layer.

14. The method of claim 13, wherein the surface protection layer comprises one or more layers of any combination of Al2O3, SiO2, or HfO2 deposited by atomic layer deposition (ALD).

15. The method of claim 14, wherein the surface protection layer is deposited by ALD to a thickness in a range of approximately 10nm to 40nm.

16. The method of claim 13, comprising heating the BSI silicon image sensor to a temperature in the range 300°C to 400°C.

17. The method of claim 1, comprising removing the silicon and the portion of dielectric material of the image sensor silicon wafer in predefined regions by a photolithography process.

18. The method of claim 1, comprising removing silicon and a portion of dielectric materials of the image sensor silicon wafer in predefined regions to expose a metal layer of the device circuitry of the image sensor to provide for electrical connection to the image sensor device through wire bond welds.

19. A back-side illuminated (BSI) silicon image sensor fabricated according to the method of claims 1-18.