WO2013118706A1 - Transistor à couches minces à structure tridimensionnelle, et son procédé de fabrication - Google Patents

Transistor à couches minces à structure tridimensionnelle, et son procédé de fabrication Download PDF

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Publication number
WO2013118706A1
WO2013118706A1 PCT/JP2013/052574 JP2013052574W WO2013118706A1 WO 2013118706 A1 WO2013118706 A1 WO 2013118706A1 JP 2013052574 W JP2013052574 W JP 2013052574W WO 2013118706 A1 WO2013118706 A1 WO 2013118706A1
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WO
WIPO (PCT)
Prior art keywords
electrode
side wall
substrate
layer
forming
Prior art date
Application number
PCT/JP2013/052574
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English (en)
Japanese (ja)
Inventor
竹谷純一
宇野真由美
Original Assignee
国立大学法人大阪大学
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Filing date
Publication date
Application filed by 国立大学法人大阪大学 filed Critical 国立大学法人大阪大学
Publication of WO2013118706A1 publication Critical patent/WO2013118706A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]

Definitions

  • Forming a gate electrode layer by removing a part of the electrode film in a state of leaving, a step of removing all the resist film, and a gate so as to cover the formed gate electrode layer A step of providing an insulator layer; and a step of sequentially forming the semiconductor layer and the source and drain electrodes or the source and drain electrodes and the semiconductor layer on the gate insulator layer. Provided with a door.
  • the thin film transistor of the present invention is suitable for use in an organic EL display or the like because parasitic capacitance due to the gate electrode is reduced to a minimum and the response speed of the transistor is dramatically improved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne : un substrat isolant (1); une structure étagée (2) formant une surface convexe par rapport à la surface principale (1a) du substrat et ayant une surface de paroi latérale (2a) qui est orientée verticalement par rapport à la surface principale; une couche d'électrode de grille (3) placée sur la surface de paroi latérale; une couche d'isolation de grille (4) placée de façon à couvrir la couche d'électrode de grille; une couche de semiconducteur (5) placée sur la couche d'isolation de grille, dans au moins une région sur la surface de paroi latérale; une électrode de source (6) placée soit dans la partie supérieure de la structure étagée, soit dans la région du substrat qui ne possède pas la structure étagée; et une électrode de drain (7) disposée dans l'autre des deux régions; l'électrode de source et l'électrode de drain étant formées de façon à être connectées à la couche de semiconducteur dans des parties haute et basse de la surface de paroi latérale. Le transistor est configuré de telle sorte que la couche de semiconducteur est disposée sur la surface de paroi latérale, qui est orientée verticalement par rapport à la surface principale du substrat, et la capacité parasite entre l'électrode de grille et les électrodes de source/de drain est réduite.
PCT/JP2013/052574 2012-02-10 2013-02-05 Transistor à couches minces à structure tridimensionnelle, et son procédé de fabrication WO2013118706A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-027505 2012-02-10
JP2012027505A JP5887591B2 (ja) 2012-02-10 2012-02-10 三次元構造を有する薄膜トランジスタ及びその製造方法

Publications (1)

Publication Number Publication Date
WO2013118706A1 true WO2013118706A1 (fr) 2013-08-15

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Country Status (2)

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JP (1) JP5887591B2 (fr)
WO (1) WO2013118706A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015025480A1 (fr) * 2013-08-22 2015-02-26 株式会社デンソー Capteur de charge utilisant un transistor vertical
JP2015056498A (ja) * 2013-09-11 2015-03-23 国立大学法人大阪大学 有機薄膜トランジスタ及びその製造方法
JP2015064328A (ja) * 2013-08-30 2015-04-09 株式会社デンソー マトリクス型の荷重センサ
WO2015134091A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft doté de poteau, capuchon et grille alignée
WO2015134092A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft comprenant des électrodes se chevauchant
WO2015134082A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft à noyau polymère
WO2015134083A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtfts comprenant des électrodes décalées
JP2016133450A (ja) * 2015-01-21 2016-07-25 株式会社デンソー 荷重センサ

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6003460B2 (ja) * 2012-09-24 2016-10-05 株式会社デンソー 縦型トランジスタの製造方法
JP6330595B2 (ja) * 2014-09-15 2018-05-30 株式会社デンソー 荷重センサ
WO2018203181A1 (fr) * 2017-05-01 2018-11-08 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur
CN110634390A (zh) * 2019-09-20 2019-12-31 武汉天马微电子有限公司 一种显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0485880A (ja) * 1990-07-26 1992-03-18 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
JPH04218971A (ja) * 1990-07-25 1992-08-10 Semiconductor Energy Lab Co Ltd 縦チャネル型絶縁ゲイト型電界効果半導体装置の作製方法
JP2008060522A (ja) * 2006-01-24 2008-03-13 Ricoh Co Ltd 電子素子、電流制御装置、演算装置及び表示装置
WO2009133891A1 (fr) * 2008-04-30 2009-11-05 国立大学法人大阪大学 Transistor à effet de champ vertical

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003282884A (ja) * 2002-03-26 2003-10-03 Kansai Tlo Kk サイドゲート型有機ｆｅｔ及び有機ｅｌ
JP2005019446A (ja) * 2003-06-23 2005-01-20 Sharp Corp 電界効果トランジスタおよびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04218971A (ja) * 1990-07-25 1992-08-10 Semiconductor Energy Lab Co Ltd 縦チャネル型絶縁ゲイト型電界効果半導体装置の作製方法
JPH0485880A (ja) * 1990-07-26 1992-03-18 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果半導体装置
JP2008060522A (ja) * 2006-01-24 2008-03-13 Ricoh Co Ltd 電子素子、電流制御装置、演算装置及び表示装置
WO2009133891A1 (fr) * 2008-04-30 2009-11-05 国立大学法人大阪大学 Transistor à effet de champ vertical

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MAYUMI UNO ET AL.: "Kosoku Oto Sanjigen Yuki Transistor", DAI 60 KAI THE JAPAN SOCIETY OF APPLIED PHYSICS SHUNKI GAKUJUTSU KOENKAI KOEN YOKOSHU, 11 March 2013 (2013-03-11), pages 27P-G15 - 14 *

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160202132A1 (en) * 2013-08-22 2016-07-14 Denso Corporation Load sensor using vertical transistor
JP2015040778A (ja) * 2013-08-22 2015-03-02 株式会社デンソー 縦型トランジスタを用いた荷重センサ
CN105473990B (zh) * 2013-08-22 2018-12-18 株式会社电装 使用纵型晶体管的载荷传感器
KR101901036B1 (ko) 2013-08-22 2018-09-20 가부시키가이샤 덴소 종형 트랜지스터를 사용한 하중 센서
WO2015025480A1 (fr) * 2013-08-22 2015-02-26 株式会社デンソー Capteur de charge utilisant un transistor vertical
US9658121B2 (en) 2013-08-22 2017-05-23 Denso Corporation Load sensor using vertical transistor
CN105473990A (zh) * 2013-08-22 2016-04-06 株式会社电装 使用纵型晶体管的载荷传感器
JP2015064328A (ja) * 2013-08-30 2015-04-09 株式会社デンソー マトリクス型の荷重センサ
JP2015056498A (ja) * 2013-09-11 2015-03-23 国立大学法人大阪大学 有機薄膜トランジスタ及びその製造方法
WO2015134082A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft à noyau polymère
US9331205B2 (en) 2014-03-06 2016-05-03 Eastman Kodak Company VTFT with post, cap, and aligned gate
WO2015134083A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtfts comprenant des électrodes décalées
WO2015134092A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft comprenant des électrodes se chevauchant
WO2015134091A1 (fr) * 2014-03-06 2015-09-11 Eastman Kodak Company Vtft doté de poteau, capuchon et grille alignée
JP2016133450A (ja) * 2015-01-21 2016-07-25 株式会社デンソー 荷重センサ

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JP5887591B2 (ja) 2016-03-16

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