WO2013064014A1 - 接触孔的形成方法 - Google Patents

接触孔的形成方法 Download PDF

Info

Publication number
WO2013064014A1
WO2013064014A1 PCT/CN2012/083049 CN2012083049W WO2013064014A1 WO 2013064014 A1 WO2013064014 A1 WO 2013064014A1 CN 2012083049 W CN2012083049 W CN 2012083049W WO 2013064014 A1 WO2013064014 A1 WO 2013064014A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact hole
etching
forming
interlayer dielectric
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/083049
Other languages
English (en)
French (fr)
Inventor
许宗能
任小兵
王吉伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Publication of WO2013064014A1 publication Critical patent/WO2013064014A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and more particularly to a method of forming a contact hole.
  • the manufacturing process of the semiconductor device can be divided into a front-end process and a back-end process.
  • the front-end process mainly forms a corresponding device such as a transistor, a capacitor or a resistor on the substrate, and the latter process mainly connects the devices formed in the previous process through metal, that is, mainly forms a metal. interconnection.
  • ILD interlayer dielectric
  • FIG. 1 there is shown a contact hole 2 formed in the interlayer dielectric 1 and the interlayer dielectric 1 and connected to the active region 4, and an overetch is formed at the corner 3 of the bottom of the contact hole 2.
  • the corner portion 3 formed by etching is located in the shallow trench dielectric layer 5.
  • the shallow trench dielectric layer 5 is used to isolate the active region 4, when one of the shallow trench dielectric layers 5 is etched to form a contact hole, it is severely activated in a serious case.
  • the source or drain within region 4 is shorted to the substrate, thereby rendering the device inoperative.
  • the prior art method for solving the corner loss when forming the contact hole is to form a layer of silicon oxynitride first before forming the ILD on the substrate, and then forming an ILD on the silicon oxynitride, and then performing contact hole etching. eclipse.
  • the silicon oxynitride layer can serve as an etch stop layer, and therefore, the problem of corner loss due to the unevenness of the ILD can be solved.
  • the problem of corner loss still occurs.
  • the method of the prior art can only reduce the corner loss generated when the contact hole is formed, but the corner loss cannot be completely eliminated.
  • the present invention provides a method of forming a contact hole which can completely eliminate corner loss and thereby improve the yield of the device.
  • the present invention provides the following technical solutions:
  • a method of forming a contact hole comprising:
  • the interlayer dielectric on the substrate before forming the interlayer dielectric on the substrate, further comprising: forming a silicon oxynitride layer on the substrate;
  • the method further includes: etching the silicon oxynitride layer to form a third contact hole after etching The third contact hole is in communication with the second contact hole.
  • the first etching when the interlayer dielectric is formed into a contact hole comprises:
  • the interlayer dielectric is first etched by using the photoresist layer having the contact hole pattern as a mask, and the first etching is performed for a preset time.
  • the interlayer medium has a thickness of 7300 ⁇ .
  • the predetermined thickness is 3000 ⁇ .
  • the protective layer is a silicon nitride layer.
  • the interlayer medium comprises: a lower layer of 7000 ⁇ of silicon dioxide and an upper layer of 300 ⁇ of an anti-reflection layer.
  • the substrate is a silicon substrate.
  • the interlayer dielectric is formed on the substrate by a chemical vapor deposition process.
  • the protective layer is etched by a dry etching process.
  • the method for forming the contact hole retains the interlayer dielectric of a predetermined thickness after the first etching of the interlayer dielectric, and simultaneously forms the first contact hole. And forming a protective layer on the interlayer dielectric, the protective layer covering the bottom and the sidewall of the first contact hole; and subsequently protecting the sidewall of the first contact hole when etching the protective layer The layer will not be etched away, that is, a part of the protective layer is left on the sidewall of the first contact hole; and finally, the second etching is performed on the interlayer dielectric of the predetermined thickness of the remaining contact hole. And forming a second contact hole.
  • the second etching since a part of the protective layer remains on the sidewall of the first contact hole, the remaining partial protective layer will protect the interlayer directly underneath The medium is not etched away, so that the width of the finally formed second contact hole is smaller than the width of the first contact hole, and when the second contact hole communicates with the first contact hole to form a contact hole, the contact hole corner There will be no over-etching. Phenomenon is avoided corner loss in the active region and / or the gate side portions, thereby reducing the failure rate of the device.
  • FIG. 1 is a schematic structural view showing a phenomenon of corner loss occurring in the formation of a contact hole which is common in the prior art
  • FIG. 2 is a schematic flow chart of a method for forming a contact hole according to an embodiment of the present invention
  • FIG. 3 to FIG. 8 are schematic cross-sectional views of a device during formation of a contact hole according to an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart diagram of a method for forming a contact hole according to an embodiment of the present invention, where the method specifically includes the following steps:
  • Step S1 providing a substrate having an active region and a gate thereon.
  • the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 may also be a semiconductor such as germanium, indium phosphide or gallium arsenide. material.
  • the substrate 100 generally includes a body layer and an epitaxial layer. During the manufacturing process of the semiconductor device, the carrier during the process of photolithography, etching, or ion implantation is generally an epitaxial layer, and the present specification will not specifically distinguish the substrate.
  • the body layer and the epitaxial layer are generally referred to as performing various process steps on or in the substrate.
  • the substrate 100 provided in this step has a gate electrode 104 and side walls 105 on both sides of the gate electrode 104; a deep well region 101 in the substrate 100, and an active region in the deep well region 101, the active region
  • the region includes a source region 102 and a drain region 103, and the source region 102 and the drain region 103 are respectively located on both sides of the gate electrode 104.
  • the substrate 100 also has a shallow trench dielectric layer 106 therein for isolating active devices.
  • Step S2 forming an interlayer medium on the substrate.
  • an interlayer dielectric 107 is formed on the substrate 100 by a chemical vapor deposition method.
  • the interlayer dielectric 107 includes a lower layer of silicon dioxide and an upper thin anti-reflection layer (about 300 ⁇ ).
  • the thickness of the interlayer dielectric 107 is 7300 ⁇ .
  • silicon dioxide is first formed on the substrate 100, and then an anti-reflection layer is formed on the silicon dioxide.
  • the anti-reflection layer may be a silicon oxynitride layer, and the anti-reflection layer may be in the following step S6. Used as a hard mask layer.
  • the silicon dioxide and silicon oxynitride layers are not specifically shown in FIG. 4 and, therefore, will be collectively referred to as interlayer dielectric 107 in the following steps.
  • Step S3 performing a first etching on the interlayer dielectric when forming a contact hole, and retaining an interlayer dielectric of a predetermined thickness after the first etching, and forming a first contact hole after the first etching.
  • a contact hole for forming a drain region is taken as an example for description.
  • This step can include the following steps:
  • Step S31 setting a preset time.
  • the preset time in this step refers to the time during which the etching is performed when etching the interlayer dielectric, and the time can be set in advance on the etching machine.
  • the preset time is set to 50s in this step. In other embodiments, different preset times may be set according to different process requirements. However, the preset time is less than the time required for the interlayer dielectric to be completely etched away.
  • Step S32 forming a photoresist layer having a drain contact hole pattern on the interlayer dielectric.
  • a photoresist layer is spin-coated on the interlayer dielectric, and then the photoresist layer is exposed by a mask having a drain contact hole pattern, developed after exposure, and formed on the interlayer dielectric.
  • a photoresist layer having a drain contact hole pattern is a photoresist layer having a drain contact hole pattern.
  • Step S33 performing the first etching on the interlayer dielectric by using the photoresist layer having the drain contact hole pattern as a mask, and performing the first etching for a preset time.
  • the interlayer dielectric 107 is first etched by using the photoresist layer (not shown) having a drain contact hole pattern as a mask, and the first etching is performed.
  • the time is the preset time set in step S31. Since the preset time is less than the time required for the interlayer dielectric 107 to be completely etched away, a certain thickness of the interlayer dielectric 107 is retained after the first etching (after the first etching is completed, the etching has been performed).
  • the antireflection layer on the interlayer dielectric 107 and a portion of the silicon dioxide layer, the interlayer dielectric 107 of a certain thickness retained is silicon dioxide, and the thickness d of the interlayer dielectric 107 remaining is shown.
  • the contact hole formed by the first etch of the interlayer dielectric 107 is referred to as a first contact hole 108 in the embodiment of the present invention.
  • the width a of the first contact hole 108 is a photoresist layer.
  • the upper drain area is the width of the contact hole pattern.
  • the thickness d can also be referred to as a preset thickness.
  • the first etching of the interlayer dielectric 107 is performed by an anisotropic dry etching process, and the second etching described below is also dry etching.
  • Step S4 forming a protective layer on the interlayer dielectric, the protective layer covering a bottom portion and a sidewall of the first contact hole.
  • a protective layer 109 is formed on the interlayer dielectric 107 by a chemical vapor deposition method, and the protective layer 109 covers the bottom and sidewalls of the first contact hole 108.
  • the protective layer 109 is a silicon nitride layer.
  • the protective layer 109 may also be another material, such as polysilicon.
  • the thickness of the protective layer 109 in this embodiment is 300 ⁇ .
  • Step S5 etching the protective layer.
  • the protective layer on the interlayer dielectric 107 is etched by a dry etching process. Since the dry etching process is anisotropic etching, the protective layer 110 covering the sidewall of the first contact hole 108 cannot Etched (according to the spacer principle), therefore, the protective layer is etched as follows: the protective layer 110 on the sidewall of the first contact hole 108 is retained, and the remaining protective layers are etched away. .
  • Step S6 performing a second etching on the interlayer dielectric of the predetermined thickness of the remaining contact layer, and forming a second contact hole after the second etching, the second contact hole and the first contact hole A contact hole is connected.
  • the contact hole forming the drain region is still taken as an example for description.
  • the interlayer dielectric 107 of the predetermined predetermined thickness d is subjected to a second etching with the anti-reflection layer in the interlayer dielectric 107 as a hard mask. After the second etching of the remaining interlayer dielectric 107 having a predetermined thickness d, a second contact hole 111 is formed, and the second contact hole 111 is in communication with the first contact hole 108.
  • the width b of the second contact hole 111 formed after the second etching is smaller than the width a of the first contact hole 108, and the difference between the two is the first contact.
  • the thickness of the protective layer 110 on the side wall of the hole 108 is twice (assuming that the thickness of the protective layer 110 on the side walls of the first contact hole 108 is the same).
  • the thickness of the protective layer formed in step S4 By controlling the thickness of the protective layer formed in step S4, the thickness of the protective layer 110 on the sidewall of the first contact hole 108 can be controlled, and the width b of the second contact hole 111 can be controlled.
  • the second contact hole 111 and the first contact hole 108 communicate with each other to form a contact hole connected to the drain region 103. Since the second contact hole 111 is directly connected to the drain region 103, the second contact hole is The width b of the 111 is the size (CD) of the contact hole connected to the drain region 103. Therefore, when the contact hole connected to the drain region 103 is formed by the method provided by the present invention, the contact hole can be effectively reduced. size.
  • the plasma used in the etching process does not etch the protective layer on the sidewall of the corresponding first contact hole 108.
  • the interlayer dielectric 112 directly under 110 therefore, when a contact hole connected to the drain region 103 is finally formed, no corner loss phenomenon occurs. Even if the etching time is slightly longer, the over-etched region is located in the drain region 103 and is not located in the shallow trench dielectric layer 106, thereby avoiding short-circuiting of the drain region 103 and the substrate 100, thereby avoiding device failure. The phenomenon occurs.
  • the method for forming the contact hole performs the etching for forming the contact hole of the interlayer dielectric twice (referred to as the first etching and the second etching, respectively), and twice.
  • a protective layer is formed on the interlayer dielectric during the etching process, and the protective layer is etched.
  • the result of etching the protective layer is: a first contact hole formed after the first etching A portion of the protective layer (spacer principle) is left on the sidewall, and the protective layer can protect the interlayer dielectric directly under the etching layer during the subsequent second etching.
  • the second etching The width of the second contact hole formed later is smaller than the width of the first contact hole, which reduces the size of the contact hole, and on the other hand avoids corner loss on both sides of the active region or the gate.
  • corner loss in the shallow trench dielectric layer can be avoided, thereby avoiding shorting of the source/drain and the substrate, and reducing the risk of device failure.
  • This embodiment adds two steps on the basis of the first embodiment, respectively as follows:
  • the silicon oxynitride layer may be formed on the substrate; after the step S6 in the first embodiment, the silicon oxynitride layer may be etched and formed by etching. a third contact hole, the third contact hole being in communication with the second contact hole.
  • a silicon oxynitride layer is first formed on the substrate, and then a second etching is performed on the interlayer dielectric of the predetermined thickness of the remaining thickness. Etching the silicon oxynitride layer, the etching result is that a third contact hole is formed, and the third contact hole is in communication with the second contact hole, thereby the first contact hole, the The second contact hole and the third contact hole together constitute a contact hole connecting the active region or the gate.
  • a silicon oxynitride layer is first formed before forming the interlayer dielectric, and the silicon oxynitride layer can be used as a stop layer in the process of performing the second etching on the interlayer dielectric, thereby avoiding the interlayer dielectric.
  • the phenomenon of corner loss caused by uniformity therefore, the occurrence of corner loss during the formation of the contact hole can be better avoided, and the failure rate of the device can be reduced.
  • the embodiment of the present invention describes a method for forming a contact hole in a progressive manner, and each embodiment has its own focus, and related and similar aspects can be referred to each other.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

一种接触孔的形成方法，包括提供基底，所述基底上具有有源区和栅极；在所述基底上形成层间介质；对所述层间介质进行形成接触孔时的第一次刻蚀，第一次刻蚀后保留预设厚度的层间介质，且第一次刻蚀后形成了第一接触孔；在所述层间介质上形成保护层，所述保护层覆盖所述第一接触孔的底部和侧壁；对所述保护层进行刻蚀；对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀，第二次刻蚀后形成了第二接触孔，所述第二接触孔与所述第一接触孔相连通。该接触孔的形成方法，可有效避免在有源区和/或栅极侧部出现角部损失的现象，进而减小了器件的失效率。

Description

接触孔的形成方法
【技术领域】
本发明涉及半导体制造技术领域，更具体地说，涉及一种接触孔的形成方法。
【背景技术】
半导体器件制造过程可分为前段工艺和后段工艺，前段工艺主要在衬底上形成晶体管、电容或电阻等相应器件，后段工艺主要将前段工艺中形成的器件通过金属相连，即主要形成金属互连。其中，在后段工艺中形成金属互连时，首先需要在已形成有晶体管、电容或电阻等相应器件的衬底上形成层间介质（ILD），然后在ILD中形成接触孔，之后在所述ILD上形成金属层，所述金属层填充满ILD中的接触孔，从而使衬底上相应器件的有源区和栅极通过接触孔内的金属与ILD上的金属层相连。
近几年来，半导体器件的特征尺寸越来越小，这对制造过程中的精度要求越来越高。在0.13μm~0.18μm的制造工艺中，后段工艺中在ILD中形成接触孔时，常会由于工艺窗口限制、光刻过程中的对位不准或设计过程中的偏差等原因而导致出现角部损失（corner loss）。参考图1，图1中示出了层间介质1及层间介质1中所形成的、与有源区4相连的接触孔2，在该接触孔2底部的角部3出现了过刻蚀，被过刻蚀而形成的角部3位于浅沟槽介质层5内。由于所述浅沟槽介质层5用于隔离有源区4，因此，当所述浅沟槽介质层5中的一个角部3被刻蚀而形成接触孔时，严重情况下会使得有源区4内的源或漏与衬底短接，从而使得器件失效。
现有工艺在形成接触孔时解决角部损失的方法有：在衬底上形成ILD之前，首先形成一层氮氧化硅，之后在所述氮氧化硅上形成ILD，然后再进行接触孔的刻蚀。在刻蚀ILD时，所述氮氧化硅层可作为刻蚀停止层，因此，可解决因ILD不均匀而导致出现的角部损失问题。但是，刻蚀完ILD后，再对所述氮氧化硅层进行刻蚀以形成接触孔时，仍然会出现角部损失的问题。
因此，采用现有工艺中的方法只能减小形成接触孔时所产生的角部损失，但不能完全消除所述角部损失。
【发明内容】
有鉴于此，本发明提供一种接触孔的形成方法，该方法能够完全消除角部损失，进而提高器件的成品率。
为实现上述目的，本发明提供如下技术方案：
一种接触孔的形成方法，该方法包括：
提供基底，所述基底上具有有源区和栅极；
在所述基底上形成层间介质；
对所述层间介质进行形成接触孔时的第一次刻蚀，第一次刻蚀后保留预设厚度的层间介质，且第一次刻蚀后形成了第一接触孔；
在所述层间介质上形成保护层，所述保护层覆盖所述第一接触孔的底部和侧壁；
对所述保护层进行刻蚀；
对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀，第二次刻蚀后形成了第二接触孔，所述第二接触孔与所述第一接触孔相连通。
优选的，上述方法中，在所述基底上形成层间介质之前，还包括：在所述基底上形成氮氧化硅层；
在对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀之后，还包括：对所述氮氧化硅层进行刻蚀，刻蚀后形成第三接触孔，所述第三接触孔与所述第二接触孔相连通。
优选的，上述方法中，对所述层间介质进行形成接触孔时的第一次刻蚀，具体包括：
设置预设时间；
在所述层间介质上形成具有接触孔图案的光刻胶层；
以所述具有接触孔图案的光刻胶层为掩膜对所述层间介质进行第一次刻蚀，且进行第一次刻蚀的时间为预设时间。
优选的，上述方法中，所述层间介质的厚度为7300Å。
优选的，上述方法中，所述预设厚度为3000Å。
优选的，上述方法中，所述保护层为氮化硅层。
优选的，上述方法中，所述层间介质包括：下层7000Å的二氧化硅和上层300Å的抗反射层。
优选的，上述方法中，所述基底为硅衬底。
优选的，上述方法中，在所述基底上形成层间介质采用化学气相沉积工艺。
优选的，上述方法中，对所述保护层进行刻蚀采用干法刻蚀工艺。
从上述技术方案可以看出，本发明所提供的接触孔的形成方法，在对层间介质进行第一次刻蚀后保留了预设厚度的层间介质，与此同时形成了第一接触孔；之后在所述层间介质上形成保护层，所述保护层覆盖所述第一接触孔的底部和侧壁；后续对所述保护层进行刻蚀时，覆盖第一接触孔侧壁的保护层将不会被刻蚀掉，即：在所述第一接触孔的侧壁上保留了部分保护层；最后对保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀，并形成了第二接触孔，在进行第二次刻蚀时，由于第一接触孔的侧壁上保留了部分保护层，因此，所述保留的部分保护层将保护其正下方的层间介质不被刻蚀掉，从而使最终形成的第二接触孔的宽度小于所述第一接触孔的宽度，当第二接触孔与第一接触孔连通形成一个接触孔时，该接触孔角部不会出现过刻蚀的现象，从而避免了在有源区和/或栅极侧部出现角部损失的现象，进而减小了器件的失效率。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中常见的接触孔的形成过程中出现角部损失现象的结构示意图；
图2为本发明实施例所提供的一种接触孔的形成方法的流程示意图；
图3~图8为本发明实施例所提供的接触孔形成过程中器件的剖面结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
参考图2，图2为本发明实施例所提供的一种接触孔的形成方法的流程示意图，该方法具体包括如下几个步骤：
步骤S1：提供基底，所述基底上具有有源区和栅极。
参考图3，图3中示出了基底100，本发明实施例中所述基底100为硅衬底，其他实施例中，所述基底100还可以为锗、磷化铟或砷化镓等半导体材料。所述基底100一般包括本体层和外延层，在半导体器件制造过程中，光刻、刻蚀或离子注入等工艺进行时的载体一般均为外延层，而本说明书将不再具体区分基底上的本体层和外延层，一律称在基底上或基底内进行各工艺步骤。
本步骤中所提供的基底100，其上具有栅极104及位于栅极104两侧的侧墙105；基底100内具有深阱区101，深阱区101内具有有源区，所述有源区包括源区102和漏区103，且源区102和漏区103分别位于栅极104两侧。所述基底100内还具有用来隔离有源器件的浅沟槽介质层106。
步骤S2：在所述基底上形成层间介质。
参考图4，采用化学气相沉积方法在基底100上形成层间介质107，本实施例中所述层间介质107包括下层的二氧化硅和上层很薄的抗反射层（约为300Å），所述层间介质107的厚度为7300Å。
具体实施过程中，首先在基底100上形成二氧化硅，之后在所述二氧化硅上形成抗反射层，所述抗反射层可以为氮氧化硅层，所述抗反射层可在下述步骤S6中充当硬掩膜层。图4中没有具体示出二氧化硅和氮氧化硅层，因此，在下面的各步骤中将统称为层间介质107。
步骤S3：对所述层间介质进行形成接触孔时的第一次刻蚀，第一次刻蚀后保留预设厚度的层间介质，且第一次刻蚀后形成了第一接触孔。
本发明实施例中以形成连接漏区的接触孔为例进行说明。
该步骤可包括如下几个步骤：
步骤S31：设置预设时间。
本步骤中所述预设时间指的是：在对层间介质进行刻蚀时，刻蚀进行的时间，该时间可预先在刻蚀机上设定。本步骤中设置所述预设时间为50s，其他实施例中根据工艺要求的不同可设置不同的预设时间。但该预设时间小于层间介质被完全刻蚀掉所需时间。
步骤S32：在所述层间介质上形成具有漏区接触孔图案的光刻胶层。
首先在所述层间介质上旋涂光刻胶层，然后采用具有漏区接触孔图案的掩膜版对所述光刻胶层进行曝光，曝光之后显影，在所述层间介质上形成了具有漏区接触孔图案的光刻胶层。
步骤S33：以所述具有漏区接触孔图案的光刻胶层为掩膜对所述层间介质进行第一次刻蚀，且进行第一次刻蚀的时间为预设时间。
参考图5，以所述具有漏区接触孔图案的光刻胶层（图中未示出）为掩膜对所述层间介质107进行第一次刻蚀，且进行第一次刻蚀的时间为步骤S31中所设置的预设时间。由于所述预设时间小于层间介质107被完全刻蚀掉所需时间，因此，第一次刻蚀后保留了一定厚度的层间介质107（第一刻蚀完成后，已经刻蚀掉了层间介质107上的抗反射层及部分二氧化硅层，所保留的一定厚度的层间介质107为二氧化硅），图中示出了所保留下来的层间介质107的厚度d。对层间介质107进行第一次刻蚀后所形成的接触孔在本发明实施例中称为第一接触孔108，本实施例中所述第一接触孔108的宽度a为光刻胶层上漏区接触孔图案的宽度。
需要说明的是，根据层间介质107的总厚度、所述预设时间及第一次刻蚀过程中的刻蚀速率，即可计算出第一次刻蚀后所保留的层间介质107的厚度d，因此，该厚度d也可称为预设厚度。
本实施例中对层间介质107进行第一次刻蚀采用的是各向异性的干法刻蚀工艺，下面所描述的第二次刻蚀也是干法刻蚀。
步骤S4：在所述层间介质上形成保护层，所述保护层覆盖所述第一接触孔的底部和侧壁。
参考图6，采用化学气相沉积方法在所述层间介质107上形成保护层109，所述保护层109覆盖所述第一接触孔108的底部和侧壁。本实施例中所述保护层109为氮化硅层，其他实施例中所述保护层109还可以为别的材料，例如：多晶硅。本实施例中所述保护层109的厚度为300Å。
步骤S5：对所述保护层进行刻蚀。
参考图7，采用干法刻蚀工艺对层间介质107上的保护层进行刻蚀，由于干法刻蚀过程属于各向异性刻蚀，故覆盖第一接触孔108侧壁的保护层110不能被刻蚀掉（依据spacer原理），因此，对所述保护层进行刻蚀的结果为：保留了第一接触孔108侧壁上的保护层110，其余部位的保护层均被刻蚀掉了。
步骤S6：对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀，第二次刻蚀后形成了第二接触孔，所述第二接触孔与所述第一接触孔相连通。
该步骤中仍以形成连接漏区的接触孔为例进行说明。
参考图8，以层间介质107中的抗反射层为硬掩膜，对所述保留的预设厚度为d的层间介质107进行第二次刻蚀。对所述保留的预设厚度为d的层间介质107进行第二次刻蚀后，形成了第二接触孔111，且所述第二接触孔111与第一接触孔108相连通。
在对所述保留的预设厚度为d的层间介质107进行第二次刻蚀时，由于第一接触孔108侧壁上具有保护层110，所述保护层110的存在可保护其正下方的层间介质112免受刻蚀，因此，第二次刻蚀后所形成的第二接触孔111的宽度b小于所述第一接触孔108的宽度a，且两者之差为第一接触孔108侧壁上保护层110厚度的2倍（假设第一接触孔108两侧侧壁上的保护层110厚度相同）。
通过控制步骤S4中所形成的保护层的厚度，可控制第一接触孔108侧壁上保护层110的厚度，进而可控制第二接触孔111的宽度b。
所述第二接触孔111与第一接触孔108相连通共同构成了与漏区103相连的接触孔，由于与漏区103直接相连的为第二接触孔111，因此，所述第二接触孔111的宽度b为与漏区103相连的接触孔的尺寸（CD），故采用本发明所提供的方法，在形成与漏区103相连的接触孔时，能够有效地减小所述接触孔的尺寸。
而且，由于在对所述保留的预设厚度为d的层间介质107进行第二次刻蚀时，刻蚀工艺中所用的等离子体不会刻蚀对应第一接触孔108侧壁上保护层110正下方的层间介质112，因此，最终形成与漏区103相连的接触孔时，也就不会出现角部损失现象。即使刻蚀时间再稍长些，过刻蚀的区域也位于漏区103内，而不会位于浅沟槽介质层106内，从而避免了漏区103与基底100的短接，避免了器件失效现象的发生。
上面详细描述了与漏区相连的接触孔的形成过程，对于与源区相连的接触孔和与栅极相连的接触孔的形成过程与此类似，不再进行描述。
由上可知，本发明所提供的接触孔的形成方法，对层间介质进行形成接触孔的刻蚀分两次进行（分别简称第一次刻蚀和第二次刻蚀），且在两次刻蚀过程中在层间介质上形成了保护层，并对所述保护层进行了刻蚀，对所述保护层进行刻蚀的结果是：在第一次刻蚀后形成的第一接触孔的侧壁上保留了部分保护层（spacer原理），进而在后续进行第二次刻蚀时，所述保护层可保护其正下方的层间介质免受刻蚀，因此，第二次刻蚀后所形成的第二接触孔的宽度小于第一接触孔的宽度，这一方面减小了接触孔的尺寸，另一方面可避免在有源区或栅极的两侧形成角部损失。对于形成与有源区相连的接触孔来说，可避免在浅沟槽介质层内形成角部损失，进而可避免源/漏与基底的短接，减小了器件失效的风险。
实施例二
本实施例在实施例一的基础上又增加了两个步骤，分别如下：
在实施例一中步骤S2之前，可增加：在所述基底上形成氮氧化硅层；在实施例一中步骤S6之后，可增加：对所述氮氧化硅层进行刻蚀，刻蚀后形成第三接触孔，所述第三接触孔与所述第二接触孔相连通。
本实施例中在基底上形成层间介质之前，首先在基底上形成了氮氧化硅层，然后在对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀后，对所述氮氧化硅层进行刻蚀，刻蚀结果是形成了第三接触孔，所述第三接触孔与所述第二接触孔相连通，从而由所述第一接触孔、所述第二接触孔和第三接触孔共同构成了连接有源区或栅极的接触孔。
本实施例中在形成层间介质前首先形成了氮氧化硅层，该氮氧化硅层可在对层间介质进行第二次刻蚀的过程中作为停止层，从而可避免因层间介质不均匀而产生的角部损失现象，因此，能够更好地避免接触孔形成过程中角部损失现象的发生，减小器件的失效率。
本发明实施例采用递进的方式对接触孔的形成方法进行描述，每个实施例均有其侧重点，相关、相似之处可相互参考。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种接触孔的形成方法，其特征在于，包括：
    提供基底，所述基底上具有有源区和栅极；
    在所述基底上形成层间介质；
    对所述层间介质进行形成接触孔时的第一次刻蚀，第一次刻蚀后保留预设厚度的层间介质，且第一次刻蚀后形成了第一接触孔；
    在所述层间介质上形成保护层，所述保护层覆盖所述第一接触孔的底部和侧壁；
    对所述保护层进行刻蚀；
    对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀，第二次刻蚀后形成了第二接触孔，所述第二接触孔与所述第一接触孔相连通。
  2. 根据权利要求1所述的方法，其特征在于，在所述基底上形成层间介质之前，还包括：在所述基底上形成氮氧化硅层；
    在对所述保留的预设厚度的层间介质进行形成接触孔时的第二次刻蚀之后，还包括：对所述氮氧化硅层进行刻蚀，刻蚀后形成第三接触孔，所述第三接触孔与所述第二接触孔相连通。
  3. 根据权利要求2所述的方法，其特征在于，对所述层间介质进行形成接触孔时的第一次刻蚀，具体包括：
    设置预设时间；
    在所述层间介质上形成具有接触孔图案的光刻胶层；
    以所述具有接触孔图案的光刻胶层为掩膜对所述层间介质进行第一次刻蚀，且进行第一次刻蚀的时间为预设时间。
  4. 根据权利要求1所述的方法，其特征在于，所述层间介质的厚度为7300Å。
  5. 根据权利要求1所述的方法，其特征在于，所述预设厚度为3000Å。
  6. 根据权利要求1所述的方法，其特征在于，所述保护层为氮化硅层。
  7. 根据权利要求4所述的方法，其特征在于，所述层间介质包括：
    下层7000Å的二氧化硅和上层300Å的抗反射层。
  8. 根据权利要求1~7任一项所述的方法，其特征在于，所述基底为硅衬底。
  9. 根据权利要求1~7任一项所述的方法，其特征在于，在所述基底上形成层间介质采用化学气相沉积工艺。
  10. 根据权利要求1~7任一项所述的方法，其特征在于，对所述保护层进行刻蚀采用干法刻蚀工艺。
PCT/CN2012/083049 2011-10-31 2012-10-17 接触孔的形成方法 Ceased WO2013064014A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2011103378634A CN103094185A (zh) 2011-10-31 2011-10-31 接触孔的形成方法
CN201110337863.4 2011-10-31

Publications (1)

Publication Number Publication Date
WO2013064014A1 true WO2013064014A1 (zh) 2013-05-10

Family

ID=48191298

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/083049 Ceased WO2013064014A1 (zh) 2011-10-31 2012-10-17 接触孔的形成方法

Country Status (2)

Country Link
CN (1) CN103094185A (zh)
WO (1) WO2013064014A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115410991A (zh) * 2022-09-16 2022-11-29 上海华力微电子有限公司 一种接触孔形成方法
CN115588613A (zh) * 2022-04-29 2023-01-10 锐立平芯微电子(广州)有限责任公司 一种体硅金属栅极制作工艺优化方法
CN115831764A (zh) * 2022-12-15 2023-03-21 成都海光集成电路设计有限公司 一种基板中过孔的制作方法、基板及芯片

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107482010B (zh) * 2016-06-07 2020-11-03 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法、电子装置
CN108400127A (zh) * 2018-03-07 2018-08-14 云谷（固安）科技有限公司 制造电容器的方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475811B1 (en) * 2001-04-27 2002-11-05 Advanced Micro Devices, Inc. System for and method of using bacteria to aid in contact hole printing
US6803307B1 (en) * 2003-06-27 2004-10-12 Macronix International Co., Ltd. Method of avoiding enlargement of top critical dimension in contact holes using spacers
CN101202245A (zh) * 2006-12-15 2008-06-18 中芯国际集成电路制造(上海)有限公司 用于蚀刻的系统和方法
CN101295643A (zh) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 通孔刻蚀方法及通孔掩膜
CN101355051A (zh) * 2007-07-25 2009-01-28 东部高科股份有限公司 具有铜金属布线的半导体器件及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6071812A (en) * 1998-10-19 2000-06-06 Taiwan Semiconductor Manufacturing Company Method of forming a modified metal contact opening to decrease its aspect ratio for deep sub-micron processes
US7572694B2 (en) * 2005-12-28 2009-08-11 Dongbu Hitek Co., Ltd. Method of manufacturing a semiconductor device
CN101764081B (zh) * 2008-12-25 2011-12-07 中芯国际集成电路制造(上海)有限公司 连接孔的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6475811B1 (en) * 2001-04-27 2002-11-05 Advanced Micro Devices, Inc. System for and method of using bacteria to aid in contact hole printing
US6803307B1 (en) * 2003-06-27 2004-10-12 Macronix International Co., Ltd. Method of avoiding enlargement of top critical dimension in contact holes using spacers
CN101202245A (zh) * 2006-12-15 2008-06-18 中芯国际集成电路制造(上海)有限公司 用于蚀刻的系统和方法
CN101295643A (zh) * 2007-04-24 2008-10-29 中芯国际集成电路制造(上海)有限公司 通孔刻蚀方法及通孔掩膜
CN101355051A (zh) * 2007-07-25 2009-01-28 东部高科股份有限公司 具有铜金属布线的半导体器件及其形成方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115588613A (zh) * 2022-04-29 2023-01-10 锐立平芯微电子(广州)有限责任公司 一种体硅金属栅极制作工艺优化方法
CN115588613B (zh) * 2022-04-29 2026-01-13 锐立平芯微电子(广州)有限责任公司 一种体硅金属栅极制作工艺优化方法
CN115410991A (zh) * 2022-09-16 2022-11-29 上海华力微电子有限公司 一种接触孔形成方法
CN115831764A (zh) * 2022-12-15 2023-03-21 成都海光集成电路设计有限公司 一种基板中过孔的制作方法、基板及芯片

Also Published As

Publication number Publication date
CN103094185A (zh) 2013-05-08

Similar Documents

Publication Publication Date Title
CN104752185B (zh) 金属栅极的形成方法
WO2013064014A1 (zh) 接触孔的形成方法
TW466683B (en) Semiconductor device manufacturing method
WO2017206812A1 (zh) 沟槽栅极引出结构及其制造方法
KR100400308B1 (ko) 반도체소자의 보더리스 콘택 형성방법
US20040063306A1 (en) Fabrication method of semiconductor device
WO2013020470A1 (zh) 半导体器件及其制造方法
CN109962035A (zh) 半导体结构和图像传感器的形成方法
CN111430241B (zh) 半导体结构及其形成方法
KR101213726B1 (ko) 노광 마스크 및 이를 이용한 반도체 소자의 제조 방법
KR100668831B1 (ko) 반도체 소자의 랜딩 플러그 폴리 형성방법
TW202147514A (zh) 導線結構及其製造方法
TWI882835B (zh) 形成晶圓結構的方法及由其形成的晶圓結構
KR100317327B1 (ko) 반도체 소자의 제조방법
KR101183640B1 (ko) 반도체 소자의 콘택 플러그 형성방법
CN115602633B (zh) 一种提升效率的光阻回刻方法及装置
CN114975285B (zh) 一种位线接触孔和dram的制造方法
KR20000045437A (ko) 반도체소자의 자기정렬적인 콘택 형성방법
KR101019698B1 (ko) 반도체 소자의 비트라인 형성방법
KR100808369B1 (ko) 반도체 소자의 제조방법
KR0147196B1 (ko) 반도체 장치의 금속배선 콘택부 형성방법
KR100604540B1 (ko) 스토퍼를 사용한 다마신 공정 개선 방법
KR100531551B1 (ko) 반도체소자 및 그의 제조방법
WO2025160947A1 (zh) 芯片及其制作方法、电子设备
JP2003007819A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12846006

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12846006

Country of ref document: EP

Kind code of ref document: A1