WO2013024584A1 - インターリービング方法、及びデインターリービング方法 - Google Patents
インターリービング方法、及びデインターリービング方法 Download PDFInfo
- Publication number
- WO2013024584A1 WO2013024584A1 PCT/JP2012/005085 JP2012005085W WO2013024584A1 WO 2013024584 A1 WO2013024584 A1 WO 2013024584A1 JP 2012005085 W JP2012005085 W JP 2012005085W WO 2013024584 A1 WO2013024584 A1 WO 2013024584A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bits
- cyclic
- block
- qam constellation
- section
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/007—Unequal error protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
- H04L1/0058—Block-coded modulation
Definitions
- the present invention relates to the field of digital communications, and more particularly, to a quasi-cyclic low-density parity check (QC-LDPC) code, quadrature amplitude modulation (QAM), for multiple transmit antennas.
- QC-LDPC quasi-cyclic low-density parity check
- QAM quadrature amplitude modulation
- an interleaving method used in a bit-interleaved coding and modulation (BICM) system using spatial multiplexing, an interleaver, a transmitter including the same, and a corresponding de-interleaving method The present invention relates to an interleaver and a receiver including the same.
- Non-Patent Document 1 a communication system including a transmitter including a bit-interleaved coding and modulation (BICM) encoder has been proposed (see, for example, Non-Patent Document 1).
- BICM bit-interleaved coding and modulation
- the BICM encoder performs, for example, the following steps:
- bits of the code word obtained as a result of encoding are subjected to bit interleaving including parity interleaving and column-row interleaving.
- the demultiplexing includes processing equivalent to permutation of the columns of the interleaver matrix in column-row interleaving when the modulation scheme is 16 QAM, 64 QAM, 256 QAM or the like.
- the invention makes it possible to properly map the bits of a codeword based on a pseudo-cyclic low density parity check code into constellation words of a spatial multiplexing block to realize improved reception performance of the communication system.
- the interleaving method of the present invention is A plurality of codewords of the pseudo cyclic low density parity check code, implemented in a transmitter in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas;
- An interleaving method for reordering bits of a codeword to generate a plurality of constellation words constituting a spatial multiplexing block of The codeword consists of N cyclic blocks, each consisting of Q bits,
- the spatial multiplexing block consists of B bits, and the spatial multiplexing block consists of T constellation words
- the interleaving method is A first permutation step for rearranging the N cyclic blocks;
- the bit of the codeword based on the pseudo-cyclic low density parity check code is appropriately mapped to the constellation word, and the reception performance of the communication system can be improved.
- FIG. 2 is a block diagram of a typical transmitter having multiple antennas and performing bit interleaved coding modulation with spatial multiplexing.
- FIG. 2 is a block diagram of the bit-interleaved coded modulation encoder for space multiplexing of FIG. 1;
- simulation cyclic low density parity check code which is cyclic coefficient Q 8.
- FIG. 7 is a diagram showing the information part of the parity check matrix, and showing the position of “1” only for the first bit in each cyclic block corresponding to FIG. 4;
- FIG. 5 shows a complete parity check matrix corresponding to FIG.
- FIG. 7 shows a pseudo cyclic structure of the parity check matrix of FIG. 6; The figure which shows the definition of the LDPC code of 16200 bit codeword length by code rate 5/15 (1/3). The figure which shows the definition of the LDPC code of 16200 bit codeword length by code rate 6/15 (2/5). The figure which shows the definition of the LDPC code of code word length 16200 bits by coding rate 7/15. The figure which shows the definition of the LDPC code of code word length 16200 bits by coding rate 8/15. The figure which shows the definition of the LDPC code of 16200 bit codeword length by coding rate 9/15 (3/5).
- QPSK is a block diagram of a QAM mapper for 16-QAM
- (c) is a block diagram of a QAM mapper for 64-QAM. Diagram showing different robust levels in 8-PAM symbols with gray coding.
- FIG. 20 is a block diagram of the BICM encoder of FIG.
- FIG. 23 is a view for explaining an operation example of a section permutation unit which performs the bit rearrangement shown in FIG. 22A.
- FIG. 23 is a view for explaining an operation example of a section permutation unit which performs bit rearrangement shown in FIG. 22B.
- FIG. 23 is a view for explaining an operation example of a section permutation unit which performs bit rearrangement shown in FIG. 22C.
- the figure which shows one structural example of the FIG. 20 bit interleaving coding modulation encoder in the case of B 8.
- the figure which shows one structural example of the bit interleaving coding modulation encoder of FIG. 20 in the case of B 10.
- FIG. 21 is a block diagram showing another configuration example of the bit interleaver of FIG. 20.
- FIG. 16 shows Monte-Calro (Monte-Carlo) simulation results using coding rate 8/15, blind mapping for channel slot bit number 8 and iterative demapping.
- the block diagram of the receiver in the communication system which concerns on embodiment of this invention.
- FIG. 1 is a block diagram showing the configuration of a general transmitter 1000.
- the transmitter 1000 includes an input processing unit 1100, a bit-interleaved coding and modulation (BICM) encoder 1200, modulators 1300-1 to 1300-2, and up-converters 1400-1 to 1400-2. , RF (radio frequency) power amplifiers 1500-1 to 1500-2, and transmit antennas 1600-1 to 1600-2.
- BICM bit-interleaved coding and modulation
- the input processing unit 1100 converts an input bit stream relating to a broadcast service into blocks of a predetermined length.
- the block is called a baseband frame.
- the BICM encoder 1200 transforms the baseband frame into multiple complex valued data streams.
- the number of data streams is equal to the number of transmit antennas.
- Each data stream is further processed by a modulation chain including at least modulators 1300-1 to 1300-2, upconverters 1400-1 to 1400-2 and RF power amplifiers 1500-1 to 1500-2, and transmit antenna 1600-1 It is output from ⁇ 1600-2.
- Each modulator 1300-1 to 1300-2 performs, for example, Orthogonal Frequency Division Multiplexing (OFDM) modulation on the input from the BICM encoder 1200, and usually performs time interleaving and frequency interleave for diversity increase. Do the reeving.
- OFDM Orthogonal Frequency Division Multiplexing
- Each up-converter 1400-1 to 1400-2 frequency-converts the input from each modulator 1300-1 to 1300-2 from digital baseband to analog RF.
- Each RF power amplifier 1500-1 to 1500-2 performs power amplification on the input from each up converter 1400-1 to 1400-2.
- FIG. 2 is a block diagram of the BICM encoder 1200 for spatial multiplexing of FIG.
- the BICM encoder 1200 includes an LDPC encoder 1210, a bit interleaver 1220, a demultiplexer 1230, QAM mappers 1240-1 and 1240-2, and a spatial-multiplexing (SM) encoder 1250.
- LDPC encoder 1210 bit interleaver 1220
- demultiplexer 1230 demultiplexer 1230
- QAM mappers 1240-1 and 1240-2 QAM mappers 1240-1 and 1240-2
- SM spatial-multiplexing
- the LDPC encoder 1210 encodes an input block, that is, a baseband frame into a codeword using an LDPC code, and outputs the encoded word to the bit interleaver 1220.
- the bit interleaver 1220 performs bit interleaving for rearranging bits of each LDPC code and outputs the result to the demultiplexer 1230.
- the demultiplexer 1230 demultiplexes the bit-interleaved codeword into two bit streams and outputs the demultiplexed codewords to the QAM mappers 1240-1 and 1240-2.
- Each QAM mapper 1240-1 to 1240-2 maps each of a plurality of constellation words constituting each bit stream to complex symbols, and outputs the complex symbols to a freely selectable SM encoder 1250.
- Each of the constellation words indicates one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word. Note that B 1 and B 2 in FIG. 2 represent the number of bits of the constellation word.
- the SM encoder 1250 normally multiplies an orthogonal square matrix by a vector consisting of two input complex symbols.
- the LDPC encoder 1210 encodes the baseband frame into a codeword using a special LDPC code.
- the present invention is particularly designed for LDPC block codes with a step-like parity structure, as employed in the DVB-S2 standard, DVB-T2 standard, DVB-C2 standard.
- DVB-S2 is an abbreviation of Digital Video Broadcasting-Second Generation Satellite
- DVB-T2 is an abbreviation of Digital Video Broadcasting-Second Generation Terrestrial
- DVB-C2 is an abbreviation of Digital Video Broadcasting-Second Generation Cable.
- An LDPC block code is a linear error correction code completely defined by a parity check matrix (PCM), and the PCM is a codeword bit (also referred to as a bit node or variable node) and a parity check (parity check). It is a binary sparse matrix that represents a connection with a check node.
- the PCM columns and rows correspond to variable nodes and check nodes, respectively.
- the connection between the variable node and the check node is indicated by an element "1" in the PCM.
- the check node is denoted as CN.
- LDPC block code There is a type of LDPC block code called a quasi-cyclic low-density parity check (QC LDPC) code.
- QC LDPC codes have a structure that is particularly suitable for hardware implementation. In fact, QC LDPC codes are used in most of today's standards.
- the PCM of the QC LDPC code has a special structure having a plurality of cyclic matrices.
- a circulant matrix is a square matrix in which each row is in the form of one cyclic shift of elements in the row immediately before it, and one, two, or more folded diagonal columns May exist.
- each circulant matrix is Q ⁇ Q.
- Q is referred to as a cyclic factor of the QC LDPC code.
- Such a pseudo-cyclic structure allows Q check nodes to be processed in parallel, and QC LDPC codes are clearly advantageous codes for efficient hardware implementation.
- the PCM of the QC LDPC code is Q ⁇ M rows and Q ⁇ N columns, and the codeword consists of N blocks of Q bits each.
- a block of Q bits is referred to herein as a pseudo cyclic block or simply as a cyclic block.
- the pseudo cyclic block (cyclic block) is abbreviated and expressed as QB.
- one of the smallest squares represents one element of the PCM, of which black square elements are “1”, and other elements are “0”. It is.
- the QC LDPC code corresponding to the PCM in FIG. 3 belongs to a special kind of QC LDPC code called repeat-accumulate quasi-cyclic low-density parity check (RA QC LDPC) code.
- RA QC LDPC codes are known for their ease of coding and are adopted in a number of standards (eg, second generation DVB standards such as DVB-S2 standard, DVB-T2 standard, DVB-C2 standard) There is.
- the left side of the PCM is the information part.
- the right side of the PCM is a parity portion, and the arrangement of the "1" elements in that portion has a step structure.
- DVB is an abbreviation of Digital Video Broadcasting.
- Each QC LDPC code is completely defined by a table including, for the first bit of each cyclic block in the information part, an index (index starts from zero) of each check node to which the first bit is connected. These indexes are described in the DVB-S2 standard as "addresses of the parity bit accumulators" (addresses of parity bit accumulators).
- FIG. 4 a table for the QC LDPC code of FIG. 3 is shown in FIG.
- the value described in the QB column in FIG. 4 is the index of the cyclic block, and is only the information portion of the parity check matrix.
- a check node index for the first bit in the cyclic block QB 1 is "13", is "24", "27", "31”, "47".
- FIG. 5 shows the information part of the parity check matrix, and shows the position of “1” only for the first bit in each cyclic block corresponding to FIG.
- the matrix element corresponding to the check nodes CN 13, CN 24, CN 27 , CN 31, CN 47 becomes "1".
- the complete parity check matrix including the input and step-wise parity parts for all the information bits, corresponding to FIG. 4, is the parity check matrix shown in FIG.
- the index of the check node is calculated by Equation 1 with respect to the other information bits (the information bits excluding the first bit in the cyclic block).
- q is the bit index within a cyclic block (0, ⁇ , Q-1 )
- i q is the index of the check node index check nodes for the first q bits
- i 0 is for the first bit in FIG. 4
- M Is the number of cyclic blocks in the parity part (6 in the example of FIG. 6)
- Q ⁇ M is the number of parity bits (48 in the example of FIG. 6)
- % is a modulo operator.
- i is the index of the check node before applying row permutation (index starts from zero)
- j is the index of the check node after applying row permutation (index starts from zero)
- M is cyclic in the parity part
- Q is the number of bits constituting a cyclic block
- % is a modulo operator
- floor (i / M) is a function that returns the largest integer value of i / M or less.
- Row permutation does not apply to bits (do not reorder columns), so it does not change the definition of the LDPC code.
- the parity part does not have a pseudo cyclic structure.
- special permutation of (Eq. 3) is applied to only the parity bits.
- the permutation calculated by (Equation 3) is referred to as parity permutation or parity interleaving throughout the present specification.
- i is an index of parity bits before applying parity permutation (index starts from zero)
- j is an index of parity bits after applying parity permutation (index starts from zero)
- M is cyclic in the parity part
- Q is the number of bits of the cyclic block
- % is the modulo operator
- floor (i / Q) is a function that returns the largest integer value of i / Q or less.
- parity permutation of (Equation 3) changes the definition of the QC LDPC code. Furthermore, hereinafter, parity permutation is regarded as part of the LDPC encoding process.
- next-generation DVB-NGH seven QC LDPC codes defined in the next-generation DVB-NGH standard will be described.
- the DVB-NGH standard is currently under development and is a standard for terrestrial reception of digital video services in portable devices.
- NGH is an abbreviation of next-generation handheld.
- the LDPC encoding process performed by the LDPC encoder 1210 will be specifically described according to the description method of the DVB-S2 standard.
- the LDPC encoder systematically encodes an information block (input of an LDPC encoder) i of size K ldpc into an LDPC code c of size N ldpc as in ( Equation 4).
- the parameters (N ldpc , K ldpc ) of the QC LDPC code are ( 16200 , 5400 ).
- the role of the LDPC encoder 1210 is to determine N ldpc -K ldpc parity bits for each block of K ldpc information bits, and the procedure is as follows.
- the first information bit i 0 is accumulated at each parity bit accumulator address (each check node index) specified in the first line of FIG. Specifically, the calculation of (Equation 6) is performed.
- the address of the parity bit accumulator is given in the second line of FIG.
- x is the address of the parity bit accumulator corresponding to the 360th information bit i 360 , that is, the address of the parity bit accumulator described in the second line of FIG.
- the final parity bits are obtained as follows.
- the parameters (N ldpc , K ldpc ) of the QC LDPC code are ( 16200
- the above description of the QC LDPC code follows the notation of the DVB-S2 standard, according to the notation of the DVB-T2 standard or the DVB-NGH standard, for example, the above q becomes Q ldpc .
- the LDPC encoder 1120 Perform the operation shown in).
- K ldpc is the number of information bits of the QC LDPC code word, and the information bits are not interleaved.
- the cyclic coefficient Q of the parity check matrix is 360.
- This block is a cyclic block of QC LDPC codewords.
- indices “1”, “2”,... are assigned to the cyclic blocks in order from the cyclic block including u 0 .
- the invention deals in particular with a spatial multiplexing system with two transmit antennas.
- two complex QAM symbols denoted s 1 and s 2 in FIG. 2
- s 1 and s 2 are transmitted from the same channel slot.
- a channel slot is called an OFDM cell and is defined as one subcarrier in an OFDM symbol.
- the two complex QAM symbols form a spatial-multiplexing pair (SM pair).
- SM pair spatial-multiplexing pair
- the two complex QAM symbols in the SM pair are either uncoded or jointly coded by applying an additional SM-coding (spatial-multiplexing) step by the SM encoder 1250 shown in FIG. Jointly encoded and transmitted from the transmit antenna.
- SM encoder 1250 shown in Figure 2 two complex QAM symbols s 1, s 2, binds encoded to generate two complex symbols x 1, x 2.
- SM coding is usually performed by multiplying a vector [s 1 s 2 ] by a 2 ⁇ 2 complex generator matrix G, as shown in equation (9).
- the invention deals particularly with the case where both of the complex QAM symbols (s1, s2) forming an SM pair are mapped to a quadrature QAM (quadrature amplitude modulation) constellation.
- the sizes of the two square QAM constellations do not necessarily have to be the same size.
- the QAM symbol is obtained by modulating the real component and the imaginary component independently of each other using PAM (pulse amplitude modulation).
- PAM pulse amplitude modulation
- FIGS. 15 (a), (b) and (c) are diagrams showing three types of square QAM constellations related to the present invention, namely, a 4-QAM constellation, a 16-QAM constellation and a 64-QAM constellation. It is.
- the real and imaginary components are each modulated using the same PAM.
- real and imaginary components are modulated using the same type of 2-PAM
- real and imaginary components each have the same 4-PAM Modulated using, in a 64-QAM constellation, real and imaginary components are each modulated using the same 8-PAM.
- gray coding as shown in FIGS. 15 (a), (b) and (c) is used for PAM mapping.
- Each QAM mapper has two independent PAM mappers, as shown in FIGS. 16 (a), (b) and (c), and the two independent PAM mappers in the QAM mapper encode the same number of bits .
- FIG. 16 (a) is a block diagram of a QAM mapper for a QPSK (4-QAM) constellation.
- the QAM mapper 1240A comprises two independent 2-PAM constellation PAM mappers 1241A, 1245A for the real and imaginary parts.
- the PAM mappers 1241A and 1245A each encode the same number of 1 bit.
- QAM mapper 1240A encodes 2 bits.
- FIG. 16 (b) is a block diagram of a QAM mapper for a 16-QAM constellation.
- the QAM mapper 1240B includes two independent 4-PAM constellation PAM mappers 1241B and 1245B for the real part and the imaginary part.
- the PAM mappers 1241B and 1245B each encode the same number of 2 bits.
- QAM mapper 1240B encodes 4 bits.
- FIG. 16 (c) is a block diagram of a QAM mapper for 64-QAM constellation.
- the QAM mapper 1240C includes two independent 8-PAM constellation PAM mappers 1241C and 1245C for the real part and the imaginary part.
- the PAM mappers 1241C and 1245C each encode the same number of 3 bits. In this way, QAM mapper 1240C encodes six bits.
- the robustness levels (reliability) of the bits encoded in the PAM symbol are different from each other.
- the robustness levels of the plurality of bits encoded in the PAM symbol are different from each other because the distances between two subsets defined by the bits (0 or 1) are different among the plurality of bits.
- the reliability of a bit is proportional to the average distance between the two subsets defined by that bit. In the example of FIG. 17, the bit b 1 robust level (reliability) is the lowest, the bit robust level (reliability) of b 2 is low in the second, robust level (confidence) of the bit b 3 is the highest.
- K sqrt (2) for QPSK (4-QAM) symbols
- K sqrt (10) for 16-QAM symbols
- K for 64-QAM symbols. It is sqrt (42).
- sqrt (x) is a function that returns the square root of x. Note that K multiplication processing for QAM symbols is performed by the QAM mapper.
- the number of bits encoded into two QAM symbols of the SM pair will be denoted as B 1 and B 2 respectively. Because the QAM constellation is a square constellation, B 1 and B 2 are even.
- a plurality of bits encoded in a QAM constellation are described as a constellation word, and a plurality of bits encoded in an SM pair are spatially multiplexed words (SM words) or spatially multiplexed blocks (spatial multiplexed blocks): Describe as SM block).
- a further aspect related to the present invention is that, since the square QAM symbol consists of two independent PAM symbols, the bits encoded in the QAM symbol are grouped into bit pairs of the same robust level.
- the spatial multiplexing profile of the DVB-NGH standard supports three SM configurations as shown in Table 1.
- the SM configuration is defined for a combination of QAM symbol sizes of the complex QAM symbols S 1 and S 2 .
- the number of bits in the channel slot (the number of bits in the SM block) is the sum of the number of bits in the QAM constellation used to generate the complex QAM symbols S 1 and S 2 (the number of bits in the constellation word constituting the SM block). Is the sum of For each of these three SM configurations, the DVB-NGH standard defines three transmit power ratios to be applied to the two transmit antennas: 1/1, 1/2, 1/4.
- the transmission power ratio is a ratio of transmission power of complex symbol x 1 to transmission power of complex symbol x 2 output from SM encoder 1250 (transmission power of complex symbol x 1 transmission power of complex symbol x 2 ) .
- the adjustment of the transmission power ratio is performed by the generation matrix G used by the SM encoder 1250.
- the generation matrix G used by the SM encoder 1250 is represented by a general formula of (Equation 10).
- the phase ⁇ (k) is a variable phase that changes for each channel slot.
- the parameters ⁇ , ⁇ and ⁇ may be changed in the final version of the standard. These specific values are not relevant to the present invention. Important is the QAM size and transmit power ratio at each transmit antenna for the three SM configurations.
- the bits of the LDPC code word have different significance, and the bits of the constellation have different robustness levels. Mapping the bits of the LDPC codeword directly to the bits of the constellation, ie without interleaving, does not lead to optimum performance. In order to avoid such performance degradation, the codeword bits need to be interleaved before being mapped to the constellation.
- bit interleaver 1220 and a demultiplexer 1230 are provided between the LDPC encoder 1210 and the QAM mappers 1240-1 and 1240-2, as shown in FIG.
- Careful design of the bit interleaver 1220 and the demultiplexer 1230 optimizes the association between the bits of the LDPC codeword and the bits encoded by the constellation, leading to improved reception performance.
- the performance is usually measured using bit error rate (BER) or block error rate (BLER) as a function of signal to noise ratio (SNR).
- BER bit error rate
- BLER block error rate
- the main reason for the different significance of the bits of the LDPC code word is that the number of parity checks related to all the bits is not always the same. As the number of parity checks (check nodes) related to code word bits (variable nodes) increases, the importance of code word bits in the iterative LDPC decoding process increases. A further reason is that connectivity to cycles in the Tanner graph representation of an LDPC code differs among variable nodes. For this reason, even if the number of parity checks to which the codeword bits are related is the same, the significance of the codeword bits may be different. These views are well known in the art. In principle, as the number of check nodes connected to a variable node increases, the importance of the variable node increases.
- the number of related parity checks is the same for all bits included in the Q-bit cyclic block, and the connectivity to cyclic in the Tanner graph is the same. The degree will be the same.
- the present invention provides a method of mapping QC LDPC codeword bits to two constellation words forming an SM block in order to improve reception performance.
- Embodiment (Part 1) provides an interleaving method of reordering bits of a code word (QC LDPC code word) based on QC LDPC code, which guarantees the following contents.
- the B t bits of each QAM symbol are exactly the B t / 2 cyclic block of the QC LDPC codeword such that each of the B t / 2 cyclic blocks is associated with the same robust level bit Is mapped to
- A2 T for example, 2) QAM symbols of a spatial multiplexing block (SM block) are mapped to different cyclic blocks of QC LDPC codewords.
- Each constellation word (bit number B t ) is formed from bits of different B t / 2 cyclic blocks of the QC LDPC code word, (B2) The same robustless level bit pairs of constellation words are made from the same cyclic block, (B3) Constellation words for different antennas are created from the bits of different cyclic blocks.
- the SM block is created from bits of B / 2 cyclic blocks.
- the SM block consists of B bits, and the SM block consists of T constellation words.
- T in B t is the index of the antenna (the index of the constellation word in the SM block).
- the transmission performance may be improved by matching the importance of the cyclic block with the robustness level of the constellation word bit to which the cyclic block is mapped.
- the bits of the most important cyclic block are mapped to the bits of the constellation word having the highest robustness level.
- the least significant cyclic bit is mapped to the least robust constellation word bit.
- mapping of the bits of the QC LDPC code word to the two constellation words constituting SM block is It becomes as follows.
- the invention is particularly optimized and works with respect to such mappings.
- the bits of the QC LDPC code are (C1) Each SM block is made up of (B 1 + B 2 ) / 2 bits of different cyclic blocks, (C2) Each bit pair of SM block, encoded at the same robust level of the same QAM symbol, is made from the same cyclic block, (C3) Constellation words for different transmit antennas are made from bits of different cyclic blocks, As such, they are mapped to two constellation words constituting an SM block.
- Q ⁇ (B / 2) bits of B / 2 cyclic blocks are mapped to Q / 2 space multiplexed blocks.
- B / 2 cyclic blocks are described as sections.
- Bits of groups belonging to the same SM block are surrounded by thick lines.
- the cyclic coefficient Q of the LDPC parameter is 8, and the number of cyclic blocks N for each codeword is 15.
- N is not a multiple of B / 2
- B 8 in the example above, the codeword can not be divided into sections each consisting of B / 2 cyclic blocks. Therefore, 1 is composed of a group of cyclic blocks of the number X (hereinafter referred to as “group of remainders”), which is the value of the remainder obtained by dividing N by B / 2, and B / 2 cyclic blocks. Divide into one or more sections.
- group of remainders is the mapping in the remainder group is not the subject of the present invention, and one option is to perform mapping continuously.
- the codeword can be divided into one or more sections, each consisting of B / 2 cyclic blocks.
- FIG. 19 is a block diagram showing the configuration of the transmitter 100 according to the embodiment of the present invention.
- the transmitter 100 includes an input processing unit 110, a bit-interleaved coding and modulation (BICM) encoder 120, (OFDM) modulators 130-1 to 130-4, and an up-converter 140-1 to 140-2, RF power amplifiers 150-1 to 150-2, and transmission antennas 160-1 to 160-2.
- BICM bit-interleaved coding and modulation
- OFDM orthogonal frequency division multiplexing and modulation
- FIG. 20 is a block diagram of the BICM encoder 120 for spatial multiplexing of FIG.
- the BICM encoder 120 includes an LDPC encoder 121, a bit interleaver 122, a demultiplexer 123, QAM mappers 124-1 to 124-4, and a spatial-multiplexing (SM) encoder 125.
- each constituent unit excluding the bit interleaver 122 and the demultiplexer 123 performs substantially the same processing as the corresponding constituent unit of the BICM encoder 1200 of FIG.
- the LDPC encoder 121 generates a codeword by encoding using a QC LDPC code, and outputs the codeword to the bit interleaver 122.
- the codeword generated by the LDPC encoder 121 consists of N cyclic blocks, and each cyclic block consists of Q bits.
- the bit interleaver 122 receives the codewords from the LDPC encoder 121 and reorders the bits of the received codewords.
- the demultiplexer 123 demultiplexes the bits of the rearranged codeword (demultiplexes into a plurality of bit strings and rearranges a plurality of bit strings), and maps the bits into constellation words.
- the QAM mappers 124-1 to 124-2 map constellation words supplied from the demultiplexer 123 to complex QAM symbols, and the SM encoder 125 calculates complex QAM symbols supplied from the QAM mappers 124-1 to 124-2. Perform coding for spatial multiplexing.
- bit interleaver 122 of FIG. 20 will be described with reference to FIG.
- FIG. 21 is a block diagram showing one configuration example of the bit interleaver 122 of FIG.
- the N cyclic blocks are one or more sections of B / 2 cyclic blocks and the number of remainders obtained by dividing N by B / 2. It is divided into groups (remaining groups) consisting of X cyclic blocks. If N is a multiple of B / 2, there are no remaining groups.
- the number is five.
- the bit interleaver 122 whose configuration example is shown in FIG. 21 comprises section permutation units 122-1, 122-2, 122-3,... Note that if N is not a multiple of B / 2, there will be a cyclic block that does not belong to any section, but bits will not be rearranged for cyclic blocks that do not belong to any section. The bits may be rearranged according to any permutation rule.
- Each section permutation unit 122-1, 122-2, 122-3,... May operate independently of the other section permutation units. Note that it is not necessary to provide one section permutation unit for each section, and a smaller number of section permutation units may be used in time division than the number of sections.
- FIG. 23A and FIGS. 23B to 23C described later the order of writing the bits is indicated by a dotted arrow, and the order of reading the bits is indicated by a solid arrow.
- the section permutation unit described with reference to FIGS. 22A to 22C and 23A to 23C can be generalized as follows.
- Section permutation unit receives as input cyclic bit QB / 2 ⁇ i + 1 to QBB / 2 ⁇ i + B / 2 bits, and SM block SMB Q / 2 ⁇ i + 1 to SMB Q / 2 ⁇ Output i + Q / 2 bits.
- the section permutation unit writes a bit in the row direction of the Q column B / 2 row interleaver matrix and performs processing equivalent to column-row interleaving in which the bit is read in the column direction.
- Q is a cyclic coefficient
- B is the number of bits of the SM block.
- the number of transmission antennas (the number of constellation words per SM block) is 2.
- the QC LDPC codeword generated by the not-shown LDPC encoder (see FIG. 20) in the BICM encoder 120A is supplied to the bit interleaver 122A provided with the section permutation unit described with reference to FIGS. 22A and 23A. .
- the bits of the QC LDPC codeword are reordered by the bit interleaver 122A, and the reordered codeword is provided to the demultiplexer 123A.
- the demultiplexer 123A rearranges the bits y 1 to y 6 into the bits y 1 , y 4 , y 2 , y 3 , y 5 and y 6 and outputs them.
- the 4-QAM mapper 124A-1 maps the constellation words C A (b 1, Re , b 1, Im ) to complex symbols (Re, Im) by means of two 2-PAM mappers.
- 16-QAM mapper 124A-2 are constellation word C B by two 4-PAM mapper (b 1, Re, b 2 , Re, b 1, Im, b 2, Im) complex symbols (Re, Im) to map.
- the SM encoder 125A performs coding to spatially multiplex the complex symbols s 1 and s 2 in order to generate transmission signals x 1 and x 2 .
- the QC LDPC codeword generated by the not-shown LDPC encoder (see FIG. 20) in the BICM encoder 120B is supplied to the bit interleaver 122B provided with the section permutation unit described with reference to FIGS. 22B and 23B. .
- the bits of the QC LDPC codeword are reordered by the bit interleaver 122B and the reordered codeword is provided to the demultiplexer 123B.
- the demultiplexer 123B in the example of FIG. 24B and outputs the rearranged bit y 1 ⁇ y 8 bit y 1, y 2, y 5 , y 6, y 3, y 4, y 7, y 8.
- bit (y 1, y 2, y 5, y 6) is a constellation word C A (b 1, Re, b 2, Re, b 1, Im, b 2, Im)
- bit ( y 3 , y 4 , y 7 , y 8 ) are mapped to constellation words C B (b 1, Re , b 2, Re , b 1, Im , b 2, Im ).
- the 16-QAM mappers 124B-1 and 124B-2 are configured to generate constellation words C A and C B (b 1, Re , b 2, Re , b 1, Im , b 2, Im ) respectively by two 4-PAM mappers. ) Is mapped to complex symbols (Re, Im).
- the SM encoder 125 B performs coding to spatially multiplex the complex symbols s 1 and s 2 in order to generate transmission signals x 1 and x 2 .
- the QC LDPC codeword generated by the not-shown LDPC encoder (see FIG. 20) in the BICM encoder 120C is supplied to the bit interleaver 122C provided with the section permutator described with reference to FIGS. 22C and 23C.
- the bits of the QC LDPC codeword are reordered by the bit interleaver 122C, and the reordered codeword is provided to the demultiplexer 123C.
- Demultiplexer 123C in the example of FIG. 13C arranges the bit y 1 ⁇ y 10 bits y 1, y 2, y 6 , y 7, y 3, y 4, y 5, y 8, y 9, y 10 Change output.
- bit (y 1, y 2, y 6, y 7) is a constellation word C A (b 1, Re, b 2, Re, b 1, Im, b 2, Im)
- bit ( y 3, y 4, y 5 , y 8, y 9, y 10) is a constellation word C B (b 1, Re, b 2, Re, b 3, Re, b 1, Im, b 2, Im, b 3, Im ) is mapped.
- 16-QAM mapper 124C-1 is constellation word C A by two 4-PAM mapper (b 1, Re, b 2 , Re, b 1, Im, b 2, Im) complex symbols (Re, Im) Map to On the other hand, the 64-QAM mapper 124C-2 generates constellation vectors C B (b 1, Re , b 2, Re , b 3, Re , b 1, Im , b 2, Im , b) by two 8-PAM mappers. (3, Im ) are mapped to complex symbols (Re, Im).
- the SM encoder 125C performs coding for spatially multiplexing the complex symbols s 1 and s 2 in order to generate transmission signals x 1 and x 2 .
- the demultiplexer described with reference to FIGS. 24A to 24C can be generalized as follows.
- the number of bits of the SM block is B
- the number of antennas (constellation words) is T
- i is an index of an antenna (constellation word), and is an integer of 1 or more and T or less.
- Embodiment (Part 2) In the embodiment (part 2), a bit interleaver having a configuration different from that of the bit interleaver 122 described in the embodiment (part 1) will be described. Note that in the embodiment (part 2), components that execute substantially the same processing as the embodiment (part 1) are assigned the same reference numerals, and descriptions thereof will be omitted.
- FIG. 25 is a block diagram showing another configuration example of the bit interleaver according to the embodiment of the present invention.
- the bit interleaver 300 shown in FIG. 25 has a configuration in which a cyclic block permutation unit 310 is added to the bit interleaver 122 shown in FIG.
- the bit interleaver 300 in FIG. 25 applies permutation consisting of at least two stages to the QC LDPC code word, and the cyclic block permutation unit 310 and the section permutation unit 122-1, 122-2, ... provided.
- the bit interleaver 300 applies, to the QC LDPC code word, cyclic block permutation that rearranges N cyclic blocks constituting the QC LDPC code. This cyclic block permutation does not affect the sequence of bits of the cyclic block.
- the first stage is performed by the cyclic block permutation unit 310.
- the bit interleaver 300 maps the bits of the QC LDPC codeword (LDPC codeword in which the sequence of cyclic blocks has been changed) to which the cyclic block permutation has been applied, to the SM block. This mapping is implemented such that the QC LDPC codeword is divided into multiple sections, and the bits of the QC LDPC codeword are mapped to SM blocks for each section.
- the second stage is executed by the section permutation units 122-1, 122-2,.
- the bits mapped to the SM block by the bit interleaver 300 are demultiplexed by the demultiplexer 123 (see FIG. 20) and then mapped to a plurality of constellation words of the SM block.
- Each section is preferably made of B / 2 cyclic blocks so as to satisfy the above conditions (i) and (ii).
- the inventor has improved communication performance by optimizing cyclic block permutation, that is, selecting cyclic block permutation which combines constellation bits of different reliability and cyclic blocks of different importance.
- the simulation results for the optimum permutation found by applying the steps disclosed in the present invention are shown in bold.
- the SNR range for various cyclic block permutations is determined. Then, the threshold SNR is set only to select the cyclic block permutation that gives good performance with blind demapping. Good performance means low SNR. For example, in FIG. 27, the threshold SNR can be set to 9.8 dB. The threshold SNR should not be set too low so that many of the cyclic block permutations that provide very good performance with iterative demapping are not excluded. In addition, cyclic block permutation strictly optimized for blind mapping degrades performance with iterative demapping. Proper selection of the initial threshold SNR is knowledge gained from significant experience.
- a large number e.g., more than 1000
- a BLER curve with blind demapping is determined, for example using a Monte-Carlo simulation. Only cyclic block permutations are selected for SNRs below the threshold SNR in the subject BLER curve.
- BLER curves using iterative demapping are determined, and the cyclic block permutation that provides the best performance is selected. As an example, it is assumed that the following cyclic block permutation is selected.
- FIG. 28 (a) This cyclic block permutation is further shown in FIG. 28 (a).
- FIG. 28 (a) and FIGS. 28 (b) and (c) described later show constellation bits and sections.
- the number of cyclic blocks per section is 4, and the complex QAM symbols S 1 and S 2 are 16-QAM symbols.
- an intermediate number for example, 100 to 1000
- constrained random cyclic block permutations derived from the cyclic block permutations selected by the first selection step is generated, and the first selection is performed.
- the step selection criteria are applied to the generated cyclic block permutation.
- This constrained cyclic block permutation is obtained by applying random permutation to a cyclic block of one randomly selected section, for example, one column of FIG. 28 (a). An example of this is shown in FIG. In the example of FIG. 28B, section 7 is selected, and the original cyclic block sequence [07 11 10 42] is rearranged so that the cyclic block sequence [10 11 42 07] is obtained.
- an intermediate number for example, 100 to 1000
- the selection criteria are applied to the generated cyclic block permutation.
- This constrained cyclic block permutation is derived, for example, by applying random permutation to the cyclic block of each row in FIG. 28 (b).
- One random permutation is applied for each row, ie for each robust level.
- Each permutation length is the number of sections. An example of this is shown in FIG. 28 (c).
- the variation is quite small in terms of performance, and affects iterative demapping more than blind demapping. Therefore, performance with iterative demapping is optimized without sacrificing performance with blind demapping.
- Cyclic block permutation based on the above approach for three different transmit power ratios (the transmit power ratio is the ratio described above), the number of bits in three different channel slots (the number of bits in SM blocks), and seven different coding rates
- the results of the optimization process are shown in FIGS. 29A-29C, 30A-30C, and 31A-31C.
- the QC LDPC codes of coding rates CR 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11/15 in these figures are shown in FIG. 10, FIG. 11, FIG. 12, FIG. 13, and FIG. 14, which are QC LDPC codes defined by the DVB-NGH standard.
- the number of transmission antennas (the number of constellation words of the SM block) corresponds to two.
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- transmission power ratio 1/1
- channel slot bit number 10
- coding rate CR 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- transmission power ratio 1/2
- number of bits of channel slot 8
- coding rate CR 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- the optimized cyclic block permutation in the case of / 15 is shown.
- each row indicates cyclic block permutation. Note that a value such as "17" shown in each drawing indicates the index of the cyclic block.
- 7 illustrates optimized cyclic block permutations.
- cyclic blocks of each QC LDPC code are produced from cyclic blocks QB 20 , QB 16 and QB 34 in the order of section 1 and in cyclic block QB 41 , QB 28 and QB 36 in the order of section 2. And so on, and so on.
- 29A to 29C, 30A to 30C, 31A to 31C They are arranged in the order described from left to right of the row, corresponding to the coding rate, the number of bits in the channel slot (the number of bits in the SM block), and the transmission power ratio that the transmitter uses for transmission.
- LDPC code LDPC code in which the cyclic block has been rearranged
- FIGS. 22A to 22C and FIGS. 23A to 23C are executed by replacing the cyclic coefficient Q from 8 to 360 (see the generalized description).
- the processing of the mapping of bits of an LDPC codeword to constellation words by a bit interleaver and demultiplexer will be further described.
- the k-th cyclic block in the following section is from the high order bit side of the rearranged LDPC codeword (from FIG. 29A to FIG. 29C from the left side on the input side of the section permutation unit in FIG. 25).
- the numbers of cyclic blocks counted from the left side of the section are the numbers of cyclic blocks counted from the left side of the section.
- the bits of the QC LDPC codeword rearranged by cyclic block permutation are mapped to constellation words as follows.
- the transmission power ratio is 1/1, 1/2, 1/4
- the coding rate is 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11 / 15 (QC LDPC code defined by the tables shown in FIGS. 8 to 14).
- the two levels of the 4-QAM constellation word with the smaller number of modulation levels are made from the 2 bits of the first cyclic block of each section, and the robust level of the 16-QAM constellation word with the higher number of modulation levels
- the lowest two bits are generated from the two bits of the second cyclic block of each section, and the two highest robust levels of the 16-QAM constellation are generated from the two bits of the third cyclic block of each section. Mapping process is performed.
- two bits of 4-QAM constellation word are generated from bits of the first cyclic block of each section (section In case 1, the least reliable 2 bits of the cyclic block QB 20 ), 16-QAM constellation word are created from the 2 bits of the second cyclic block of each section (in the case of section 1, cyclic block QB 16 ) , The most reliable two bits of the 16-QAM constellation word are made from the two bits of the third cyclic block of each section (in the case of section 1, cyclic block QB 34 ).
- the bits of the QC LDPC codeword rearranged by cyclic block permutation are mapped to constellation words as follows.
- the transmission power ratio is 1/1, 1/2, 1/4
- the coding rate is 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11 / 15 (QC LDPC code defined by the tables shown in FIGS. 8 to 14).
- the two least robust levels of one 16-QAM constellation word are generated from the two bits of the first cyclic block of each section, and the two most robust levels of one 16-QAM constellation word are selected.
- Two bits of the second 16-block constellation word with the lowest robustness level of the other are generated from two bits of the third cyclic block of each section.
- the mapping process is performed such that the two bits with the highest robustness level of the 16-QAM constellation word are produced from the two bits of the fourth cyclic block of each section.
- the bits of the QC LDPC codeword rearranged by cyclic block permutation are mapped to constellation words as follows.
- the transmission power ratio is 1/1, 1/2, 1/4
- the coding rate is 1/3, 2/5, 7/15, 8/15, 3/5, 2/3, 11 / 15 (QC LDPC code defined by the tables shown in FIGS. 8 to 14).
- the two least robust 2-QAM constellations with lower modulation levels are constructed from the two bits of the first cyclic block in each section, and the most robust level of the 16-QAM constellation is the most robust.
- the higher 2 bits are made from the 2 bits of the second cyclic block of each section, and the lower 2 levels of the robust level of the 64-QAM constellation word with the higher number of modulation levels is the third cyclic block of each section Of the 64-QAM constellation word with the second lowest robustness level from the 2 bits of the fourth cyclic block of each section, the 64- QAM constellation word of the robustness level
- the highest 2 bits are the 2 bits of the 5th cyclic block of each section As made from, the mapping process is performed.
- FIG. 32 is a block diagram showing a configuration of receiver 500 in the embodiment of the present invention.
- the receiver reflects the functionality of the transmitter.
- the receiver 500 of FIG. 32 includes receiving antennas 510-1 to 510-2, RF (radio frequency) front end units 520-1 to 520-2, demodulators 530-1 to 530-2, and a MIMO decoder 540. , A multiplexer 550, a bit deinterleaver 560, and an LDPC decoder 570.
- the MIMO decoder 540 includes a spatial-multiplexing (SM) decoder 541 and QAM demappers 545-1 to 545-2.
- SM spatial-multiplexing
- the signals received by the receiving antennas 510-1 to 510-2 are processed by the RF front end units 520-1 to 520-2 and the demodulators 530-1 to 530-2.
- the RF front end units 520-1 to 520-2 generally include a tuner and a down converter, and the tuner tunes a desired frequency channel, and the down converter downconverts to a desired frequency band.
- Demodulators 530-1 to 530-4 obtain one received symbol and T channel fading coefficients for each channel slot.
- the received symbols and channel fading coefficients are complex values. For each channel slot, R received symbols and T ⁇ R channel fading coefficients are provided as inputs to the SM decoder 541.
- the SM decoder 541 performs SM decoding using R received symbols and T ⁇ R fading coefficients, and outputs T complex QAM symbols. Complex symbols are subjected to QAM constellation demapping, multiplexing, deinterleaving, and LDPC decoding. That is, exactly the reverse processing steps are performed in the transmitter of the embodiment (part 1) and the embodiment (part 2).
- the QAM demappers 545-1 to 545-2 respectively perform QAM constellation demapping corresponding to QAM constellation mapping by the QAM mappers 124-1 to 124-2 which the transmitter has with respect to the input complex QAM symbols. Do.
- the multiplexer 550 performs processing reverse to that of the demultiplexer 123 included in the transmitter (processing before reordering by the demultiplexer 123, multiplexing processing) on the input from the QAM demappers 545-1 to 545-2. .
- the bit deinterleaver 560 performs processing reverse to that of the bit interleavers 122 and 300 that the transmitter has with respect to the input from the multiplexer 550 (processing before reordering by the bit interleavers 122 and 300), ie, Perform bit de-interleaving.
- the LDPC decoder 570 performs, on the input from the bit de-interleaver 560, LDPC decoding based on the same QC-LCPC code as the LDPC encoder 121 of the transmitter.
- SM decoding and QAM constellation demapping are sometimes referred to in the art as multiple-input multiple output (MIMO) decoding.
- MIMO multiple-input multiple output
- so-called maximum-likelihood decoding is performed and SM decoding and QAM constellation demapping are performed jointly in one MIMO decoder 540.
- the present invention is not particularly limited thereto.
- the present invention is applicable to any number of antennas except one (for example, 2, 4, 8 etc.).
- the invention is applicable to any QAM constellation, where the constellation includes a square QAM constellation (4-QAM, 16-QAM, 64-QAM, 256-QAM, etc.).
- the value of B is the sum of the number of bits of constellation used, and is an integer of 2 ⁇ T or more.
- the present invention is a pseudo cyclic parity check code in which QC LDPC codes are adopted in second generation digital video broadcasting standards such as DVB-S2, DVB-T2, DVB-C2 (for example, ETSI EN 302 755 of DVB-T2 standard).
- Any pseudo cyclic parity check code such as the pseudo cyclic parity check code defined in Tables A1 to 6 of Table 1 is applicable.
- the values of N, M, and Q are integers that change depending on the pseudo cyclic parity check code to be used.
- the present invention is not limited to any particular mode for implementation of a method or device using software or hardware described in the embodiment.
- the invention can be implemented in a computer, microprocessor, microcontroller, etc. and in the form of a computer readable medium embodied in computer executable instructions for performing all the steps according to the above embodiments. It may be realized.
- the present invention may be realized in the form of an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- the first interleaving method is A plurality of codewords of the pseudo cyclic low density parity check code, implemented in a transmitter in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas;
- An interleaving method for reordering bits of a codeword to generate a plurality of constellation words constituting a spatial multiplexing block of The codeword consists of N cyclic blocks, each consisting of Q bits,
- the spatial multiplexing block consists of B bits, and the spatial multiplexing block consists of T constellation words
- the interleaving method is A first permutation step for rearranging the N cyclic blocks; A second permutation step of reordering the bits of the codewords in which the arrangement of the N cyclic blocks has been changed, to map the T constellation words constituting the plurality of spatial multiplexing blocks; Have.
- the first de-interleaving method is A method of de-interleaving implemented in a receiver in a communication system using a pseudo-cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
- the de-interleaving method is A process opposite to the above-described bit reordering performed by the first interleaving method is performed on a plurality of spatial multiplexing blocks composed of a plurality of constellation words.
- the first interleaver is A transmitter in a communication system using a pseudo-cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas, the code word of the pseudo-cyclic low density parity check code comprising a plurality of spaces
- An interleaver which rearranges bits of a codeword to generate a plurality of constellation words constituting a multiplex block,
- the codeword consists of N cyclic blocks, each consisting of Q bits
- the spatial multiplexing block consists of B bits
- the spatial multiplexing block consists of T constellation words
- the interleaver is A first permutation unit that rearranges the N cyclic blocks;
- a second permutation unit which rearranges the bits of the codewords in which the arrangement of the N cyclic blocks has been changed, to the T constellation words constituting the plurality of spatial multiplexing blocks; Equipped with
- the first deinterleaver is A deinterleaver comprising: a receiver in a communication system using a pseudo-cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
- the deinterleaver is The reverse processing of the bit rearrangement performed by the first interleaver is performed on a plurality of spatial multiplexing blocks composed of a plurality of constellation words.
- the first transmitter is A transmitter in a communication system using a pseudo-cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas, A pseudo-cyclic low density parity check encoder that generates a codeword using a pseudo-cyclic low density parity check code; A first interleaver that rearranges the bits of the codeword and outputs one or more spatial multiplexing blocks; A constellation mapper which maps each of a plurality of constellation words constituting each of the spatial multiplexing blocks to complex symbols; Equipped with
- the first receiver is A receiver in a communication system using a pseudo-cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas, Converts a signal received by multiple receive antennas into T complex symbols corresponding to each of one or more spatial multiplexing blocks including T constellation words (multiple-input multiple-output) A decoder, A first deinterleaver that deinterleaves the T complex symbols; A pseudo-cyclic low density parity check decoder that decodes the de-interleaving processing result by the de-interleaver using the pseudo-cyclic low density parity check code; Equipped with
- the reception performance of the communication system can be improved.
- the T is 2 and the N is 45, the Q is 360, and the B is any of 6, 8, and 10. It is.
- the third interleaving method is the second interleaving method, If the N is a multiple of B / 2, the N cyclic blocks are divided into multiple sections of B / 2 cyclic blocks; If the N is not a multiple of B / 2, N ⁇ X cyclic blocks excluding the cyclic block of remainder X divided by B / 2 are divided into a plurality of sections of B / 2 cyclic blocks.
- Each of the spatial multiplexing blocks associated with any section is made up of only the bits of the B / 2 different cyclic blocks divided into the sections to which the spatial multiplexing block is associated;
- Each of the T constellation words constituting each of the spatial multiplexing blocks associated with any section is B t / 2 different cyclic blocks which is 1/2 of the number B t of bits of the constellation word.
- Made from a bit of The same robust level bit pair among the plurality of bits of the T constellation words constituting each of the spatial multiplexing blocks associated with any section is one of the B t / 2 cyclic blocks. Made from two common cyclic blocks, As done.
- the fourth interleaving method is the third interleaving method
- the B is 6, the transmission power ratio is 1/1, and the pseudo cyclic low density parity check code has a coding rate 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into 4-QAM constellation word and 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 2 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is Two bits of the 4-QAM constellation word are generated from two bits of the first cyclic block of each section, and the least reliable two bits of the 16-QAM constellation word are second circular block of each section , And so that the two most reliable two bits of the 16-QAM constellation word are made from the two bits of the third cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the fifth interleaving method is the third interleaving method,
- the B is 8, the transmission power ratio is 1/1, and the pseudo cyclic low density parity check code has a coding rate 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into a 16-QAM constellation word and a 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 3 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The two least reliable two bits of one of the 16-QAM constellation words are generated from the two bits of the first cyclic block of each section, and the most reliable two of the one one of the 16-QAM constellation words are generated.
- the bits are made from the 2 bits of the second cyclic block of each section, and the 2 least reliable bits of the other 16-QAM constellation word are made from the 2 bits of the 3rd cyclic block of each section, It is done such that the two most reliable two bits of the other said 16-QAM constellation word are made from the two bits of the fourth cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the sixth interleaving method is the third interleaving method,
- the B is 10
- the transmission power ratio is 1/1
- the pseudo cyclic low density parity check code has a coding rate 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard
- the bits of each spatial multiplexing block are divided into 16-QAM constellation words and 64-QAM constellation words,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 4 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The least reliable two bits of the 16-QAM constellation word are made from the two bits of the first cyclic block of each section, and the most reliable two bits of the 16-QAM constellation word are each section.
- the least reliable 2 bits of the 64-QAM constellation word are made of 2 bits of the second cyclic block, and the 64-QAM constellation word is made of 2 bits of the third cyclic block of each section.
- the second least reliable two bits of are made from the two bits of the fourth cyclic block of each section, and the two most reliable two bits of the 64-QAM constellation word are the fifth circular block of each section It is done to be made from 2 bits of.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the seventh interleaving method is the third interleaving method
- the B is 6, the transmission power ratio is 1/2, and the pseudo cyclic low density parity check code has coding rates of 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into 4-QAM constellation word and 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 5 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is Two bits of the 4-QAM constellation word are generated from two bits of the first cyclic block of each section, and the least reliable two bits of the 16-QAM constellation word are second circular block of each section , And so that the two most reliable two bits of the 16-QAM constellation word are made from the two bits of the third cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the eighth interleaving method is the third interleaving method,
- the B is 8, the transmission power ratio is 1/2, and the pseudo cyclic low density parity check code has coding rates of 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into a 16-QAM constellation word and a 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 6 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The two least reliable two bits of one of the 16-QAM constellation words are generated from the two bits of the first cyclic block of each section, and the most reliable two of the one one of the 16-QAM constellation words are generated.
- the bits are made from the 2 bits of the second cyclic block of each section, and the 2 least reliable bits of the other 16-QAM constellation word are made from the 2 bits of the 3rd cyclic block of each section, It is done such that the two most reliable two bits of the other said 16-QAM constellation word are made from the two bits of the fourth cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the ninth interleaving method is the third interleaving method,
- the B is 10
- the transmission power ratio is 1/2
- the pseudo cyclic low density parity check code has coding rates of 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard
- the bits of each spatial multiplexing block are divided into 16-QAM constellation words and 64-QAM constellation words
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 7 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The least reliable two bits of the 16-QAM constellation word are made from the two bits of the first cyclic block of each section, and the most reliable two bits of the 16-QAM constellation word are each section.
- the least reliable 2 bits of the 64-QAM constellation word are made of 2 bits of the second cyclic block, and the 64-QAM constellation word is made of 2 bits of the third cyclic block of each section.
- the second least reliable two bits of are made from the two bits of the fourth cyclic block of each section, and the two most reliable two bits of the 64-QAM constellation word are the fifth circular block of each section It is done to be made from 2 bits of.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the tenth interleaving method is the third interleaving method,
- the B is 6, the transmission power ratio is 1/4, and the pseudo cyclic low density parity check code has coding rates 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into 4-QAM constellation word and 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 8 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is Two bits of the 4-QAM constellation word are generated from two bits of the first cyclic block of each section, and the least reliable two bits of the 16-QAM constellation word are second circular block of each section , And so that the two most reliable two bits of the 16-QAM constellation word are made from the two bits of the third cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the eleventh interleaving method is the third interleaving method:
- the B is 8, the transmission power ratio is 1/4, and the pseudo cyclic low density parity check code has coding rates of 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard,
- the bits of each spatial multiplexing block are divided into a 16-QAM constellation word and a 16-QAM constellation word,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 9 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The two least reliable two bits of one of the 16-QAM constellation words are generated from the two bits of the first cyclic block of each section, and the most reliable two of the one one of the 16-QAM constellation words are generated.
- the bits are made from the 2 bits of the second cyclic block of each section, and the 2 least reliable bits of the other 16-QAM constellation word are made from the 2 bits of the 3rd cyclic block of each section, It is done such that the two most reliable two bits of the other said 16-QAM constellation word are made from the two bits of the fourth cyclic block of each section.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the twelfth interleaving method is the third interleaving method,
- the B is 10
- the transmission power ratio is 1/4
- the pseudo cyclic low density parity check code has coding rates 1/3, 2/5, 7/15, 8/15, 3/5, Any of the pseudo-cyclic low density parity check codes defined in the 2/3, 11/15 DVB-NGH standard
- the bits of each spatial multiplexing block are divided into 16-QAM constellation words and 64-QAM constellation words,
- the rearrangement in the first permutation step is According to the cyclic block permutation shown in Table 10 according to the coding rate of the pseudo cyclic low density parity check code to be used,
- the rearrangement in the second permutation step is The least reliable two bits of the 16-QAM constellation word are made from the two bits of the first cyclic block of each section, and the most reliable two bits of the 16-QAM constellation word are each section.
- the least reliable 2 bits of the 64-QAM constellation word are made of 2 bits of the second cyclic block, and the 64-QAM constellation word is made of 2 bits of the third cyclic block of each section.
- the second least reliable two bits of are made from the two bits of the fourth cyclic block of each section, and the two most reliable two bits of the 64-QAM constellation word are the fifth circular block of each section It is done to be made from 2 bits of.
- the bits of the code word for which the cyclic block has been reordered are suitable for two constellation words. It is possible to map in the communication system and further improve the reception performance of the communication system.
- the present invention can be used for bit-interleaved coded modulation that performs spatial multiplexing using a pseudo-cyclic low density parity check code.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Error Detection And Correction (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機において実行される、前記疑似巡回低密度パリティ検査符号の符号語から複数の空間多重ブロックを構成する複数のコンステレーション語を生成するために、当該符号語のビットを並び換えるインターリービング方法であって、
前記符号語は、夫々がQ個のビットからなるN個の巡回ブロックで構成され、
前記空間多重ブロックはB個のビットからなり、前記空間多重ブロックはT個のコンステレーション語により構成され、
前記インターリービング方法は、
前記N個の巡回ブロックを並び換える第1パーミュテーションステップと、
前記N個の巡回ブロックの並びが換えられた前記符号語のビットを前記複数の空間多重ブロックを構成する前記T個のコンステレーション語にマッピングするために並び換える第2パーミュテーションステップと、
を有する。
図1は、一般的な送信機1000の構成を示すブロック図である。送信機1000は、入力処理部1100と、ビットインターリーブ符号化変調(bit-interleaved coding and modulation:BICM)エンコーダ1200と、変調器1300-1~1300-2と、アップコンバータ1400-1~1400-2、RF(radio frequency)電力増幅器1500-1~1500-2と、送信アンテナ1600-1~1600-2を備える。
本発明の実施の形態は、次の内容を保証する、QC LDPC符号に基づく符号語(QC LDPC符号語)のビットを並び換えるインターリービング方法を提供するものである。
(B1)各コンステレーション語(ビット数Bt)は、QC LDPC符号語の異なるBt/2個の巡回ブロックのビットから作られ、
(B2)コンステレーション語の同じロバストレスレベルのビット対は同じ巡回ブロックから作られ、
(B3)異なるアンテナに関するコンステレーション語は、異なる巡回ブロックのビットから作られる。
(C1)各SMブロックは、(B1+B2)/2個の互いに異なる巡回ブロックのビットから作られ、
(C2)同じQAMシンボルの同じロバストレベルで符号化される、SMブロックの各ビット対は、同じ巡回ブロックから作られ、
(C3)異なる送信アンテナに関するコンステレーション語は、異なる巡回ブロックのビットから作られる、
ように、SMブロックを構成する2つのコンステレーション語にマッピングされる。
以下、本発明の実施の形態に係る通信システムにおける送信機について図面を参照しつつ説明する。
実施の形態(その2)では、実施の形態(その1)で説明したビットインターリーバ122と異なる構成のビットインターリーバについて説明する。なお、実施の形態(その2)では、実施の形態(その1)と実質的に同じ処理を実行する構成要素には同じ符号を付し、その説明を省略する。
なお、この巡回ブロックパーミュテーションは、巡回ブロックをQB1,QB2,QB3,・・・の並びからQB6,QB3,QB38,・・・の並びに並び換えるものである。
<受信機>
以下、本発明の実施の形態に係る通信システムにおける受信機について図面を参照しつつ説明する。
本発明は上記の実施の形態で説明した内容に限定されず、本発明の目的とそれに関連又は付随する目的を達成するためのいかなる形態においても実施可能であり、例えば、以下であってもよい。
実施の形態に係るインターリービング方法、インターリーバ、及びこれを備える送信機、並びにこれらに対応するデインターリービング方法、デインターリーバ、及びこれを備える受信機とその効果についてまとめる。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機において実行される、前記疑似巡回低密度パリティ検査符号の符号語から複数の空間多重ブロックを構成する複数のコンステレーション語を生成するために、当該符号語のビットを並び換えるインターリービング方法であって、
前記符号語は、夫々がQ個のビットからなるN個の巡回ブロックで構成され、
前記空間多重ブロックはB個のビットからなり、前記空間多重ブロックはT個のコンステレーション語により構成され、
前記インターリービング方法は、
前記N個の巡回ブロックを並び換える第1パーミュテーションステップと、
前記N個の巡回ブロックの並びが換えられた前記符号語のビットを前記複数の空間多重ブロックを構成する前記T個のコンステレーション語にマッピングするために並び換える第2パーミュテーションステップと、
を有する。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機において実行される、デインターリービング方法であって、
前記デインターリービング方法は、
複数のコンステレーション語からなる複数の空間多重ブロックに対して、第1のインターリービング方法によって行われる前記ビットの並び換えと逆の処理を行う。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機が備える、前記疑似巡回低密度パリティ検査符号の符号語から複数の空間多重ブロックを構成する複数のコンステレーション語を生成するために、当該符号語のビットを並び換えるインターリーバであって、
前記符号語は、夫々がQ個のビットからなるN個の巡回ブロックで構成され、
前記空間多重ブロックはB個のビットからなり、前記空間多重ブロックはT個のコンステレーション語により構成され、
前記インターリーバは、
前記N個の巡回ブロックを並び換える第1パーミュテーション部と、
前記N個の巡回ブロックの並びが換えられた前記符号語のビットを前記複数の空間多重ブロックを構成する前記T個のコンステレーション語にマッピングするために並び換える第2パーミュテーション部と、
を備える。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機が備える、デインターリーバであって、
前記デインターリーバは、
複数のコンステレーション語からなる複数の空間多重ブロックに対して、第1のインターリーバによって行われる前記ビットの並び換えと逆の処理を行う。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機であって、
疑似巡回低密度パリティ検査符号を用いて符号語を生成する疑似巡回低密度パリティ検査エンコーダと、
前記符号語のビットを並び換えて1以上の空間多重ブロックを出力する第1のインターリーバと、
各前記空間多重ブロックを構成する複数のコンステレーション語の夫々を複素シンボルにマッピングするコンステレーションマッパと、
を備える。
疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機であって、
複数の受信アンテナによって受信された信号を、T個のコンステレーション語を含む1以上の空間多重ブロックの夫々に対応するT個の複素シンボルに変換する他入力他出力(multiple - input multiple - output)デコーダと、
前記T個の複素シンボルに対してデインターリービング処理を行う第1のデインターリーバと、
前記デインターリーバによるデインターリービング処理結果を前記疑似巡回低密度パリティ検査符号を用いて復号する疑似巡回低密度パリティ検査デコーダと、
を備える。
前記NがB/2の倍数の場合には、前記N個の巡回ブロックはB/2個の巡回ブロックからなる複数のセクションに分けられ、
前記NがB/2の倍数でない場合には、B/2で割った余りXの巡回ブロックを除いたN-X個の巡回ブロックはB/2個の巡回ブロックからなる複数のセクションに分けられ、
前記第2パーミュテーションにおける並び換えは、
何れかのセクションに関連する各前記空間多重ブロックは、当該空間多重ブロックが関連する前記セクションに分けられた前記B/2個の異なる巡回ブロックのビットのみから作られ、
何れかのセクションに関連する各前記空間多重ブロックを構成する前記T個のコンステレーション語の夫々は当該コンステレーション語のビット数Btの1/2であるBt/2個の異なる前記巡回ブロックのビットから作られ、
何れかのセクションに関連する各前記空間多重ブロックを構成する前記T個のコンステレーション語の夫々の複数ビットのうちの同じロバストレベルのビット対は前記Bt/2個の巡回ブロックのうちの1つの共通の巡回ブロックから作られる、
ように行われる。
前記Bは6であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表2に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは8であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表3に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは10であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表4に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは6であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表5に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは8であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表6に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは10であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表7に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは6であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表8に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは8であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表9に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる。
前記Bは10であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率1/3、2/5、7/15、8/15、3/5、2/3、11/15のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表10に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる。
110 入力処理部
120 BICMエンコーダ
121 LDPCエンコーダ
122 ビットインターリーバ
122-1~122-3 セクションパーミュテーションユニット
123 デマルチプレクサ
124-1~124-2 QAMマッパ
125 SMエンコーダ
130-1~130-2 変調器
140-1~140-2 増幅器
150-1~150-2 送信アンテナ
300 ビットインターリーバ
310 ブロックパーミュテーションユニット
500 受信機
510-1~510-2 受信アンテナ
520-1~520-2 RFフロントエンド部
530-1~530-2 復調器
540 MIMOデコーダ
541 SMデコーダ
545-1~545-2 QAMデマッパ
550 マルチプレクサ
560 ビットデインターリーバ
570 LDPCデコーダ
Claims (17)
- 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機において実行される、前記疑似巡回低密度パリティ検査符号の符号語から複数の空間多重ブロックを構成する複数のコンステレーション語を生成するために、当該符号語のビットを並び換えるインターリービング方法であって、
前記符号語は、夫々がQ個のビットからなるN個の巡回ブロックで構成され、
前記空間多重ブロックはB個のビットからなり、前記空間多重ブロックはT個のコンステレーション語により構成され、
前記インターリービング方法は、
前記N個の巡回ブロックを並び換える第1パーミュテーションステップと、
前記N個の巡回ブロックの並びが換えられた前記符号語のビットを前記複数の空間多重ブロックを構成する前記T個のコンステレーション語にマッピングするために並び換える第2パーミュテーションステップと、
を有するインターリービング方法。 - 前記Tは2であり、前記Nは45であり、前記Qは360であり、前記Bは6、8及び10の何れかである
請求項1記載のインターリービング方法。 - 前記NがB/2の倍数の場合には、前記N個の巡回ブロックはB/2個の巡回ブロックからなる複数のセクションに分けられ、
前記NがB/2の倍数でない場合には、B/2で割った余りXの巡回ブロックを除いたN-X個の巡回ブロックはB/2個の巡回ブロックからなる複数のセクションに分けられ、
前記第2パーミュテーションにおける並び換えは、
何れかのセクションに関連する各前記空間多重ブロックは、当該空間多重ブロックが関連する前記セクションに分けられた前記B/2個の異なる巡回ブロックのビットのみから作られ、
何れかのセクションに関連する各前記空間多重ブロックを構成する前記T個のコンステレーション語の夫々は当該コンステレーション語のビット数Btの1/2であるBt/2個の異なる前記巡回ブロックのビットから作られ、
何れかのセクションに関連する各前記空間多重ブロックを構成する前記T個のコンステレーション語の夫々の複数ビットのうちの同じロバストレベルのビット対は前記Bt/2個の巡回ブロックのうちの1つの共通の巡回ブロックから作られる、
ように行われる
請求項2記載のインターリービング方法。 - 前記Bは6であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表1に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは8であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表2に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは10であり、送信電力比は1/1であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表3に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは6であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表4に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは8であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表5に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは10であり、送信電力比は1/2であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表6に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは6であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは4-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表7に示される巡回ブロックパーミュテーションに従って行われ、
前記4-QAMコンステレーション語の2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは8であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と16-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表8に示される巡回ブロックパーミュテーションに従って行われ、
一方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、当該一方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、他方の前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、当該他方の前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 前記Bは10であり、送信電力比は1/4であり、前記疑似巡回低密度パリティ検査符号は、符号化率7/15、8/15、3/5のDVB-NGH規格において定義された疑似巡回低密度パリティ検査符号の何れかであり、
各空間多重ブロックのビットは16-QAMコンステレーション語と64-QAMコンステレーション語とに分けられ、
前記第1パーミュテーションステップにおける並び換えは、
使用する前記疑似巡回低密度パリティ検査符号の符号化率に応じた表9に示される巡回ブロックパーミュテーションに従って行われ、
前記16-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの1番目の巡回ブロックの2ビットから作られ、前記16-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの2番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が低い2ビットが各セクションの3番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の2番目に信頼度が低い2ビットが各セクションの4番目の巡回ブロックの2ビットから作られ、前記64-QAMコンステレーション語の最も信頼度が高い2ビットが各セクションの5番目の巡回ブロックの2ビットから作られるように、行われる
請求項3記載のインターリービング方法。 - 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機において実行される、デインターリービング方法であって、
前記デインターリービング方法は、
複数のコンステレーション語からなる複数の空間多重ブロックに対して、請求項1記載のインターリービング方法によって行われる前記ビットの並び換えと逆の処理を行う
デインターリービング方法。 - 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機が備える、前記疑似巡回低密度パリティ検査符号の符号語から複数の空間多重ブロックを構成する複数のコンステレーション語を生成するために、当該符号語のビットを並び換えるインターリーバであって、
前記符号語は、夫々がQ個のビットからなるN個の巡回ブロックで構成され、
前記空間多重ブロックはB個のビットからなり、前記空間多重ブロックはT個のコンステレーション語により構成され、
前記インターリーバは、
前記N個の巡回ブロックを並び換える第1パーミュテーション部と、
前記N個の巡回ブロックの並びが換えられた前記符号語のビットを前記複数の空間多重ブロックを構成する前記T個のコンステレーション語にマッピングするために並び換える第2パーミュテーション部と、
を備えるインターリーバ。 - 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機が備える、デインターリーバであって、
前記デインターリーバは、
複数のコンステレーション語からなる複数の空間多重ブロックに対して、請求項14記載のインターリーバによって行われる前記ビットの並び換えと逆の処理を行う
デインターリーバ。 - 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける送信機であって、
疑似巡回低密度パリティ検査符号を用いて符号語を生成する疑似巡回低密度パリティ検査エンコーダと、
前記符号語のビットを並び換えて1以上の空間多重ブロックを出力する請求項14記載のインターリーバと、
各前記空間多重ブロックを構成する複数のコンステレーション語の夫々を複素シンボルにマッピングするコンステレーションマッパと、
を備える送信機。 - 疑似巡回低密度パリティ検査符号、空間多重、及びT(Tは1より大きい整数)本の送信アンテナを用いる通信システムにおける受信機であって、
複数の受信アンテナによって受信された信号を、T個のコンステレーション語を含む1以上の空間多重ブロックの夫々に対応するT個の複素シンボルに変換する他入力他出力(multiple - input multiple - output)デコーダと、
前記T個の複素シンボルに対してデインターリービング処理を行う請求項15記載のデインターリーバと、
前記デインターリーバによるデインターリービング処理結果を前記疑似巡回低密度パリティ検査符号を用いて復号する疑似巡回低密度パリティ検査デコーダと、
を備える受信機。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201280003370.XA CN103181085B (zh) | 2011-08-17 | 2012-08-09 | 交织方法及解交织方法 |
US13/824,791 US9130814B2 (en) | 2011-08-17 | 2012-08-09 | Interleaving method and deinterleaving method |
ES12824056.1T ES2562017T3 (es) | 2011-08-17 | 2012-08-09 | Método de intercalación y método de desintercalación |
EP12824056.1A EP2615738B1 (en) | 2011-08-17 | 2012-08-09 | Interleaving method and deinterleaving method |
JP2013505236A JP5873073B2 (ja) | 2011-08-17 | 2012-08-09 | インターリービング方法、及びデインターリービング方法 |
EP17156258.0A EP3200375B1 (en) | 2011-08-17 | 2012-08-09 | Devices and methods for interleaving and deinterleaving |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP11177841.1 | 2011-08-17 | ||
EP20110177841 EP2560311A1 (en) | 2011-08-17 | 2011-08-17 | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
EP20110008671 EP2560310A1 (en) | 2011-08-17 | 2011-10-28 | Cyclic-block permutations for spatial multiplexing with quasi-cyclic LDPC codes |
EP11008671.7 | 2011-10-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013024584A1 true WO2013024584A1 (ja) | 2013-02-21 |
Family
ID=44862349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/005085 WO2013024584A1 (ja) | 2011-08-17 | 2012-08-09 | インターリービング方法、及びデインターリービング方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9130814B2 (ja) |
EP (5) | EP2560311A1 (ja) |
JP (1) | JP5873073B2 (ja) |
CN (1) | CN103181085B (ja) |
ES (3) | ES2711928T3 (ja) |
TW (1) | TWI606698B (ja) |
WO (1) | WO2013024584A1 (ja) |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014178299A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178296A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178300A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178298A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178297A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014199865A1 (ja) * | 2013-06-12 | 2014-12-18 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015041072A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015041075A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015041073A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015041074A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015045912A1 (ja) * | 2013-09-24 | 2015-04-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP2015136017A (ja) * | 2014-01-16 | 2015-07-27 | 日本放送協会 | インターリーブ装置及びデインターリーブ装置、並びにインターリーブ方法 |
JP2015154119A (ja) * | 2014-02-10 | 2015-08-24 | パナソニックIpマネジメント株式会社 | 可変シフタ、ldpc復号器、及びデータシフト方法 |
WO2015178011A1 (ja) * | 2014-05-22 | 2015-11-26 | パナソニック株式会社 | 通信方法および通信装置 |
JP2015222942A (ja) * | 2014-05-22 | 2015-12-10 | パナソニック株式会社 | 通信方法 |
JPWO2015178214A1 (ja) * | 2014-05-21 | 2017-04-20 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP2017512410A (ja) * | 2014-02-20 | 2017-05-18 | エルジー エレクトロニクス インコーポレイティド | 放送信号送信装置、放送信号受信装置、放送信号送信方法及び放送信号受信方法 |
JP2017518676A (ja) * | 2014-12-08 | 2017-07-06 | エルジー エレクトロニクス インコーポレイティド | 放送信号送信装置、放送信号受信装置、放送信号送信方法及び放送信号受信方法 |
KR101781883B1 (ko) | 2013-08-01 | 2017-09-26 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
Families Citing this family (68)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5664919B2 (ja) * | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP2552043A1 (en) * | 2011-07-25 | 2013-01-30 | Panasonic Corporation | Spatial multiplexing for bit-interleaved coding and modulation with quasi-cyclic LDPC codes |
US8885766B2 (en) | 2012-09-11 | 2014-11-11 | Inphi Corporation | Optical communication interface utilizing N-dimensional double square quadrature amplitude modulation |
US9246730B2 (en) * | 2013-06-19 | 2016-01-26 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcase signals and method for receiving broadcast signals |
KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
KR102002559B1 (ko) | 2013-07-05 | 2019-07-22 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
GB201312243D0 (en) * | 2013-07-08 | 2013-08-21 | Samsung Electronics Co Ltd | Non-Uniform Constellations |
CN105519100B (zh) | 2013-08-01 | 2018-12-07 | Lg 电子株式会社 | 发送广播信号的设备、接收广播信号的设备、发送广播信号的方法以及接收广播信号的方法 |
KR101733503B1 (ko) | 2013-08-01 | 2017-05-10 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
WO2015016673A1 (en) | 2013-08-01 | 2015-02-05 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
KR101774325B1 (ko) | 2013-08-01 | 2017-09-19 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
KR101763601B1 (ko) * | 2013-08-01 | 2017-08-01 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
JPWO2015045901A1 (ja) * | 2013-09-26 | 2017-03-09 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
MX2016003551A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
EP3051704A4 (en) * | 2013-09-26 | 2017-06-21 | Sony Corporation | Data processing device and data processing method |
US20160197625A1 (en) * | 2013-09-26 | 2016-07-07 | Sony Corporation | Data processing device and data processing method |
MX2016003553A (es) * | 2013-09-26 | 2016-07-21 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
CN105556855A (zh) * | 2013-09-26 | 2016-05-04 | 索尼公司 | 数据处理装置和数据处理方法 |
WO2015065040A1 (ko) * | 2013-10-29 | 2015-05-07 | 엘지전자 주식회사 | 무선접속 시스템에서 256qam을 이용한 변조 심볼 전송 방법 및 장치 |
WO2015089741A1 (zh) | 2013-12-17 | 2015-06-25 | 华为技术有限公司 | 接收数据的方法及设备,以及发送数据的方法及设备 |
US10425110B2 (en) * | 2014-02-19 | 2019-09-24 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9602137B2 (en) | 2014-02-19 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
JP2015156531A (ja) * | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR101776275B1 (ko) | 2014-02-19 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
JP2015156530A (ja) | 2014-02-19 | 2015-08-27 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR101884273B1 (ko) | 2014-02-20 | 2018-08-30 | 상하이 내셔널 엔지니어링 리서치 센터 오브 디지털 텔레비전 컴퍼니, 리미티드 | Ldpc 코드워드 인터리빙 매핑 방법 및 디인터리빙 디매핑 방법 |
CN111200443B (zh) | 2014-03-19 | 2023-09-12 | 三星电子株式会社 | 发送设备及其交织方法 |
KR101776272B1 (ko) | 2014-03-19 | 2017-09-07 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
US10419023B2 (en) * | 2014-03-20 | 2019-09-17 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 1024-symbol mapping, and bit interleaving method using same |
US10432228B2 (en) * | 2014-03-27 | 2019-10-01 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 4096-symbol mapping, and bit interleaving method using same |
US9602245B2 (en) | 2014-05-21 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
KR101785692B1 (ko) * | 2014-05-21 | 2017-10-16 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
WO2015178210A1 (ja) | 2014-05-21 | 2015-11-26 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR101775704B1 (ko) | 2014-05-21 | 2017-09-19 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
CN106464269B (zh) * | 2014-05-21 | 2019-12-06 | 索尼公司 | 数据处理装置和数据处理方法 |
JP6428650B2 (ja) * | 2014-05-21 | 2018-11-28 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
EP3148087B1 (en) * | 2014-05-21 | 2021-03-03 | Sony Corporation | Bit interleaved coded modulation with a group-wise interleaver adapted to a rate 12/15 ldpc code of length 16200 |
MX357178B (es) * | 2014-05-21 | 2018-06-28 | Sony Corp | Dispositivo de procesamiento de datos y metodo de procesamiento de datos. |
KR101775703B1 (ko) * | 2014-05-21 | 2017-09-06 | 삼성전자주식회사 | 송신 장치 및 그의 인터리빙 방법 |
US9800269B2 (en) | 2014-05-21 | 2017-10-24 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9780808B2 (en) * | 2014-05-21 | 2017-10-03 | Samsung Electronics Co., Ltd. | Transmitter apparatus and bit interleaving method thereof |
JP6424888B2 (ja) | 2014-05-21 | 2018-11-21 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
KR102260767B1 (ko) * | 2014-05-22 | 2021-06-07 | 한국전자통신연구원 | 길이가 16200이며, 부호율이 3/15인 ldpc 부호어 및 64-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
US10361720B2 (en) * | 2014-05-22 | 2019-07-23 | Electronics And Telecommunications Research Institute | Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 64-symbol mapping, and bit interleaving method using same |
KR102260775B1 (ko) * | 2014-05-22 | 2021-06-07 | 한국전자통신연구원 | 길이가 16200이며, 부호율이 10/15인 ldpc 부호어 및 256-심볼 맵핑을 위한 비트 인터리버 및 이를 이용한 비트 인터리빙 방법 |
CN111510246B (zh) | 2014-12-29 | 2023-06-16 | Lg 电子株式会社 | 接收广播信号的方法和装置及发送广播信号的方法和装置 |
JP2016149738A (ja) * | 2015-02-10 | 2016-08-18 | 日本放送協会 | 送信装置、受信装置、及び半導体チップ |
KR102426771B1 (ko) | 2015-02-25 | 2022-07-29 | 삼성전자주식회사 | 송신 장치 및 그의 부가 패리티 생성 방법 |
KR102326036B1 (ko) | 2015-03-02 | 2021-11-12 | 삼성전자주식회사 | 송신 장치 및 그의 쇼트닝 방법 |
KR101800415B1 (ko) * | 2015-03-02 | 2017-11-23 | 삼성전자주식회사 | 송신 장치 및 그의 패리티 퍼뮤테이션 방법 |
WO2016140515A1 (en) * | 2015-03-02 | 2016-09-09 | Samsung Electronics Co., Ltd. | Transmitter and parity permutation method thereof |
US10340952B2 (en) | 2015-03-02 | 2019-07-02 | Samsung Electronics Co., Ltd. | Transmitter and shortening method thereof |
US9667274B2 (en) * | 2015-03-19 | 2017-05-30 | Telefonaktiebolaget Lm Ericsson (Publ) | Method of constructing a parity-check matrix for using message-passing algorithm to decode the repeat-accumulate type of modulation and coding schemes |
US9602232B2 (en) * | 2015-05-19 | 2017-03-21 | Samsung Electronics Co., Ltd. | Transmitting apparatus and mapping method thereof |
US9595978B2 (en) * | 2015-05-19 | 2017-03-14 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9748975B2 (en) * | 2015-05-19 | 2017-08-29 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9762346B2 (en) * | 2015-05-19 | 2017-09-12 | Samsung Electronics Co., Ltd. | Transmitting apparatus and mapping method thereof |
US9680505B2 (en) * | 2015-05-19 | 2017-06-13 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9692453B2 (en) | 2015-05-19 | 2017-06-27 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US9634692B2 (en) * | 2015-05-19 | 2017-04-25 | Samsung Electronics Co., Ltd. | Transmitting apparatus and interleaving method thereof |
US11296823B2 (en) * | 2017-05-30 | 2022-04-05 | Qualcomm Incorporated | Priority based mapping of encoded bits to symbols |
US10997060B2 (en) * | 2019-05-09 | 2021-05-04 | United States Of America As Represented By The Secretary Of The Navy | Device, system, and method for detecting a defect in a computer program by generating and testing semantically equivalent computer program variants |
JP2020188357A (ja) * | 2019-05-14 | 2020-11-19 | 富士通株式会社 | 符号化回路、復号化回路、符号化方法、及び復号化方法 |
US11032023B1 (en) | 2019-05-21 | 2021-06-08 | Tarana Wireless, Inc. | Methods for creating check codes, and systems for wireless communication using check codes |
US11223372B2 (en) | 2019-11-27 | 2022-01-11 | Hughes Network Systems, Llc | Communication throughput despite periodic blockages |
CN113055067B (zh) * | 2019-12-27 | 2024-04-26 | 中兴通讯股份有限公司 | 下行信号处理方法、装置及基站 |
CN114268410B (zh) * | 2020-09-16 | 2023-10-31 | 中国科学院上海高等研究院 | 基于循环移位的交织方法、系统、设备及计算机存储介质 |
US11838127B2 (en) | 2022-03-11 | 2023-12-05 | Hughes Network Systems, Llc | Adaptive satellite communications |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008125085A (ja) * | 2007-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 変調器及び変調方法 |
WO2009116204A1 (ja) * | 2008-03-18 | 2009-09-24 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2454193B (en) * | 2007-10-30 | 2012-07-18 | Sony Corp | Data processing apparatus and method |
US7978649B2 (en) * | 2004-07-15 | 2011-07-12 | Qualcomm, Incorporated | Unified MIMO transmission and reception |
US7539463B2 (en) * | 2005-03-30 | 2009-05-26 | Intel Corporation | Techniques to enhance diversity for a wireless system |
JP4065283B2 (ja) * | 2005-07-06 | 2008-03-19 | 松下電器産業株式会社 | 送信方法 |
WO2007108396A1 (ja) * | 2006-03-17 | 2007-09-27 | Mitsubishi Electric Corporation | 通信装置、復号装置、情報伝送方法および復号方法 |
DK2056510T3 (da) | 2007-10-30 | 2013-05-21 | Sony Corp | Anordning og fremgangsmåde til databehandling |
TWI497920B (zh) | 2007-11-26 | 2015-08-21 | Sony Corp | Data processing device and data processing method |
TWI390856B (zh) | 2007-11-26 | 2013-03-21 | Sony Corp | Data processing device and data processing method |
TWI459724B (zh) | 2007-11-26 | 2014-11-01 | Sony Corp | Data processing device and data processing method |
TWI410055B (zh) | 2007-11-26 | 2013-09-21 | Sony Corp | Data processing device, data processing method and program product for performing data processing method on computer |
TWI538415B (zh) | 2007-11-26 | 2016-06-11 | Sony Corp | Data processing device and data processing method |
AU2008330816B2 (en) | 2007-11-26 | 2013-01-17 | Sony Corporation | Data process device, data process method, coding device, coding method |
DK2254250T3 (en) | 2008-03-03 | 2015-08-31 | Rai Radiotelevisione Italiana | Bitpermutationsmønstre for LDPC coded modulation and 64QAM constellations |
JP4898858B2 (ja) * | 2009-03-02 | 2012-03-21 | パナソニック株式会社 | 符号化器、復号化器及び符号化方法 |
EP2525496A1 (en) * | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
-
2011
- 2011-08-17 EP EP20110177841 patent/EP2560311A1/en not_active Withdrawn
- 2011-10-28 EP EP20110008671 patent/EP2560310A1/en not_active Withdrawn
-
2012
- 2012-08-09 US US13/824,791 patent/US9130814B2/en active Active
- 2012-08-09 ES ES17156258T patent/ES2711928T3/es active Active
- 2012-08-09 JP JP2013505236A patent/JP5873073B2/ja active Active
- 2012-08-09 WO PCT/JP2012/005085 patent/WO2013024584A1/ja active Application Filing
- 2012-08-09 EP EP12824056.1A patent/EP2615738B1/en active Active
- 2012-08-09 EP EP17156258.0A patent/EP3200375B1/en active Active
- 2012-08-09 ES ES12824056.1T patent/ES2562017T3/es active Active
- 2012-08-09 ES ES15185803.2T patent/ES2631814T3/es active Active
- 2012-08-09 CN CN201280003370.XA patent/CN103181085B/zh active Active
- 2012-08-09 EP EP15185803.2A patent/EP2996273B1/en active Active
- 2012-08-15 TW TW101129514A patent/TWI606698B/zh active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008125085A (ja) * | 2007-11-13 | 2008-05-29 | Matsushita Electric Ind Co Ltd | 変調器及び変調方法 |
WO2009116204A1 (ja) * | 2008-03-18 | 2009-09-24 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
Non-Patent Citations (2)
Title |
---|
DOUILLARD C. ET AL.: "The Bit Interleaved Coded Modulation module for DVB-NGH: Enhanced features for mobile reception, Telecommunications (ICT)", 2012 19TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS (ICT), 23 April 2012 (2012-04-23) - 25 April 2012 (2012-04-25), pages 1 - 6, XP055041408 * |
See also references of EP2615738A4 * |
Cited By (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2656725C2 (ru) * | 2013-05-02 | 2018-06-06 | Сони Корпорейшн | Устройство обработки данных и способ обработки данных |
JPWO2014178297A1 (ja) * | 2013-05-02 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178299A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178298A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178297A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US9793925B2 (en) | 2013-05-02 | 2017-10-17 | Sony Corporation | Data processing device and data processing method |
US10312940B2 (en) | 2013-05-02 | 2019-06-04 | Sony Corporation | Data processing apparatus and data processing method |
US9806742B2 (en) | 2013-05-02 | 2017-10-31 | Sony Corporation | Data processing device and data processing method |
US9859922B2 (en) | 2013-05-02 | 2018-01-02 | Sony Corporation | Data processing device and data processing method |
JPWO2014178296A1 (ja) * | 2013-05-02 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
RU2656723C2 (ru) * | 2013-05-02 | 2018-06-06 | Сони Корпорейшн | Устройство обработки данных и способ обработки данных |
RU2656726C2 (ru) * | 2013-05-02 | 2018-06-06 | Сони Корпорейшн | Устройство обработки данных и способ обработки данных |
WO2014178300A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2014178296A1 (ja) * | 2013-05-02 | 2014-11-06 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US9838037B2 (en) | 2013-05-02 | 2017-12-05 | Sony Corporation | Data processing device and data processing method |
JPWO2014178298A1 (ja) * | 2013-05-02 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JPWO2014178299A1 (ja) * | 2013-05-02 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JPWO2014178300A1 (ja) * | 2013-05-02 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JPWO2014199865A1 (ja) * | 2013-06-12 | 2017-02-23 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US10432225B2 (en) | 2013-06-12 | 2019-10-01 | Saturn Licensing Llc | Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio |
WO2014199865A1 (ja) * | 2013-06-12 | 2014-12-18 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US11082065B2 (en) | 2013-06-12 | 2021-08-03 | Saturn Licensing Llc | Data processing apparatus and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio |
KR101781883B1 (ko) | 2013-08-01 | 2017-09-26 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
US10103920B2 (en) | 2013-08-01 | 2018-10-16 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
US10142153B2 (en) | 2013-08-01 | 2018-11-27 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
US9838233B2 (en) | 2013-08-01 | 2017-12-05 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
KR101781882B1 (ko) | 2013-08-01 | 2017-09-26 | 엘지전자 주식회사 | 방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법 |
JPWO2015041074A1 (ja) * | 2013-09-20 | 2017-03-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015041073A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US10320416B2 (en) | 2013-09-20 | 2019-06-11 | Saturn Licensing Llc | Data processing device and data processing method |
WO2015041072A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US20190215020A1 (en) | 2013-09-20 | 2019-07-11 | Saturn Licensing Llc | Data processing device and data processing method |
JPWO2015041073A1 (ja) * | 2013-09-20 | 2017-03-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US10277257B2 (en) | 2013-09-20 | 2019-04-30 | Saturn Licensing Llc | Data processing device and data processing method |
US10972128B2 (en) | 2013-09-20 | 2021-04-06 | Saturn Licensing Llc | Data processing device and data processing method |
WO2015041075A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
US10951241B2 (en) | 2013-09-20 | 2021-03-16 | Saturn Licensing Llc | Data processing device and data processing method |
WO2015041074A1 (ja) * | 2013-09-20 | 2015-03-26 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
WO2015045912A1 (ja) * | 2013-09-24 | 2015-04-02 | ソニー株式会社 | データ処理装置、及びデータ処理方法 |
JP2015136017A (ja) * | 2014-01-16 | 2015-07-27 | 日本放送協会 | インターリーブ装置及びデインターリーブ装置、並びにインターリーブ方法 |
JP2015154119A (ja) * | 2014-02-10 | 2015-08-24 | パナソニックIpマネジメント株式会社 | 可変シフタ、ldpc復号器、及びデータシフト方法 |
JP2017512410A (ja) * | 2014-02-20 | 2017-05-18 | エルジー エレクトロニクス インコーポレイティド | 放送信号送信装置、放送信号受信装置、放送信号送信方法及び放送信号受信方法 |
US9979578B2 (en) | 2014-02-20 | 2018-05-22 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
USRE49301E1 (en) | 2014-02-20 | 2022-11-15 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
US9813275B2 (en) | 2014-02-20 | 2017-11-07 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
JPWO2015178214A1 (ja) * | 2014-05-21 | 2017-04-20 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
WO2015178011A1 (ja) * | 2014-05-22 | 2015-11-26 | パナソニック株式会社 | 通信方法および通信装置 |
US10355816B2 (en) | 2014-05-22 | 2019-07-16 | Panasonic Corporation | Communication method and communication device |
JP2020031433A (ja) * | 2014-05-22 | 2020-02-27 | パナソニック株式会社 | 通信方法 |
JP2019009826A (ja) * | 2014-05-22 | 2019-01-17 | パナソニック株式会社 | 通信方法 |
US10979173B2 (en) | 2014-05-22 | 2021-04-13 | Panasonic Corporation | Communication method and communication device |
JP2021073759A (ja) * | 2014-05-22 | 2021-05-13 | パナソニック株式会社 | 通信方法 |
US11362761B2 (en) | 2014-05-22 | 2022-06-14 | Panasonic Corporation | Communication method and communication device |
JP2015222942A (ja) * | 2014-05-22 | 2015-12-10 | パナソニック株式会社 | 通信方法 |
JP7273075B2 (ja) | 2014-05-22 | 2023-05-12 | パナソニックホールディングス株式会社 | 通信方法 |
US11916665B2 (en) | 2014-05-22 | 2024-02-27 | Panasonic Holdings Corporation | Communication method and communication device |
US10237108B2 (en) | 2014-12-08 | 2019-03-19 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
US9866420B2 (en) | 2014-12-08 | 2018-01-09 | Lg Electronics Inc. | Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals |
JP2017518676A (ja) * | 2014-12-08 | 2017-07-06 | エルジー エレクトロニクス インコーポレイティド | 放送信号送信装置、放送信号受信装置、放送信号送信方法及び放送信号受信方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5873073B2 (ja) | 2016-03-01 |
EP2560311A1 (en) | 2013-02-20 |
EP3200375A1 (en) | 2017-08-02 |
US20130216001A1 (en) | 2013-08-22 |
TW201320623A (zh) | 2013-05-16 |
US9130814B2 (en) | 2015-09-08 |
CN103181085A (zh) | 2013-06-26 |
EP2615738B1 (en) | 2015-12-09 |
EP2615738A4 (en) | 2014-04-09 |
ES2711928T3 (es) | 2019-05-08 |
EP2996273A1 (en) | 2016-03-16 |
EP3200375B1 (en) | 2018-11-28 |
EP2560310A1 (en) | 2013-02-20 |
ES2562017T3 (es) | 2016-03-02 |
EP2996273B1 (en) | 2017-04-05 |
ES2631814T3 (es) | 2017-09-05 |
TWI606698B (zh) | 2017-11-21 |
EP2615738A1 (en) | 2013-07-17 |
CN103181085B (zh) | 2017-05-31 |
JPWO2013024584A1 (ja) | 2015-03-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5873073B2 (ja) | インターリービング方法、及びデインターリービング方法 | |
AU2019253907B2 (en) | Parallel bit interleaver | |
US11115060B2 (en) | Parallel bit interleaver | |
US10361726B2 (en) | Parallel bit interleaver | |
JP6050458B2 (ja) | インターリービング方法、及びデインターリービング方法 | |
JP5844905B2 (ja) | 送信方法、送信機、受信方法、及び受信機 | |
KR102257962B1 (ko) | 통신 방법 및 통신 장치 | |
KR102400538B1 (ko) | 통신 방법 및 통신 장치 | |
EP2947837A1 (en) | Cyclic-block permutations for 1D-4096-QAM with quasi-cyclic LDPC codes and code rates 9/15 and 13/15 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2013505236 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13824791 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012824056 Country of ref document: EP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12824056 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |