Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C11/419—Read-write [R-W] circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/14—Word line organisation; Word line lay-out

Definitions

• the present invention relates generally to memory circuits and in particular, to dynamic read port circuits.
• Vccmin The minimum operational supply voltage (Vccmin) is an important parameter of today's processors. Reducing Vccmin is an important way to reduce the power consumption of a processor.
• Register files (RF) memory cells commonly used for cache, inside the processor are the limiting blocks in reducing Vccmin. RF Vccmin is typically the maximum of three components: write Vccmin, read Vccmin, and retention Vccmin.
• Figure 1 shows a conventional, so-called "8T" register file (RF) bit cell having a separate read port for decoupled read operation.
• Read Vmin is determined by the Local Bit-Line (LBL) evaluation delay and/or LBL noise.
• Keeper devices p-type transistors, (K1-K3) are used to mitigate the noise impact. Due to contention between pull-down devices (N6, N7) of the read port and those of the keeper devices, the LBL evaluation delay is affected by Vmin, i.e., as Vmin goes down, the LBL delay typically increases.
• Figure 1 shows a conventional bit cell circuit with a read port.
• Figure 2 shows a bit cell circuit having a read port with data dependent boosting in accordance with some embodiments.
• Figure 3 lustrates data dependent capacitance for capacitive coupling in accordance with some embodiments.
• Figure 4 shows a bit cell circuit having a read port with a selectably engageable data dependent boosting circuit in accordance with some embodiments.
• Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
• Vmin may be reduced from 220 to 260 mV (e.g., down to around 0.6 V) for up to, or even in excess of, 64 bit cells on each local bit line (LBL).
• the drive strength of a read port data transistor may be improved, during a read operation, by capacitively coupling a rising transition from the asserted read word line onto the gate of the read port data transistor.
• FIG. 2 shows a bit cell circuit with data dependent boosting in accordance with some embodiments.
• the circuit incorporates a data pass device formed from N5 and P3, along with a coupling capacitor formed from p-type transistor P4.
• a data pass device formed from N5 and P3, along with a coupling capacitor formed from p-type transistor P4.
• P4 any type of capacitor, depending on available options for a given process, may be used.
• capacitors are derived from transistors such as a PMOS transistor with the source and drain connected together for one terminal and the gate used for the other terminal.
• the data pass device is made from P and N devices in a quasi pass gate arrangement. In this embodiment, the N device is always on. It should be appreciated, however, that any suitable coupling pathway could be used.
• the N device, N5 could be omitted, although both P and N devices may be desired for more effective coupling of both logic ' Is and logic Os.
• the entire pass device could be omitted, with just the capacitor P4 used to capacitively couple the RWL to the data transistor gate.
• the separate capacitor (P4) could be omitted if the gate-source capacitance of P3 is sufficient. Note also that in some schemes, the RWL node may be boosted.
• FIG. 3 illustrates data dependent capacitance for capacitive coupling in the circuit of
• Figure 2 in accordance with some embodiments, it shows how the capacitance of P4, the capacitively-configured p-type transistor, is dependent on the value of the bit (Bit) in the bit cell.
• the x-axis V represents the voltage across P4 (V RWL - Vv x ).
• the RWL signal may be boosted, when asserted, for a read operation.
• Vx being capacitively coupled to RWL, this not only causes the word line transistor (N6) to be driven harder, but also, it causes the data transistor (N7) to be driven harder as well .
• This can result in further improvement for LBL evaluation, even if the Vmin is reduced.
• RWL boosting it is believed that when RWL boosting is employed, increasing the RWL voltage to a level of about 30% above Vcc for a read operation may achieve desired read operation performance, e.g., when the data bit is a logic ' 1.
• lower RWL boosting may be desired in some cases from a noise perspective.
• Vss and N7 is turned off.
• RWL is asserted (High)
• node Vx momentarily rises above Vss due to the capacitive coupling from the RWL Low-to-High transition.
• Transistors N5 and N2 then restore node Vx to Vss, reducing the impact of the RWL coupling on the LBL noise for the read ⁇ case.
• the reduced amount of coupling from P4 will at least help and if necessary, other solutions might be employed to maintain the voltage at Vx sufficiently small. It should be appreciated that with some embodiments, in addition to better LBL evaluation, other benefits may be available. For example, with bit cells having DDB features as described in Figure 2, improved diffusion balancing may result.
• the DDB cell of Figure 2 has 4 PMOS and 7 NMOS devices, as contrasted with the conventional cell of Figure 1, which has 2 PMOS and 6 NMOS devices. Accordingly, the DDB cell has a more balanced P/N diffusion density.
• Figure 4 shows a DDB bit cell of Figure 2 with a selectably engageable DDB circuit for high and low Vcc operational modes.
• a mode select feature is provided to selectably disengage the capacitive device(s) from the RWL node to at least reduce Vx boosting when Vcc is at a higher voltage.
• a switch (SI), controlled by a mode select (Mode Sel.) signal connects the capacitor coupling node (Vy) to Vss when the circuit is in the higher Vcc mode.
• Vcc Vmin
• the DDB is enabled, when most needed, for lower supply levels and de-activated when the supply is higher, when DDB is not as helpful and could actually potentially be destructive.
• DDB cells in accordance with embodiments disclosed herein, could be used in a variety of different memory structures for a variety of different computing platforms. For example, they could be used in dynamic register file arrays, e.g., for so-called cache memory systems.
• any type of computing systems such as mobile personal computers, PDAs, cell phones, tablets, server computers, or the like could exploit memory cells with DDB as taught herein.
• Coupled is used to indicate that two or more elements are in direct physical or electrical contact with each other.
• Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
• Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
• Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
• Connected is used to indicate that two or more elements are in direct physical or electrical contact with each other.
• Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.
• PMOS transistor refers to a P-type metal oxide semiconductor field effect transistor.
• NMOS transistor refers to an N-type metal oxide semiconductor field effect transistor.
• MOS transistor MOS transistor
• NMOS transistor NMOS transistor
• PMOS transistor PMOS transistor
• transistor can include other suitable transistor types, e.g., junction-field-effect transistors, bipolar-junction transistors, metal semiconductor FETs, and various types of three dimensional transistors, MOS or otherwise, known today or not yet developed.
• suitable transistor types e.g., junction-field-effect transistors, bipolar-junction transistors, metal semiconductor FETs, and various types of three dimensional transistors, MOS or otherwise, known today or not yet developed.
• IC semiconductor integrated circuit
• PDA programmable logic arrays
• signal conductor lines are represented with lines. Some may be thicker, to indicate more constituent signal paths, have a number label, to indicate a number of constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. This, however, should not be construed in a limiting manner. Rather, such added detail may be used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit. Any represented signal lines, whether or not having additional information, may actually comprise one or more signals that may travel in multiple directions and may be implemented with any suitable type of signal scheme, e.g., digital or analog lines implemented with differential pairs, optical fiber lines, and/or single-ended lines.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Dram (AREA)
• Semiconductor Memories (AREA)

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• 2011
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  • 2012-04-09 WO PCT/US2012/032688 patent/WO2013002868A2/en active Application Filing
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