WO2012176701A1 - Device board, display apparatus, television receiver apparatus, and method for making device board - Google Patents

Device board, display apparatus, television receiver apparatus, and method for making device board Download PDF

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Publication number
WO2012176701A1
WO2012176701A1 PCT/JP2012/065331 JP2012065331W WO2012176701A1 WO 2012176701 A1 WO2012176701 A1 WO 2012176701A1 JP 2012065331 W JP2012065331 W JP 2012065331W WO 2012176701 A1 WO2012176701 A1 WO 2012176701A1
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WIPO (PCT)
Prior art keywords
wiring
gate
pair
slit
wirings
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Application number
PCT/JP2012/065331
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French (fr)
Japanese (ja)
Inventor
達朗 黒田
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シャープ株式会社
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Publication of WO2012176701A1 publication Critical patent/WO2012176701A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects

Definitions

  • the present invention relates to an element substrate, a display device, a television receiver, and a method for manufacturing the element substrate.
  • a liquid crystal panel used for a liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between a pair of glass substrates.
  • One of the glass substrates has a TFT as an active element for controlling the operation of each pixel.
  • the formed array substrate is used.
  • the display area of the array substrate has a structure in which a large number of gate lines and source lines are provided in a grid pattern, and TFTs are provided at intersections between the gate lines and the source lines.
  • capacitor lines parallel to the gate lines are formed.
  • a lead-out line is formed in parallel with the source line and across each gate line and each capacitor line.
  • a slit is formed in the lead wiring to divide the lead wiring into a plurality of parts, and when a short circuit occurs, a short-circuit portion in a portion divided by the slit in the lead wiring. Repair is performed by selectively cutting off the portion having the.
  • the slits are provided, the line width of the routing wiring is increased, and the overlapping area with each gate wiring and each capacitance wiring is increased accordingly. For this reason, the parasitic capacitance generated between the routing wiring and each gate wiring is increased, the signal transmitted to each gate wiring is likely to become dull, and the overlapping area is large. There is a risk that a short circuit is likely to occur between the wiring and each gate wiring and each capacitor wiring.
  • the present invention has been completed based on the above situation, and is an element suitable for repairing when a short circuit occurs while reducing the overlapping area of the first wiring, the second wiring, and the third wiring.
  • An object is to provide a substrate.
  • the element substrate of the present invention includes a first wiring, a second wiring that is parallel to the first wiring and arranged adjacent to the first wiring, and an insulating layer for the first wiring and the second wiring.
  • first wiring and the second wiring are insulated from the bridging portion by being arranged via the insulating layer with respect to the bridging portion spanned between the first wiring and the second wiring, If a short circuit does not occur at the intersection with the three wirings, a signal or the like can be transmitted to each of the first wiring, the second wiring, and the third wiring.
  • a short circuit occurs at the intersection of the first wiring and the third wiring
  • at least a pair of the bridging portions spanned between the first wiring and the second wiring adjacent thereto are short-circuited to the first wiring and the second wiring, respectively.
  • a portion that is short-circuited by at least a pair of bridge portions with respect to the first wiring is cut and separated from the second wiring.
  • a signal or the like can be transmitted to the first wiring by using a part of the second wiring.
  • the line width of the third wiring can be reduced. Since the third wiring intersects with both the first wiring and the second wiring, the overlapping area between the first wiring and the second wiring decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the first wiring, the second wiring, and the third wiring is reduced, and the possibility that a short circuit occurs is reduced.
  • the space between the first wiring and the second wiring can be reduced as compared with the case where the wiring dedicated for repair is provided separately from the first wiring and the second wiring, so that space saving can be achieved. This is suitable for achieving the above.
  • the second wiring is arranged with the slit in between.
  • a signal or the like can be transmitted to the second wiring using a portion that is not short-circuited with the third wiring.
  • a plurality of the first wirings and the second wirings are arranged alternately. In this way, it is possible to increase the number of installations of the transfer section, as compared with the case where a plurality of the first wirings or the second wirings are continuously arranged, which is preferable in increasing the degree of freedom of repair. Obviously.
  • At least a pair of the bridging portions are formed so as to bridge between the first wiring and a pair of the second wirings adjacent to each other with the first wiring interposed therebetween.
  • any of the pair of second wirings adjacent to the first wiring can be used for repair.
  • the degree of freedom increases. For example, even when one second wiring adjacent to the first wiring short-circuited with the third wiring is short-circuited with the third wiring, the first second wiring adjacent to the first wiring is used to make the first wiring. While repairing to transmit the signal of the wiring, it is possible to repair the one second wiring by separating the short-circuited portion from the third wiring.
  • One of the bridging portions that bridges between the first wiring and one of the pair of second wirings, and of the first wiring and the pair of second wirings is arranged at a position shifted from each other in the extending direction of the first wiring. If it does in this way, compared with the case where one bridging part and the other bridging part are arranged in the same position about the extension direction of the 1st wiring, one bridging part and the other bridging part Since the distance between the two is relatively large, it is difficult to short-circuit one of the bridges and the other bridge.
  • One of the bridging portions that bridges between the second wiring and the first wiring of one of the pair of the first wirings arranged across the second wiring, and the second wiring The other bridging portion that bridges between the wiring and the other first wiring of the pair of first wirings is disposed at a position shifted from each other in the extending direction of the second wiring. . If it does in this way, compared with the case where one bridging part and the other bridging part are arranged in the same position about the extension direction of the 2nd wiring, one bridging part and the other bridging part Since the distance between the two is relatively large, it is difficult to short-circuit one of the bridges and the other bridge.
  • the second wiring includes a slit forming portion in which the slit is formed and a slit non-forming portion in which the slit is not formed, and the slit forming portion and the slit non-forming portion have the same line width. It is said. In this way, the line width of the second wiring does not change between the slit forming portion and the slit non-forming portion, which is more suitable for facilitating manufacture and space saving.
  • the slit is formed over a range exceeding at least a pair of the spanning portions arranged at a position sandwiching the third wiring in the second wiring.
  • the second wiring is connected to the first wiring out of the plurality of portions arranged with the slit interposed therebetween. Then, at least a portion that is short-circuited by the pair of bridge portions is cut.
  • the cutting position in the second wiring can be set to a positional relationship that overlaps with the slit in the extending direction of the second wiring, so that a part of the second wiring can be cut in a straight line. It becomes possible. Therefore, it is possible to obtain an effect that the certainty at the time of separating a part of the second wiring is increased.
  • At least a pair of second bridging portions spanned between the second wiring and the first wiring adjacent thereto are short-circuited to the first wiring and the second wiring, respectively. Furthermore, among the plurality of portions arranged across the second slit in the first wiring, the first wiring is cut by cutting at least a portion short-circuited by the pair of second bridging portions with respect to the second wiring. Disconnect from. As described above, a signal or the like can be transmitted to the second wiring by using a part of the first wiring.
  • the first wiring is compared with the case where both the slit and the second slit are formed in the second wiring.
  • the difference in wiring resistance that can occur between the first wiring and the second wiring can be reduced.
  • the second slit is formed in the first wiring.
  • signals or the like can be transmitted to the first wiring using a portion that is not short-circuited with the fourth wiring.
  • a plurality of the first wirings and the second wirings are arranged in an alternating manner, and the bridge portion includes a pair of adjacent ones sandwiching the first wiring and the first wiring. Whereas at least one pair is formed so as to bridge between the second wirings, the second bridging portion is a pair of the second wirings and the second wirings adjacent to each other. At least one pair is formed so as to bridge the first wiring.
  • any of the pair of second wirings adjacent to the first wiring can be used for repair, and in addition, the second wiring Even if a short circuit occurs with the fourth wiring, any one of the pair of first wirings adjacent to the second wiring can be used for repair, and the degree of freedom in repairing is extremely high. Obviously, when the first wiring is short-circuited with the third wiring, any of the pair of second wirings adjacent to the first wiring can be used for repair, and in addition, the second wiring Even if a short circuit occurs with the fourth wiring, any one of the pair of first wirings adjacent to the second wiring can be used for repair, and the degree of freedom in repairing is extremely high. Become.
  • a switching element having at least an electrode connected to the first wiring or the second wiring is provided. In this way, a short circuit occurring at the intersection of the first wiring and the third wiring and a short circuit occurring at the intersection of the second wiring and the third wiring can be repaired, respectively. Can be driven.
  • a display device of the present invention is sealed between the element substrate described above, a counter substrate facing the element substrate, and the element substrate and the counter substrate.
  • a liquid crystal layer is sealed between the element substrate described above, a counter substrate facing the element substrate, and the element substrate and the counter substrate.
  • such a display device since the overlapping area of the first wiring, the second wiring, and the third wiring can be reduced and the repair can be suitably performed even when a short circuit occurs, the display quality is high and the display reliability is improved. It becomes a thing with high property. Further, such a display device can be applied as a liquid crystal display device to various uses such as a display of a television or a personal computer, and is particularly suitable for a large screen. In addition, when such a display device includes a lighting device that emits light toward the element substrate and the counter substrate, high luminance can be obtained and display quality can be improved.
  • a method for manufacturing an element substrate according to the present invention includes a first wiring and a first wiring arranged in parallel with the first wiring and adjacent to the first wiring. Two wirings, a third wiring intersecting the first wiring and the second wiring with an insulating layer interposed therebetween, a slit disposed in at least a portion of the second wiring across the third wiring, At least a pair is arranged at a position sandwiching the third wiring, and is insulated from the first wiring and the second wiring by being arranged through an insulating layer with respect to the first wiring and the second wiring.
  • a wiring forming step for forming a bridging portion that is bridged between the first wiring and the second wiring, an intersection between the first wiring and the third wiring, and the second wiring Whether or not a short circuit has occurred at the intersection of the wiring and the third wiring
  • a short circuit has occurred at each of the inspection step for inspecting and the intersection of the first wiring and the third wiring
  • at least a pair of the bridges sandwiching the third wiring among the first wiring
  • the first wiring and the second wiring is short-circuited, and among the plurality of portions arranged across the slit in the second wiring, at least a pair of the bridging portions with respect to the first wiring
  • the part to be short-circuited is cut off and separated from the second wiring, and when a short circuit occurs at the intersection of the second wiring and the third wiring, the slit
  • the line width of the third wiring can be reduced. Since the third wiring intersects with both the first wiring and the second wiring, the overlapping area between the first wiring and the second wiring decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the first wiring, the second wiring, and the third wiring is reduced, and the possibility that a short circuit occurs is reduced.
  • the space between the first wiring and the second wiring can be reduced as compared with the case where the wiring dedicated for repair is provided separately from the first wiring and the second wiring, so that space saving can be achieved. This is suitable for achieving the above.
  • substrate suitable for performing the repair at the time of the occurrence of a short circuit can be provided, reducing the overlapping area of 1st wiring, 2nd wiring, and 3rd wiring.
  • FIG. 1 is an exploded perspective view showing a schematic configuration of a television receiver according to Embodiment 1 of the present invention.
  • the exploded perspective view which shows schematic structure of the liquid crystal display device with which a television receiver is equipped
  • Sectional drawing which shows schematically the cross-sectional structure of a liquid crystal display device
  • Sectional drawing which shows the cross-sectional structure of a liquid crystal panel roughly
  • the top view which shows the plane structure of the display area in the array substrate which comprises a liquid crystal panel
  • a plan view schematically showing a wiring configuration in an array substrate constituting a liquid crystal panel The top view which shows the structure in the intersection of gate wiring and capacity wiring, and lead wiring Xx sectional view of FIG. Xi-xi sectional view of FIG. Plan view showing the repair method when the gate wiring and lead-out wiring are short-circuited, or when the capacity wiring and lead-out wiring are short-circuited.
  • the top view which shows the structure in the cross
  • the top view which shows the structure in the intersection part of the gate wiring which concerns on the modification 3 of Embodiment 1, and a capacity
  • the top view which shows the structure in the cross
  • a plan view showing a case where a patterning defect occurs in the transfer part The top view which shows the repair method when the gate wiring and lead wiring which concern on Embodiment 3 of this invention short-circuit Sectional drawing which shows the lamination
  • the top view which shows roughly the wiring structure in the array board
  • capacitance wiring and the lead wiring The top view which shows the structure in the cross
  • FIGS. 1 A first embodiment of the present invention will be described with reference to FIGS.
  • a method for manufacturing the array substrate 20 provided in the liquid crystal panel (display panel) 11 constituting the liquid crystal display device 10 is illustrated.
  • a part of each drawing shows an X axis, a Y axis, and a Z axis, and each axis direction is drawn to be a direction shown in each drawing.
  • the upper side shown in FIG. 3 be a front side
  • the lower side of the figure be a back side.
  • the television receiver TV includes a liquid crystal display device (display device) 10, front and back cabinets Ca and Cb that are accommodated so as to sandwich the liquid crystal display device 10, a power supply P, A tuner T and a stand S are provided.
  • the liquid crystal display device 10 has a horizontally long rectangular shape as a whole, and includes a liquid crystal panel 11 as a display panel and a backlight device (illumination device) 12 as an external light source, as shown in FIGS. Is integrally held by the bezel 13 or the like.
  • the backlight device 12 is a so-called direct type in which a light source is disposed directly under the back surface of the liquid crystal panel 11.
  • the backlight device 12 includes a chassis 14 having a light emitting portion opened on the front side (light emitting side, liquid crystal panel 11 side), a reflective sheet (reflecting member) 15 laid in the chassis 14, and light emitting from the chassis 14.
  • An optical member 16 attached so as to cover the portion, a frame 17 for holding the optical member 16, a plurality of cold cathode tubes (light sources) 18 accommodated in parallel in the chassis 14, and a cold cathode
  • the lamp holder 19 is configured to shield the end of the tube 18 and to have light reflectivity.
  • the liquid crystal panel 11 is formed by enclosing a liquid crystal layer 22 containing a liquid crystal material, which is a substance whose optical characteristics change with application of an electric field, between a pair of substrates 20 and 21.
  • the liquid crystal panel 11 has a frame shape (frame shape) surrounding the display area AA on the outer periphery side of the screen, whereas the area on the center side of the screen is a display area (inner periphery area) AA capable of displaying an image. This area is a non-display area (outer peripheral area) NAA incapable of displaying an image (see FIG. 8).
  • the inner area surrounded by the alternate long and short dash line indicates the display area AA.
  • a pair of front and back polarizing plates 23 are respectively attached to the outer surface sides of the substrates 20 and 21.
  • the one disposed on the back side (backlight device 12 side) is an array substrate (element substrate, active matrix substrate) 20, as shown in FIG.
  • a substrate disposed on the front side (light emitting side) is a CF substrate (counter substrate) 21.
  • Each of the array substrate 20 and the CF substrate 21 is formed by laminating various structures (thin films) described later on a transparent (translucent) glass substrate GS.
  • three electrodes 24a to 24c are provided in the display area AA on the inner surface side (the liquid crystal layer 22 side, the surface facing the CF substrate 21, and the wiring forming surface) of the array substrate 20 (glass substrate GS).
  • a large number of TFTs (Thin Film Transistors) 24 and pixel electrodes 25 that are switching elements having a plurality of TFTs are provided side by side, and the TFTs 24 and the pixel electrodes 25 extend in the X-axis direction in a lattice shape.
  • a large number of gate wirings (first wirings) 26 and a large number of source wirings 27 extending along the Y-axis direction are disposed so as to surround them.
  • the gate wiring 26 and the source wiring 27 are connected to the gate electrode 24a and the source electrode 24b of the TFT 24, respectively, and the pixel electrode 25 is connected to the drain electrode 24c of the TFT 24 via the drain wiring 34.
  • the array substrate 20 is provided with a large number of capacitor wirings (second wirings, auxiliary capacitor wirings, storage capacitor wirings, Cs wirings) 33 that are parallel to the gate wirings 26 and overlap the pixel electrodes 25 in plan view. Yes.
  • the capacitor wiring 33 is made of the same material as the gate wiring 26 and is formed in the same layer in the same process in the manufacturing process.
  • a large number of capacitor wirings 33 and gate wirings 26 are arranged in a line alternately in the Y-axis direction.
  • the gate wiring 26 is disposed between the pixel electrodes 25 adjacent in the Y-axis direction, while the capacitor wiring 33 is disposed at a position that substantially crosses the central portion of each pixel electrode 25 in the Y-axis direction.
  • the gate wiring 26 and the capacitor wiring 33 that are parallel to each other and the source wiring 27 that intersects with the gate wiring 26 and the capacitor wiring 33 are kept in an insulated state by interposition of a gate insulating film (insulating layer) 35 to be described later.
  • the pixel electrode 25 and the source wiring 27 that overlap each other in a plan view are kept in an insulated state by interposition of an interlayer insulating film 37 and a protective film 38 described later (see FIG. 7).
  • the pixel electrode 25 is made of a translucent conductive material (transparent conductive material) such as ITO (Indium Tin Oxide).
  • Both the gate wiring 26 and the source wiring 27 are made of a conductive metal material.
  • the source wiring 27 has a two-layer structure in which different metal films 39 and 40 are laminated. Of these, the lower metal film 39 is made of titanium (Ti), whereas the upper metal film is formed. 40 is made of aluminum (Al) (see FIG. 7).
  • An alignment film 28 for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the inner surface side of the array substrate 20 (FIG. 4).
  • each colored portion 29 has a vertically long rectangular shape in plan view following the outer shape of the pixel electrode 25.
  • each coloring part 29 which comprises a color filter
  • the light-shielding part (black matrix) 30 which makes the grid
  • the light shielding portion 30 is disposed so as to overlap with the gate wiring 26, the source wiring 27, and the capacitor wiring 33 on the array substrate 20 in plan view.
  • a counter electrode 31 is provided on the surface of each colored portion 29 and the light shielding portion 30 so as to face the pixel electrode 25 on the array substrate 20 side.
  • An alignment film 32 for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the inner surface side of the CF substrate 21.
  • the TFT 24 that is a switching element in the structure of the array substrate 20 will be described in detail.
  • the TFT 24 has a structure in which a plurality of thin films are sequentially stacked on a glass substrate GS forming the array substrate 20, and specifically, gates in order from the lower layer side (glass substrate GS side).
  • An interlayer insulating film (passivation film) 37 and a protective film 38 are stacked.
  • the gate electrode 24a is made of the same material as the gate wiring 26 and is patterned immediately above the glass substrate GS in the same process as the gate wiring 26 and the capacitor wiring 33.
  • Al aluminum
  • Cr chromium
  • It can be formed of a single metal film such as tantalum (Ta), titanium (Ti), copper (Cu), or a laminated film thereof.
  • the gate electrode 24a extends from the vicinity of the intersection of the gate wiring 26 extending along the X-axis direction with the source wiring 27 in the branch line extending along the Y-axis direction. It is constituted by.
  • the gate insulating film 35 is made of, for example, a silicon nitride film (SiNx), and as shown in FIG.
  • the gate insulating film 35 has a solid pattern that covers not only the TFT 24 formation region but also the entire surface of the glass substrate GS. Outside the formation region of the TFT 24, the gate insulating film 35 is located at the intersection of the relatively lower gate wiring 26 and the capacitor wiring 33, the relatively upper source wiring 27, and a later-described routing wiring 43. It is assumed that they are interposed between them and kept in an insulated state.
  • the semiconductor film 36 is made of, for example, amorphous silicon (a-Si). As shown in FIG. 7, one end side is connected to the source electrode 24b and the other end side is connected to the drain electrode 24c. It has a channel region CH for conducting.
  • the doped semiconductor film 42 is made of amorphous silicon (n + Si) doped with an n-type impurity such as phosphorus (P) at a high concentration.
  • the doping semiconductor film 42 extends along the semiconductor film 36 but is removed with respect to the range of the channel region CH, and a pair of portions arranged with the channel region CH interposed therebetween are a source electrode 24b and a drain described below. It constitutes a part of the electrode 24c.
  • the source electrode 24 b and the drain electrode 24 c include the same material as the source wiring 27 and the drain wiring 34 and are patterned on the glass substrate GS in the same process as the source wiring 27 and the drain wiring 34. .
  • the source electrode 24b and the drain electrode 24c are arranged to face each other with a predetermined interval in the X-axis direction.
  • the source electrode 24b and the drain electrode 24c are disposed on the upper layer side with respect to the gate electrode 24a via the gate insulating film 35 and the semiconductor film 36, respectively, and a part (opposing portion) of the source electrode 24b and the drain electrode 24c is planar with respect to the gate electrode 24a.
  • the overlapping portion is placed on the gate electrode 24a.
  • the source electrode 24b and the drain electrode 24c are formed by laminating first conductive films 24b1 and 24c1 on the lower layer side (semiconductor film 36 side) and second conductive films 24b2 and 24c2 on the upper layer side (interlayer insulating film 37 side). Is done.
  • the first conductive films 24b1 and 24c1 on the lower layer side are respectively constituted by the end portions of the doping semiconductor film 42 described above, and function as ohmic contact layers that are in ohmic contact with the semiconductor film 36 on the lower layer side. is there.
  • the second conductive films 24b2 and 24c2 on the upper layer side have a two-layer structure in which different metal films are laminated, and the metal film 39 on the lower layer side is made of titanium (Ti), whereas the metal on the upper layer side is made.
  • the film 40 is made of aluminum (Al). That is, the source electrode 24b and the drain electrode 24c are common to the source wiring 27 in that they have the second conductive films 24b2 and 24c2 made of two metal films 39 and 40.
  • the structure differs from the source wiring 27 in that the first conductive films 24b1 and 24c1 are provided. Further, as shown in FIG. 5, the source electrode 24b extends along a branch line extending along the X-axis direction from the vicinity of the intersection with the gate wiring 26 in the source wiring 27 extending along the Y-axis direction. It is comprised by the front-end
  • the interlayer insulating film 37 is made of, for example, a silicon nitride film (SiNx), and is made of the same material as the gate insulating film 35 described above.
  • the protective film 38 is made of an acrylic resin (for example, polymethyl methacrylate resin (PMMA)) or a polyimide resin, which is an organic material. Therefore, the protective film 38 is thicker than the gate insulating film 35 and the interlayer insulating film 37 made of other inorganic materials and functions as a planarizing film.
  • Each of the interlayer insulating film 37 and the protective film 38 has a substantially solid pattern that covers not only the region where the TFT 24 is formed but also the entire surface of the glass substrate GS.
  • the interlayer insulating film 37 and the protective film 38 are interposed between the relatively lower source wiring 27 and drain wiring 34 and the relatively upper pixel electrode 25 outside the TFT 24 formation region. These are kept in an insulating state.
  • the drain wiring 34 connected to the drain electrode 24c is substantially L-shaped in plan view as shown in FIG. 5, and one end side of the drain wiring 34 is connected to the drain electrode 24c. In contrast, the other end is connected to the pixel connection portion 41 connected to the pixel electrode 25. As shown in FIG. 7, the drain wiring 34 is formed on the gate insulating film 35, is made of the same material as the source wiring 27, and has the same two-layer structure. Titanium (Ti) A lower metal film 39 made of aluminum and an upper metal film 40 made of aluminum (Al).
  • the drain wiring 34 is composed of only the second conductive films 24b2 and 24c2 (39, 40) of the source electrode 24b and the drain electrode 24c, as in the case of the source wiring 27, and the first conductive films 24b1, 24c1 (42). It differs from these in that it does not have.
  • a gate driver (gate side driving component) GD and a source driver (source side driving component) for driving the TFT 24 are provided in the non-display area NAA on the inner surface side of the glass substrate GS constituting the array substrate 20, as shown in FIG. 8, a gate driver (gate side driving component) GD and a source driver (source side driving component) for driving the TFT 24 are provided.
  • SD is connected through an anisotropic conductive film.
  • the gate driver GD and the source driver SD are connected to a control board (not shown), and the TFT 24 can be driven by supplying various signals output from the control board to each wiring of the array substrate 20.
  • the source driver SD is attached to one end (upper end shown in FIG. 8) of the array substrate 20 along the long side direction (X-axis direction).
  • the gate driver GD is attached to one end (the right end shown in FIG. 8) of the array substrate 20 along the short side direction (Y-axis direction).
  • a gate wiring 26, a source wiring 27, and a capacitor wiring 33 existing on the display area AA side are respectively extended.
  • the source wiring 27 reaches the connection point of the source driver SD at the connection point of the driver GD. That is, the gate line 26, the source line 27, and the capacitor line 33 are formed so as to straddle the display area AA and the non-display area NAA.
  • the capacitor wiring 33 its extended end is arranged at a position inside the display area AA side of the non-display area NAA than the connection position of the gate driver GD, and the lead wiring 43 formed there. Connected to.
  • the routing wiring 43 is arranged at one end of the non-display area NAA of the array substrate 20 along the short side direction, and extends along the Y-axis direction while crossing each gate wiring 26 and each capacitance wiring 33 arranged in parallel. (In parallel with the source wiring 27), and its end reaches the connection location of the source driver SD and is connected to the source driver SD.
  • a plurality of lead wirings 43 are arranged in parallel with each other, and are connected to specific capacitance wirings 33 respectively.
  • the lead wiring 43 is made of the same material as that of the source wiring 27 and is formed in the same layer in the same manufacturing process. As shown in FIG. 10, the lower metal film 39 and the upper metal film 40 are formed. With.
  • the routing wiring 43 is arranged on the upper layer side with respect to each intersecting gate wiring 26 and each capacitance wiring 33 via the gate insulating film 35, so that the gate wiring 26 and the capacitance wiring 33 are different. Insulated state is maintained. However, a contact hole (not shown) is formed in the gate insulating film 35 at the intersection of the routing wiring 43 with the predetermined capacitance wiring 33, so that the predetermined capacitance wiring 33 is connected to the contact wiring through the contact hole. Are electrically connected. In this way, various signals and the like are supplied from the gate driver GD to the gate wiring 26 and from the source driver SD to the capacitor wiring 33 via the source wiring 27 and the routing wiring 43, respectively. Yes.
  • a slit 44 is formed at the intersection of the capacitive wiring 33 with the routing wiring 43.
  • the slit 44 is formed over a predetermined range across the lead wire 43 in the capacitor wire 33.
  • the slit 44 is formed of an elongated opening extending linearly in parallel with the X-axis direction, that is, the extending direction of the capacitor wiring 33, and both end portions thereof have a semicircular shape when viewed in a plane.
  • a slit forming portion 33a in which a slit 44 is formed is divided into two, and these are defined as two divided portions 33a1.
  • the capacitor wiring 33 includes a slit forming portion 33a and a slit non-forming portion 33b in which the slit 44 is not formed.
  • the line widths of the slit forming portion 33a and the slit non-forming portion 33b are equal to each other.
  • the capacity wiring 33 has a substantially uniform size over almost the entire length, with the line width hardly changing in the middle.
  • all of the many gate wirings 26 become “first wirings” that do not have the slits 44
  • all of the many capacitive wirings 33 become “second wirings” that have the slits 44
  • the routing wiring 43 that intersects with the "third wiring”.
  • FIG. 9 focuses on representing the planar configuration of each of the wirings 26, 33, 43 and the transfer portion 45, so that the gate insulating film 35, the interlayer insulating film 37, and the protective film 38 are illustrated. Omitted.
  • a bridge portion 45 is bridged between the gate wirings 26 and the capacitor wirings 33 that are arranged in large numbers alternately in the Y-axis direction.
  • the bridge portion 45 extends along the Y-axis direction (the direction orthogonal to the extending direction of the gate wiring 26 and the capacitor wiring 33, the extending direction of the routing wiring 43), and is adjacent to each other. 26 and the capacitor wiring 33 are bridged between the two.
  • One end of the transfer portion 45 overlaps the gate wiring 26 in a plan view, while the other end overlaps the capacitance wiring 33 adjacent to the gate wiring 26 in a plan view. Are superimposed. As shown in FIG.
  • the bridge portion 45 is made of the same material as the source wiring 27 and the routing wiring 43 and is formed in the same layer in the same process in the manufacturing process. And an upper metal film 40. That is, the bridge portion 45 has conductivity similar to the source wiring 27 and the routing wiring 43, but is arranged on the upper layer side through the gate insulating film 35 with respect to the gate wiring 26 and the capacitor wiring 33. Thus, normally, the gate wiring 26 and the capacitor wiring 33 are kept in an insulated state. However, when laser light or the like is irradiated to a portion of the transfer portion 45 that overlaps with the gate wiring 26 and the capacitor wiring 33 in a plan view, the gate insulating film 35 is melted at the irradiated portion, whereby the transfer portion 45. The gate line 26 and the capacitor line 33 are short-circuited.
  • the bridge portion 45 is arranged as a pair at a position sandwiching the routing wiring 43 in the extending direction between the adjacent gate wiring 26 and the capacitor wiring 33.
  • 26 and two sets of capacitor wirings 33 are arranged. That is, four transfer portions 45 are provided for each of the gate lines 26 and the capacity lines 33.
  • a pair of spanning portions 45 forming one set are positioned closer to the routing wiring 43 than both ends of the slit 44 in the X-axis direction, that is, between the end of the slit 44 and the routing wiring 43.
  • Each is arranged. In other words, the slit 44 is formed over a range that exceeds the pair of bridge portions 45 that sandwich the routing wiring 43 in the capacitor wiring 33.
  • the bridging portion 45 bridges the slit forming portion 33a of the capacitor wiring 33 and the gate wiring 26, and more specifically, one of the two divided portions 33a1 constituting the slit forming portion 33a and the gate.
  • the wiring 26 is bridged. That is, one set (one pair) of the crossover portions 45 is arranged for each of the two divided portions 33a1 with respect to the capacitor wiring 33. Then, the pair of spanning portions 45 forming one set has one division portion 33a1 at two positions separated in the X-axis direction with respect to the gate wiring 26 adjacent on the opposite side to the other division portion 33a1 side. It will be handed over.
  • a pair of bridge portions 45 that bridges one divided portion 33a1 and the gate wiring 26 and a pair of bridge portions 45 that bridge the other divided portion 33a1 and the gate wiring 26 opposite to the above are X It is arranged at almost the same position in the axial direction.
  • the pair of spanning portions 45 forming a pair are substantially equal in distance from the routing wire 43 (distance from each end portion of the slit 44), and in a symmetrical position with the routing wire 43 as the center. It is arranged.
  • This embodiment has the structure as described above, and its operation will be described next.
  • a manufacturing method of the liquid crystal display device 10 will be schematically described.
  • the liquid crystal panel 11 and the backlight device 12 are separately manufactured, and the liquid crystal panel 11 and the backlight device 12 are assembled via a bezel 13 or the like.
  • the manufacturing method of the liquid crystal panel 11, especially the manufacturing method of the array substrate 20, will be described in detail.
  • an array substrate structure forming step (wiring forming step) for forming each structure on the glass substrate GS forming the array substrate 20, and each structure on the glass substrate GS forming the CF substrate 21.
  • the substrate bonding step for bonding the glass substrate GS forming the array substrate 20 and the glass substrate GS forming the CF substrate 21 with the liquid crystal layer 22 interposed therebetween is performed.
  • an inspection process is performed for inspecting whether or not the wirings 26, 27, 33, and 43 are broken or short-circuited. For the liquid crystal panel 11 in which a defect is detected, repair for repairing the defective part is performed. Perform the process.
  • the gate driver GD and the source driver SD are mounted on the non-display area NAA of the array substrate 20.
  • the liquid crystal panel 11 is manufactured by performing the driver mounting process. Subsequently, each step will be described in detail.
  • the TFT 24, the wirings 26, 27, 33, and 43, the insulating films 35, 37, and 38, and the pixel electrode 25 are formed on the glass substrate GS that forms the array substrate 20 by a known photolithography method. Etc. are sequentially laminated.
  • the gate wiring 26 and the capacitor wiring 33 are formed in the same process at the same time using the same material and the same manufacturing apparatus, and particularly when the capacitor wiring 33 is formed.
  • a slit 44 is formed at a portion that intersects the circuit wiring 43.
  • the source wiring 27, the routing wiring 43, and the transfer portion 45 are formed in a lump in the same process using the same material and the same manufacturing apparatus.
  • the array substrate structure forming process includes a wiring forming process for forming the slits 44 and the bridge portions 45 in addition to the wirings 26, 27, 33, and 43.
  • an alignment film 28 is formed and the alignment process is performed.
  • the substrate bonding step is performed by applying a sealing agent on one glass substrate GS and dropping a liquid crystal material, and then curing the sealing agent while bonding the other glass substrate GS.
  • the liquid crystal panel 11 is irradiated with light from a backlight device for inspection (not shown), and each wiring 26, 27, 33 (43) of the array substrate 20 is inspected from an inspection device (not shown).
  • a backlight device for inspection not shown
  • each wiring 26, 27, 33 (43) of the array substrate 20 is inspected from an inspection device (not shown).
  • By inputting a signal it is performed while displaying a predetermined inspection image, and an operator visually observes the displayed inspection image or picks up the inspection image with an image sensor and performs image processing. Therefore, the presence or absence of defects is inspected.
  • a linear display defect called a line defect occurs.
  • a certain capacitance wiring 33 is short-circuited at a crossing portion with respect to the routing wiring 43 that is not scheduled to be connected among the plurality of routing wirings 43, the same line defect may occur. There is.
  • troublesome wiring is repaired for the liquid crystal panel 11 in which a defect is detected in the inspection process.
  • a short-circuit portion SP1 occurs at a portion where a certain gate wiring 26 (the gate wiring 26 illustrated at the top in FIG. 12) intersects the routing wiring 43
  • the gate wiring 26 is irradiated with laser light.
  • the short-circuited portion with the lead wiring 43 is cut off.
  • laser light is irradiated to two positions between the short-circuited wiring wiring 43 and the pair of bridge portions 45, A cut portion BP1 is formed by linearly cutting along the Y-axis direction so as to cross the gate wiring 26 at the position.
  • each of the bridging portions 45 and the gate wiring. 26 and the capacitor wiring 33 are short-circuited.
  • laser light is respectively applied to a portion of the bridge portion 45 that overlaps with the gate wiring 26 where the short circuit has occurred and a portion that overlaps with the capacitance wiring 33 in plan view.
  • the gate insulating film 35 at the irradiation location is melted, whereby each of the overlapping portions in the transfer portion 45 is short-circuited with respect to the gate wiring 26 and the capacitor wiring 33 to form a short-circuit portion SP2.
  • the main body part (the part excluding the shorted part) of the gate wiring 26 short-circuited to the routing wiring 43 can be electrically connected to the divided portion 33 a 1 which is a part of the adjacent capacitor wiring 33. it can.
  • the divided portion 33a1 that is short-circuited to the gate wiring 26 by the transfer portion 45 is irradiated with laser light to cut it.
  • the X-axis direction is opposite to the routed wire 43 side with respect to each bridge portion 45. Laser light is irradiated to two positions on the side (each end side of the slit 44).
  • the irradiation position (cutting position) of this laser beam is in a positional relationship overlapping with the slit 44 in the X-axis direction, it can be cut linearly along the Y-axis direction across the dividing portion 33a1. Thereby, the cutting part BP2 is formed. Thereby, the division part 33a1 short-circuited with the gate wiring 26 by the bridge
  • the signal supplied to the gate wiring 26 short-circuited to the routing wiring 43 is transmitted from the main body portion of the gate wiring 26 to a part of the adjacent capacitive wiring 33 via the bridge 45. Displayed normally by bypassing a certain divided portion 33a1 (specifically, the divided portion 33a1 on the gate wiring 26 side where the short circuit occurred) and flowing again to the main body portion of the gate wiring 26 via the transfer portion 45 The data is transmitted to each TFT 24 in the area AA.
  • the gate wiring 26 can be repaired by using a part of the capacitor wiring 33 adjacent to the gate wiring 26, compared with the conventional case where a slit is provided in the lead wiring.
  • the line width of the lead wiring 43 can be reduced.
  • the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Therefore, the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the routing wiring 43 is reduced, and the possibility of a short circuit itself is reduced. Further, as compared with the case where a wiring dedicated for repair is provided, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced, so that space saving can be achieved and the pitch between wirings can be reduced. This is also suitable for (high definition).
  • the gate wirings 26 are respectively spanned by the bridging portions 45 with respect to the pair of capacitive wirings 33 adjacent to each other in the Y-axis direction.
  • the divided portions 33a1 on the side of the shorted gate wiring 26 can be selectively used as detours for transmitting the signal of the gate wiring 26, respectively. Thereby, the following effects can be obtained.
  • one of the capacitor wirings 33 adjacent to the gate wiring 26 short-circuited to the routing wiring 43 (capacitance wiring 33 adjacent to the upper side of the shorted gate wiring 26 in FIG. 12) on the gate wiring 26 side.
  • the divided portion 33a1 is short-circuited to the routing wiring 43 (when a short-circuited portion SP3 indicated by a two-dot chain line in FIG. 12 occurs)
  • the other adjacent one is repaired. What is necessary is just to repair so that the division
  • capacitance wiring 33 may be utilized.
  • the repair can be performed by selectively using the pair of capacitor wirings 33 adjacent to the gate wiring 26, so that the degree of freedom in repairing is high, and the gate wiring 26 can be repaired. The probability of being able to rescue is high.
  • a short-circuit spot SP3 (shown by a two-dot chain line in FIG. 12) occurs at a crossing portion of a certain capacitance wiring 33 with respect to the routing wiring 43, the capacitance wiring 33 is short-circuited.
  • a portion short-circuited with the lead wiring 43 is separated.
  • FIG. 12 shows that among the divided portions 33a1 in which the short circuit occurs in the capacitor wiring 33, two positions between the short-circuited wiring wire 43 and the pair of bridge portions 45 in the X-axis direction.
  • the array substrate (element substrate) 20 of the present embodiment has the gate wiring (first wiring) 26 and the capacitor wiring (second wiring) arranged in parallel with the gate wiring 26 and adjacent to the gate wiring 26.
  • Wiring) 33 a routing wiring (third wiring) 43 that intersects the gate wiring 26 and the capacitive wiring 33 with a gate insulating film (insulating layer) 35 interposed therebetween, and at least the routing wiring 43 among the capacitive wiring 33.
  • At least a pair of slits 44 arranged in the straddling portion and the routing wiring 43 are arranged, and the gate wiring 26 and the capacitor wiring 33 are arranged via the gate insulating film 35 by being arranged.
  • a cross-over portion 45 that is insulated from the gate wiring 26 and the capacitive wiring 33 and is bridged between the gate wiring 26 and the capacitive wiring 33.
  • the gate wiring 26 and the capacitor wiring 33 are insulated from the bridge portion 45 by being arranged via the gate insulating film 35 with respect to the bridge portion 45 bridged between them, If a short circuit does not occur at the intersection between the wiring 33 and the routing wiring 43, a signal or the like can be transmitted to each of the gate wiring 26, the capacitance wiring 33, and the routing wiring 43.
  • the routing wiring 43 is sandwiched between the gate wiring 26 and at least between the pair of crossover portions 45.
  • the portion to be cut is cut off from the gate wiring 26.
  • at least a pair of the bridging portions 45 spanned between the gate wiring 26 and the capacitor wiring 33 adjacent thereto are short-circuited to the gate wiring 26 and the capacitor wiring 33, respectively.
  • at least a portion short-circuited by the pair of bridge portions 45 with respect to the gate wiring 26 is cut and separated from the capacitor wiring 33.
  • a signal or the like can be transmitted to the gate wiring 26 using a part of the capacitor wiring 33.
  • the capacitor wiring 33 adjacent to the gate wiring 26 can be used for repair when a short circuit occurs in the gate wiring 26, so that provision is made by providing a slit 44 in the lead wiring 43.
  • the line width of the lead wiring 43 can be reduced. Since the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the lead wiring 43 is reduced, and that the possibility of a short circuit is reduced. Further, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced as compared with the case where a repair-dedicated wiring is provided separately from the gate wiring 26 and the capacitor wiring 33, so that space saving can be achieved. This is suitable for achieving the above.
  • the slit 44 is sandwiched in the capacitive wiring 33.
  • a signal or the like can be transmitted to the capacitor wiring 33 using a portion that is not short-circuited with the lead-out wiring 43.
  • a plurality of gate wirings 26 and capacitor wirings 33 are arranged alternately. In this way, it is possible to increase the number of installation portions 45 and to increase the degree of freedom in repair, as compared with a case where a plurality of gate wirings 26 or capacitor wirings 33 are continuously arranged. It becomes.
  • At least one pair of the bridging portions 45 are formed so as to bridge between the gate wiring 26 and the pair of adjacent capacitor wirings 33 with the gate wiring 26 interposed therebetween. In this way, when the gate line 26 is short-circuited with the routing line 43, any of the pair of capacitor lines 33 adjacent to the gate line 26 can be used for repair. Increases freedom in For example, even when one capacitor wiring 33 adjacent to the gate wiring 26 short-circuited to the routing wiring 43 is short-circuited to the routing wiring 43, the other capacitance wiring 33 adjacent to the gate wiring 26 is used. While repairing to transmit the signal of the gate wiring 26, one capacity wiring 33 can be repaired by disconnecting the short-circuited portion with the lead wiring 43.
  • the capacitor wiring 33 includes a slit forming portion 33a where the slit 44 is formed and a slit non-forming portion 33b where the slit 44 is not formed, and the slit forming portion 33a and the slit non-forming portion 33b have the same line width. It is said. By doing so, the line width of the capacitor wiring 33 does not change between the slit forming portion 33a and the slit non-forming portion 33b, which is more suitable for facilitating manufacturing and space saving.
  • the transfer portion 45 and the routing wiring 43 are arranged in the same layer, and a gate insulating film 35 interposed between the routing portion 45 and the routing wiring 43, the gate wiring 26 and the capacitor wiring 33 is provided. Identical. In this way, the transfer portion 45 can be formed collectively when the lead wiring 43 is formed, which is preferable in reducing the manufacturing cost.
  • the slit 44 is formed over a range exceeding at least a pair of the spanning portions 45 arranged at positions where the lead wiring 43 is sandwiched in the capacitor wiring 33.
  • the gate wiring 26 among the plurality of portions arranged with the slit 44 interposed in the capacitor wiring 33.
  • at least a portion short-circuited by the pair of spanning portions 45 is cut.
  • the cutting position in the capacitor wiring 33 can be set to a positional relationship overlapping with the slit 44 in the extending direction of the capacitor wiring 33, thereby cutting a part of the capacitor wiring 33 linearly. Is possible. Therefore, it is possible to obtain an effect such as high reliability when part of the capacitor wiring 33 is cut off.
  • a TFT (switching element) 24 having at least a gate electrode (first electrode) 24 a connected to the gate wiring 26 is provided.
  • a short circuit occurring at the intersection between the gate wiring 26 and the routing wiring 43 and a short circuit occurring at the intersection between the capacitance wiring 33 and the routing wiring 43 can be repaired. Can be driven to.
  • the method for manufacturing the array substrate 20 according to the present embodiment includes a gate wiring 26 on the glass substrate (substrate) GS, and a capacitor wiring 33 that is arranged in parallel with the gate wiring 26 and adjacent to the gate wiring 26.
  • the gate wiring 26 and the capacitor wiring 33 are arranged via the gate insulating film 35 so as to be insulated from the gate wiring 26 and the capacitor wiring 33 and to be gated.
  • a portion sandwiched between the routing wiring 43 and at least a pair of the crossing portions 45 is cut off and separated from the gate wiring 26, while the gate wiring 26 and the capacitor wiring 33 adjacent thereto are separated.
  • At least a pair of the bridging portions 45 spanned between them are short-circuited with respect to the gate wiring 26 and the capacitor wiring 33, respectively.
  • At least a portion short-circuited by the pair of crossover portions 45 is cut so as to be separated from the capacitor wiring 33, and the capacitor wiring 33 and the lead wiring 43 are interchanged.
  • the short circuit has occurred in the portion cuts the portion of short-circuited with lead-wires 43 of the plurality of portions are arranged to sandwich the slit 44 in the capacitor line 33, it performs a repair process.
  • the capacitor wiring 33 adjacent to the gate wiring 26 can be used for repair when a short circuit occurs in the gate wiring 26, so that provision is made by providing a slit 44 in the lead wiring 43.
  • the line width of the lead wiring 43 can be reduced. Since the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the lead wiring 43 is reduced, and that the possibility of a short circuit is reduced. Further, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced as compared with the case where a repair-dedicated wiring is provided separately from the gate wiring 26 and the capacitor wiring 33, so that space saving can be achieved. This is suitable for achieving the above.
  • Embodiment 1 of this invention was shown, this invention is not restricted to the said embodiment, For example, the following modifications can also be included.
  • members similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and illustration and description thereof may be omitted.
  • the transfer part 45-1 is one of the divided parts 33a1-1 (the upper divided part in FIG. 13) of the pair of divided parts 33a1-1 constituting the slit forming part 33a-1 in the capacitor wiring 33-1. Only a portion that bridges the portion 33a1-1) and the gate wiring 26-1 adjacent thereto is formed, and the other divided portion 33a1-1 (the lower divided portion 33a1-1 in FIG. 13), No bridge is formed between adjacent gate lines 26-1. Even in such a configuration, each of the gate wirings 26-1 is bridged by the bridging portion 45-1 with respect to the adjacent one of the capacitance wirings 33-1. Even when the crossing point with the short circuit is short-circuited, it is possible to perform repair using the capacitive wiring 33-1 spanned over the bridging portion 45-1.
  • the gate wiring 26-2 and the capacitor wiring 33-2 according to the present modification are each formed with a slit 44-2 and without a slit 44-2.
  • the gate wiring 26-2 and the capacitor wiring 33-2 are formed in a plurality of lines alternately arranged in the Y-axis direction.
  • the gate wiring 26-2 and the capacitor wiring 33- having the slit 44-2 are formed. 2 are arranged one by one, and then the gate wiring 26-2 and the capacitor wiring 33-2 not having the slit 44-2 are arranged one by one. That is, the gate wiring 26-2 and the capacitor wiring 33-2 are arranged in such a manner that two having a slit 44-2 and one having no slit are alternately arranged.
  • the bridge portion 45-2 is formed so as to bridge the gate wiring 26-2 and the capacitor wiring 33-2 that have the slit 44-2 and the one that does not have the slit 44-2 adjacent thereto. ing. Accordingly, between the gate wiring 26-2 and the capacitor wiring 33-2 having the slits 44-2 adjacent to each other, the bridge portion 45-2 is not formed, and the slits 44 adjacent to each other are not formed. The bridge portion 45-2 is not formed between those having no -2. In the present modification, a large number of gate wirings 26-2 and a large number of capacitance wirings 33-2 each have a “first wiring” that does not have the slit 44-2 and a “second wiring that has the slit 44-2. ”And the routing wiring 43-2 intersecting with these are“ third wiring ”.
  • the slit 44-3 extends over a range not exceeding a pair of spanning portions 45-3 arranged at positions where the lead wiring 43-3 is sandwiched in the capacitance wiring 33-3. Is formed. Specifically, the slit 44-3 has both ends positioned closer to the routing wiring 43-3 than the pair of routing portions 45-3 in the X-axis direction, that is, the routing portion 45-3 and the routing wiring 43-. It is arranged at a position between three. Therefore, the bridge portion 45-3 bridges the slit non-formed portion 33b-3 and the gate line 26-3 in the capacitor line 33-3.
  • the crossover portion Cut linearly along the Y-axis direction toward the gate wiring 26-3 side that is short-circuited by 45-3 (cutting portion BP2-3).
  • the non-slit portion 33b-3 of the capacitor wiring 33-3 into an L shape, the portion short-circuited with the gate wiring 26-3 by the bridge portion 45-3 is replaced with the original capacitor wiring. It can be separated from 33-3 and made electrically independent.
  • the transfer portions 145 are arranged in a staggered manner when viewed in plan. Specifically, of a pair of capacitor wirings 133 that are adjacent to each other with the gate wiring 126 interposed therebetween, a pair of bridging portions 145 (hereinafter referred to as the first wiring section 145) spanned between one capacitor wiring 133 and the gate wiring 126. A pair of bridge portions 145A forming a pair) and a pair of bridge portions 145 (hereinafter referred to as a second pair of bridge portions 145) bridged between the other capacitor wiring 133 and the gate wiring 126.
  • the pair of the bridging portions 145A and the pair of the bridging portions 145B that form the first group spanned over the same gate wiring 126 or the capacitor wiring 133 extend along the Y-axis direction. They are not arranged in a straight line, but are arranged in a staggered (zigzag) pattern.
  • the distance between one spanning portion 145A and one end of the slit 144 is the other spanning as shown in FIG.
  • the distance between the portion 145A and the other end of the slit 144 is different.
  • the distance between one spanning portion 145B and one end of the slit 144 is the other spanning portion 145A forming the first set. Is substantially equal to the distance between the other end portion of the slit 144 and the distance between the other span portion 145B and the other end portion of the slit 144 is one of the above-mentioned first set.
  • the pair of bridging portions 145 spanned between one gate wiring 126 and the capacitor wiring 133, the other gate wiring 126, and the above-described gate wiring 126. It can also be said that the pair of bridge portions 145 spanned between the capacitor wiring 133 are arranged at positions shifted from each other in the X-axis direction, that is, the extending direction of the gate wiring 126 and the capacitor wiring 133.
  • the size and shape of the transfer part 145 are not normal and normal. There is a possibility that it is formed over a wider range than the one. Even in such a case, as described above, the spanning portion 145A forming the first set and the spanning portion 145B forming the second set are arranged at positions shifted in the X-axis direction. The distance between 145A and 145B is secured sufficiently large, and even if a patterning failure occurs in any of the transfer portions 145, the transfer portion 145 in which the failure has occurred is adjacent to the adjacent transfer portion 145. In contrast, short-circuiting is unlikely to occur. Thereby, when repairing the gate wiring 126 and the capacitor wiring 133, the function of each bridge portion 145 can be reliably exhibited.
  • the other crossing part 145 ⁇ / b> B that bridges the other wiring line 133 among the wiring lines 133 is arranged at a position shifted from each other in the extending direction of the gate line 126.
  • one of the crossover portions 145A and the other of the crossover portions 145A and the other crossover portion 145B are disposed at the same position in the extending direction of the gate wiring 126. Since the distance between the transfer part 145B is relatively large, it is difficult for one transfer part 145B and the other transfer part 145B to be short-circuited.
  • the other bridging portion 145B that bridges between the other gate wiring 126 of 126 is arranged at a position shifted from each other in the extending direction of the capacitor wiring 133. In this way, if compared with the case where one bridge 145A and the other bridge 145B are arranged at the same position in the extending direction of the capacitor wiring 133, the one bridge 145A and the other bridge 145B are compared with each other. Since the distance between the transfer part 145B is relatively large, it is difficult for one transfer part 145A and the other transfer part 145B to be short-circuited.
  • each crossing portion of the two routing wirings 243A and 243B, the gate wiring 226, and the capacitance wiring 233 among the plurality of routing wirings 243 parallel to each other will be described.
  • the two routing wirings 243A and 243B the one shown on the left side in FIG. 18 is referred to as a first routing wiring (third wiring) 243A, and the one shown on the right side in FIG. (Fourth wiring) 243B.
  • the configuration of the intersection of the first lead wiring 243A, the gate wiring 226, and the capacitor wiring 233 is substantially the same as in the first embodiment. That is, as shown in FIG. 18, a slit 244 is formed in a portion of the capacitor wiring 233 that straddles the first routing wiring 243A, and a pair of the wirings 233A that are disposed at positions sandwiching the first routing wiring 243A. The intermediate portion 245 bridges between the adjacent gate wiring 226 and the capacitor wiring 233.
  • the configuration of the intersection of the second routing wiring 243B, the gate wiring 226, and the capacitance wiring 233 will be described.
  • the second slit 46 is formed in the gate wiring 226 across the second routing wiring 243B. Is formed.
  • the adjacent gate wiring 226 and the capacitor wiring 233 are bridged by the second bridge 47 arranged in pairs at positions sandwiching the second routing wiring 243B. Therefore, in the present embodiment, the capacitor wiring 233 having the slit 244 at the intersection with the first routing wiring 243A and the gate wiring 226 having the second slit 47 at the intersection with the second routing wiring 243B are provided. It will be arranged in an alternating form. Since each of the gate wiring 226 and the capacitor wiring 233 has the slit 244 or the second slit 46, the wiring resistance difference between the wirings 226 and 233 is different from that in the first embodiment. Is getting smaller.
  • the second slit 46 included in the gate wiring 226 has a planar shape and a formation range substantially the same as the slit 244 included in the capacitor wiring 233. Further, the formation range and arrangement of the second transfer portion 47 are substantially the same as those of the transfer portion 245. Therefore, the second slit 46 is formed over a range exceeding the pair of second transfer portions 47 arranged at positions where the second lead wiring 243 ⁇ / b> B is sandwiched in the gate wiring 226. A pair of second bridging portions 47 are formed so as to bridge between the gate wiring 226 and a pair of adjacent capacitor wirings 233 across the gate wiring 226.
  • the repair is performed as follows.
  • the repair method related to the first lead wiring 243A is as described in the first embodiment, and therefore the description thereof will be omitted.
  • the repair method related to the second lead wiring 243B will be described.
  • the second wiring wiring 243B shorted in the X-axis direction of the capacitance wiring 233 and a pair of Laser light is applied to two positions between the second crossing section 47 and linearly cut along the Y-axis direction so as to cross the capacitive wiring 233 at the position to form a cut section BP4. .
  • the short circuit location in the capacity wiring 233 is separated from the main body portion.
  • the laser beam is irradiated to the portion of the second transfer portion 47 that overlaps the capacitor wiring 233 in which the short circuit occurs and the portion that overlaps the gate wiring 226 in plan view
  • the gate insulating film is melted, the overlapping portions in the second transfer portion 47 are short-circuited to the gate wiring 226 and the capacitor wiring 233 to form the short-circuit portion SP5.
  • the main body portion (the portion excluding the short-circuited portion) of the capacitor wiring 233 short-circuited with the second routing wiring 243B is electrically connected to a part of the adjacent gate wiring 226 (dividing portion 226a1). be able to.
  • the laser light is irradiated to the divided portion 226a1 short-circuited with the capacitor wiring 233 by the second bridge portion 47.
  • the cutting part BP5 is formed by cutting and cutting this. Thereby, the division part 226a1 short-circuited with the capacitor wiring 233 by the second transfer part 47 can be separated from the original gate wiring 226 and electrically independent.
  • the signal supplied to the capacitor wiring 233 short-circuited to the second routing wiring 243 ⁇ / b> B is transmitted from the main body portion of the capacitance wiring 233 to the adjacent gate wiring via the second bridging portion 47.
  • the dividing unit 226a1 which is a part of the H.226 and flowing again to the main body portion of the capacitive wiring 233 via the second transfer unit 47 normal transmission is achieved.
  • the gate wiring 226 and the capacitor wiring 233 are arranged via the gate insulating film in parallel with the first routing wiring 243A and adjacent to the first routing wiring 243A.
  • the second routing wiring (fourth wiring) 243B intersecting with the second slit 46 sandwiched between at least the second routing wiring 243B of the gate wiring 226 and the second routing wiring 243B are sandwiched.
  • At least a pair is arranged at the position, and the gate wiring 226 and the capacitor wiring 233 are arranged via a gate insulating film so as to be insulated from the gate wiring 226 and the capacitor wiring 233, and at the same time, the gate wiring 226 and the capacitor And a second bridge portion 47 that is bridged between the wiring 233 and the wiring 233.
  • the second routing wiring 243B of the capacitance wiring 233 is sandwiched and at least a pair of the second routing wiring 243B is interposed. The portion sandwiched between the two transfer portions 47 is cut and separated from the capacitor wiring 233.
  • At least a pair of second bridging portions 47 spanned between the capacitor wiring 233 and the gate wiring 226 adjacent thereto are short-circuited to the gate wiring 226 and the capacitor wiring 233, respectively. Further, among the plurality of portions arranged with the second slit 46 interposed in the gate wiring 226, a portion short-circuited by at least the pair of second bridging portions 47 with respect to the capacitor wiring 233 is cut to form a gate. Disconnect from the wiring 226. As described above, a signal or the like can be transmitted to the capacitor wiring 233 by using part of the gate wiring 226.
  • the slit 44 is formed in the capacitor wiring 233 and the second slit 46 is formed in the gate wiring 226, respectively.
  • the difference in wiring resistance that can occur between the gate wiring 226 and the capacitor wiring 233 can be reduced.
  • the first in the gate wiring 226 By cutting a portion short-circuited with the second routing wiring 243B among a plurality of portions arranged with the two slits 46 interposed therebetween, gates are used by utilizing a portion not short-circuited with the second routing wiring 243B. A signal or the like can be transmitted to the wiring 226.
  • a plurality of gate wirings 226 and capacitor wirings 233 are arranged in an alternating manner, and the crossover portion 45 includes a gate wiring 226 and a pair of capacitor wirings 233 adjacent to each other with the gate wiring 226 interposed therebetween. Whereas each pair is formed so as to bridge between each other, the second bridging portion 47 is formed between the capacitor wiring 233 and a pair of adjacent gate wirings 226 across the capacitor wiring 233. At least one pair is formed so as to be bridged. In this way, when the gate wiring 226 is short-circuited with the first routing wiring 243A, any of the pair of capacitor wirings 233 adjacent to the gate wiring 226 can be used for repair. Even when the capacitor wiring 233 is short-circuited with the second lead wiring 243B, any one of the pair of gate wirings 226 adjacent to the capacitor wiring 233 can be used for repair. The degree is extremely high.
  • Embodiment 4 A fourth embodiment of the present invention will be described with reference to FIG. In this Embodiment 4, what changed the arrangement
  • the transfer portion 345 is made of the same material (ITO or the like) as the pixel electrode 25 described in the first embodiment, and is formed in the same layer in the same process in the manufacturing process. Yes. Therefore, the transfer portion 345 is disposed on the upper layer side of the protective film 338, and between the gate wiring 326 and the capacitor wiring 333 to be transferred, the gate insulating film 335, the interlayer insulating film 337, and the protective film With the film 338 interposed, an insulating state between the gate wiring 326 and the capacitor wiring 333 is maintained.
  • the gate insulating film 335, the interlayer insulating film 337, and the protective film are irradiated by irradiating laser light. It is possible to melt the 338 and connect the transfer portion 345 to the gate wiring 326 and the capacitor wiring 333.
  • a plurality of spare wirings 48 are formed for repairing when a defect such as disconnection occurs in the source wiring 427. ing.
  • the spare wiring 48 is formed so as to surround three ends of the non-display area NAA having a frame shape except for the end on the gate driver GD side, and is connected to the end on the source driver SD side. The other end of the source wiring 427 crosses each other while intersecting the opposite ends.
  • the spare wiring 48 is made of the same material as the gate wiring 426 and the capacitor wiring 433 and is formed in the same layer in the same process in the manufacturing process. Therefore, as shown in FIG. 22, the spare wiring 48 is kept insulated from the source wiring 427 through the gate insulating film 435 at the intersection of the source wiring 427.
  • any of the source wirings 427 is disconnected, for example, laser light is irradiated to two intersecting portions of the disconnected source wiring 427 and the spare wiring 48 in the repair process. Thus, the two are short-circuited (see FIG. 20). Then, by supplying a signal or the like to be supplied to the source wiring 427 to the short-circuited spare wiring 48, the signal can be transmitted ahead (on the opposite side to the source driver SD side) in the source wiring 427. It is.
  • the configuration of the intersection of the spare wiring 48 and each source wiring 427 will be described in detail.
  • a slit 444 is formed in either the odd-numbered or even-numbered source wiring 427 among the source wirings 427 arranged in parallel. Accordingly, on the array substrate 420, there are a source wiring 427 in which the slit 444 is not formed (hereinafter referred to as a first source wiring 427A) and a source wiring 427 in which the slit 444 is formed (hereinafter referred to as a second source wiring 427B). A plurality of lines are arranged alternately in the X-axis direction. The slit 444 is formed over a predetermined range across the spare wiring 48 in the second source wiring 427B.
  • the second source wiring 427B an overlapping portion that overlaps the spare wiring 48 in a plan view
  • the overlapping portion is formed in a range covering a pair of non-overlapping portions sandwiching the overlapping portion from both sides and not overlapping with the spare wiring 48.
  • the slit 444 is formed of an elongated opening extending linearly in parallel with the Y-axis direction, that is, the extending direction of the source wiring 427, and both ends thereof have a semicircular shape when viewed in a plane.
  • the slit forming portion 427a in which the slit 444 is formed is divided into two, and these are defined as two divided portions 427a1.
  • the second source wiring 427B includes a slit forming portion 427a and a slit non-forming portion 427b in which the slit 444 is not formed.
  • the slit forming portion 427a and the slit non-forming portion 427b have the same line width.
  • the Therefore, the capacity wiring 33 has a substantially uniform size over almost the entire length, with the line width hardly changing in the middle.
  • a large number of source wirings 427 include a mixture of “first wirings” that do not have slits 444 and “second wirings” that have slits 444, and spare wirings 48 that intersect these. Is the “third wiring”.
  • FIG. 21 shows the gap between the second source wiring 427B in which a plurality of slits 444 are arranged in a line alternately in the X-axis direction and the first source wiring 427A in which no slit 444 is formed.
  • the transfer unit 445 is set over.
  • the bridge portion 445 is configured to extend along the X-axis direction, and is bridged between the two source wires 427A and 427B adjacent to each other.
  • the bridge portion 445 overlaps the source wirings 427A and 427B whose both ends are adjacent to each other in a plan view. As shown in FIG.
  • the transfer portion 445 is made of the same material as the gate wiring 426 and the spare wiring 48 and is formed in the same layer in the same process in the manufacturing process. That is, the bridge portion 445 has conductivity similar to the gate wiring 426 and the spare wiring 48, but is disposed on the lower layer side with respect to the source wirings 427 A and 427 B via the gate insulating film 435. In general, the source wiring 427 is kept in an insulated state.
  • the gate insulating film 435 is melted at the irradiated portion, so that The overlapping portion and the source wirings 427A and 427B are short-circuited.
  • a pair of the bridging portions 445 is arranged at a position sandwiching the spare wiring 48 in the extending direction between adjacent source wirings 427A and 427B, and does not have a slit 444.
  • Two sets are arranged for each first source wiring 427A and each second source wiring 427B having slits 444. That is, four transfer portions 445 are provided for each of the first source wiring 427A and the second source wiring 427B.
  • the pair of spanning portions 445 forming one set is arranged at a position closer to the spare wiring 48 than both ends of the slit 444 in the X-axis direction, that is, a position between the end of the slit 444 and the spare wiring 48. Has been.
  • the slit 444 is formed over a range that exceeds the pair of bridge portions 445 that sandwich the spare wiring 48 in the second source wiring 427B.
  • the bridge portion 445 bridges the slit forming portion 427a and the first source wire 427A of the second source wiring 427B, and more specifically, of the two divided portions 427a1 constituting the slit forming portion 427a.
  • the first source wiring 427A are bridged. That is, the bridging portion 445 is arranged for each of the two divided portions 427a1 with respect to the second source wiring 427B.
  • the pair of crossing portions 445 that form one set are separated from each other in the X-axis direction with respect to the first source wiring 427A adjacent to the other divided portion 427a1 on the side opposite to the other divided portion 427a1 side. It will be bridged at the position.
  • a pair of bridging portions 445 that bridges one dividing portion 427a1 and the first source wiring 427A, and a pair of bridging portions 445 that bridges the other dividing portion 427a1 and the first source wiring 427A opposite to the above. Are arranged at substantially the same position in the X-axis direction.
  • the repair is performed as follows. For example, when a short circuit occurs at the intersection between the spare wiring 48 and the first source wiring 427A, the shorted spare wiring 48 and the pair of bridge portions 445 in the X-axis direction of the first source wiring 427A The short-circuited portion is separated from the main body portion of the first source wiring 427A by irradiating the laser beam to the two positions between and cutting. On the other hand, the laser beam is irradiated to the portion of the bridge portion 445 that overlaps with the first source wiring 427A in which the short circuit occurs and the portion that overlaps with the second source wiring 427B in plan view.
  • the overlapping portions in the transfer portion 445 are short-circuited to the source wirings 427A and 427B. Further, among the two divided portions 427a1 arranged across the slit 444 in the second source wiring 427B, the divided portion 427a1 short-circuited with the first source wiring 427A by the transfer portion 445 is irradiated with laser light. Cut this off. As described above, a signal supplied to the first source wiring 427A short-circuited to the spare wiring 48 is a part of the second source wiring 427B adjacent from the main body portion of the first source wiring 427A via the bridge portion 445.
  • the spare wiring 48 short-circuited to the first source wiring 427A can be used for repair when the other source wiring 427 is disconnected.
  • a repair wiring 49 is provided separately from the gate wiring 526 and the capacitor wiring 533.
  • a repair wiring 49 for repairing each wiring 526, 533 is formed between the adjacent gate wiring 526 and the capacitor wiring 533.
  • the repair wiring 49 extends in parallel to the gate wiring 526 and the capacitor wiring 533 and extends over a predetermined range across the lead wiring 543.
  • a pair of repair wirings 49 are arranged at positions sandwiching the respective gate wirings 526, and a pair of repair wirings 49 are disposed at positions sandwiching the respective capacitive wirings 533. That is, a pair of repair wirings 49 are individually arranged adjacent to each other in the Y-axis direction in each gate wiring 526 and each capacitance wiring 533.
  • the repair wiring 49 is made of the same material as the gate wiring 526 and the capacitor wiring 533 and is formed in the same layer in the same process in the manufacturing process. Note that slits 544 are formed in all gate wirings 526 and capacitor wirings 533 so as to straddle the routing wirings 543.
  • a bridge portion 545 is bridged between the adjacent repair wiring 49, the gate wiring 526, and the capacitor wiring 533. Therefore, when the gate wiring 526 or the capacitor wiring 533 is short-circuited to the routing wiring 543, the short-circuited portion is separated from the main body portion, and the repair wiring 49 adjacent to the main body portion is connected to the transfer portion 545. By short-circuiting, it is possible to transmit a signal or the like using the repair wiring 49 as a bypass. Thereby, since the signal etc. can be transmitted using both the short-circuited gate wiring 526 or the main body portion of the capacity wiring 533 and the repair wiring 49, the gate wiring 526 or the capacity wiring 533 and the wiring which do not require repair are transmitted. The effect that resistance becomes equal is obtained.
  • a seventh embodiment will be described with reference to FIG.
  • the seventh embodiment should also be referred to as a modification of the above-described sixth embodiment, and shows a case where repair wiring 649 is provided using a part of the light shielding portion 50.
  • the light shielding portion 50 is formed adjacent to the gate wiring 626.
  • the light shielding portion 50 is made of a conductive metal material, and is formed in a solid shape over a predetermined range.
  • a slit 51 is formed in a portion of the light shielding portion 50 adjacent to the gate wiring 626, thereby forming a repair wiring 649 that straddles the lead wiring 643.
  • a pair of spanning portions 645 is spanned. As a result, even when the gate wiring 626 is short-circuited to the routing wiring 643, the repair can be performed by using the repair wiring 649 and the transfer portion 645.
  • the slits 744 are formed in all of the gate wiring 726 and the capacitor wiring 733, and the slits 52 are also formed in the routing wiring 743 that intersects these. Yes. Therefore, when a short circuit occurs at the intersection between the gate wiring 726 or the capacitor wiring 733 and the lead wiring 743, the gate wiring 726 or the capacitor wiring 733 and the lead wiring 743 are respectively located at two positions sandwiching the short circuit portion. Repair can be performed by cutting the divided portion.
  • a ninth embodiment will be described with reference to FIG.
  • the ninth embodiment should be referred to as a modification of the above-described eighth embodiment, and shows a configuration in which a plurality of slits 844 and 852 are formed.
  • three slits 844 are formed in each of the gate wiring 826 and the capacitor wiring 833, and three slits 852 are also formed in the lead wiring 843.
  • the slit extending over the first routing wiring is formed only on the capacitor wiring.
  • the slit extending over the first routing wiring is formed on all of the gate wiring and the capacitance wiring. It doesn't matter if you do.
  • a second slit that straddles the second lead wiring may be formed in all of the gate wiring and the capacitor wiring.
  • the configuration related to the intersection of the two routing wirings, the gate wiring, and the capacitance wiring is illustrated, but the intersection of three or more routing wirings, the gate wiring, and the capacitance wiring
  • the technique can be applied to the portions as in the third embodiment. Specifically, as many as the number of routing lines crossing the gate wiring and the capacity wiring, slits are formed so as to straddle each routing line, and a pair of bridging portions are provided at positions straddling each routing line. What is necessary is just to form.
  • the capacitor wiring or the gate wiring has been shown to have the same line width in the slit forming portion and the slit non-forming portion. A configuration in which the width is changed is also possible.
  • the slit forming range extends beyond the pair of spanning portions.
  • the slit forming range is set to be equal to the distance between the pair of spanning portions. It is also possible to set it to be shorter than the distance between the pair of spanning parts.
  • the cold cathode tube is used as the light source of the backlight device that constitutes the liquid crystal display device, but other light sources such as a hot cathode tube and an LED are also used. It is included in the present invention.
  • the direct type is exemplified as the backlight device included in the liquid crystal display device, but the present invention includes one using an edge light type backlight device.
  • a transmissive liquid crystal display device including a backlight device as an external light source has been exemplified.
  • the present invention is a reflective liquid crystal display that performs display using external light.
  • the present invention can also be applied to a device, in which case the backlight device can be omitted.
  • the TFT is used as the switching element of the liquid crystal display device.
  • the present invention can be applied to a liquid crystal display device for monochrome display.
  • the liquid crystal display device using the liquid crystal panel as the display panel is exemplified, but the present invention is also applied to a display device using another type of display panel (PDP, organic EL panel, etc.).
  • the invention is applicable. In that case, the backlight device can be omitted.

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Abstract

An array board (device board) comprises: gate wires (first wires) (26); capacitance wires (second wires) (33) arranged in parallel with and adjacent to the gate wires; a guiding wire (third wire) (43) crossing the gate and capacitance wires with a gate insulating film (insulating layer) intervening between the guiding wire and the gate and capacitance wires; slits (44) arranged at least in those portions of the capacitance wires which cross over the guiding wire; and at least one pair of bridges (45) positioned and arranged such that the guiding wire exists between the bridges and that the gate insulating film intervenes between the pair of bridges and the gate and capacitance wires to insulate the pair of bridges from the gate and capacitance wires and that each bridge extends between the gate and capacitance wires.

Description

素子基板、表示装置、テレビ受信装置、及び素子基板の製造方法Element substrate, display device, television receiver, and element substrate manufacturing method
 本発明は、素子基板、表示装置、テレビ受信装置、及び素子基板の製造方法に関する。 The present invention relates to an element substrate, a display device, a television receiver, and a method for manufacturing the element substrate.
 液晶表示装置に用いられる液晶パネルは、一対のガラス基板間に液晶層が挟持された構成とされているが、そのうち一方のガラス基板は、各画素の動作を制御するためのアクティブ素子としてTFTが形成されたアレイ基板とされる。このアレイ基板における表示領域には、ゲート配線とソース配線とが多数本ずつ格子状に設けられ、ゲート配線とソース配線との交差箇所にTFTが設けられた構成を有している。また、隣り合うゲート配線の間には、ゲート配線に並行する容量配線がそれぞれ形成されている。一方、アレイ基板における非表示領域には、ソース配線に並行するとともに各ゲート配線及び各容量配線を横切る形で引廻配線が形成されており、この引廻配線がコンタクトホールを介して横切る各容量配線に対して接続されることで、引廻配線を介して各容量配線に信号を供給することが可能とされている。 A liquid crystal panel used for a liquid crystal display device has a structure in which a liquid crystal layer is sandwiched between a pair of glass substrates. One of the glass substrates has a TFT as an active element for controlling the operation of each pixel. The formed array substrate is used. The display area of the array substrate has a structure in which a large number of gate lines and source lines are provided in a grid pattern, and TFTs are provided at intersections between the gate lines and the source lines. In addition, between the adjacent gate lines, capacitor lines parallel to the gate lines are formed. On the other hand, in the non-display area of the array substrate, a lead-out line is formed in parallel with the source line and across each gate line and each capacitor line. By being connected to the wiring, it is possible to supply a signal to each capacitor wiring through the lead wiring.
 ところで、引廻配線と各ゲート配線との交差部分は絶縁層を介して相互に絶縁状態に保たれているものの、アレイ基板の製造過程で発生する静電気などの影響によって絶縁層が破壊されるおそれがあり、そうなると引廻配線とゲート配線とが短絡される可能性があった。このような問題に対処したものの一例として下記特許文献1に記載されたものが知られている。 By the way, although the intersections between the routing wiring and each gate wiring are kept insulative with each other via the insulating layer, the insulating layer may be destroyed by the influence of static electricity generated during the manufacturing process of the array substrate. Then, there is a possibility that the lead wiring and the gate wiring are short-circuited. As an example of one that addresses such a problem, one described in Patent Document 1 below is known.
特開2005-215094号公報Japanese Patent Laid-Open No. 2005-215094
(発明が解決しようとする課題)
 上記した特許文献1では、引廻配線にスリットを形成することで引廻配線を複数に分割しており、短絡が生じた場合には、引廻配線におけるスリットにより分割された部分のうち短絡箇所を有する部分を選択的に切り離すことで、修理を行うようにしている。しかしながら、スリットを設けるために引廻配線の線幅が大きくなってしまい、それにより各ゲート配線及び各容量配線との重畳面積も大きなものとなっていた。このため、引廻配線と各ゲート配線との間に生じる寄生容量が大きくなって、各ゲート配線に伝送される信号に鈍りが生じ易くなったり、また、重畳面積が大きいがために、引廻配線と各ゲート配線及び各容量配線との間に短絡が生じ易くなるなどの問題が生じるおそれがあった。
(Problems to be solved by the invention)
In the above-mentioned Patent Document 1, a slit is formed in the lead wiring to divide the lead wiring into a plurality of parts, and when a short circuit occurs, a short-circuit portion in a portion divided by the slit in the lead wiring. Repair is performed by selectively cutting off the portion having the. However, since the slits are provided, the line width of the routing wiring is increased, and the overlapping area with each gate wiring and each capacitance wiring is increased accordingly. For this reason, the parasitic capacitance generated between the routing wiring and each gate wiring is increased, the signal transmitted to each gate wiring is likely to become dull, and the overlapping area is large. There is a risk that a short circuit is likely to occur between the wiring and each gate wiring and each capacitor wiring.
 本発明は上記のような事情に基づいて完成されたものであって、第1配線及び第2配線と第3配線との重畳面積を小さくしつつ短絡発生時の修理を行うのに好適な素子基板を提供することを目的とする。 The present invention has been completed based on the above situation, and is an element suitable for repairing when a short circuit occurs while reducing the overlapping area of the first wiring, the second wiring, and the third wiring. An object is to provide a substrate.
(課題を解決するための手段)
 本発明の素子基板は、第1配線と、前記第1配線に並行するとともに前記第1配線に隣り合って配される第2配線と、前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第3配線と、前記第2配線のうち少なくとも前記第3配線を跨ぐ部分に配されるスリットと、前記第3配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される架渡し部と、を備える。
(Means for solving problems)
The element substrate of the present invention includes a first wiring, a second wiring that is parallel to the first wiring and arranged adjacent to the first wiring, and an insulating layer for the first wiring and the second wiring. A third wiring intersecting with each other through, a slit disposed in at least a portion of the second wiring straddling the third wiring, and at least a pair disposed at a position sandwiching the third wiring, By being arranged with respect to the first wiring and the second wiring through an insulating layer, the first wiring and the second wiring are insulated and spanned between the first wiring and the second wiring. And a transfer section.
 第1配線及び第2配線は、その間に架け渡される架渡し部に対して絶縁層を介して配されることで架渡し部とは絶縁されているから、第1配線及び第2配線と第3配線との交差部分に短絡が生じていなければ、第1配線、第2配線及び第3配線のそれぞれに信号などを伝送させることができる。 Since the first wiring and the second wiring are insulated from the bridging portion by being arranged via the insulating layer with respect to the bridging portion spanned between the first wiring and the second wiring, If a short circuit does not occur at the intersection with the three wirings, a signal or the like can be transmitted to each of the first wiring, the second wiring, and the third wiring.
 ここで、例えば、第1配線と第3配線との交差部分に短絡が生じた場合には、第1配線のうち、第3配線を挟み且つ少なくとも一対の架渡し部の間に挟まれる部分を切断して第1配線から切り離す。一方、第1配線とそれに隣り合う第2配線との間に架け渡された少なくとも一対の架渡し部を、第1配線及び第2配線に対してそれぞれ短絡させる。さらには、第2配線においてスリットを挟んで配される複数の部分のうち、第1配線に対して少なくとも一対の架渡し部により短絡される部分を切断して第2配線から切り離す。以上により、第2配線の一部を利用して第1配線に信号などを伝送させることができる。 Here, for example, when a short circuit occurs at the intersection of the first wiring and the third wiring, a portion of the first wiring that sandwiches the third wiring and is sandwiched between at least a pair of the bridging portions. Disconnect and disconnect from the first wiring. On the other hand, at least a pair of the bridging portions spanned between the first wiring and the second wiring adjacent thereto are short-circuited to the first wiring and the second wiring, respectively. Further, among the plurality of portions arranged across the slit in the second wiring, a portion that is short-circuited by at least a pair of bridge portions with respect to the first wiring is cut and separated from the second wiring. As described above, a signal or the like can be transmitted to the first wiring by using a part of the second wiring.
 このように、第1配線に隣り合う第2配線の一部を、第1配線に短絡が生じた場合の修理に利用することができるから、仮に第3配線にスリットを設けることで対応した場合に比べると、第3配線の線幅を小さくすることができる。第3配線は、第1配線及び第2配線の双方に対して交差するものであるから、その線幅が小さくなれば、第1配線及び第2配線との重畳面積も小さくなる。従って、第1配線及び第2配線と第3配線との間に生じ得る寄生容量が小さくなり、また短絡が生じる可能性自体が低減される、などの効果を得ることができる。また、仮に第1配線及び第2配線とは別途に修理専用の配線を設けた場合に比べると、第1配線と第2配線との間のスペースを小さくすることができるので、省スペース化などを図る上で好適となる。 As described above, since a part of the second wiring adjacent to the first wiring can be used for repair when a short circuit occurs in the first wiring, it is possible to cope by providing a slit in the third wiring. As compared with the above, the line width of the third wiring can be reduced. Since the third wiring intersects with both the first wiring and the second wiring, the overlapping area between the first wiring and the second wiring decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the first wiring, the second wiring, and the third wiring is reduced, and the possibility that a short circuit occurs is reduced. In addition, the space between the first wiring and the second wiring can be reduced as compared with the case where the wiring dedicated for repair is provided separately from the first wiring and the second wiring, so that space saving can be achieved. This is suitable for achieving the above.
 なお、例えば、第2配線においてスリットを挟んで配される複数の部分のうちの一つと第3配線との交差部分に短絡が生じた場合には、第2配線においてスリットを挟んで配される複数の部分のうち、第3配線と短絡した部分を切断することで、第3配線とは短絡していない部分を利用して第2配線に信号などを伝送させることができる。 For example, when a short circuit occurs at the intersection of the third wiring and one of the plurality of parts arranged with the slit in the second wiring, the second wiring is arranged with the slit in between. By cutting a portion short-circuited with the third wiring among the plurality of portions, a signal or the like can be transmitted to the second wiring using a portion that is not short-circuited with the third wiring.
 本発明の実施態様として、次の構成が好ましい。
(1)前記第1配線と前記第2配線とは、交互に並ぶ形で複数ずつ配されている。このようにすれば、仮に第1配線または第2配線を複数続けて並べた場合に比べると、架渡し部の設置数を多くすることが可能となり、もって修理の自由度を高める上で好適となる。
The following configuration is preferable as an embodiment of the present invention.
(1) A plurality of the first wirings and the second wirings are arranged alternately. In this way, it is possible to increase the number of installations of the transfer section, as compared with the case where a plurality of the first wirings or the second wirings are continuously arranged, which is preferable in increasing the degree of freedom of repair. Become.
(2)前記架渡し部は、前記第1配線と、前記第1配線を挟んで隣り合う一対の前記第2配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている。このようにすれば、第1配線が第3配線と短絡した場合、その第1配線に対して隣り合う一対の第2配線のいずれをも修理に利用することができるから、修理を行う上での自由度が高まる。例えば、第3配線と短絡した第1配線に対して隣り合う一方の第2配線が第3配線と短絡した場合でも、第1配線に対して隣り合う他方の第2配線を利用して第1配線の信号を伝送するよう修理しつつ、一方の第2配線については第3配線との短絡箇所を切り離すことで修理を行うことができる。 (2) At least a pair of the bridging portions are formed so as to bridge between the first wiring and a pair of the second wirings adjacent to each other with the first wiring interposed therebetween. In this way, when the first wiring is short-circuited with the third wiring, any of the pair of second wirings adjacent to the first wiring can be used for repair. The degree of freedom increases. For example, even when one second wiring adjacent to the first wiring short-circuited with the third wiring is short-circuited with the third wiring, the first second wiring adjacent to the first wiring is used to make the first wiring. While repairing to transmit the signal of the wiring, it is possible to repair the one second wiring by separating the short-circuited portion from the third wiring.
(3)前記第1配線と前記一対の第2配線のうちの一方の前記第2配線との間を架け渡す一方の前記架渡し部と、前記第1配線と前記一対の第2配線のうちの他方の前記第2配線との間を架け渡す他方の前記架渡し部とは、前記第1配線の延在方向について互いにずれた位置に配されている。このようにすれば、仮に、一方の架渡し部と他方の架渡し部とを第1配線の延在方向について同じ位置に配した場合に比べると、一方の架渡し部と他方の架渡し部との間の距離が相対的に大きくなるから、一方の架渡し部と他方の架渡し部とが短絡し難くなる。 (3) One of the bridging portions that bridges between the first wiring and one of the pair of second wirings, and of the first wiring and the pair of second wirings The other bridging portion that bridges the other second wiring is arranged at a position shifted from each other in the extending direction of the first wiring. If it does in this way, compared with the case where one bridging part and the other bridging part are arranged in the same position about the extension direction of the 1st wiring, one bridging part and the other bridging part Since the distance between the two is relatively large, it is difficult to short-circuit one of the bridges and the other bridge.
(4)前記第2配線と前記第2配線を挟んで配される一対の前記第1配線のうちの一方の前記第1配線との間を架け渡す一方の前記架渡し部と、前記第2配線と前記一対の第1配線のうちの他方の前記第1配線との間を架け渡す他方の前記架渡し部とは、前記第2配線の延在方向について互いにずれた位置に配されている。このようにすれば、仮に、一方の架渡し部と他方の架渡し部とを第2配線の延在方向について同じ位置に配した場合に比べると、一方の架渡し部と他方の架渡し部との間の距離が相対的に大きくなるから、一方の架渡し部と他方の架渡し部とが短絡し難くなる。 (4) One of the bridging portions that bridges between the second wiring and the first wiring of one of the pair of the first wirings arranged across the second wiring, and the second wiring The other bridging portion that bridges between the wiring and the other first wiring of the pair of first wirings is disposed at a position shifted from each other in the extending direction of the second wiring. . If it does in this way, compared with the case where one bridging part and the other bridging part are arranged in the same position about the extension direction of the 2nd wiring, one bridging part and the other bridging part Since the distance between the two is relatively large, it is difficult to short-circuit one of the bridges and the other bridge.
(5)前記第2配線は、前記スリットが形成されるスリット形成部分と、前記スリットが形成されないスリット非形成部分とからなり、前記スリット形成部分と前記スリット非形成部分とで線幅が等しいものとされる。このようにすれば、第2配線の線幅がスリット形成部分とスリット非形成部分とで変化することがないから、製造が容易になるとともに省スペース化を図る上でもより好適となる。 (5) The second wiring includes a slit forming portion in which the slit is formed and a slit non-forming portion in which the slit is not formed, and the slit forming portion and the slit non-forming portion have the same line width. It is said. In this way, the line width of the second wiring does not change between the slit forming portion and the slit non-forming portion, which is more suitable for facilitating manufacture and space saving.
(6)前記架渡し部と前記第3配線とが同じ層に配されており、前記架渡し部及び前記第3配線と、前記第1配線及び前記第2配線との間に介在する前記絶縁層が同一とされている。このようにすれば、第3配線を形成する際に一括して架渡し部を形成することができるから、製造コストを低減する上で好適となる。 (6) The insulating portion interposed between the bridge portion and the third wire, and the first wire and the second wire, wherein the bridge portion and the third wire are arranged in the same layer. The layers are the same. This makes it possible to form the crossover portion all together when forming the third wiring, which is suitable for reducing the manufacturing cost.
(7)前記スリットは、前記第2配線において前記第3配線を挟む位置に配される少なくとも一対の前記架渡し部を超える範囲にわたって形成されている。このようにすれば、例えば、第1配線と第3配線との交差部分に短絡が生じた場合には、第2配線においてスリットを挟んで配される複数の部分のうち、第1配線に対して少なくとも一対の架渡し部により短絡される部分を切断する。このとき、第2配線における切断位置を、第2配線の延在方向についてスリットと重なる位置関係とすることができ、それにより第2配線の一部を直線的に横断する形で切断することが可能となる。従って、第2配線の一部を切り離す際の確実性が高くなるなどの効果を得ることができる。 (7) The slit is formed over a range exceeding at least a pair of the spanning portions arranged at a position sandwiching the third wiring in the second wiring. In this way, for example, when a short circuit occurs at the intersection between the first wiring and the third wiring, the second wiring is connected to the first wiring out of the plurality of portions arranged with the slit interposed therebetween. Then, at least a portion that is short-circuited by the pair of bridge portions is cut. At this time, the cutting position in the second wiring can be set to a positional relationship that overlaps with the slit in the extending direction of the second wiring, so that a part of the second wiring can be cut in a straight line. It becomes possible. Therefore, it is possible to obtain an effect that the certainty at the time of separating a part of the second wiring is increased.
(8)前記第3配線に並行するとともに前記第3配線に隣り合って配され且つ前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第4配線と、前記第1配線のうち少なくとも前記第4配線を跨ぐ部分に配される第2のスリットと、前記第4配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される第2の架渡し部とを備える。このようにすれば、例えば、第2配線と第4配線との交差部分に短絡が生じた場合には、第2配線のうち、第4配線を挟み且つ少なくとも一対の第2の架渡し部の間に挟まれる部分を切断して第2配線から切り離す。一方、第2配線とそれに隣り合う第1配線との間に架け渡された少なくとも一対の第2の架渡し部を、第1配線及び第2配線に対してそれぞれ短絡させる。さらには、第1配線において第2のスリットを挟んで配される複数の部分のうち、第2配線に対して少なくとも一対の第2の架渡し部により短絡される部分を切断して第1配線から切り離す。以上により、第1配線の一部を利用して第2配線に信号などを伝送させることができる。 (8) Fourth wiring parallel to the third wiring and adjacent to the third wiring and intersecting the first wiring and the second wiring through an insulating layer, and the first wiring And at least a pair of second slits arranged in a portion straddling the fourth wiring, and at a position sandwiching the fourth wiring, and with respect to the first wiring and the second wiring The second wiring part is provided between the first wiring and the second wiring while being insulated from the first wiring and the second wiring by being arranged through an insulating layer. In this way, for example, when a short circuit occurs at the intersection of the second wiring and the fourth wiring, the fourth wiring among the second wirings is sandwiched and at least a pair of the second bridge portions The part sandwiched between them is cut and separated from the second wiring. On the other hand, at least a pair of second bridging portions spanned between the second wiring and the first wiring adjacent thereto are short-circuited to the first wiring and the second wiring, respectively. Furthermore, among the plurality of portions arranged across the second slit in the first wiring, the first wiring is cut by cutting at least a portion short-circuited by the pair of second bridging portions with respect to the second wiring. Disconnect from. As described above, a signal or the like can be transmitted to the second wiring by using a part of the first wiring.
 このように、第2配線にスリットを、第1配線に第2のスリットをそれぞれ形成しているから、仮に第2配線にスリット及び第2のスリットを共に形成した場合に比べると、第1配線と第2配線との間に生じ得る配線抵抗の差を軽減することができる。 Thus, since the slit is formed in the second wiring and the second slit is formed in the first wiring, the first wiring is compared with the case where both the slit and the second slit are formed in the second wiring. The difference in wiring resistance that can occur between the first wiring and the second wiring can be reduced.
 なお、例えば、第1配線において第2のスリットを挟んで配される複数の部分のうちの一つと第4配線との間に短絡が生じた場合には、第1配線において第2のスリットを挟んで配される複数の部分のうち、第4配線と短絡した部分を切断することで、第4配線とは短絡していない部分を利用して第1配線に信号などを伝送させることができる。 For example, when a short circuit occurs between one of a plurality of portions arranged across the second slit in the first wiring and the fourth wiring, the second slit is formed in the first wiring. By cutting a portion that is short-circuited with the fourth wiring among a plurality of portions arranged with being sandwiched, signals or the like can be transmitted to the first wiring using a portion that is not short-circuited with the fourth wiring. .
(9)前記第1配線と前記第2配線とは、交互に並ぶ形で複数ずつ配されており、前記架渡し部は、前記第1配線と、前記第1配線を挟んで隣り合う一対の前記第2配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されているのに対して、前記第2の架渡し部は、前記第2配線と、前記第2配線を挟んで隣り合う一対の前記第1配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている。このようにすれば、第1配線が第3配線と短絡した場合、その第1配線に対して隣り合う一対の第2配線のいずれをも修理に利用することができるのに加え、第2配線が第4配線と短絡した場合でも、その第2配線に対して隣り合う一対の第1配線のいずれをも修理に利用することができるから、修理を行う上での自由度が極めて高いものとなる。 (9) A plurality of the first wirings and the second wirings are arranged in an alternating manner, and the bridge portion includes a pair of adjacent ones sandwiching the first wiring and the first wiring. Whereas at least one pair is formed so as to bridge between the second wirings, the second bridging portion is a pair of the second wirings and the second wirings adjacent to each other. At least one pair is formed so as to bridge the first wiring. In this way, when the first wiring is short-circuited with the third wiring, any of the pair of second wirings adjacent to the first wiring can be used for repair, and in addition, the second wiring Even if a short circuit occurs with the fourth wiring, any one of the pair of first wirings adjacent to the second wiring can be used for repair, and the degree of freedom in repairing is extremely high. Become.
(10)前記第1配線または前記第2配線に接続される電極を少なくとも有するスイッチング素子を備える。このようにすれば、第1配線と第3配線との交差部分に生じる短絡、及び第2配線と第3配線との交差部分に生じる短絡をそれぞれ修理することができるから、スイッチング素子を適切に駆動することができる。 (10) A switching element having at least an electrode connected to the first wiring or the second wiring is provided. In this way, a short circuit occurring at the intersection of the first wiring and the third wiring and a short circuit occurring at the intersection of the second wiring and the third wiring can be repaired, respectively. Can be driven.
 次に、上記課題を解決するために、本発明の表示装置は、上記記載の素子基板と、前記素子基板と対向状をなす対向基板と、前記素子基板と前記対向基板との間に封入される液晶層とを備える。 Next, in order to solve the above problem, a display device of the present invention is sealed between the element substrate described above, a counter substrate facing the element substrate, and the element substrate and the counter substrate. A liquid crystal layer.
 このような表示装置によると、第1配線及び第2配線と第3配線との重畳面積を小さくしつつ短絡発生時にも好適に修理を行うことができるから、表示品位が高く且つ表示に係る信頼性が高いものとなる。また、このような表示装置は液晶表示装置として、種々の用途、例えばテレビやパソコンのディスプレイ等に適用でき、特に大型画面用として好適である。また、このような表示装置として、素子基板及び対向基板に向けて光を照射する照明装置を備えた構成とすれば、高い輝度が得られて表示品位により優れる。 According to such a display device, since the overlapping area of the first wiring, the second wiring, and the third wiring can be reduced and the repair can be suitably performed even when a short circuit occurs, the display quality is high and the display reliability is improved. It becomes a thing with high property. Further, such a display device can be applied as a liquid crystal display device to various uses such as a display of a television or a personal computer, and is particularly suitable for a large screen. In addition, when such a display device includes a lighting device that emits light toward the element substrate and the counter substrate, high luminance can be obtained and display quality can be improved.
 次に、上記課題を解決するために、本発明の素子基板の製造方法は、基板上に、第1配線と、前記第1配線に並行するとともに前記第1配線に隣り合って配される第2配線と、前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第3配線と、前記第2配線のうち少なくとも前記第3配線を跨ぐ部分に配されるスリットと、前記第3配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される架渡し部と、を形成する配線形成工程と、前記第1配線と前記第3配線との交差部分と、前記第2配線と前記第3配線との交差部分とに短絡が生じているか否かをそれぞれ検査する検査工程と、前記第1配線と前記第3配線との交差部分に短絡が生じていた場合には、前記第1配線のうち、前記第3配線を挟み且つ少なくとも一対の前記架渡し部の間に挟まれる部分を切断して前記第1配線から切り離す一方で、前記第1配線とそれに隣り合う前記第2配線との間に架け渡された少なくとも一対の前記架渡し部を、前記第1配線及び前記第2配線に対してそれぞれ短絡させ、さらには前記第2配線において前記スリットを挟んで配される複数の部分のうち前記第1配線に対して少なくとも一対の前記架渡し部により短絡される部分を切断して前記第2配線から切り離すようにし、また前記第2配線と前記第3配線との交差部分に短絡が生じていた場合には、前記第2配線において前記スリットを挟んで配される複数の部分のうち前記第3配線と短絡した部分を切断する、修理工程とを行う。 Next, in order to solve the above-described problem, a method for manufacturing an element substrate according to the present invention includes a first wiring and a first wiring arranged in parallel with the first wiring and adjacent to the first wiring. Two wirings, a third wiring intersecting the first wiring and the second wiring with an insulating layer interposed therebetween, a slit disposed in at least a portion of the second wiring across the third wiring, At least a pair is arranged at a position sandwiching the third wiring, and is insulated from the first wiring and the second wiring by being arranged through an insulating layer with respect to the first wiring and the second wiring. And a wiring forming step for forming a bridging portion that is bridged between the first wiring and the second wiring, an intersection between the first wiring and the third wiring, and the second wiring Whether or not a short circuit has occurred at the intersection of the wiring and the third wiring In the case where a short circuit has occurred at each of the inspection step for inspecting and the intersection of the first wiring and the third wiring, at least a pair of the bridges sandwiching the third wiring among the first wiring While cutting the portion sandwiched between the first wiring and separating from the first wiring, at least a pair of the bridging portions spanned between the first wiring and the second wiring adjacent to the first wiring, Each of the first wiring and the second wiring is short-circuited, and among the plurality of portions arranged across the slit in the second wiring, at least a pair of the bridging portions with respect to the first wiring The part to be short-circuited is cut off and separated from the second wiring, and when a short circuit occurs at the intersection of the second wiring and the third wiring, the slit is sandwiched in the second wiring. so Cutting the portion of short-circuited with the third wiring among the plurality of portions to be performed and a repair process.
 このように、第1配線に隣り合う第2配線の一部を、第1配線に短絡が生じた場合の修理に利用することができるから、仮に第3配線にスリットを設けることで対応した場合に比べると、第3配線の線幅を小さくすることができる。第3配線は、第1配線及び第2配線の双方に対して交差するものであるから、その線幅が小さくなれば、第1配線及び第2配線との重畳面積も小さくなる。従って、第1配線及び第2配線と第3配線との間に生じ得る寄生容量が小さくなり、また短絡が生じる可能性自体が低減される、などの効果を得ることができる。また、仮に第1配線及び第2配線とは別途に修理専用の配線を設けた場合に比べると、第1配線と第2配線との間のスペースを小さくすることができるので、省スペース化などを図る上で好適となる。 As described above, since a part of the second wiring adjacent to the first wiring can be used for repair when a short circuit occurs in the first wiring, it is possible to cope by providing a slit in the third wiring. As compared with the above, the line width of the third wiring can be reduced. Since the third wiring intersects with both the first wiring and the second wiring, the overlapping area between the first wiring and the second wiring decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the first wiring, the second wiring, and the third wiring is reduced, and the possibility that a short circuit occurs is reduced. In addition, the space between the first wiring and the second wiring can be reduced as compared with the case where the wiring dedicated for repair is provided separately from the first wiring and the second wiring, so that space saving can be achieved. This is suitable for achieving the above.
(発明の効果)
 本発明によれば、第1配線及び第2配線と第3配線との重畳面積を小さくしつつ短絡発生時の修理を行うのに好適な素子基板を提供することができる。
(The invention's effect)
ADVANTAGE OF THE INVENTION According to this invention, the element board | substrate suitable for performing the repair at the time of the occurrence of a short circuit can be provided, reducing the overlapping area of 1st wiring, 2nd wiring, and 3rd wiring.
本発明の実施形態1に係るテレビ受信装置の概略構成を示す分解斜視図1 is an exploded perspective view showing a schematic configuration of a television receiver according to Embodiment 1 of the present invention. テレビ受信装置が備える液晶表示装置の概略構成を示す分解斜視図The exploded perspective view which shows schematic structure of the liquid crystal display device with which a television receiver is equipped 液晶表示装置の断面構成を概略的に示す断面図Sectional drawing which shows schematically the cross-sectional structure of a liquid crystal display device 液晶パネルの断面構成を概略的に示す断面図Sectional drawing which shows the cross-sectional structure of a liquid crystal panel roughly 液晶パネルを構成するアレイ基板における表示領域の平面構成を示す平面図The top view which shows the plane structure of the display area in the array substrate which comprises a liquid crystal panel 液晶パネルを構成するCF基板における表示領域の平面構成を示す平面図The top view which shows the plane structure of the display area in CF substrate which comprises a liquid crystal panel 図5のvii-vii線断面図Vii-vii cross-sectional view of FIG. 液晶パネルを構成するアレイ基板における配線構成を概略的に示す平面図A plan view schematically showing a wiring configuration in an array substrate constituting a liquid crystal panel ゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the intersection of gate wiring and capacity wiring, and lead wiring 図9のx-x線断面図Xx sectional view of FIG. 図9のxi-xi線断面図Xi-xi sectional view of FIG. ゲート配線と引廻配線とが短絡した場合や、容量配線と引廻配線とが短絡した場合の修理方法を示す平面図Plan view showing the repair method when the gate wiring and lead-out wiring are short-circuited, or when the capacity wiring and lead-out wiring are short-circuited 実施形態1の変形例1に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring which concerns on the modification 1 of Embodiment 1, and a capacity | capacitance wiring and lead wiring. 実施形態1の変形例2に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the intersection part of the gate wiring which concerns on the modification 2 of Embodiment 1, and a capacity | capacitance wiring and a lead wiring. 実施形態1の変形例3に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the intersection part of the gate wiring which concerns on the modification 3 of Embodiment 1, and a capacity | capacitance wiring and a lead wiring. 本発明の実施形態2に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring which concerns on Embodiment 2 of this invention, a capacity | capacitance wiring, and a lead wiring. 架渡し部にパターニング不良が生じた場合を示す平面図A plan view showing a case where a patterning defect occurs in the transfer part 本発明の実施形態3に係るゲート配線と引廻配線とが短絡した場合の修理方法を示す平面図The top view which shows the repair method when the gate wiring and lead wiring which concern on Embodiment 3 of this invention short-circuit 本発明の実施形態4に係る架渡し部とゲート配線及び容量配線との積層関係を示す断面図Sectional drawing which shows the lamination | stacking relationship between the bridge | bridging part which concerns on Embodiment 4 of this invention, a gate wiring, and a capacity | capacitance wiring 本発明の実施形態5に係る液晶パネルを構成するアレイ基板における配線構成を概略的に示す平面図The top view which shows roughly the wiring structure in the array board | substrate which comprises the liquid crystal panel which concerns on Embodiment 5 of this invention. ソース配線と予備配線との交差部分における構成を示す平面図Plan view showing the configuration at the intersection of source wiring and spare wiring 図21のxxii-xxii線断面図Xxii-xxii cross-sectional view of FIG. 図21のxxiii-xxiii線断面図Xxiii-xxiii sectional view of FIG. 実施形態6に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring which concerns on Embodiment 6, and the capacity | capacitance wiring and the lead wiring. 実施形態7に係るゲート配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring which concerns on Embodiment 7, and routing wiring 実施形態8に係るゲート配線及び容量配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring which concerns on Embodiment 8, and a capacity | capacitance wiring and a lead wiring. 実施形態9に係るゲート配線と引廻配線との交差部分における構成を示す平面図The top view which shows the structure in the cross | intersection part of the gate wiring and the lead wiring which concern on Embodiment 9.
 <実施形態1>
 本発明の実施形態1を図1から図12によって説明する。本実施形態では、液晶表示装置10を構成する液晶パネル(表示パネル)11に備えられるアレイ基板20の製造方法について例示する。なお、各図面の一部にはX軸、Y軸及びZ軸を示しており、各軸方向が各図面で示した方向となるように描かれている。また、図3に示す上側を表側とするとともに同図下側を裏側とする。
<Embodiment 1>
A first embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a method for manufacturing the array substrate 20 provided in the liquid crystal panel (display panel) 11 constituting the liquid crystal display device 10 is illustrated. In addition, a part of each drawing shows an X axis, a Y axis, and a Z axis, and each axis direction is drawn to be a direction shown in each drawing. Moreover, let the upper side shown in FIG. 3 be a front side, and let the lower side of the figure be a back side.
 本実施形態に係るテレビ受信装置TVは、図1に示すように、液晶表示装置(表示装置)10と、当該液晶表示装置10を挟むようにして収容する表裏両キャビネットCa,Cbと、電源Pと、チューナーTと、スタンドSとを備えて構成される。液晶表示装置10は、全体として横長の方形をなし、図2及び図3に示すように、表示パネルである液晶パネル11と、外部光源であるバックライト装置(照明装置)12とを備え、これらがベゼル13などにより一体的に保持されるようになっている。 As shown in FIG. 1, the television receiver TV according to this embodiment includes a liquid crystal display device (display device) 10, front and back cabinets Ca and Cb that are accommodated so as to sandwich the liquid crystal display device 10, a power supply P, A tuner T and a stand S are provided. The liquid crystal display device 10 has a horizontally long rectangular shape as a whole, and includes a liquid crystal panel 11 as a display panel and a backlight device (illumination device) 12 as an external light source, as shown in FIGS. Is integrally held by the bezel 13 or the like.
 先に、バックライト装置12の構成の概略について説明する。バックライト装置12は、液晶パネル11の背面直下に光源を配置してなる、いわゆる直下型とされる。バックライト装置12は、表側(光出射側、液晶パネル11側)に開口した光出射部を有するシャーシ14と、シャーシ14内に敷設される反射シート(反射部材)15と、シャーシ14の光出射部を覆うようにして取り付けられる光学部材16と、光学部材16を保持するためのフレーム17と、シャーシ14内に並列した状態で収容される複数本の冷陰極管(光源)18と、冷陰極管18の端部を遮光するとともに自身が光反射性を備えてなるランプホルダ19と、を有して構成されている。 First, an outline of the configuration of the backlight device 12 will be described. The backlight device 12 is a so-called direct type in which a light source is disposed directly under the back surface of the liquid crystal panel 11. The backlight device 12 includes a chassis 14 having a light emitting portion opened on the front side (light emitting side, liquid crystal panel 11 side), a reflective sheet (reflecting member) 15 laid in the chassis 14, and light emitting from the chassis 14. An optical member 16 attached so as to cover the portion, a frame 17 for holding the optical member 16, a plurality of cold cathode tubes (light sources) 18 accommodated in parallel in the chassis 14, and a cold cathode The lamp holder 19 is configured to shield the end of the tube 18 and to have light reflectivity.
 次に、液晶パネル11について説明する。液晶パネル11は、図4に示すように、一対の基板20,21間に、電界印加に伴って光学特性が変化する物質である液晶材料を含む液晶層22を封入してなる。液晶パネル11は、画面中央側の領域が画像を表示可能な表示領域(内周側領域)AAとされるのに対し、画面外周端側にあって表示領域AAを取り囲む枠状(額縁状)の領域が画像を表示不能な非表示領域(外周側領域)NAAとされる(図8を参照)。なお、図8において一点鎖線で囲った内側の領域が表示領域AAを示している。また、両基板20,21の外面側には、表裏一対の偏光板23がそれぞれ貼り付けられている。 Next, the liquid crystal panel 11 will be described. As shown in FIG. 4, the liquid crystal panel 11 is formed by enclosing a liquid crystal layer 22 containing a liquid crystal material, which is a substance whose optical characteristics change with application of an electric field, between a pair of substrates 20 and 21. The liquid crystal panel 11 has a frame shape (frame shape) surrounding the display area AA on the outer periphery side of the screen, whereas the area on the center side of the screen is a display area (inner periphery area) AA capable of displaying an image. This area is a non-display area (outer peripheral area) NAA incapable of displaying an image (see FIG. 8). In FIG. 8, the inner area surrounded by the alternate long and short dash line indicates the display area AA. In addition, a pair of front and back polarizing plates 23 are respectively attached to the outer surface sides of the substrates 20 and 21.
 液晶パネル11を構成する一対の基板20,21のうち裏側(バックライト装置12側)に配されるものが、図4に示すように、アレイ基板(素子基板、アクティブマトリクス基板)20とされ、表側(光出射側)に配されるものが、CF基板(対向基板)21とされている。これらアレイ基板20及びCF基板21は、それぞれ透明な(透光性を有する)ガラス基板GS上に後述する様々な構造物(薄膜)を積層形成してなるものとされる。 Of the pair of substrates 20 and 21 constituting the liquid crystal panel 11, the one disposed on the back side (backlight device 12 side) is an array substrate (element substrate, active matrix substrate) 20, as shown in FIG. A substrate disposed on the front side (light emitting side) is a CF substrate (counter substrate) 21. Each of the array substrate 20 and the CF substrate 21 is formed by laminating various structures (thin films) described later on a transparent (translucent) glass substrate GS.
 先に、アレイ基板20における表示領域AAに係る構成の概略について説明する。アレイ基板20(ガラス基板GS)における内面側(液晶層22側、CF基板21との対向面側、配線形成面)の表示領域AAには、図5に示すように、3つの電極24a~24cを有するスイッチング素子であるTFT(Thin Film Transistor)24及び画素電極25が多数個並んで設けられるとともに、これらTFT24及び画素電極25の周りには、格子状をなす、X軸方向に沿って延在する多数本のゲート配線(第1配線)26と、Y軸方向に沿って延在する多数本のソース配線27とが取り囲むようにして配設されている。ゲート配線26とソース配線27とがそれぞれTFT24のゲート電極24aとソース電極24bとに接続され、画素電極25がドレイン配線34を介してTFT24のドレイン電極24cに接続されている。アレイ基板20には、ゲート配線26に並行するとともに画素電極25に対して平面に視て重畳する容量配線(第2配線、補助容量配線、蓄積容量配線、Cs配線)33が多数本設けられている。この容量配線33は、ゲート配線26と同一材料からなり且つ製造工程における同一工程にて同一層に形成されている。容量配線33とゲート配線26とは、Y軸方向について交互に並ぶ形で多数本ずつ配されている。ゲート配線26は、Y軸方向に隣り合う画素電極25の間に配されているのに対し、容量配線33は、各画素電極25におけるY軸方向のほぼ中央部を横切る位置に配されている。互いに並行するゲート配線26及び容量配線33とこれらと交差するソース配線27とは、交差部分において後述するゲート絶縁膜(絶縁層)35が介在することで相互に絶縁状態に保たれている。一方、平面に視て互いに重畳する画素電極25とソース配線27とは、後述する層間絶縁膜37及び保護膜38が介在することで相互に絶縁状態に保たれている(図7を参照)。また、画素電極25は、ITO(Indium Tin Oxide)などの透光性導電材料(透明導電材料)からなる。ゲート配線26及びソース配線27は、共に導電性金属材料からなる。特に、ソース配線27については、異なる金属膜39,40を積層してなる2層構造とされており、そのうち下層側の金属膜39がチタン(Ti)からなるのに対し、上層側の金属膜40がアルミニウム(Al)からなる(図7を参照)。なお、アレイ基板20の内面側には、液晶層22に含まれる液晶分子を配向させるための配向膜28が形成されている(図4)。 First, an outline of the configuration related to the display area AA in the array substrate 20 will be described. As shown in FIG. 5, three electrodes 24a to 24c are provided in the display area AA on the inner surface side (the liquid crystal layer 22 side, the surface facing the CF substrate 21, and the wiring forming surface) of the array substrate 20 (glass substrate GS). A large number of TFTs (Thin Film Transistors) 24 and pixel electrodes 25 that are switching elements having a plurality of TFTs are provided side by side, and the TFTs 24 and the pixel electrodes 25 extend in the X-axis direction in a lattice shape. A large number of gate wirings (first wirings) 26 and a large number of source wirings 27 extending along the Y-axis direction are disposed so as to surround them. The gate wiring 26 and the source wiring 27 are connected to the gate electrode 24a and the source electrode 24b of the TFT 24, respectively, and the pixel electrode 25 is connected to the drain electrode 24c of the TFT 24 via the drain wiring 34. The array substrate 20 is provided with a large number of capacitor wirings (second wirings, auxiliary capacitor wirings, storage capacitor wirings, Cs wirings) 33 that are parallel to the gate wirings 26 and overlap the pixel electrodes 25 in plan view. Yes. The capacitor wiring 33 is made of the same material as the gate wiring 26 and is formed in the same layer in the same process in the manufacturing process. A large number of capacitor wirings 33 and gate wirings 26 are arranged in a line alternately in the Y-axis direction. The gate wiring 26 is disposed between the pixel electrodes 25 adjacent in the Y-axis direction, while the capacitor wiring 33 is disposed at a position that substantially crosses the central portion of each pixel electrode 25 in the Y-axis direction. . The gate wiring 26 and the capacitor wiring 33 that are parallel to each other and the source wiring 27 that intersects with the gate wiring 26 and the capacitor wiring 33 are kept in an insulated state by interposition of a gate insulating film (insulating layer) 35 to be described later. On the other hand, the pixel electrode 25 and the source wiring 27 that overlap each other in a plan view are kept in an insulated state by interposition of an interlayer insulating film 37 and a protective film 38 described later (see FIG. 7). The pixel electrode 25 is made of a translucent conductive material (transparent conductive material) such as ITO (Indium Tin Oxide). Both the gate wiring 26 and the source wiring 27 are made of a conductive metal material. In particular, the source wiring 27 has a two-layer structure in which different metal films 39 and 40 are laminated. Of these, the lower metal film 39 is made of titanium (Ti), whereas the upper metal film is formed. 40 is made of aluminum (Al) (see FIG. 7). An alignment film 28 for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the inner surface side of the array substrate 20 (FIG. 4).
 次に、CF基板21における表示領域AAに係る構成の概略について説明する。CF基板21(ガラス基板GS)における内面側(液晶層22側、アレイ基板20との対向面側)の表示領域AAには、図4及び図6に示すように、アレイ基板20側の各画素電極25と平面に視て重畳する位置に多数個のカラーフィルタが並んで設けられている。カラーフィルタは、R(赤色),G(緑色),B(青色)を呈する各着色部29がX軸方向に沿って交互に並ぶ配置とされる。また、各着色部29の外形は、画素電極25の外形に倣って平面に視て縦長の方形状をなしている。カラーフィルタを構成する各着色部29間には、混色を防ぐための格子状をなす遮光部(ブラックマトリクス)30が形成されている。遮光部30は、アレイ基板20側のゲート配線26、ソース配線27及び容量配線33に対して平面視重畳する配置とされる。また、各着色部29及び遮光部30の表面には、アレイ基板20側の画素電極25と対向する対向電極31が設けられている。なお、CF基板21の内面側には、液晶層22に含まれる液晶分子を配向させるための配向膜32がそれぞれ形成されている。 Next, an outline of the configuration related to the display area AA in the CF substrate 21 will be described. In the display area AA on the inner surface side (the liquid crystal layer 22 side, the surface facing the array substrate 20) of the CF substrate 21 (glass substrate GS), as shown in FIGS. A large number of color filters are arranged side by side at a position overlapping the electrode 25 in a plan view. In the color filter, the colored portions 29 exhibiting R (red), G (green), and B (blue) are arranged alternately along the X-axis direction. In addition, the outer shape of each colored portion 29 has a vertically long rectangular shape in plan view following the outer shape of the pixel electrode 25. Between each coloring part 29 which comprises a color filter, the light-shielding part (black matrix) 30 which makes the grid | lattice shape for preventing color mixing is formed. The light shielding portion 30 is disposed so as to overlap with the gate wiring 26, the source wiring 27, and the capacitor wiring 33 on the array substrate 20 in plan view. A counter electrode 31 is provided on the surface of each colored portion 29 and the light shielding portion 30 so as to face the pixel electrode 25 on the array substrate 20 side. An alignment film 32 for aligning liquid crystal molecules contained in the liquid crystal layer 22 is formed on the inner surface side of the CF substrate 21.
 ここで、アレイ基板20が有する構造物のうちスイッチング素子であるTFT24に関して詳しく説明する。TFT24は、図7に示すように、アレイ基板20をなすガラス基板GS上に複数の薄膜を順次に積層した構成とされており、具体的には下層側(ガラス基板GS側)から順に、ゲート配線26に接続されたゲート電極24a、ゲート絶縁膜(絶縁層)35、半導体膜36、ドーピング半導体膜42、ソース配線27に接続されたソース電極24b及びドレイン配線34に接続されたドレイン電極24c、層間絶縁膜(パッシベーション膜)37、保護膜38が積層されている。 Here, the TFT 24 that is a switching element in the structure of the array substrate 20 will be described in detail. As shown in FIG. 7, the TFT 24 has a structure in which a plurality of thin films are sequentially stacked on a glass substrate GS forming the array substrate 20, and specifically, gates in order from the lower layer side (glass substrate GS side). A gate electrode 24a connected to the wiring 26, a gate insulating film (insulating layer) 35, a semiconductor film 36, a doping semiconductor film 42, a source electrode 24b connected to the source wiring 27, and a drain electrode 24c connected to the drain wiring 34; An interlayer insulating film (passivation film) 37 and a protective film 38 are stacked.
 ゲート電極24aは、ゲート配線26と同一材料からなるとともにゲート配線26及び容量配線33と同一工程にてガラス基板GSの直上にパターニングされており、例えばアルミニウム(Al)の他、クロム(Cr)、タンタル(Ta)、チタン(Ti)、銅(Cu)等の金属膜単体又はこれらの積層膜で形成することができる。ゲート電極24aは、図5に示すように、X軸方向に沿って延在するゲート配線26におけるソース配線27との交差部付近からY軸方向に沿って延出する分岐線における延出先端部によって構成されている。ゲート絶縁膜35は、例えばシリコン窒化膜(SiNx)からなり、図7に示すように、ゲート電極24aと次述する半導体膜36とを絶縁状態に保つものとされる。このゲート絶縁膜35は、TFT24の形成領域のみならずガラス基板GSのほぼ全面にわたるベタ状のパターンとされている。ゲート絶縁膜35は、TFT24の形成領域外においては、相対的に下層側のゲート配線26及び容量配線33と、相対的に上層側のソース配線27及び後述する引廻配線43との交差部分の間に介在していてこれらをそれぞれ絶縁状態に保つものとされる。 The gate electrode 24a is made of the same material as the gate wiring 26 and is patterned immediately above the glass substrate GS in the same process as the gate wiring 26 and the capacitor wiring 33. For example, in addition to aluminum (Al), chromium (Cr), It can be formed of a single metal film such as tantalum (Ta), titanium (Ti), copper (Cu), or a laminated film thereof. As shown in FIG. 5, the gate electrode 24a extends from the vicinity of the intersection of the gate wiring 26 extending along the X-axis direction with the source wiring 27 in the branch line extending along the Y-axis direction. It is constituted by. The gate insulating film 35 is made of, for example, a silicon nitride film (SiNx), and as shown in FIG. 7, the gate electrode 24a and the semiconductor film 36 described below are kept in an insulating state. The gate insulating film 35 has a solid pattern that covers not only the TFT 24 formation region but also the entire surface of the glass substrate GS. Outside the formation region of the TFT 24, the gate insulating film 35 is located at the intersection of the relatively lower gate wiring 26 and the capacitor wiring 33, the relatively upper source wiring 27, and a later-described routing wiring 43. It is assumed that they are interposed between them and kept in an insulated state.
 半導体膜36は、例えばアモルファスシリコン(a‐Si)からなるものとされ、図7に示すように、一端側がソース電極24bに、他端側がドレイン電極24cにそれぞれ接続されることで、相互間の導通を図るチャネル領域CHを有している。ドーピング半導体膜42は、例えばリン(P)等のn型不純物を高濃度にドーピングしたアモルファスシリコン(n+Si)からなるものとされる。ドーピング半導体膜42は、半導体膜36に沿って延在するもののチャネル領域CHの範囲に関しては除去されており、そのチャネル領域CHを挟んで配される一対の部分が次述するソース電極24b及びドレイン電極24cの一部を構成している。 The semiconductor film 36 is made of, for example, amorphous silicon (a-Si). As shown in FIG. 7, one end side is connected to the source electrode 24b and the other end side is connected to the drain electrode 24c. It has a channel region CH for conducting. The doped semiconductor film 42 is made of amorphous silicon (n + Si) doped with an n-type impurity such as phosphorus (P) at a high concentration. The doping semiconductor film 42 extends along the semiconductor film 36 but is removed with respect to the range of the channel region CH, and a pair of portions arranged with the channel region CH interposed therebetween are a source electrode 24b and a drain described below. It constitutes a part of the electrode 24c.
 ソース電極24b及びドレイン電極24cは、図7に示すように、ソース配線27及びドレイン配線34と同一材料を含むとともにソース配線27及びドレイン配線34と同一工程にてガラス基板GS上にパターニングされている。ソース電極24b及びドレイン電極24cは、X軸方向について所定の間隔を空けつつ対向状に配置されている。ソース電極24b及びドレイン電極24cは、それぞれゲート電極24aに対してゲート絶縁膜35及び半導体膜36を介して上層側に配されるとともに、その一部(対向部分)がゲート電極24aに対して平面に視て重畳する位置に配され、その重畳部分がゲート電極24a上に乗り上げている。ソース電極24b及びドレイン電極24cは、下層側(半導体膜36側)の第1導電膜24b1,24c1と、上層側(層間絶縁膜37側)の第2導電膜24b2,24c2とを積層した構成とされる。下層側の第1導電膜24b1,24c1は、既述したドーピング半導体膜42の端部によってそれぞれ構成されており、下層側の半導体膜36に対してオーミック接触されるオーミックコンタクト層として機能するものである。上層側の第2導電膜24b2,24c2は、異なる金属膜を積層してなる2層構造とされており、そのうち下層側の金属膜39がチタン(Ti)からなるのに対し、上層側の金属膜40がアルミニウム(Al)からなる。つまり、ソース電極24b及びドレイン電極24cは、2層の金属膜39,40からなる第2導電膜24b2,24c2を有している点でソース配線27と共通しているが、ドーピング半導体膜42からなる第1導電膜24b1,24c1を有している点でソース配線27とは構成上異なる。また、ソース電極24bは、図5に示すように、Y軸方向に沿って延在するソース配線27におけるゲート配線26との交差部付近からX軸方向に沿って延出する分岐線における延出先端部によって構成されている。 As shown in FIG. 7, the source electrode 24 b and the drain electrode 24 c include the same material as the source wiring 27 and the drain wiring 34 and are patterned on the glass substrate GS in the same process as the source wiring 27 and the drain wiring 34. . The source electrode 24b and the drain electrode 24c are arranged to face each other with a predetermined interval in the X-axis direction. The source electrode 24b and the drain electrode 24c are disposed on the upper layer side with respect to the gate electrode 24a via the gate insulating film 35 and the semiconductor film 36, respectively, and a part (opposing portion) of the source electrode 24b and the drain electrode 24c is planar with respect to the gate electrode 24a. The overlapping portion is placed on the gate electrode 24a. The source electrode 24b and the drain electrode 24c are formed by laminating first conductive films 24b1 and 24c1 on the lower layer side (semiconductor film 36 side) and second conductive films 24b2 and 24c2 on the upper layer side (interlayer insulating film 37 side). Is done. The first conductive films 24b1 and 24c1 on the lower layer side are respectively constituted by the end portions of the doping semiconductor film 42 described above, and function as ohmic contact layers that are in ohmic contact with the semiconductor film 36 on the lower layer side. is there. The second conductive films 24b2 and 24c2 on the upper layer side have a two-layer structure in which different metal films are laminated, and the metal film 39 on the lower layer side is made of titanium (Ti), whereas the metal on the upper layer side is made. The film 40 is made of aluminum (Al). That is, the source electrode 24b and the drain electrode 24c are common to the source wiring 27 in that they have the second conductive films 24b2 and 24c2 made of two metal films 39 and 40. The structure differs from the source wiring 27 in that the first conductive films 24b1 and 24c1 are provided. Further, as shown in FIG. 5, the source electrode 24b extends along a branch line extending along the X-axis direction from the vicinity of the intersection with the gate wiring 26 in the source wiring 27 extending along the Y-axis direction. It is comprised by the front-end | tip part.
 層間絶縁膜37は、例えばシリコン窒化膜(SiNx)からなり、上記したゲート絶縁膜35と同一材料とされる。保護膜38は、有機材料であるアクリル樹脂(例えばポリメタクリル酸メチル樹脂(PMMA))やポリイミド樹脂からなる。従って、この保護膜38は、他の無機材料からなるゲート絶縁膜35、層間絶縁膜37に比べて膜厚が厚いものとされるとともに、平坦化膜として機能するものである。これら層間絶縁膜37及び保護膜38は、いずれもTFT24の形成領域のみならずガラス基板GSの概ね全面にわたる略ベタ状のパターンとされている。層間絶縁膜37及び保護膜38は、TFT24の形成領域外においては、相対的に下層側のソース配線27及びドレイン配線34と、相対的に上層側の画素電極25との間に介在していてこれらを絶縁状態に保つものとされる。 The interlayer insulating film 37 is made of, for example, a silicon nitride film (SiNx), and is made of the same material as the gate insulating film 35 described above. The protective film 38 is made of an acrylic resin (for example, polymethyl methacrylate resin (PMMA)) or a polyimide resin, which is an organic material. Therefore, the protective film 38 is thicker than the gate insulating film 35 and the interlayer insulating film 37 made of other inorganic materials and functions as a planarizing film. Each of the interlayer insulating film 37 and the protective film 38 has a substantially solid pattern that covers not only the region where the TFT 24 is formed but also the entire surface of the glass substrate GS. The interlayer insulating film 37 and the protective film 38 are interposed between the relatively lower source wiring 27 and drain wiring 34 and the relatively upper pixel electrode 25 outside the TFT 24 formation region. These are kept in an insulating state.
 上記のような構成とされるTFT24のうち、ドレイン電極24cに接続されるドレイン配線34は、図5に示すように、平面に視て略L字型をなしており、その一端側がドレイン電極24cに接続されるのに対して、他端側が画素電極25に対して接続される画素接続部41に接続されている。このドレイン配線34は、図7に示すように、ゲート絶縁膜35上に形成されるものであり、ソース配線27と同一の材料からなり且つ同一の2層構造とされており、チタン(Ti)からなる下層側の金属膜39と、アルミニウム(Al)からなる上層側の金属膜40とからなる。従って、ドレイン配線34は、ソース配線27と同様に、ソース電極24b及びドレイン電極24cのうち、第2導電膜24b2,24c2(39,40)のみからなり、第1導電膜24b1,24c1(42)を有していない点でこれらとは構成上異なる。 Of the TFT 24 configured as described above, the drain wiring 34 connected to the drain electrode 24c is substantially L-shaped in plan view as shown in FIG. 5, and one end side of the drain wiring 34 is connected to the drain electrode 24c. In contrast, the other end is connected to the pixel connection portion 41 connected to the pixel electrode 25. As shown in FIG. 7, the drain wiring 34 is formed on the gate insulating film 35, is made of the same material as the source wiring 27, and has the same two-layer structure. Titanium (Ti) A lower metal film 39 made of aluminum and an upper metal film 40 made of aluminum (Al). Therefore, the drain wiring 34 is composed of only the second conductive films 24b2 and 24c2 (39, 40) of the source electrode 24b and the drain electrode 24c, as in the case of the source wiring 27, and the first conductive films 24b1, 24c1 (42). It differs from these in that it does not have.
 続いて、アレイ基板20における非表示領域NAAに係る構成について説明する。アレイ基板20を構成するガラス基板GSの内面側の非表示領域NAAには、図8に示すように、TFT24を駆動するためのゲートドライバ(ゲート側駆動部品)GD及びソースドライバ(ソース側駆動部品)SDが異方性導電膜を介して接続されている。ゲートドライバGD及びソースドライバSDは、図示しないコントロール基板に接続されており、そのコントロール基板から出力される各種信号などをアレイ基板20の各配線に供給することで、TFT24を駆動することが可能とされている。ソースドライバSDは、アレイ基板20のうち長辺方向(X軸方向)に沿った一方の端部(図8に示す上側の端部)に取り付けられている。一方、ゲートドライバGDは、アレイ基板20のうち短辺方向(Y軸方向)に沿った一方の端部(図8に示す右側の端部)に取り付けられている。 Subsequently, a configuration related to the non-display area NAA in the array substrate 20 will be described. In the non-display area NAA on the inner surface side of the glass substrate GS constituting the array substrate 20, as shown in FIG. 8, a gate driver (gate side driving component) GD and a source driver (source side driving component) for driving the TFT 24 are provided. ) SD is connected through an anisotropic conductive film. The gate driver GD and the source driver SD are connected to a control board (not shown), and the TFT 24 can be driven by supplying various signals output from the control board to each wiring of the array substrate 20. Has been. The source driver SD is attached to one end (upper end shown in FIG. 8) of the array substrate 20 along the long side direction (X-axis direction). On the other hand, the gate driver GD is attached to one end (the right end shown in FIG. 8) of the array substrate 20 along the short side direction (Y-axis direction).
 アレイ基板20の非表示領域NAAには、図8に示すように、表示領域AA側に存するゲート配線26、ソース配線27及び容量配線33がそれぞれ延出されており、このうちゲート配線26がゲートドライバGDの接続箇所に、ソース配線27がソースドライバSDの接続箇所にそれぞれ達している。つまり、ゲート配線26、ソース配線27及び容量配線33は、表示領域AAと非表示領域NAAとに跨る形で形成されている。容量配線33については、その延出端部が非表示領域NAAのうちゲートドライバGDの接続箇所よりも内側(表示領域AA側)の位置に配されるとともに、そこに形成された引廻配線43に対して接続されている。引廻配線43は、アレイ基板20の非表示領域NAAのうち短辺方向に沿った一方の端部に配されるとともに並列する各ゲート配線26及び各容量配線33を横切りつつY軸方向に沿って(ソース配線27に並行して)延在し、その端部がソースドライバSDの接続箇所に達していて当該ソースドライバSDに対して接続されている。引廻配線43は、複数が互いに並行する形で配されており、それぞれ特定の容量配線33に対して接続されている。引廻配線43は、ソース配線27と同一材料からなり且つ製造工程における同一工程にて同一層に形成されており、図10に示すように、下層側の金属膜39と上層側の金属膜40とを備える。従って、引廻配線43は、交差する各ゲート配線26及び各容量配線33に対してゲート絶縁膜35を介して相対的に上層側に配されることで、ゲート配線26及び容量配線33とは絶縁状態に保たれている。しかし、引廻配線43のうち所定の容量配線33との交差部分については、ゲート絶縁膜35にコンタクトホール(図示せず)が形成されることで、そのコンタクトホールを通して所定の容量配線33に対して電気的に接続されている。このように、ゲートドライバGDからはゲート配線26に対して、ソースドライバSDからはソース配線27及び引廻配線43を介する容量配線33に対して、それぞれ各種信号などが供給されるようになっている。 In the non-display area NAA of the array substrate 20, as shown in FIG. 8, a gate wiring 26, a source wiring 27, and a capacitor wiring 33 existing on the display area AA side are respectively extended. The source wiring 27 reaches the connection point of the source driver SD at the connection point of the driver GD. That is, the gate line 26, the source line 27, and the capacitor line 33 are formed so as to straddle the display area AA and the non-display area NAA. Regarding the capacitor wiring 33, its extended end is arranged at a position inside the display area AA side of the non-display area NAA than the connection position of the gate driver GD, and the lead wiring 43 formed there. Connected to. The routing wiring 43 is arranged at one end of the non-display area NAA of the array substrate 20 along the short side direction, and extends along the Y-axis direction while crossing each gate wiring 26 and each capacitance wiring 33 arranged in parallel. (In parallel with the source wiring 27), and its end reaches the connection location of the source driver SD and is connected to the source driver SD. A plurality of lead wirings 43 are arranged in parallel with each other, and are connected to specific capacitance wirings 33 respectively. The lead wiring 43 is made of the same material as that of the source wiring 27 and is formed in the same layer in the same manufacturing process. As shown in FIG. 10, the lower metal film 39 and the upper metal film 40 are formed. With. Therefore, the routing wiring 43 is arranged on the upper layer side with respect to each intersecting gate wiring 26 and each capacitance wiring 33 via the gate insulating film 35, so that the gate wiring 26 and the capacitance wiring 33 are different. Insulated state is maintained. However, a contact hole (not shown) is formed in the gate insulating film 35 at the intersection of the routing wiring 43 with the predetermined capacitance wiring 33, so that the predetermined capacitance wiring 33 is connected to the contact wiring through the contact hole. Are electrically connected. In this way, various signals and the like are supplied from the gate driver GD to the gate wiring 26 and from the source driver SD to the capacitor wiring 33 via the source wiring 27 and the routing wiring 43, respectively. Yes.
 次に、アレイ基板20の非表示領域NAAにおいて、ゲート配線26及び容量配線33と引廻配線43との交差部分に係る構成について詳しく説明する。容量配線33における引廻配線43との交差部分には、図9に示すように、スリット44が形成されている。スリット44は、容量配線33において引廻配線43を跨ぐ所定の範囲にわたって形成されており、詳しくは、容量配線33のうち、引廻配線43と平面に視て重畳する重畳部分(図9では引廻配線43の形成範囲において破線で表される部分)と、その重畳部分を両側から挟み且つ引廻配線43とは重畳しない一対の非重畳部分とにわたる範囲に形成されている。スリット44は、X軸方向、つまり容量配線33の延在方向に並行して直線的に延びる細長い開口からなり、その両端部が平面に視て半円形状をなしている。容量配線33は、スリット44が形成されたスリット形成部分33aが2つに分割されており、ここが2つの分割部33a1とされる。容量配線33は、スリット形成部分33aと、スリット44が形成されないスリット非形成部分33bとからなるのであるが、これらスリット形成部分33a及びスリット非形成部分33bの線幅は互いに等しいものとされる。従って、容量配線33は、線幅が途中で殆ど変化することがなく、ほぼ全長にわたってほぼ均一な大きさとされている。本実施形態では、多数本あるゲート配線26の全てがスリット44を有さない「第1配線」となり、且つ多数本ある容量配線33の全てがスリット44を有する「第2配線」となり、またこれらと交差する引廻配線43が「第3配線」となっている。なお、図9は、各配線26,33,43及び架渡し部45の平面構成を表すことに主眼を置いたものであるため、ゲート絶縁膜35、層間絶縁膜37及び保護膜38の図示を省略している。 Next, in the non-display area NAA of the array substrate 20, the configuration related to the intersection of the gate wiring 26, the capacitor wiring 33 and the lead wiring 43 will be described in detail. As shown in FIG. 9, a slit 44 is formed at the intersection of the capacitive wiring 33 with the routing wiring 43. The slit 44 is formed over a predetermined range across the lead wire 43 in the capacitor wire 33. Specifically, the overlapping portion of the capacitor wire 33 that overlaps the lead wire 43 in a plan view (shown in FIG. 9). The portion shown by the broken line in the formation range of the surrounding wiring 43) and the pair of non-overlapping portions that sandwich the overlapping portion from both sides and do not overlap the surrounding wiring 43. The slit 44 is formed of an elongated opening extending linearly in parallel with the X-axis direction, that is, the extending direction of the capacitor wiring 33, and both end portions thereof have a semicircular shape when viewed in a plane. In the capacitor wiring 33, a slit forming portion 33a in which a slit 44 is formed is divided into two, and these are defined as two divided portions 33a1. The capacitor wiring 33 includes a slit forming portion 33a and a slit non-forming portion 33b in which the slit 44 is not formed. The line widths of the slit forming portion 33a and the slit non-forming portion 33b are equal to each other. Therefore, the capacity wiring 33 has a substantially uniform size over almost the entire length, with the line width hardly changing in the middle. In the present embodiment, all of the many gate wirings 26 become “first wirings” that do not have the slits 44, and all of the many capacitive wirings 33 become “second wirings” that have the slits 44, and these The routing wiring 43 that intersects with the "third wiring". Note that FIG. 9 focuses on representing the planar configuration of each of the wirings 26, 33, 43 and the transfer portion 45, so that the gate insulating film 35, the interlayer insulating film 37, and the protective film 38 are illustrated. Omitted.
 そして、Y軸方向について交互に並ぶ形で多数本ずつ配されるゲート配線26と容量配線33との間には、図9に示すように、架渡し部45が架け渡されている。架渡し部45は、Y軸方向(ゲート配線26及び容量配線33の延在方向と直交する方向、引廻配線43の延在方向)に沿って延びる形態とされていて、互いに隣り合うゲート配線26と容量配線33とを跨ぐようにして両者間に架け渡されている。架渡し部45は、その片方の端部がゲート配線26に対して平面に視て重畳するのに対して、もう片方の端部がゲート配線26に隣り合う容量配線33に対して平面に視て重畳している。この架渡し部45は、図11に示すように、ソース配線27及び引廻配線43と同一材料からなり且つ製造工程における同一工程にて同一層に形成されており、下層側の金属膜39と上層側の金属膜40とを備えている。つまり、架渡し部45は、ソース配線27及び引廻配線43と同様に導電性を有しているものの、ゲート配線26及び容量配線33に対してゲート絶縁膜35を介して上層側に配されることで、通常はゲート配線26及び容量配線33とは絶縁状態に保たれている。ところが、架渡し部45のうちゲート配線26及び容量配線33と平面に視て重畳する部分にレーザ光などを照射すると、その照射箇所においてゲート絶縁膜35が溶融されることで、架渡し部45の重畳部分とゲート配線26及び容量配線33とが短絡されるようになっている。 Further, as shown in FIG. 9, a bridge portion 45 is bridged between the gate wirings 26 and the capacitor wirings 33 that are arranged in large numbers alternately in the Y-axis direction. The bridge portion 45 extends along the Y-axis direction (the direction orthogonal to the extending direction of the gate wiring 26 and the capacitor wiring 33, the extending direction of the routing wiring 43), and is adjacent to each other. 26 and the capacitor wiring 33 are bridged between the two. One end of the transfer portion 45 overlaps the gate wiring 26 in a plan view, while the other end overlaps the capacitance wiring 33 adjacent to the gate wiring 26 in a plan view. Are superimposed. As shown in FIG. 11, the bridge portion 45 is made of the same material as the source wiring 27 and the routing wiring 43 and is formed in the same layer in the same process in the manufacturing process. And an upper metal film 40. That is, the bridge portion 45 has conductivity similar to the source wiring 27 and the routing wiring 43, but is arranged on the upper layer side through the gate insulating film 35 with respect to the gate wiring 26 and the capacitor wiring 33. Thus, normally, the gate wiring 26 and the capacitor wiring 33 are kept in an insulated state. However, when laser light or the like is irradiated to a portion of the transfer portion 45 that overlaps with the gate wiring 26 and the capacitor wiring 33 in a plan view, the gate insulating film 35 is melted at the irradiated portion, whereby the transfer portion 45. The gate line 26 and the capacitor line 33 are short-circuited.
 架渡し部45は、図9に示すように、隣り合うゲート配線26及び容量配線33においてその延在方向について引廻配線43を挟んだ位置に一対が1組で配されており、各ゲート配線26及び各容量配線33に対して2組ずつ配置されている。つまり、架渡し部45は、各ゲート配線26及び各容量配線33の個々に対して4つずつ設けられていることになる。1つの組をなす一対の架渡し部45は、X軸方向についてスリット44の両端部よりも引廻配線43寄りの位置、つまりスリット44の端部と引廻配線43との間となる位置にそれぞれ配されている。言い換えると、スリット44は、容量配線33において引廻配線43を挟む一対の架渡し部45を超える範囲にわたって形成されていることになる。従って、架渡し部45は、容量配線33のうちのスリット形成部分33aとゲート配線26とを架け渡しており、さらに詳しくはスリット形成部分33aを構成する2つの分割部33a1のうちの片方とゲート配線26とを架け渡している。つまり、架渡し部45は、容量配線33に対しては2つの分割部33a1毎に1組(一対)ずつ配置されている。そして、1つの組をなす一対の架渡し部45は、一方の分割部33a1を、他方の分割部33a1側とは反対側に隣り合うゲート配線26に対してX軸方向に離間した2位置にて架け渡していることになる。一方の分割部33a1とゲート配線26とを架け渡す一対の架渡し部45と、他方の分割部33a1と上記とは反対側のゲート配線26とを架け渡す一対の架渡し部45とは、X軸方向についてほぼ同じ位置に配されている。また、組をなす一対の架渡し部45は、引廻配線43からの距離(スリット44の各端部からの距離)が互いにほぼ等しくなっており、引廻配線43を中心にした対称位置に配されている。 As shown in FIG. 9, the bridge portion 45 is arranged as a pair at a position sandwiching the routing wiring 43 in the extending direction between the adjacent gate wiring 26 and the capacitor wiring 33. 26 and two sets of capacitor wirings 33 are arranged. That is, four transfer portions 45 are provided for each of the gate lines 26 and the capacity lines 33. A pair of spanning portions 45 forming one set are positioned closer to the routing wiring 43 than both ends of the slit 44 in the X-axis direction, that is, between the end of the slit 44 and the routing wiring 43. Each is arranged. In other words, the slit 44 is formed over a range that exceeds the pair of bridge portions 45 that sandwich the routing wiring 43 in the capacitor wiring 33. Therefore, the bridging portion 45 bridges the slit forming portion 33a of the capacitor wiring 33 and the gate wiring 26, and more specifically, one of the two divided portions 33a1 constituting the slit forming portion 33a and the gate. The wiring 26 is bridged. That is, one set (one pair) of the crossover portions 45 is arranged for each of the two divided portions 33a1 with respect to the capacitor wiring 33. Then, the pair of spanning portions 45 forming one set has one division portion 33a1 at two positions separated in the X-axis direction with respect to the gate wiring 26 adjacent on the opposite side to the other division portion 33a1 side. It will be handed over. A pair of bridge portions 45 that bridges one divided portion 33a1 and the gate wiring 26 and a pair of bridge portions 45 that bridge the other divided portion 33a1 and the gate wiring 26 opposite to the above are X It is arranged at almost the same position in the axial direction. In addition, the pair of spanning portions 45 forming a pair are substantially equal in distance from the routing wire 43 (distance from each end portion of the slit 44), and in a symmetrical position with the routing wire 43 as the center. It is arranged.
 本実施形態は以上のような構造であり、続いてその作用を説明する。まず、液晶表示装置10の製造方法について概略的に説明する。液晶表示装置10を製造するに際しては、液晶パネル11及びバックライト装置12をそれぞれ別途に製造し、それら液晶パネル11とバックライト装置12とをベゼル13などを介して組み付けるようにしている。以下では、液晶パネル11の製造方法、特にアレイ基板20の製造方法について詳しく説明する。 This embodiment has the structure as described above, and its operation will be described next. First, a manufacturing method of the liquid crystal display device 10 will be schematically described. When the liquid crystal display device 10 is manufactured, the liquid crystal panel 11 and the backlight device 12 are separately manufactured, and the liquid crystal panel 11 and the backlight device 12 are assembled via a bezel 13 or the like. Below, the manufacturing method of the liquid crystal panel 11, especially the manufacturing method of the array substrate 20, will be described in detail.
 液晶パネル11の製造に際しては、アレイ基板20をなすガラス基板GS上に各構造物を形成するアレイ基板用構造物形成工程(配線形成工程)、及びCF基板21をなすガラス基板GS上に各構造物を形成するCF基板構造物形成工程をそれぞれ行った後、アレイ基板20をなすガラス基板GSとCF基板21をなすガラス基板GSとを液晶層22を介在させつつ貼り合わせる基板貼り合わせ工程を行う。次に、各配線26,27,33,43に断線や短絡などが生じているか否かを検査する検査工程を行い、不良が検出された液晶パネル11に対しては、不良箇所を修理する修理工程を行う。それから、液晶パネル11をなす一対のガラス基板GSの外面側に偏光板23を貼り付ける偏光板貼り付け工程を行った後に、アレイ基板20の非表示領域NAAにゲートドライバGD及びソースドライバSDを実装するドライバ実装工程を行うことで、液晶パネル11が製造される。続いて、各工程に関して詳しく説明する。 When manufacturing the liquid crystal panel 11, an array substrate structure forming step (wiring forming step) for forming each structure on the glass substrate GS forming the array substrate 20, and each structure on the glass substrate GS forming the CF substrate 21. After performing the CF substrate structure forming step for forming the object, the substrate bonding step for bonding the glass substrate GS forming the array substrate 20 and the glass substrate GS forming the CF substrate 21 with the liquid crystal layer 22 interposed therebetween is performed. . Next, an inspection process is performed for inspecting whether or not the wirings 26, 27, 33, and 43 are broken or short-circuited. For the liquid crystal panel 11 in which a defect is detected, repair for repairing the defective part is performed. Perform the process. Then, after performing a polarizing plate attaching step of attaching the polarizing plate 23 to the outer surface side of the pair of glass substrates GS forming the liquid crystal panel 11, the gate driver GD and the source driver SD are mounted on the non-display area NAA of the array substrate 20. The liquid crystal panel 11 is manufactured by performing the driver mounting process. Subsequently, each step will be described in detail.
 アレイ基板用構造物形成工程では、既知のフォトリソグラフィ法によってアレイ基板20をなすガラス基板GS上にTFT24、各配線26,27,33,43、各絶縁膜35,37,38、及び画素電極25などを順次に積層形成している。このアレイ基板用構造物形成工程では、ゲート配線26及び容量配線33を同じ材料及び同じ製造装置を用い、同じ工程にて一括して形成しており、特に容量配線33を形成する際には引廻配線43と交差する予定の部分にスリット44を形成している。同様に、アレイ基板用構造物形成工程では、ソース配線27、引廻配線43及び架渡し部45を同じ材料及び同じ製造装置を用い、同じ工程にて一括して形成している。このように、アレイ基板用構造物形成工程には、各配線26,27,33,43に加えてスリット44及び架渡し部45を形成する配線形成工程が含まれている、と言える。また、画素電極25を形成した後に、配向膜28を成膜し、その配向処理を行う。 In the array substrate structure forming step, the TFT 24, the wirings 26, 27, 33, and 43, the insulating films 35, 37, and 38, and the pixel electrode 25 are formed on the glass substrate GS that forms the array substrate 20 by a known photolithography method. Etc. are sequentially laminated. In this array substrate structure forming process, the gate wiring 26 and the capacitor wiring 33 are formed in the same process at the same time using the same material and the same manufacturing apparatus, and particularly when the capacitor wiring 33 is formed. A slit 44 is formed at a portion that intersects the circuit wiring 43. Similarly, in the array substrate structure forming process, the source wiring 27, the routing wiring 43, and the transfer portion 45 are formed in a lump in the same process using the same material and the same manufacturing apparatus. Thus, it can be said that the array substrate structure forming process includes a wiring forming process for forming the slits 44 and the bridge portions 45 in addition to the wirings 26, 27, 33, and 43. In addition, after the pixel electrode 25 is formed, an alignment film 28 is formed and the alignment process is performed.
 基板貼り合わせ工程は、一方のガラス基板GS上にシール剤を塗布するとともに液晶材料を滴下した後に、他方のガラス基板GSを貼り合わせつつシール剤を硬化させることで行われる。検査工程は、液晶パネル11に対して検査用のバックライト装置(図示せず)からの光を照射するとともに、アレイ基板20の各配線26,27,33(43)に図示しない検査装置から検査信号を入力することで、所定の検査用画像を表示させつつ行っており、表示された検査用画像を作業員が目視したり、或いは検査用画像を撮像素子にて撮像して画像処理を行うことで、不良の有無を検査している。このとき、例えばあるゲート配線26が引廻配線43に対して交差部分にて短絡した場合には、ライン欠陥と呼ばれる線状の表示不良が生じることになる。それ以外にも、例えばある容量配線33が、複数ある引廻配線43のうち接続される予定ではない引廻配線43に対して交差部分にて短絡した場合にも、同様のライン欠陥が生じるおそれがある。 The substrate bonding step is performed by applying a sealing agent on one glass substrate GS and dropping a liquid crystal material, and then curing the sealing agent while bonding the other glass substrate GS. In the inspection process, the liquid crystal panel 11 is irradiated with light from a backlight device for inspection (not shown), and each wiring 26, 27, 33 (43) of the array substrate 20 is inspected from an inspection device (not shown). By inputting a signal, it is performed while displaying a predetermined inspection image, and an operator visually observes the displayed inspection image or picks up the inspection image with an image sensor and performs image processing. Therefore, the presence or absence of defects is inspected. At this time, for example, when a certain gate wiring 26 is short-circuited to the routing wiring 43 at an intersection, a linear display defect called a line defect occurs. In addition, for example, when a certain capacitance wiring 33 is short-circuited at a crossing portion with respect to the routing wiring 43 that is not scheduled to be connected among the plurality of routing wirings 43, the same line defect may occur. There is.
 修理工程では、検査工程にて不良が検出された液晶パネル11について問題のある配線の修理を行う。例えばあるゲート配線26(図12では最も上に図示されるゲート配線26)が引廻配線43に対して交差部分に短絡箇所SP1が生じていた場合には、そのゲート配線26にレーザ光を照射することで、引廻配線43と短絡した部分を切り離す。具体的には、図12に示すように、ゲート配線26のうち、X軸方向について、短絡した引廻配線43と一対の架渡し部45との間の2位置にレーザ光を照射し、当該位置にてゲート配線26を横切るようにしてY軸方向に沿って直線的に切断して切断部BP1を形成する。これにより、ゲート配線26から、短絡した引廻配線43を挟み且つ一対の架渡し部45の間に挟まれる部分を切り離すことができる。もって、ゲート配線26のうち引廻配線43と短絡した部分を、ゲート配線26の本体部分から切り離して電気的に孤立させることができる。 In the repair process, troublesome wiring is repaired for the liquid crystal panel 11 in which a defect is detected in the inspection process. For example, when a short-circuit portion SP1 occurs at a portion where a certain gate wiring 26 (the gate wiring 26 illustrated at the top in FIG. 12) intersects the routing wiring 43, the gate wiring 26 is irradiated with laser light. By doing so, the short-circuited portion with the lead wiring 43 is cut off. Specifically, as shown in FIG. 12, in the X-axis direction of the gate wiring 26, laser light is irradiated to two positions between the short-circuited wiring wiring 43 and the pair of bridge portions 45, A cut portion BP1 is formed by linearly cutting along the Y-axis direction so as to cross the gate wiring 26 at the position. As a result, it is possible to separate from the gate wiring 26 the portion sandwiched between the short-circuited routing wiring 43 and sandwiched between the pair of bridge portions 45. Therefore, a portion of the gate wiring 26 that is short-circuited with the lead wiring 43 can be separated from the main body portion of the gate wiring 26 to be electrically isolated.
 その一方で、短絡が生じたゲート配線26とそれに隣り合う容量配線33との間に架け渡された一対の架渡し部45にレーザ光を照射することで、それら各架渡し部45とゲート配線26及び容量配線33とをそれぞれ短絡させる。具体的には、図12に示すように、架渡し部45のうち、短絡が生じたゲート配線26と平面視重畳する部分、及び容量配線33と平面視重畳する部分に対してそれぞれレーザ光を照射すると、照射箇所におけるゲート絶縁膜35が溶融されることで、架渡し部45における上記各重畳部分がゲート配線26及び容量配線33に対して短絡されて短絡部SP2が形成される。これにより、引廻配線43と短絡したゲート配線26の本体部分(短絡した部分を除いた部分)を、隣り合う容量配線33の一部である分割部33a1に対して電気的に接続することができる。 On the other hand, by irradiating a pair of spanning portions 45 spanned between the gate wiring 26 in which the short circuit has occurred and the capacitor wiring 33 adjacent thereto, each of the bridging portions 45 and the gate wiring. 26 and the capacitor wiring 33 are short-circuited. Specifically, as shown in FIG. 12, laser light is respectively applied to a portion of the bridge portion 45 that overlaps with the gate wiring 26 where the short circuit has occurred and a portion that overlaps with the capacitance wiring 33 in plan view. When the irradiation is performed, the gate insulating film 35 at the irradiation location is melted, whereby each of the overlapping portions in the transfer portion 45 is short-circuited with respect to the gate wiring 26 and the capacitor wiring 33 to form a short-circuit portion SP2. Thereby, the main body part (the part excluding the shorted part) of the gate wiring 26 short-circuited to the routing wiring 43 can be electrically connected to the divided portion 33 a 1 which is a part of the adjacent capacitor wiring 33. it can.
 さらには、容量配線33においてスリット44を挟んで配される2つの分割部33a1のうち、架渡し部45によってゲート配線26と短絡される分割部33a1にレーザ光を照射することでこれを切断して切り離す。具体的には、図12に示すように、架渡し部45によってゲート配線26と短絡される分割部33a1のうち、X軸方向について各架渡し部45に対して引廻配線43側とは反対側(スリット44の各端部側)の2位置にレーザ光を照射する。このレーザ光の照射位置(切断位置)は、X軸方向についてスリット44と重なり合う位置関係にあることから、分割部33a1を横切るようにしてY軸方向に沿って直線的に切断することができ、それにより切断部BP2が形成される。これにより、架渡し部45によってゲート配線26と短絡される分割部33a1を、元の容量配線33から切り離して電気的に独立させることができる。 Further, of the two divided portions 33a1 arranged across the slit 44 in the capacitor wiring 33, the divided portion 33a1 that is short-circuited to the gate wiring 26 by the transfer portion 45 is irradiated with laser light to cut it. To separate. Specifically, as shown in FIG. 12, among the divided portions 33 a 1 that are short-circuited to the gate wiring 26 by the bridge portion 45, the X-axis direction is opposite to the routed wire 43 side with respect to each bridge portion 45. Laser light is irradiated to two positions on the side (each end side of the slit 44). Since the irradiation position (cutting position) of this laser beam is in a positional relationship overlapping with the slit 44 in the X-axis direction, it can be cut linearly along the Y-axis direction across the dividing portion 33a1. Thereby, the cutting part BP2 is formed. Thereby, the division part 33a1 short-circuited with the gate wiring 26 by the bridge | crossover part 45 can be isolate | separated from the original capacity | capacitance wiring 33, and can be made electrically independent.
 以上の修理を行うことで、引廻配線43に短絡されたゲート配線26に供給される信号は、ゲート配線26の本体部分から架渡し部45を経由して隣り合う容量配線33の一部である分割部33a1(詳細には、短絡が生じたゲート配線26側の分割部33a1)に迂回され、再び架渡し部45を経由してゲート配線26の本体部分に流されることで、正常に表示領域AA内の各TFT24へと伝送される。このように、ゲート配線26に隣り合う容量配線33の一部を利用してゲート配線26の修理を行うことができるから、従来のように引廻配線にスリットを設けることで対応した場合に比べると、引廻配線43の線幅を小さくすることができる。引廻配線43は、ゲート配線26及び容量配線33の双方に対して交差するものであるから、その線幅が小さくなれば、ゲート配線26及び容量配線33との重畳面積も小さくなる。従って、ゲート配線26及び容量配線33と引廻配線43との間に生じ得る寄生容量が小さくなり、また短絡が生じる可能性自体が低減される。また、仮に修理専用の配線を設けるようにした場合に比べると、ゲート配線26と容量配線33との間のスペースを小さくすることができるので、省スペース化を図ったり、配線間ピッチを小さくする(高精細化を図る)上でも好適となる。 By performing the above repair, the signal supplied to the gate wiring 26 short-circuited to the routing wiring 43 is transmitted from the main body portion of the gate wiring 26 to a part of the adjacent capacitive wiring 33 via the bridge 45. Displayed normally by bypassing a certain divided portion 33a1 (specifically, the divided portion 33a1 on the gate wiring 26 side where the short circuit occurred) and flowing again to the main body portion of the gate wiring 26 via the transfer portion 45 The data is transmitted to each TFT 24 in the area AA. As described above, since the gate wiring 26 can be repaired by using a part of the capacitor wiring 33 adjacent to the gate wiring 26, compared with the conventional case where a slit is provided in the lead wiring. Thus, the line width of the lead wiring 43 can be reduced. Since the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Therefore, the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the routing wiring 43 is reduced, and the possibility of a short circuit itself is reduced. Further, as compared with the case where a wiring dedicated for repair is provided, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced, so that space saving can be achieved and the pitch between wirings can be reduced. This is also suitable for (high definition).
 ところで、本実施形態では、引廻配線43と短絡したゲート配線26を修理するに際しては、そのゲート配線26を挟んで隣り合う一対の容量配線33のいずれをも修理に利用することが可能とされている。つまり、ゲート配線26は、図12に示すように、Y軸方向について隣り合う一対の容量配線33に対して架渡し部45によってそれぞれ架け渡されているので、一対の容量配線33のスリット形成部分33aのうち、短絡したゲート配線26側の分割部33a1をそれぞれゲート配線26の信号を伝送する迂回路として選択的に利用することができるのである。これにより、下記の効果を得ることができる。すなわち、例えば、引廻配線43と短絡したゲート配線26に対して隣り合う片方の容量配線33(図12では短絡したゲート配線26の上側に隣り合う容量配線33)のうち上記ゲート配線26側の分割部33a1までもが引廻配線43に短絡していた場合(図12において2点鎖線にて示す短絡箇所SP3が生じた場合)には、ゲート配線26を修理するにあたっては隣り合うもう片方の容量配線33(図12では短絡したゲート配線26の下側に隣り合う容量配線33)におけるゲート配線26側の分割部33a1を利用するよう修理すればよい。ここで、仮にゲート配線が片側の容量配線に対してのみ架渡し部により架け渡されていない場合には、その架け渡された容量配線が引廻配線に短絡していると、修理不能になってしまう。その点、本実施形態では、ゲート配線26に隣り合う一対の容量配線33を選択的に利用して修理を行うことができるから、修理を行う上での自由度が高く、修理によってゲート配線26を救済できる確率が高いものとなっている。 By the way, in the present embodiment, when repairing the gate wiring 26 short-circuited with the routing wiring 43, it is possible to use any of the pair of capacitor wirings 33 adjacent to each other across the gate wiring 26 for repair. ing. That is, as shown in FIG. 12, the gate wirings 26 are respectively spanned by the bridging portions 45 with respect to the pair of capacitive wirings 33 adjacent to each other in the Y-axis direction. Among the portions 33a, the divided portions 33a1 on the side of the shorted gate wiring 26 can be selectively used as detours for transmitting the signal of the gate wiring 26, respectively. Thereby, the following effects can be obtained. In other words, for example, one of the capacitor wirings 33 adjacent to the gate wiring 26 short-circuited to the routing wiring 43 (capacitance wiring 33 adjacent to the upper side of the shorted gate wiring 26 in FIG. 12) on the gate wiring 26 side. When even the divided portion 33a1 is short-circuited to the routing wiring 43 (when a short-circuited portion SP3 indicated by a two-dot chain line in FIG. 12 occurs), when repairing the gate wiring 26, the other adjacent one is repaired. What is necessary is just to repair so that the division | segmentation part 33a1 by the side of the gate wiring 26 in the capacity | capacitance wiring 33 (capacity wiring 33 adjacent to the lower side of the shorted gate wiring 26 in FIG. 12) may be utilized. Here, if the gate wiring is not bridged only to the capacitive wiring on one side by the spanning part, it cannot be repaired if the bridged capacitive wiring is short-circuited to the routing wiring. End up. In this respect, in the present embodiment, the repair can be performed by selectively using the pair of capacitor wirings 33 adjacent to the gate wiring 26, so that the degree of freedom in repairing is high, and the gate wiring 26 can be repaired. The probability of being able to rescue is high.
 また、例えばある容量配線33が引廻配線43に対して交差部分に短絡箇所SP3(図12では二点鎖線にて図示している)が生じていた場合には、その容量配線33のうち短絡が生じた分割部33a1にレーザ光を照射することで、引廻配線43と短絡した部分を切り離す。具体的には、図12に示すように、容量配線33における短絡が生じた分割部33a1のうち、X軸方向について、短絡した引廻配線43と一対の架渡し部45との間の2位置にレーザ光を照射し、当該位置にて分割部33a1を横切るようにしてY軸方向に沿って直線的に切断して切断部BP3(図12では二点鎖線にて図示している)を形成する。これにより、容量配線33の分割部33a1から、短絡した引廻配線43を挟み且つ一対の架渡し部45の間に挟まれる部分を切り離すことができる。もって、容量配線33の分割部33a1のうち引廻配線43と短絡した部分を、容量配線33の本体部分から切り離して電気的に孤立させることができる。以上の修理を行うことで、引廻配線43に短絡された容量配線33に供給される信号は、短絡が生じていない側の分割部33a1によって適切に伝送される。 Further, for example, when a short-circuit spot SP3 (shown by a two-dot chain line in FIG. 12) occurs at a crossing portion of a certain capacitance wiring 33 with respect to the routing wiring 43, the capacitance wiring 33 is short-circuited. By irradiating a laser beam to the divided portion 33a1 where the occurrence of the problem occurs, a portion short-circuited with the lead wiring 43 is separated. Specifically, as shown in FIG. 12, among the divided portions 33a1 in which the short circuit occurs in the capacitor wiring 33, two positions between the short-circuited wiring wire 43 and the pair of bridge portions 45 in the X-axis direction. Is irradiated with a laser beam, and is cut linearly along the Y-axis direction so as to cross the dividing portion 33a1 at that position to form a cut portion BP3 (shown by a two-dot chain line in FIG. 12). To do. As a result, it is possible to separate a portion sandwiched between the short-circuited routing wire 43 and between the pair of spanning portions 45 from the divided portion 33 a 1 of the capacitor wiring 33. Accordingly, a portion of the divided portion 33a1 of the capacitive wiring 33 that is short-circuited with the lead wiring 43 can be separated from the main body portion of the capacitive wiring 33 and electrically isolated. By performing the repair described above, the signal supplied to the capacitor wiring 33 short-circuited to the lead wiring 43 is appropriately transmitted by the dividing portion 33a1 on the side where no short-circuiting occurs.
 以上説明したように本実施形態のアレイ基板(素子基板)20は、ゲート配線(第1配線)26と、ゲート配線26に並行するとともにゲート配線26に隣り合って配される容量配線(第2配線)33と、ゲート配線26及び容量配線33に対してゲート絶縁膜(絶縁層)35を介しつつ交差する引廻配線(第3配線)43と、容量配線33のうち少なくとも引廻配線43を跨ぐ部分に配されるスリット44と、引廻配線43を挟む位置に少なくとも一対配されるものであって、ゲート配線26及び容量配線33に対してゲート絶縁膜35を介して配されることでゲート配線26及び容量配線33と絶縁されるとともにゲート配線26と容量配線33との間に架け渡される架渡し部45と、を備える。 As described above, the array substrate (element substrate) 20 of the present embodiment has the gate wiring (first wiring) 26 and the capacitor wiring (second wiring) arranged in parallel with the gate wiring 26 and adjacent to the gate wiring 26. Wiring) 33, a routing wiring (third wiring) 43 that intersects the gate wiring 26 and the capacitive wiring 33 with a gate insulating film (insulating layer) 35 interposed therebetween, and at least the routing wiring 43 among the capacitive wiring 33. At least a pair of slits 44 arranged in the straddling portion and the routing wiring 43 are arranged, and the gate wiring 26 and the capacitor wiring 33 are arranged via the gate insulating film 35 by being arranged. And a cross-over portion 45 that is insulated from the gate wiring 26 and the capacitive wiring 33 and is bridged between the gate wiring 26 and the capacitive wiring 33.
 ゲート配線26及び容量配線33は、その間に架け渡される架渡し部45に対してゲート絶縁膜35を介して配されることで架渡し部45とは絶縁されているから、ゲート配線26及び容量配線33と引廻配線43との交差部分に短絡が生じていなければ、ゲート配線26、容量配線33及び引廻配線43のそれぞれに信号などを伝送させることができる。 Since the gate wiring 26 and the capacitor wiring 33 are insulated from the bridge portion 45 by being arranged via the gate insulating film 35 with respect to the bridge portion 45 bridged between them, If a short circuit does not occur at the intersection between the wiring 33 and the routing wiring 43, a signal or the like can be transmitted to each of the gate wiring 26, the capacitance wiring 33, and the routing wiring 43.
 ここで、例えば、ゲート配線26と引廻配線43との交差部分に短絡が生じた場合には、ゲート配線26のうち、引廻配線43を挟み且つ少なくとも一対の架渡し部45の間に挟まれる部分を切断してゲート配線26から切り離す。一方、ゲート配線26とそれに隣り合う容量配線33との間に架け渡された少なくとも一対の架渡し部45を、ゲート配線26及び容量配線33に対してそれぞれ短絡させる。さらには、容量配線33においてスリット44を挟んで配される複数の部分のうち、ゲート配線26に対して少なくとも一対の架渡し部45により短絡される部分を切断して容量配線33から切り離す。以上により、容量配線33の一部を利用してゲート配線26に信号などを伝送させることができる。 Here, for example, when a short circuit occurs at the intersection between the gate wiring 26 and the routing wiring 43, the routing wiring 43 is sandwiched between the gate wiring 26 and at least between the pair of crossover portions 45. The portion to be cut is cut off from the gate wiring 26. On the other hand, at least a pair of the bridging portions 45 spanned between the gate wiring 26 and the capacitor wiring 33 adjacent thereto are short-circuited to the gate wiring 26 and the capacitor wiring 33, respectively. Further, among the plurality of portions arranged across the slit 44 in the capacitor wiring 33, at least a portion short-circuited by the pair of bridge portions 45 with respect to the gate wiring 26 is cut and separated from the capacitor wiring 33. As described above, a signal or the like can be transmitted to the gate wiring 26 using a part of the capacitor wiring 33.
 このように、ゲート配線26に隣り合う容量配線33の一部を、ゲート配線26に短絡が生じた場合の修理に利用することができるから、仮に引廻配線43にスリット44を設けることで対応した場合に比べると、引廻配線43の線幅を小さくすることができる。引廻配線43は、ゲート配線26及び容量配線33の双方に対して交差するものであるから、その線幅が小さくなれば、ゲート配線26及び容量配線33との重畳面積も小さくなる。従って、ゲート配線26及び容量配線33と引廻配線43との間に生じ得る寄生容量が小さくなり、また短絡が生じる可能性自体が低減される、などの効果を得ることができる。また、仮にゲート配線26及び容量配線33とは別途に修理専用の配線を設けた場合に比べると、ゲート配線26と容量配線33との間のスペースを小さくすることができるので、省スペース化などを図る上で好適となる。 In this way, a part of the capacitor wiring 33 adjacent to the gate wiring 26 can be used for repair when a short circuit occurs in the gate wiring 26, so that provision is made by providing a slit 44 in the lead wiring 43. Compared to the case, the line width of the lead wiring 43 can be reduced. Since the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the lead wiring 43 is reduced, and that the possibility of a short circuit is reduced. Further, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced as compared with the case where a repair-dedicated wiring is provided separately from the gate wiring 26 and the capacitor wiring 33, so that space saving can be achieved. This is suitable for achieving the above.
 なお、例えば、容量配線33においてスリット44を挟んで配される複数の部分のうちの一つと引廻配線43との交差部分に短絡が生じた場合には、容量配線33においてスリット44を挟んで配される複数の部分のうち、引廻配線43と短絡した部分を切断することで、引廻配線43とは短絡していない部分を利用して容量配線33に信号などを伝送させることができる。以上のように、本実施形態によれば、ゲート配線26及び容量配線33と引廻配線43との重畳面積を小さくしつつ短絡発生時の修理を行うのに好適なアレイ基板20を提供することができる。 For example, when a short circuit occurs at an intersection between one of a plurality of portions arranged across the slit 44 in the capacitive wiring 33 and the lead wiring 43, the slit 44 is sandwiched in the capacitive wiring 33. By cutting a portion that is short-circuited with the lead-out wiring 43 among the plurality of portions that are arranged, a signal or the like can be transmitted to the capacitor wiring 33 using a portion that is not short-circuited with the lead-out wiring 43. . As described above, according to the present embodiment, it is possible to provide an array substrate 20 suitable for repairing when a short circuit occurs while reducing the overlapping area of the gate wiring 26 and the capacitor wiring 33 and the routing wiring 43. Can do.
 また、ゲート配線26と容量配線33とは、交互に並ぶ形で複数ずつ配されている。このようにすれば、仮にゲート配線26または容量配線33を複数続けて並べた場合に比べると、架渡し部45の設置数を多くすることが可能となり、もって修理の自由度を高める上で好適となる。 In addition, a plurality of gate wirings 26 and capacitor wirings 33 are arranged alternately. In this way, it is possible to increase the number of installation portions 45 and to increase the degree of freedom in repair, as compared with a case where a plurality of gate wirings 26 or capacitor wirings 33 are continuously arranged. It becomes.
 また、架渡し部45は、ゲート配線26と、ゲート配線26を挟んで隣り合う一対の容量配線33との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている。このようにすれば、ゲート配線26が引廻配線43と短絡した場合、そのゲート配線26に対して隣り合う一対の容量配線33のいずれをも修理に利用することができるから、修理を行う上での自由度が高まる。例えば、引廻配線43と短絡したゲート配線26に対して隣り合う一方の容量配線33が引廻配線43と短絡した場合でも、ゲート配線26に対して隣り合う他方の容量配線33を利用してゲート配線26の信号を伝送するよう修理しつつ、一方の容量配線33については引廻配線43との短絡箇所を切り離すことで修理を行うことができる。 Further, at least one pair of the bridging portions 45 are formed so as to bridge between the gate wiring 26 and the pair of adjacent capacitor wirings 33 with the gate wiring 26 interposed therebetween. In this way, when the gate line 26 is short-circuited with the routing line 43, any of the pair of capacitor lines 33 adjacent to the gate line 26 can be used for repair. Increases freedom in For example, even when one capacitor wiring 33 adjacent to the gate wiring 26 short-circuited to the routing wiring 43 is short-circuited to the routing wiring 43, the other capacitance wiring 33 adjacent to the gate wiring 26 is used. While repairing to transmit the signal of the gate wiring 26, one capacity wiring 33 can be repaired by disconnecting the short-circuited portion with the lead wiring 43.
 また、容量配線33は、スリット44が形成されるスリット形成部分33aと、スリット44が形成されないスリット非形成部分33bとからなり、スリット形成部分33aとスリット非形成部分33bとで線幅が等しいものとされる。このようにすれば、容量配線33の線幅がスリット形成部分33aとスリット非形成部分33bとで変化することがないから、製造が容易になるとともに省スペース化を図る上でもより好適となる。 The capacitor wiring 33 includes a slit forming portion 33a where the slit 44 is formed and a slit non-forming portion 33b where the slit 44 is not formed, and the slit forming portion 33a and the slit non-forming portion 33b have the same line width. It is said. By doing so, the line width of the capacitor wiring 33 does not change between the slit forming portion 33a and the slit non-forming portion 33b, which is more suitable for facilitating manufacturing and space saving.
 また、架渡し部45と引廻配線43とが同じ層に配されており、架渡し部45及び引廻配線43と、ゲート配線26及び容量配線33との間に介在するゲート絶縁膜35が同一とされている。このようにすれば、引廻配線43を形成する際に一括して架渡し部45を形成することができるから、製造コストを低減する上で好適となる。 In addition, the transfer portion 45 and the routing wiring 43 are arranged in the same layer, and a gate insulating film 35 interposed between the routing portion 45 and the routing wiring 43, the gate wiring 26 and the capacitor wiring 33 is provided. Identical. In this way, the transfer portion 45 can be formed collectively when the lead wiring 43 is formed, which is preferable in reducing the manufacturing cost.
 また、スリット44は、容量配線33において引廻配線43を挟む位置に配される少なくとも一対の架渡し部45を超える範囲にわたって形成されている。このようにすれば、例えば、ゲート配線26と引廻配線43との交差部分に短絡が生じた場合には、容量配線33においてスリット44を挟んで配される複数の部分のうち、ゲート配線26に対して少なくとも一対の架渡し部45により短絡される部分を切断する。このとき、容量配線33における切断位置を、容量配線33の延在方向についてスリット44と重なる位置関係とすることができ、それにより容量配線33の一部を直線的に横断する形で切断することが可能となる。従って、容量配線33の一部を切り離す際の確実性が高くなるなどの効果を得ることができる。 Further, the slit 44 is formed over a range exceeding at least a pair of the spanning portions 45 arranged at positions where the lead wiring 43 is sandwiched in the capacitor wiring 33. In this way, for example, when a short circuit occurs at the intersection of the gate wiring 26 and the routing wiring 43, the gate wiring 26 among the plurality of portions arranged with the slit 44 interposed in the capacitor wiring 33. In contrast, at least a portion short-circuited by the pair of spanning portions 45 is cut. At this time, the cutting position in the capacitor wiring 33 can be set to a positional relationship overlapping with the slit 44 in the extending direction of the capacitor wiring 33, thereby cutting a part of the capacitor wiring 33 linearly. Is possible. Therefore, it is possible to obtain an effect such as high reliability when part of the capacitor wiring 33 is cut off.
 また、ゲート配線26に接続されるゲート電極(第1電極)24aを少なくとも有するTFT(スイッチング素子)24を備える。このようにすれば、ゲート配線26と引廻配線43との交差部分に生じる短絡、及び容量配線33と引廻配線43との交差部分に生じる短絡をそれぞれ修理することができるから、TFT24を適切に駆動することができる。 Further, a TFT (switching element) 24 having at least a gate electrode (first electrode) 24 a connected to the gate wiring 26 is provided. In this way, a short circuit occurring at the intersection between the gate wiring 26 and the routing wiring 43 and a short circuit occurring at the intersection between the capacitance wiring 33 and the routing wiring 43 can be repaired. Can be driven to.
 また、本実施形態に係るアレイ基板20の製造方法は、ガラス基板(基板)GS上に、ゲート配線26と、ゲート配線26に並行するとともにゲート配線26に隣り合って配される容量配線33と、ゲート配線26及び容量配線33に対してゲート絶縁膜35を介しつつ交差する引廻配線43と、容量配線33のうち少なくとも引廻配線43を跨ぐ部分に配されるスリット44と、引廻配線43を挟む位置に少なくとも一対配されるものであって、ゲート配線26及び容量配線33に対してゲート絶縁膜35を介して配されることでゲート配線26及び容量配線33と絶縁されるとともにゲート配線26と容量配線33との間に架け渡される架渡し部45と、を形成する配線形成工程と、ゲート配線26と引廻配線43との交差部分と、容量配線33と引廻配線43との交差部分とに短絡が生じているか否かをそれぞれ検査する検査工程と、ゲート配線26と引廻配線43との交差部分に短絡が生じていた場合には、ゲート配線26のうち、引廻配線43を挟み且つ少なくとも一対の架渡し部45の間に挟まれる部分を切断してゲート配線26から切り離す一方で、ゲート配線26とそれに隣り合う容量配線33との間に架け渡された少なくとも一対の架渡し部45を、ゲート配線26及び容量配線33に対してそれぞれ短絡させ、さらには容量配線33においてスリット44を挟んで配される複数の部分のうちゲート配線26に対して少なくとも一対の架渡し部45により短絡される部分を切断して容量配線33から切り離すようにし、また容量配線33と引廻配線43との交差部分に短絡が生じていた場合には、容量配線33においてスリット44を挟んで配される複数の部分のうち引廻配線43と短絡した部分を切断する、修理工程とを行う。 In addition, the method for manufacturing the array substrate 20 according to the present embodiment includes a gate wiring 26 on the glass substrate (substrate) GS, and a capacitor wiring 33 that is arranged in parallel with the gate wiring 26 and adjacent to the gate wiring 26. The routing wiring 43 intersecting the gate wiring 26 and the capacitance wiring 33 with the gate insulating film 35 interposed therebetween, the slit 44 disposed at least in the portion of the capacitance wiring 33 across the routing wiring 43, and the routing wiring The gate wiring 26 and the capacitor wiring 33 are arranged via the gate insulating film 35 so as to be insulated from the gate wiring 26 and the capacitor wiring 33 and to be gated. A wiring forming step for forming a bridge portion 45 that is bridged between the wiring 26 and the capacitor wiring 33, an intersection between the gate wiring 26 and the routing wiring 43, When an inspection process for inspecting whether or not a short circuit has occurred at the intersection of the wiring 33 and the lead wiring 43 and when a short circuit has occurred at the intersection of the gate wiring 26 and the lead wiring 43, Of the gate wiring 26, a portion sandwiched between the routing wiring 43 and at least a pair of the crossing portions 45 is cut off and separated from the gate wiring 26, while the gate wiring 26 and the capacitor wiring 33 adjacent thereto are separated. At least a pair of the bridging portions 45 spanned between them are short-circuited with respect to the gate wiring 26 and the capacitor wiring 33, respectively. 26, at least a portion short-circuited by the pair of crossover portions 45 is cut so as to be separated from the capacitor wiring 33, and the capacitor wiring 33 and the lead wiring 43 are interchanged. When the short circuit has occurred in the portion cuts the portion of short-circuited with lead-wires 43 of the plurality of portions are arranged to sandwich the slit 44 in the capacitor line 33, it performs a repair process.
 このように、ゲート配線26に隣り合う容量配線33の一部を、ゲート配線26に短絡が生じた場合の修理に利用することができるから、仮に引廻配線43にスリット44を設けることで対応した場合に比べると、引廻配線43の線幅を小さくすることができる。引廻配線43は、ゲート配線26及び容量配線33の双方に対して交差するものであるから、その線幅が小さくなれば、ゲート配線26及び容量配線33との重畳面積も小さくなる。従って、ゲート配線26及び容量配線33と引廻配線43との間に生じ得る寄生容量が小さくなり、また短絡が生じる可能性自体が低減される、などの効果を得ることができる。また、仮にゲート配線26及び容量配線33とは別途に修理専用の配線を設けた場合に比べると、ゲート配線26と容量配線33との間のスペースを小さくすることができるので、省スペース化などを図る上で好適となる。 In this way, a part of the capacitor wiring 33 adjacent to the gate wiring 26 can be used for repair when a short circuit occurs in the gate wiring 26, so that provision is made by providing a slit 44 in the lead wiring 43. Compared to the case, the line width of the lead wiring 43 can be reduced. Since the routing wiring 43 intersects with both the gate wiring 26 and the capacitor wiring 33, the overlapping area between the gate wiring 26 and the capacitor wiring 33 decreases as the line width decreases. Accordingly, it is possible to obtain an effect that the parasitic capacitance that can be generated between the gate wiring 26 and the capacitor wiring 33 and the lead wiring 43 is reduced, and that the possibility of a short circuit is reduced. Further, the space between the gate wiring 26 and the capacitor wiring 33 can be reduced as compared with the case where a repair-dedicated wiring is provided separately from the gate wiring 26 and the capacitor wiring 33, so that space saving can be achieved. This is suitable for achieving the above.
 以上、本発明の実施形態1を示したが、本発明は上記実施の形態に限られるものではなく、例えば以下のような変形例を含むこともできる。なお、以下の各変形例において、上記実施形態と同様の部材には、上記実施形態と同符号を付して図示及び説明を省略するものもある。 As mentioned above, although Embodiment 1 of this invention was shown, this invention is not restricted to the said embodiment, For example, the following modifications can also be included. In the following modifications, members similar to those in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and illustration and description thereof may be omitted.
[実施形態1の変形例1]
 実施形態1の変形例1について図13を用いて説明する。ここでは、架渡し部45‐1の設置数を変更したものを示す。
[Modification 1 of Embodiment 1]
A first modification of the first embodiment will be described with reference to FIG. Here, what changed the installation number of the transfer part 45-1 is shown.
 本変形例に係る架渡し部45‐1は、図13に示すように、その設置数が上記した実施形態1の半分程度となっている。詳しくは、架渡し部45‐1は、容量配線33‐1におけるスリット形成部分33a‐1を構成する一対の分割部33a1‐1のうちの一方の分割部33a1‐1(図13では上側の分割部33a1‐1)と、それに隣り合うゲート配線26‐1とを架け渡すもののみが形成されており、他方の分割部33a1‐1(図13では下側の分割部33a1‐1)と、それに隣り合うゲート配線26‐1とを架け渡すものが形成されていない。このような構成であっても、各ゲート配線26‐1は、隣り合う1本の容量配線33‐1に対して架渡し部45‐1によって架け渡されているから、引廻配線43‐1との交差部分が短絡した場合でも、架渡し部45‐1に架け渡された容量配線33‐1を利用して修理を行うことが可能となっている。 As shown in FIG. 13, the number of installations of the transfer unit 45-1 according to this modification is about half that of the first embodiment described above. Specifically, the transfer part 45-1 is one of the divided parts 33a1-1 (the upper divided part in FIG. 13) of the pair of divided parts 33a1-1 constituting the slit forming part 33a-1 in the capacitor wiring 33-1. Only a portion that bridges the portion 33a1-1) and the gate wiring 26-1 adjacent thereto is formed, and the other divided portion 33a1-1 (the lower divided portion 33a1-1 in FIG. 13), No bridge is formed between adjacent gate lines 26-1. Even in such a configuration, each of the gate wirings 26-1 is bridged by the bridging portion 45-1 with respect to the adjacent one of the capacitance wirings 33-1. Even when the crossing point with the short circuit is short-circuited, it is possible to perform repair using the capacitive wiring 33-1 spanned over the bridging portion 45-1.
[実施形態1の変形例2]
 実施形態1の変形例2について図14を用いて説明する。ここでは、ゲート配線26‐2及び容量配線33‐2の構成を変更したものを示す。
[Modification 2 of Embodiment 1]
A second modification of the first embodiment will be described with reference to FIG. Here, the configuration of the gate wiring 26-2 and the capacitor wiring 33-2 is changed.
 本変形例に係るゲート配線26‐2及び容量配線33‐2には、図14に示すように、スリット44‐2が形成されたものと、スリット44‐2が形成されていないものとがそれぞれ含まれている。詳しくは、ゲート配線26‐2及び容量配線33‐2は、Y軸方向について交互に並ぶ形で多数本ずつ形成されているが、スリット44‐2を有するゲート配線26‐2及び容量配線33‐2が1本ずつ続けて並んでから、スリット44‐2を有さないゲート配線26‐2及び容量配線33‐2が1本ずつ続けて並ぶ、といった順で配列されている。つまり、ゲート配線26‐2及び容量配線33‐2は、スリット44‐2を有するものと、スリットを有さないものとが2本ずつ交互に並ぶ形で配されている。架渡し部45‐2は、ゲート配線26‐2及び容量配線33‐2のうち、スリット44‐2を有するものと、それに隣り合うスリット44‐2を有さないものとを架け渡すよう形成されている。従って、ゲート配線26‐2及び容量配線33‐2のうち、互いに隣り合うスリット44‐2を有するもの同士の間には架渡し部45‐2が形成されておらず、また互いに隣り合うスリット44‐2を有さないもの同士の間には架渡し部45‐2が形成されていない。本変形例では、多数本あるゲート配線26‐2及び多数本ある容量配線33‐2に、それぞれスリット44‐2を有さない「第1配線」と、スリット44‐2を有する「第2配線」とが混在しており、またこれらと交差する引廻配線43‐2が「第3配線」となっている。 As shown in FIG. 14, the gate wiring 26-2 and the capacitor wiring 33-2 according to the present modification are each formed with a slit 44-2 and without a slit 44-2. include. Specifically, the gate wiring 26-2 and the capacitor wiring 33-2 are formed in a plurality of lines alternately arranged in the Y-axis direction. However, the gate wiring 26-2 and the capacitor wiring 33- having the slit 44-2 are formed. 2 are arranged one by one, and then the gate wiring 26-2 and the capacitor wiring 33-2 not having the slit 44-2 are arranged one by one. That is, the gate wiring 26-2 and the capacitor wiring 33-2 are arranged in such a manner that two having a slit 44-2 and one having no slit are alternately arranged. The bridge portion 45-2 is formed so as to bridge the gate wiring 26-2 and the capacitor wiring 33-2 that have the slit 44-2 and the one that does not have the slit 44-2 adjacent thereto. ing. Accordingly, between the gate wiring 26-2 and the capacitor wiring 33-2 having the slits 44-2 adjacent to each other, the bridge portion 45-2 is not formed, and the slits 44 adjacent to each other are not formed. The bridge portion 45-2 is not formed between those having no -2. In the present modification, a large number of gate wirings 26-2 and a large number of capacitance wirings 33-2 each have a “first wiring” that does not have the slit 44-2 and a “second wiring that has the slit 44-2. ”And the routing wiring 43-2 intersecting with these are“ third wiring ”.
[実施形態1の変形例3]
 実施形態1の変形例3について図15を用いて説明する。ここでは、スリット44‐3の形成範囲(架渡し部45‐3の配置)を変更したものを示す。
[Modification 3 of Embodiment 1]
A third modification of the first embodiment will be described with reference to FIG. Here, what changed the formation range (arrangement | positioning of the spanning part 45-3) of the slit 44-3 is shown.
 本変形例に係るスリット44‐3は、図15に示すように、容量配線33‐3において引廻配線43‐3を挟む位置に配される一対の架渡し部45‐3を超えない範囲にわたって形成されている。詳しくは、スリット44‐3は、その両端部がX軸方向について一対の架渡し部45‐3よりも引廻配線43‐3寄りの位置、つまり架渡し部45‐3と引廻配線43‐3との間の位置に配されている。従って、架渡し部45‐3は、容量配線33‐3のうちスリット非形成部分33b‐3とゲート配線26‐3とを架け渡している。このような構成において、ゲート配線26‐3が引廻配線43‐3に短絡した場合には、ゲート配線26‐3における短絡箇所を切り離すとともに、短絡したゲート配線26‐3の本体部分と隣り合う容量配線33‐3とを架け渡す架渡し部45‐3をそれらゲート配線26‐3及び容量配線33‐3に対して短絡させ、且つ容量配線33‐3のうち架渡し部45‐3によってゲート配線26‐3に短絡された部分を切り離すよう修理を行う。ここで、容量配線33‐3の一部を切り離す際には、容量配線33‐3のスリット非形成部分33b‐3のうち、スリット44‐3の端部に対してレーザ光を照射し、そこから引廻配線43‐3側とは反対側に向けてX軸方向に沿って直線的に切断し、ゲート配線26‐3に短絡される架渡し部45‐3を超えたところで、架渡し部45‐3により短絡されるゲート配線26‐3側に向けてY軸方向に沿って直線的に切断する(切断部BP2‐3)。このように、容量配線33‐3のスリット非形成部分33b‐3をL字型に切断することで、架渡し部45‐3によってゲート配線26‐3と短絡される部分を、元の容量配線33‐3から切り離して電気的に独立させることができる。 As shown in FIG. 15, the slit 44-3 according to the present modification extends over a range not exceeding a pair of spanning portions 45-3 arranged at positions where the lead wiring 43-3 is sandwiched in the capacitance wiring 33-3. Is formed. Specifically, the slit 44-3 has both ends positioned closer to the routing wiring 43-3 than the pair of routing portions 45-3 in the X-axis direction, that is, the routing portion 45-3 and the routing wiring 43-. It is arranged at a position between three. Therefore, the bridge portion 45-3 bridges the slit non-formed portion 33b-3 and the gate line 26-3 in the capacitor line 33-3. In such a configuration, when the gate wiring 26-3 is short-circuited to the routing wiring 43-3, the short-circuited portion in the gate wiring 26-3 is separated and adjacent to the main body portion of the shorted gate wiring 26-3. The connecting portion 45-3 that bridges the capacitor wiring 33-3 is short-circuited to the gate wiring 26-3 and the capacitor wiring 33-3, and the gate is formed by the connecting portion 45-3 of the capacitor wiring 33-3. Repair is performed so as to separate the part short-circuited to the wiring 26-3. Here, when part of the capacitor wiring 33-3 is cut off, laser light is irradiated to the end of the slit 44-3 in the slit non-formed portion 33b-3 of the capacitor wiring 33-3. Is cut linearly along the X-axis direction from the lead wire 43-3 toward the opposite side to the side of the lead wire 43-3 and beyond the crossover portion 45-3 short-circuited to the gate wire 26-3, the crossover portion Cut linearly along the Y-axis direction toward the gate wiring 26-3 side that is short-circuited by 45-3 (cutting portion BP2-3). In this way, by cutting the non-slit portion 33b-3 of the capacitor wiring 33-3 into an L shape, the portion short-circuited with the gate wiring 26-3 by the bridge portion 45-3 is replaced with the original capacitor wiring. It can be separated from 33-3 and made electrically independent.
 <実施形態2>
 本発明の実施形態2を図16または図17によって説明する。この実施形態2では、架渡し部145の配置を変更したものを示す。なお、上記した実施形態1と同様の構造、作用及び効果について重複する説明は省略する。
<Embodiment 2>
A second embodiment of the present invention will be described with reference to FIG. 16 or FIG. In the second embodiment, the arrangement of the transfer unit 145 is changed. In addition, the overlapping description about the same structure, an effect | action, and effect as above-mentioned Embodiment 1 is abbreviate | omitted.
 本実施形態に係る架渡し部145は、図16に示すように、平面に視て千鳥状に配置されている。詳しくは、ゲート配線126を挟んで隣り合う一対の容量配線133のうち、一方の容量配線133と上記ゲート配線126との間に架け渡される一対の架渡し部145(以下、これを第1の組をなす一対の架渡し部145Aとする)と、他方の容量配線133と上記ゲート配線126との間に架け渡される一対の架渡し部145(以下、これを第2の組をなす一対の架渡し部145Bとする)とでは、X軸方向、つまりゲート配線126及び容量配線133の延在方向について互いにずれた位置に配されている。従って、同じゲート配線126または容量配線133に架け渡された第1の組をなす一対の架渡し部145Aと、第2の組をなす一対の架渡し部145Bとは、Y軸方向に沿って直線的に並ぶことがなく、千鳥状(ジグザグ状)に交互に並ぶ形で配されている。 As shown in FIG. 16, the transfer portions 145 according to the present embodiment are arranged in a staggered manner when viewed in plan. Specifically, of a pair of capacitor wirings 133 that are adjacent to each other with the gate wiring 126 interposed therebetween, a pair of bridging portions 145 (hereinafter referred to as the first wiring section 145) spanned between one capacitor wiring 133 and the gate wiring 126. A pair of bridge portions 145A forming a pair) and a pair of bridge portions 145 (hereinafter referred to as a second pair of bridge portions 145) bridged between the other capacitor wiring 133 and the gate wiring 126. In this case, they are arranged at positions shifted from each other in the X-axis direction, that is, in the extending direction of the gate wiring 126 and the capacitor wiring 133. Therefore, the pair of the bridging portions 145A and the pair of the bridging portions 145B that form the first group spanned over the same gate wiring 126 or the capacitor wiring 133 extend along the Y-axis direction. They are not arranged in a straight line, but are arranged in a staggered (zigzag) pattern.
 詳しくは、第1の組をなす一対の架渡し部145Aのうち、一方の架渡し部145Aとスリット144における一方の端部との間の距離は、図16に示すように、他方の架渡し部145Aとスリット144における他方の端部との間の距離とは異なるものとされる。第2の組をなす一対の架渡し部145Bのうち、一方の架渡し部145Bとスリット144における一方の端部との間の距離は、上記した第1の組をなす他方の架渡し部145Aとスリット144における他方の端部との間の距離にほぼ等しく、また他方の架渡し部145Bと、スリット144における他方の端部との間の距離は、上記した第1の組をなす一方の架渡し部145Aとスリット144における一方の端部との間の距離にほぼ等しい。また、容量配線133を挟んで隣り合う一対のゲート配線126のうち、一方のゲート配線126と上記容量配線133との間に架け渡される一対の架渡し部145と、他方のゲート配線126と上記容量配線133との間に架け渡される一対の架渡し部145とでは、X軸方向、つまりゲート配線126及び容量配線133の延在方向について互いにずれた位置に配されている、とも言える。 Specifically, of the pair of spanning portions 145A forming the first set, the distance between one spanning portion 145A and one end of the slit 144 is the other spanning as shown in FIG. The distance between the portion 145A and the other end of the slit 144 is different. Of the pair of spanning portions 145B forming the second set, the distance between one spanning portion 145B and one end of the slit 144 is the other spanning portion 145A forming the first set. Is substantially equal to the distance between the other end portion of the slit 144 and the distance between the other span portion 145B and the other end portion of the slit 144 is one of the above-mentioned first set. It is approximately equal to the distance between the span 145A and one end of the slit 144. Of the pair of gate wirings 126 adjacent to each other with the capacitor wiring 133 interposed therebetween, the pair of bridging portions 145 spanned between one gate wiring 126 and the capacitor wiring 133, the other gate wiring 126, and the above-described gate wiring 126. It can also be said that the pair of bridge portions 145 spanned between the capacitor wiring 133 are arranged at positions shifted from each other in the X-axis direction, that is, the extending direction of the gate wiring 126 and the capacitor wiring 133.
 ところで、架渡し部145をパターニングする際には、パターニング不良が生じる可能性があり、その場合には、図17に示すように、架渡し部145の大きさや形状などが正常ではなくなり、正常なものよりも広範囲にわたって形成されるおそれがある。そのような場合でも、上記したように第1の組をなす架渡し部145Aと、第2の組をなす架渡し部145Bとが、X軸方向についてずれた位置に配されているから、両者145A,145B間の距離が十分に大きく確保されており、それによりいずれかの架渡し部145にパターニング不良が生じたとしても、その不良が生じた架渡し部145が隣り合う架渡し部145に対して短絡する、といった事態が生じ難くなっている。これにより、ゲート配線126や容量配線133の修理を行う際に、各架渡し部145の機能を確実に発揮させることができる。 By the way, when patterning the transfer part 145, patterning failure may occur. In this case, as shown in FIG. 17, the size and shape of the transfer part 145 are not normal and normal. There is a possibility that it is formed over a wider range than the one. Even in such a case, as described above, the spanning portion 145A forming the first set and the spanning portion 145B forming the second set are arranged at positions shifted in the X-axis direction. The distance between 145A and 145B is secured sufficiently large, and even if a patterning failure occurs in any of the transfer portions 145, the transfer portion 145 in which the failure has occurred is adjacent to the adjacent transfer portion 145. In contrast, short-circuiting is unlikely to occur. Thereby, when repairing the gate wiring 126 and the capacitor wiring 133, the function of each bridge portion 145 can be reliably exhibited.
 以上説明したように本実施形態によれば、ゲート配線126と一対の容量配線133のうちの一方の容量配線133との間を架け渡す一方の架渡し部145Aと、ゲート配線126と一対の容量配線133のうちの他方の容量配線133との間を架け渡す他方の架渡し部145Bとは、ゲート配線126の延在方向について互いにずれた位置に配されている。このようにすれば、仮に、一方の架渡し部145Aと他方の架渡し部145Bとをゲート配線126の延在方向について同じ位置に配した場合に比べると、一方の架渡し部145Aと他方の架渡し部145Bとの間の距離が相対的に大きくなるから、一方の架渡し部145Bと他方の架渡し部145Bとが短絡し難くなる。 As described above, according to the present embodiment, one bridge portion 145A that bridges between the gate line 126 and one of the pair of capacitor lines 133, and the gate line 126 and the pair of capacitors. The other crossing part 145 </ b> B that bridges the other wiring line 133 among the wiring lines 133 is arranged at a position shifted from each other in the extending direction of the gate line 126. In this way, it is assumed that one of the crossover portions 145A and the other of the crossover portions 145A and the other crossover portion 145B are disposed at the same position in the extending direction of the gate wiring 126. Since the distance between the transfer part 145B is relatively large, it is difficult for one transfer part 145B and the other transfer part 145B to be short-circuited.
 また、容量配線133と容量配線133を挟んで配される一対のゲート配線126のうちの一方のゲート配線126との間を架け渡す一方の架渡し部145Aと、容量配線133と一対のゲート配線126のうちの他方のゲート配線126との間を架け渡す他方の架渡し部145Bとは、容量配線133の延在方向について互いにずれた位置に配されている。このようにすれば、仮に、一方の架渡し部145Aと他方の架渡し部145Bとを容量配線133の延在方向について同じ位置に配した場合に比べると、一方の架渡し部145Aと他方の架渡し部145Bとの間の距離が相対的に大きくなるから、一方の架渡し部145Aと他方の架渡し部145Bとが短絡し難くなる。 In addition, one cross-over portion 145A that bridges between the gate wiring 126 of the pair of gate wirings 126 arranged with the capacitance wiring 133 and the capacitance wiring 133 interposed therebetween, and the capacitance wiring 133 and the pair of gate wirings The other bridging portion 145B that bridges between the other gate wiring 126 of 126 is arranged at a position shifted from each other in the extending direction of the capacitor wiring 133. In this way, if compared with the case where one bridge 145A and the other bridge 145B are arranged at the same position in the extending direction of the capacitor wiring 133, the one bridge 145A and the other bridge 145B are compared with each other. Since the distance between the transfer part 145B is relatively large, it is difficult for one transfer part 145A and the other transfer part 145B to be short-circuited.
 <実施形態3>
 本発明の実施形態3を図18によって説明する。この実施形態3では、複数の引廻配線243に対するゲート配線226及び容量配線233の各交差部分の構成を示す。なお、上記した実施形態1と同様の構造、作用及び効果について重複する説明は省略する。
<Embodiment 3>
A third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the configuration of each intersection of the gate wiring 226 and the capacitor wiring 233 with respect to the plurality of routing wirings 243 is shown. In addition, the overlapping description about the same structure, an effect | action, and effect as above-mentioned Embodiment 1 is abbreviate | omitted.
 本実施形態では、互いに並行する複数本の引廻配線243のうち、2本の引廻配線243A,243Bと、ゲート配線226及び容量配線233との各交差部分の構成について説明する。なお、以下では、2本の引廻配線243A,243Bのうち、図18において左側に示すものを第1引廻配線(第3配線)243Aとし、同図右側に示すものを第2引廻配線(第4配線)243Bとする。 In the present embodiment, the configuration of each crossing portion of the two routing wirings 243A and 243B, the gate wiring 226, and the capacitance wiring 233 among the plurality of routing wirings 243 parallel to each other will be described. In the following, of the two routing wirings 243A and 243B, the one shown on the left side in FIG. 18 is referred to as a first routing wiring (third wiring) 243A, and the one shown on the right side in FIG. (Fourth wiring) 243B.
 まず、第1引廻配線243Aと、ゲート配線226及び容量配線233との交差部分の構成については、上記した実施形態1と概ね同様である。すなわち、容量配線233のうち、第1引廻配線243Aを跨ぐ部分には、図18に示すように、スリット244が形成されており、また第1引廻配線243Aを挟む位置に配された一対の架渡し部245が隣り合うゲート配線226と容量配線233との間を架け渡している。一方、第2引廻配線243Bと、ゲート配線226及び容量配線233との交差部分の構成について説明すると、ゲート配線226のうち第2引廻配線243Bを跨ぐ部分には、第2のスリット46が形成されている。さらには、隣り合うゲート配線226と容量配線233との間は、第2引廻配線243Bを挟む位置に一対ずつ配された第2の架渡し部47によって架け渡されている。従って、本実施形態では、第1引廻配線243Aとの交差部分にスリット244を有する容量配線233と、第2引廻配線243Bとの交差部分に第2のスリット47を有するゲート配線226とが交互に並ぶ形で配されていることになる。そして、これらゲート配線226と容量配線233とは、それぞれがスリット244または第2のスリット46を有しているため、上記した実施形態1に比べると、両配線226,233間における配線抵抗の差が小さくなっている。 First, the configuration of the intersection of the first lead wiring 243A, the gate wiring 226, and the capacitor wiring 233 is substantially the same as in the first embodiment. That is, as shown in FIG. 18, a slit 244 is formed in a portion of the capacitor wiring 233 that straddles the first routing wiring 243A, and a pair of the wirings 233A that are disposed at positions sandwiching the first routing wiring 243A. The intermediate portion 245 bridges between the adjacent gate wiring 226 and the capacitor wiring 233. On the other hand, the configuration of the intersection of the second routing wiring 243B, the gate wiring 226, and the capacitance wiring 233 will be described. The second slit 46 is formed in the gate wiring 226 across the second routing wiring 243B. Is formed. Further, the adjacent gate wiring 226 and the capacitor wiring 233 are bridged by the second bridge 47 arranged in pairs at positions sandwiching the second routing wiring 243B. Therefore, in the present embodiment, the capacitor wiring 233 having the slit 244 at the intersection with the first routing wiring 243A and the gate wiring 226 having the second slit 47 at the intersection with the second routing wiring 243B are provided. It will be arranged in an alternating form. Since each of the gate wiring 226 and the capacitor wiring 233 has the slit 244 or the second slit 46, the wiring resistance difference between the wirings 226 and 233 is different from that in the first embodiment. Is getting smaller.
 ゲート配線226が有する第2のスリット46は、図18に示すように、その平面形状及び形成範囲が、容量配線233が有するスリット244とほぼ同様とされる。また、第2の架渡し部47についても、その形成範囲及び配置が架渡し部245とほぼ同様とされる。従って、第2のスリット46は、ゲート配線226において第2引廻配線243Bを挟む位置に配される一対の第2の架渡し部47を超える範囲にわたって形成されている。また、第2の架渡し部47は、ゲート配線226と、ゲート配線226を挟んで隣り合う一対の容量配線233との間をそれぞれ架け渡す形で一対ずつ形成されている。 As shown in FIG. 18, the second slit 46 included in the gate wiring 226 has a planar shape and a formation range substantially the same as the slit 244 included in the capacitor wiring 233. Further, the formation range and arrangement of the second transfer portion 47 are substantially the same as those of the transfer portion 245. Therefore, the second slit 46 is formed over a range exceeding the pair of second transfer portions 47 arranged at positions where the second lead wiring 243 </ b> B is sandwiched in the gate wiring 226. A pair of second bridging portions 47 are formed so as to bridge between the gate wiring 226 and a pair of adjacent capacitor wirings 233 across the gate wiring 226.
 このような構成のものにおいて、各引廻配線243とゲート配線226または容量配線233との交差部分に短絡が生じた場合には、次のようにして修理を行う。なお、第1引廻配線243Aに関する修理方法は、上記した実施形態1に記載した通りであるからその説明は割愛し、以下では第2引廻配線243Bに関する修理方法についてのみ説明する。第2引廻配線243Bと容量配線233との交差部分において短絡(短絡箇所SP4)が発生した場合には、容量配線233のうち、X軸方向について、短絡した第2引廻配線243Bと一対の第2の架渡し部47との間の2位置にレーザ光を照射し、当該位置にて容量配線233を横切るようにしてY軸方向に沿って直線的に切断して切断部BP4を形成する。これにより、容量配線233における短絡箇所を本体部分から切り離す。 In such a configuration, when a short circuit occurs at the intersection between each routing wiring 243 and the gate wiring 226 or the capacitor wiring 233, the repair is performed as follows. The repair method related to the first lead wiring 243A is as described in the first embodiment, and therefore the description thereof will be omitted. Hereinafter, only the repair method related to the second lead wiring 243B will be described. When a short circuit (short circuit location SP4) occurs at the intersection between the second routing wiring 243B and the capacitance wiring 233, the second wiring wiring 243B shorted in the X-axis direction of the capacitance wiring 233 and a pair of Laser light is applied to two positions between the second crossing section 47 and linearly cut along the Y-axis direction so as to cross the capacitive wiring 233 at the position to form a cut section BP4. . Thereby, the short circuit location in the capacity wiring 233 is separated from the main body portion.
 その一方で、第2の架渡し部47のうち、短絡が生じた容量配線233と平面視重畳する部分、及びゲート配線226と平面視重畳する部分に対してそれぞれレーザ光を照射すると、照射箇所におけるゲート絶縁膜が溶融されることで、第2の架渡し部47における上記各重畳部分がゲート配線226及び容量配線233に対して短絡されて短絡部SP5が形成される。これにより、第2引廻配線243Bと短絡した容量配線233の本体部分(短絡した部分を除いた部分)を、隣り合うゲート配線226の一部(分割部226a1)に対して電気的に接続することができる。さらには、ゲート配線226において第2のスリット46を挟んで配される2つの分割部226a1のうち、第2の架渡し部47によって容量配線233と短絡される分割部226a1にレーザ光を照射することでこれを切断して切り離すことで切断部BP5が形成される。これにより、第2の架渡し部47によって容量配線233と短絡される分割部226a1を、元のゲート配線226から切り離して電気的に独立させることができる。 On the other hand, when the laser beam is irradiated to the portion of the second transfer portion 47 that overlaps the capacitor wiring 233 in which the short circuit occurs and the portion that overlaps the gate wiring 226 in plan view, When the gate insulating film is melted, the overlapping portions in the second transfer portion 47 are short-circuited to the gate wiring 226 and the capacitor wiring 233 to form the short-circuit portion SP5. As a result, the main body portion (the portion excluding the short-circuited portion) of the capacitor wiring 233 short-circuited with the second routing wiring 243B is electrically connected to a part of the adjacent gate wiring 226 (dividing portion 226a1). be able to. Further, of the two divided portions 226a1 arranged across the second slit 46 in the gate wiring 226, the laser light is irradiated to the divided portion 226a1 short-circuited with the capacitor wiring 233 by the second bridge portion 47. The cutting part BP5 is formed by cutting and cutting this. Thereby, the division part 226a1 short-circuited with the capacitor wiring 233 by the second transfer part 47 can be separated from the original gate wiring 226 and electrically independent.
 以上の修理を行うことで、第2引廻配線243Bに短絡された容量配線233に供給される信号は、容量配線233の本体部分から第2の架渡し部47を経由して隣り合うゲート配線226の一部である分割部226a1に迂回され、再び第2の架渡し部47を経由して容量配線233の本体部分に流されることで、正常な伝送が図られる。 As a result of the above repair, the signal supplied to the capacitor wiring 233 short-circuited to the second routing wiring 243 </ b> B is transmitted from the main body portion of the capacitance wiring 233 to the adjacent gate wiring via the second bridging portion 47. By diverting to the dividing unit 226a1 which is a part of the H.226 and flowing again to the main body portion of the capacitive wiring 233 via the second transfer unit 47, normal transmission is achieved.
 以上説明したように本実施形態によれば、第1引廻配線243Aに並行するとともに第1引廻配線243Aに隣り合って配され且つゲート配線226及び容量配線233に対してゲート絶縁膜を介しつつ交差する第2引廻配線(第4配線)243Bと、ゲート配線226のうち少なくとも第2引廻配線243Bを跨ぐ部分に配される第2のスリット46と、第2引廻配線243Bを挟む位置に少なくとも一対配されるものであって、ゲート配線226及び容量配線233に対してゲート絶縁膜を介して配されることでゲート配線226及び容量配線233と絶縁されるとともにゲート配線226と容量配線233との間に架け渡される第2の架渡し部47とを備える。このようにすれば、例えば、容量配線233と第2引廻配線243Bとの交差部分に短絡が生じた場合には、容量配線233のうち、第2引廻配線243Bを挟み且つ少なくとも一対の第2の架渡し部47の間に挟まれる部分を切断して容量配線233から切り離す。一方、容量配線233とそれに隣り合うゲート配線226との間に架け渡された少なくとも一対の第2の架渡し部47を、ゲート配線226及び容量配線233に対してそれぞれ短絡させる。さらには、ゲート配線226において第2のスリット46を挟んで配される複数の部分のうち、容量配線233に対して少なくとも一対の第2の架渡し部47により短絡される部分を切断してゲート配線226から切り離す。以上により、ゲート配線226の一部を利用して容量配線233に信号などを伝送させることができる。 As described above, according to the present embodiment, the gate wiring 226 and the capacitor wiring 233 are arranged via the gate insulating film in parallel with the first routing wiring 243A and adjacent to the first routing wiring 243A. The second routing wiring (fourth wiring) 243B intersecting with the second slit 46 sandwiched between at least the second routing wiring 243B of the gate wiring 226 and the second routing wiring 243B are sandwiched. At least a pair is arranged at the position, and the gate wiring 226 and the capacitor wiring 233 are arranged via a gate insulating film so as to be insulated from the gate wiring 226 and the capacitor wiring 233, and at the same time, the gate wiring 226 and the capacitor And a second bridge portion 47 that is bridged between the wiring 233 and the wiring 233. In this way, for example, when a short circuit occurs at the intersection between the capacitive wiring 233 and the second routing wiring 243B, the second routing wiring 243B of the capacitance wiring 233 is sandwiched and at least a pair of the second routing wiring 243B is interposed. The portion sandwiched between the two transfer portions 47 is cut and separated from the capacitor wiring 233. On the other hand, at least a pair of second bridging portions 47 spanned between the capacitor wiring 233 and the gate wiring 226 adjacent thereto are short-circuited to the gate wiring 226 and the capacitor wiring 233, respectively. Further, among the plurality of portions arranged with the second slit 46 interposed in the gate wiring 226, a portion short-circuited by at least the pair of second bridging portions 47 with respect to the capacitor wiring 233 is cut to form a gate. Disconnect from the wiring 226. As described above, a signal or the like can be transmitted to the capacitor wiring 233 by using part of the gate wiring 226.
 このように、容量配線233にスリット44を、ゲート配線226に第2のスリット46をそれぞれ形成しているから、仮に容量配線233にスリット44及び第2のスリット46を共に形成した場合に比べると、ゲート配線226と容量配線233との間に生じ得る配線抵抗の差を軽減することができる。 In this way, the slit 44 is formed in the capacitor wiring 233 and the second slit 46 is formed in the gate wiring 226, respectively. The difference in wiring resistance that can occur between the gate wiring 226 and the capacitor wiring 233 can be reduced.
 なお、例えば、ゲート配線226において第2のスリット46を挟んで配される複数の部分のうちの一つと第2引廻配線243Bとの間に短絡が生じた場合には、ゲート配線226において第2のスリット46を挟んで配される複数の部分のうち、第2引廻配線243Bと短絡した部分を切断することで、第2引廻配線243Bとは短絡していない部分を利用してゲート配線226に信号などを伝送させることができる。 For example, in the case where a short circuit occurs between one of the plurality of portions arranged across the second slit 46 in the gate wiring 226 and the second routing wiring 243B, the first in the gate wiring 226 By cutting a portion short-circuited with the second routing wiring 243B among a plurality of portions arranged with the two slits 46 interposed therebetween, gates are used by utilizing a portion not short-circuited with the second routing wiring 243B. A signal or the like can be transmitted to the wiring 226.
 また、ゲート配線226と容量配線233とは、交互に並ぶ形で複数ずつ配されており、架渡し部45は、ゲート配線226と、ゲート配線226を挟んで隣り合う一対の容量配線233との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されているのに対して、第2の架渡し部47は、容量配線233と、容量配線233を挟んで隣り合う一対のゲート配線226との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている。このようにすれば、ゲート配線226が第1引廻配線243Aと短絡した場合、そのゲート配線226に対して隣り合う一対の容量配線233のいずれをも修理に利用することができるのに加え、容量配線233が第2引廻配線243Bと短絡した場合でも、その容量配線233に対して隣り合う一対のゲート配線226のいずれをも修理に利用することができるから、修理を行う上での自由度が極めて高いものとなる。 A plurality of gate wirings 226 and capacitor wirings 233 are arranged in an alternating manner, and the crossover portion 45 includes a gate wiring 226 and a pair of capacitor wirings 233 adjacent to each other with the gate wiring 226 interposed therebetween. Whereas each pair is formed so as to bridge between each other, the second bridging portion 47 is formed between the capacitor wiring 233 and a pair of adjacent gate wirings 226 across the capacitor wiring 233. At least one pair is formed so as to be bridged. In this way, when the gate wiring 226 is short-circuited with the first routing wiring 243A, any of the pair of capacitor wirings 233 adjacent to the gate wiring 226 can be used for repair. Even when the capacitor wiring 233 is short-circuited with the second lead wiring 243B, any one of the pair of gate wirings 226 adjacent to the capacitor wiring 233 can be used for repair. The degree is extremely high.
 <実施形態4>
 本発明の実施形態4を図19によって説明する。この実施形態4では、架渡し部345の積層方向における配置を変更したものを示す。なお、上記した実施形態1と同様の構造、作用及び効果について重複する説明は省略する。
<Embodiment 4>
A fourth embodiment of the present invention will be described with reference to FIG. In this Embodiment 4, what changed the arrangement | positioning in the lamination direction of the transfer part 345 is shown. In addition, the overlapping description about the same structure, an effect | action, and effect as above-mentioned Embodiment 1 is abbreviate | omitted.
 本実施形態に係る架渡し部345は、図18に示すように、実施形態1に記載した画素電極25と同一材料(ITOなど)からなり且つ製造工程における同一工程にて同一層に形成されている。従って、架渡し部345は、保護膜338のさらに上層側に配されており、架渡し対象であるゲート配線326及び容量配線333との間には、ゲート絶縁膜335、層間絶縁膜337及び保護膜338が介在することで、ゲート配線326及び容量配線333との絶縁状態が保たれている。このような構成であっても、修理に際して架渡し部345をゲート配線326及び容量配線333に短絡させる場合には、レーザ光を照射することで、ゲート絶縁膜335、層間絶縁膜337及び保護膜338を溶融させて架渡し部345をゲート配線326及び容量配線333に接続することが可能とされる。 As shown in FIG. 18, the transfer portion 345 according to the present embodiment is made of the same material (ITO or the like) as the pixel electrode 25 described in the first embodiment, and is formed in the same layer in the same process in the manufacturing process. Yes. Therefore, the transfer portion 345 is disposed on the upper layer side of the protective film 338, and between the gate wiring 326 and the capacitor wiring 333 to be transferred, the gate insulating film 335, the interlayer insulating film 337, and the protective film With the film 338 interposed, an insulating state between the gate wiring 326 and the capacitor wiring 333 is maintained. Even in such a configuration, when the transfer portion 345 is short-circuited to the gate wiring 326 and the capacitor wiring 333 at the time of repair, the gate insulating film 335, the interlayer insulating film 337, and the protective film are irradiated by irradiating laser light. It is possible to melt the 338 and connect the transfer portion 345 to the gate wiring 326 and the capacitor wiring 333.
 <実施形態5>
 本発明の実施形態5を図20から図23によって説明する。この実施形態5では、予備配線48を備えたものを示す。なお、上記した実施形態1と同様の構造、作用及び効果について重複する説明は省略する。
<Embodiment 5>
A fifth embodiment of the present invention will be described with reference to FIGS. In the fifth embodiment, one having a spare wiring 48 is shown. In addition, the overlapping description about the same structure, an effect | action, and effect as above-mentioned Embodiment 1 is abbreviate | omitted.
 本実施形態に係るアレイ基板420における非表示領域NAAには、図20に示すように、ソース配線427に断線などの不良が発生した場合にその修理を行うための予備配線48が複数本形成されている。予備配線48は、枠状をなす非表示領域NAAのうち、ゲートドライバGD側の端部を除いた3つの端部を取り囲むようにして配索形成されており、ソースドライバSD側の端部とその反対側の端部とにおいて、全てのソース配線427の両端部に対してそれぞれ交差しつつ横切っている。予備配線48は、ゲート配線426及び容量配線433と同一材料からなり且つ製造工程における同一工程にて同一層に形成されている。従って、予備配線48は、図22に示すように、ソース配線427の交差部分に対してゲート絶縁膜435を介することで、ソース配線427と絶縁状態に保たれている。 In the non-display area NAA of the array substrate 420 according to the present embodiment, as shown in FIG. 20, a plurality of spare wirings 48 are formed for repairing when a defect such as disconnection occurs in the source wiring 427. ing. The spare wiring 48 is formed so as to surround three ends of the non-display area NAA having a frame shape except for the end on the gate driver GD side, and is connected to the end on the source driver SD side. The other end of the source wiring 427 crosses each other while intersecting the opposite ends. The spare wiring 48 is made of the same material as the gate wiring 426 and the capacitor wiring 433 and is formed in the same layer in the same process in the manufacturing process. Therefore, as shown in FIG. 22, the spare wiring 48 is kept insulated from the source wiring 427 through the gate insulating film 435 at the intersection of the source wiring 427.
 検査工程においていずれかのソース配線427に例えば断線が生じていたことが判明した場合には、修理工程において、断線したソース配線427と予備配線48との2箇所の交差部分にレーザ光を照射することで、相互を短絡させるようにする(図20を参照)。そして、短絡した予備配線48にソース配線427に供給すべき信号などを供給することで、ソース配線427における断線箇所よりも先(ソースドライバSD側とは反対側)に信号を伝送させることができるのである。以下、予備配線48と各ソース配線427との交差部分の構成について詳しく説明する。 In the inspection process, if it is found that any of the source wirings 427 is disconnected, for example, laser light is irradiated to two intersecting portions of the disconnected source wiring 427 and the spare wiring 48 in the repair process. Thus, the two are short-circuited (see FIG. 20). Then, by supplying a signal or the like to be supplied to the source wiring 427 to the short-circuited spare wiring 48, the signal can be transmitted ahead (on the opposite side to the source driver SD side) in the source wiring 427. It is. Hereinafter, the configuration of the intersection of the spare wiring 48 and each source wiring 427 will be described in detail.
 多数本が並列されたソース配線427のうちの奇数番目または偶数番目のいずれかのソース配線427には、図21に示すように、スリット444が形成されている。従って、アレイ基板420上には、スリット444が形成されないソース配線427(以下、第1ソース配線427Aという)と、スリット444が形成されたソース配線427(以下、第2ソース配線427Bという)とがX軸方向について交互に並ぶ形で複数本ずつ配されていることになる。スリット444は、第2ソース配線427Bにおいて予備配線48を跨ぐ所定の範囲にわたって形成されており、詳しくは、第2ソース配線427Bのうち、予備配線48と平面に視て重畳する重畳部分と、その重畳部分を両側から挟み且つ予備配線48とは重畳しない一対の非重畳部分とにわたる範囲に形成されている。スリット444は、Y軸方向、つまりソース配線427の延在方向に並行して直線的に延びる細長い開口からなり、その両端部が平面に視て半円形状をなしている。第2ソース配線427Bは、スリット444が形成されたスリット形成部分427aが2つに分割されており、ここが2つの分割部427a1とされる。第2ソース配線427Bは、スリット形成部分427aと、スリット444が形成されないスリット非形成部分427bとからなるのであるが、これらスリット形成部分427a及びスリット非形成部分427bの線幅は互いに等しいものとされる。従って、容量配線33は、線幅が途中で殆ど変化することがなく、ほぼ全長にわたってほぼ均一な大きさとされている。本実施形態では、多数本あるソース配線427に、スリット444を有さない「第1配線」と、スリット444を有する「第2配線」とが混在しており、またこれらと交差する予備配線48が「第3配線」となっている。 As shown in FIG. 21, a slit 444 is formed in either the odd-numbered or even-numbered source wiring 427 among the source wirings 427 arranged in parallel. Accordingly, on the array substrate 420, there are a source wiring 427 in which the slit 444 is not formed (hereinafter referred to as a first source wiring 427A) and a source wiring 427 in which the slit 444 is formed (hereinafter referred to as a second source wiring 427B). A plurality of lines are arranged alternately in the X-axis direction. The slit 444 is formed over a predetermined range across the spare wiring 48 in the second source wiring 427B. Specifically, in the second source wiring 427B, an overlapping portion that overlaps the spare wiring 48 in a plan view, The overlapping portion is formed in a range covering a pair of non-overlapping portions sandwiching the overlapping portion from both sides and not overlapping with the spare wiring 48. The slit 444 is formed of an elongated opening extending linearly in parallel with the Y-axis direction, that is, the extending direction of the source wiring 427, and both ends thereof have a semicircular shape when viewed in a plane. In the second source wiring 427B, the slit forming portion 427a in which the slit 444 is formed is divided into two, and these are defined as two divided portions 427a1. The second source wiring 427B includes a slit forming portion 427a and a slit non-forming portion 427b in which the slit 444 is not formed. The slit forming portion 427a and the slit non-forming portion 427b have the same line width. The Therefore, the capacity wiring 33 has a substantially uniform size over almost the entire length, with the line width hardly changing in the middle. In the present embodiment, a large number of source wirings 427 include a mixture of “first wirings” that do not have slits 444 and “second wirings” that have slits 444, and spare wirings 48 that intersect these. Is the “third wiring”.
 そして、X軸方向について交互に並ぶ形で多数本ずつ配されるスリット444が形成された第2ソース配線427Bと、スリット444が形成されない第1ソース配線427Aとの間には、図21に示すように、架渡し部445が架け渡されている。架渡し部445は、X軸方向に沿って延びる形態とされていて、互いに隣り合う2本のソース配線427A,427Bを跨ぐようにして両者間に架け渡されている。架渡し部445は、両端部がそれぞれ隣り合うソース配線427A,427Bに対して平面に視て重畳している。この架渡し部445は、図23に示すように、ゲート配線426及び予備配線48と同一材料からなり且つ製造工程における同一工程にて同一層に形成されている。つまり、架渡し部445は、ゲート配線426及び予備配線48と同様に導電性を有しているものの、各ソース配線427A,427Bに対してゲート絶縁膜435を介して下層側に配されることで、通常はソース配線427とは絶縁状態に保たれている。ところが、架渡し部445のうち各ソース配線427A,427Bと平面に視て重畳する部分にレーザ光などを照射すると、その照射箇所においてゲート絶縁膜435が溶融されることで、架渡し部445の重畳部分と各ソース配線427A,427Bとが短絡されるようになっている。 FIG. 21 shows the gap between the second source wiring 427B in which a plurality of slits 444 are arranged in a line alternately in the X-axis direction and the first source wiring 427A in which no slit 444 is formed. As described above, the transfer unit 445 is set over. The bridge portion 445 is configured to extend along the X-axis direction, and is bridged between the two source wires 427A and 427B adjacent to each other. The bridge portion 445 overlaps the source wirings 427A and 427B whose both ends are adjacent to each other in a plan view. As shown in FIG. 23, the transfer portion 445 is made of the same material as the gate wiring 426 and the spare wiring 48 and is formed in the same layer in the same process in the manufacturing process. That is, the bridge portion 445 has conductivity similar to the gate wiring 426 and the spare wiring 48, but is disposed on the lower layer side with respect to the source wirings 427 A and 427 B via the gate insulating film 435. In general, the source wiring 427 is kept in an insulated state. However, when laser light or the like is irradiated on a portion of the transfer portion 445 that overlaps each of the source wirings 427A and 427B in plan view, the gate insulating film 435 is melted at the irradiated portion, so that The overlapping portion and the source wirings 427A and 427B are short-circuited.
 架渡し部445は、図21に示すように、隣り合うソース配線427A,427Bにおいてその延在方向について予備配線48を挟んだ位置に一対が1組で配されており、スリット444を有さない各第1ソース配線427A及びスリット444を有する各第2ソース配線427Bに対して2組ずつ配置されている。つまり、架渡し部445は、各第1ソース配線427A及び第2ソース配線427Bの個々に対して4つずつ設けられていることになる。1つの組をなす一対の架渡し部445は、X軸方向についてスリット444の両端部よりも予備配線48寄りの位置、つまりスリット444の端部と予備配線48との間となる位置にそれぞれ配されている。言い換えると、スリット444は、第2ソース配線427Bにおいて予備配線48を挟む一対の架渡し部445を超える範囲にわたって形成されていることになる。従って、架渡し部445は、第2ソース配線427Bのうちのスリット形成部分427aと第1ソース配線427Aとを架け渡しており、さらに詳しくはスリット形成部分427aを構成する2つの分割部427a1のうちの片方と第1ソース配線427Aとを架け渡している。つまり、架渡し部445は、第2ソース配線427Bに対しては2つの分割部427a1毎に1組(一対)ずつ配置されている。そして、1つの組をなす一対の架渡し部445は、一方の分割部427a1を、他方の分割部427a1側とは反対側に隣り合う第1ソース配線427Aに対してX軸方向に離間した2位置にて架け渡していることになる。一方の分割部427a1と第1ソース配線427Aとを架け渡す一対の架渡し部445と、他方の分割部427a1と上記とは反対側の第1ソース配線427Aとを架け渡す一対の架渡し部445とは、X軸方向についてほぼ同じ位置に配されている。 As shown in FIG. 21, a pair of the bridging portions 445 is arranged at a position sandwiching the spare wiring 48 in the extending direction between adjacent source wirings 427A and 427B, and does not have a slit 444. Two sets are arranged for each first source wiring 427A and each second source wiring 427B having slits 444. That is, four transfer portions 445 are provided for each of the first source wiring 427A and the second source wiring 427B. The pair of spanning portions 445 forming one set is arranged at a position closer to the spare wiring 48 than both ends of the slit 444 in the X-axis direction, that is, a position between the end of the slit 444 and the spare wiring 48. Has been. In other words, the slit 444 is formed over a range that exceeds the pair of bridge portions 445 that sandwich the spare wiring 48 in the second source wiring 427B. Accordingly, the bridge portion 445 bridges the slit forming portion 427a and the first source wire 427A of the second source wiring 427B, and more specifically, of the two divided portions 427a1 constituting the slit forming portion 427a. And the first source wiring 427A are bridged. That is, the bridging portion 445 is arranged for each of the two divided portions 427a1 with respect to the second source wiring 427B. The pair of crossing portions 445 that form one set are separated from each other in the X-axis direction with respect to the first source wiring 427A adjacent to the other divided portion 427a1 on the side opposite to the other divided portion 427a1 side. It will be bridged at the position. A pair of bridging portions 445 that bridges one dividing portion 427a1 and the first source wiring 427A, and a pair of bridging portions 445 that bridges the other dividing portion 427a1 and the first source wiring 427A opposite to the above. Are arranged at substantially the same position in the X-axis direction.
 このような構成のものにおいて、予備配線48とソース配線427との交差部分に短絡が生じた場合には、次のようにして修理を行う。例えば、予備配線48と第1ソース配線427Aとの交差部分において短絡が発生した場合には、第1ソース配線427Aのうち、X軸方向について、短絡した予備配線48と一対の架渡し部445との間の2位置にレーザ光を照射して切断することで、第1ソース配線427Aの本体部分から短絡箇所を切り離す。その一方で、架渡し部445のうち、短絡が生じた第1ソース配線427Aと平面視重畳する部分、及び第2ソース配線427Bと平面視重畳する部分に対してそれぞれレーザ光を照射し、その照射箇所におけるゲート絶縁膜435を溶融させることで、架渡し部445における上記各重畳部分を各ソース配線427A,427Bに対して短絡させる。さらには、第2ソース配線427Bにおいてスリット444を挟んで配される2つの分割部427a1のうち、架渡し部445によって第1ソース配線427Aと短絡される分割部427a1にレーザ光を照射することでこれを切断して切り離す。以上により、予備配線48に短絡された第1ソース配線427Aに供給される信号は、第1ソース配線427Aの本体部分から架渡し部445を経由して隣り合う第2ソース配線427Bの一部である分割部427a1に迂回され、再び架渡し部445を経由して第1ソース配線427Aの本体部分に流されることで、正常な伝送が図られる。また、第1ソース配線427Aに短絡した予備配線48は、他のソース配線427に断線が生じた場合の修理に利用することが可能とされる。 In such a configuration, when a short circuit occurs at the intersection between the spare wiring 48 and the source wiring 427, the repair is performed as follows. For example, when a short circuit occurs at the intersection between the spare wiring 48 and the first source wiring 427A, the shorted spare wiring 48 and the pair of bridge portions 445 in the X-axis direction of the first source wiring 427A The short-circuited portion is separated from the main body portion of the first source wiring 427A by irradiating the laser beam to the two positions between and cutting. On the other hand, the laser beam is irradiated to the portion of the bridge portion 445 that overlaps with the first source wiring 427A in which the short circuit occurs and the portion that overlaps with the second source wiring 427B in plan view. By melting the gate insulating film 435 at the irradiation location, the overlapping portions in the transfer portion 445 are short-circuited to the source wirings 427A and 427B. Further, among the two divided portions 427a1 arranged across the slit 444 in the second source wiring 427B, the divided portion 427a1 short-circuited with the first source wiring 427A by the transfer portion 445 is irradiated with laser light. Cut this off. As described above, a signal supplied to the first source wiring 427A short-circuited to the spare wiring 48 is a part of the second source wiring 427B adjacent from the main body portion of the first source wiring 427A via the bridge portion 445. By diverting to a certain division part 427a1 and flowing again to the main body portion of the first source wiring 427A via the transfer part 445, normal transmission is achieved. In addition, the spare wiring 48 short-circuited to the first source wiring 427A can be used for repair when the other source wiring 427 is disconnected.
 <実施形態6>
 実施形態6を図24によって説明する。この実施形態6では、ゲート配線526及び容量配線533とは別途に修理配線49を設けたものを示す。
<Embodiment 6>
A sixth embodiment will be described with reference to FIG. In the sixth embodiment, a repair wiring 49 is provided separately from the gate wiring 526 and the capacitor wiring 533.
 本実施形態では、図24に示すように、隣り合うゲート配線526と容量配線533との間に、各配線526,533を修理するための修理配線49を形成するようにしている。修理配線49は、ゲート配線526及び容量配線533に並行するとともに引廻配線543を跨ぐ所定範囲にわたって延在している。修理配線49は、各ゲート配線526を挟み込む位置に一対ずつ配されるのに加えて、各容量配線533を挟み込む位置に一対ずつ配されている。つまり、各ゲート配線526及び各容量配線533には、個別に一対ずつの修理配線49がY軸方向について隣り合って配されていることになる。修理配線49は、ゲート配線526及び容量配線533と同一材料からなり且つ製造工程における同一工程にて同一層に形成されている。なお、全てのゲート配線526及び容量配線533には、引廻配線543を跨ぐ形でスリット544が形成されている。 In this embodiment, as shown in FIG. 24, a repair wiring 49 for repairing each wiring 526, 533 is formed between the adjacent gate wiring 526 and the capacitor wiring 533. The repair wiring 49 extends in parallel to the gate wiring 526 and the capacitor wiring 533 and extends over a predetermined range across the lead wiring 543. A pair of repair wirings 49 are arranged at positions sandwiching the respective gate wirings 526, and a pair of repair wirings 49 are disposed at positions sandwiching the respective capacitive wirings 533. That is, a pair of repair wirings 49 are individually arranged adjacent to each other in the Y-axis direction in each gate wiring 526 and each capacitance wiring 533. The repair wiring 49 is made of the same material as the gate wiring 526 and the capacitor wiring 533 and is formed in the same layer in the same process in the manufacturing process. Note that slits 544 are formed in all gate wirings 526 and capacitor wirings 533 so as to straddle the routing wirings 543.
 そして、隣り合う修理配線49とゲート配線526及び容量配線533との間には、架渡し部545が架け渡されている。従って、ゲート配線526または容量配線533が引廻配線543と短絡した場合には、その短絡した部分を本体部分から切り離すとともに、その本体部分と隣り合う修理配線49とを架渡し部545に対して短絡させることで、修理配線49を迂回路として信号などの伝送を可能にすることができる。これにより、短絡したゲート配線526または容量配線533の本体部分と、修理配線49との双方を利用して信号などを伝送させることができるので、修理を要しないゲート配線526または容量配線533と配線抵抗が同等になる効果が得られる。 Further, a bridge portion 545 is bridged between the adjacent repair wiring 49, the gate wiring 526, and the capacitor wiring 533. Therefore, when the gate wiring 526 or the capacitor wiring 533 is short-circuited to the routing wiring 543, the short-circuited portion is separated from the main body portion, and the repair wiring 49 adjacent to the main body portion is connected to the transfer portion 545. By short-circuiting, it is possible to transmit a signal or the like using the repair wiring 49 as a bypass. Thereby, since the signal etc. can be transmitted using both the short-circuited gate wiring 526 or the main body portion of the capacity wiring 533 and the repair wiring 49, the gate wiring 526 or the capacity wiring 533 and the wiring which do not require repair are transmitted. The effect that resistance becomes equal is obtained.
 <実施形態7>
 実施形態7を図25によって説明する。この実施形態7は、上記した実施形態6の変形例とも言うべきものであって、遮光部50の一部を利用して修理配線649を設けたものを示す。
<Embodiment 7>
A seventh embodiment will be described with reference to FIG. The seventh embodiment should also be referred to as a modification of the above-described sixth embodiment, and shows a case where repair wiring 649 is provided using a part of the light shielding portion 50.
 本実施形態では、図25に示すように、ゲート配線626に隣り合う形で遮光部50が形成されている。この遮光部50は、導電性を有する金属材料からなるものとされ、所定範囲にわたってベタ状に形成されている。そして、遮光部50のうちゲート配線626に隣り合う部分には、スリット51が形成されることで、引廻配線643を跨ぐ形の修理配線649が形成されている。この修理配線649とゲート配線626との間には、一対の架渡し部645が架け渡されている。これにより、ゲート配線626が引廻配線643に短絡された場合でも、修理配線649及び架渡し部645を用いることで、その修理を行うことが可能とされる。 In this embodiment, as shown in FIG. 25, the light shielding portion 50 is formed adjacent to the gate wiring 626. The light shielding portion 50 is made of a conductive metal material, and is formed in a solid shape over a predetermined range. A slit 51 is formed in a portion of the light shielding portion 50 adjacent to the gate wiring 626, thereby forming a repair wiring 649 that straddles the lead wiring 643. Between the repair wiring 649 and the gate wiring 626, a pair of spanning portions 645 is spanned. As a result, even when the gate wiring 626 is short-circuited to the routing wiring 643, the repair can be performed by using the repair wiring 649 and the transfer portion 645.
 <実施形態8>
 実施形態8を図26によって説明する。この実施形態8では、架渡し部を用いない構成のものを示す。
<Eighth embodiment>
An eighth embodiment will be described with reference to FIG. In the eighth embodiment, a configuration that does not use a bridge is shown.
 本実施形態では、図26に示すように、ゲート配線726及び容量配線733の全てにスリット744が形成されているのに加えて、これらと交差する引廻配線743にもスリット52が形成されている。従って、ゲート配線726または容量配線733と引廻配線743との交差部分に短絡が生じた場合には、ゲート配線726または容量配線733と引廻配線743とについて、それぞれ短絡箇所を挟む2位置で分割部を切断することで、修理を行うことができる。 In the present embodiment, as shown in FIG. 26, the slits 744 are formed in all of the gate wiring 726 and the capacitor wiring 733, and the slits 52 are also formed in the routing wiring 743 that intersects these. Yes. Therefore, when a short circuit occurs at the intersection between the gate wiring 726 or the capacitor wiring 733 and the lead wiring 743, the gate wiring 726 or the capacitor wiring 733 and the lead wiring 743 are respectively located at two positions sandwiching the short circuit portion. Repair can be performed by cutting the divided portion.
 <実施形態9>
 実施形態9を図27によって説明する。この実施形態9は、上記した実施形態8の変形例とも言うべきものであって、各スリット844,852を複数本ずつ形成したものを示す。
<Ninth Embodiment>
A ninth embodiment will be described with reference to FIG. The ninth embodiment should be referred to as a modification of the above-described eighth embodiment, and shows a configuration in which a plurality of slits 844 and 852 are formed.
 本実施形態では、図27に示すように、ゲート配線826及び容量配線833に3本ずつスリット844を形成するとともに、引廻配線843にも3本のスリット852を形成している。 In this embodiment, as shown in FIG. 27, three slits 844 are formed in each of the gate wiring 826 and the capacitor wiring 833, and three slits 852 are also formed in the lead wiring 843.
 <他の実施形態>
 本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような実施形態も本発明の技術的範囲に含まれる。
 (1)上記した実施形態1,2では、ゲート配線がスリットを有さない「第1配線」であり、容量配線がスリットを有する「第2配線」である場合を示したが、逆にゲート配線にスリットを形成してこれを「第2配線」とし、容量配線にスリットを形成せずにこれを「第1配線」とする構成を採ることも勿論可能である。
<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.
(1) In the first and second embodiments, the case where the gate wiring is the “first wiring” having no slit and the capacitor wiring is the “second wiring” having the slit is shown. Of course, it is also possible to adopt a configuration in which a slit is formed in the wiring and this is used as a “second wiring”, and this is used as a “first wiring” without forming a slit in the capacitor wiring.
 (2)上記した実施形態1,2では、容量配線のみに引廻配線を跨ぐスリットを形成した場合を示したが、ゲート配線及び容量配線の全てに引廻配線を跨ぐスリットを形成するようにしても構わない。 (2) In the above-described first and second embodiments, the case where the slits straddling the lead wiring is formed only on the capacitor wiring is shown. However, the slit straddling the lead wiring is formed on all of the gate wiring and the capacitor wiring. It doesn't matter.
 (3)上記した実施形態3では、ゲート配線が第2のスリットを有する「第1配線」であり、容量配線がスリットを有する「第2配線」である場合を示したが、逆にゲート配線にスリットを形成してこれを「第2配線」とし、容量配線に第2のスリットを形成してこれを「第1配線」とする構成を採ることも勿論可能である。 (3) In the above-described third embodiment, the case where the gate wiring is the “first wiring” having the second slit and the capacitor wiring is the “second wiring” having the slit is shown. It is of course possible to adopt a configuration in which a slit is formed as a “second wiring” and a second slit is formed in the capacitor wiring as a “first wiring”.
 (4)上記した実施形態3では、容量配線のみに第1引廻配線を跨ぐスリットを形成した場合を示したが、ゲート配線及び容量配線の全てに第1引廻配線を跨ぐスリットを形成するようにしても構わない。同様に、ゲート配線及び容量配線の全てに第2引廻配線を跨ぐ第2のスリットを形成するようにしても構わない。 (4) In the above-described third embodiment, the case where the slit extending over the first routing wiring is formed only on the capacitor wiring is shown. However, the slit extending over the first routing wiring is formed on all of the gate wiring and the capacitance wiring. It doesn't matter if you do. Similarly, a second slit that straddles the second lead wiring may be formed in all of the gate wiring and the capacitor wiring.
 (5)上記した実施形態3では、2本の引廻配線とゲート配線及び容量配線との交差部分に係る構成について例示したが、3本以上の引廻配線とゲート配線及び容量配線との交差部分にも、実施形態3と同様に技術を適用することが可能である。具体的には、ゲート配線と容量配線とに交差する引廻配線の数だけ、各引廻配線を跨ぐ形のスリットを形成するとともに、各引廻配線を跨ぐ位置に一対ずつの架渡し部を形成するようにすればよい。 (5) In the above-described third embodiment, the configuration related to the intersection of the two routing wirings, the gate wiring, and the capacitance wiring is illustrated, but the intersection of three or more routing wirings, the gate wiring, and the capacitance wiring The technique can be applied to the portions as in the third embodiment. Specifically, as many as the number of routing lines crossing the gate wiring and the capacity wiring, slits are formed so as to straddle each routing line, and a pair of bridging portions are provided at positions straddling each routing line. What is necessary is just to form.
 (6)上記した実施形態5に、実施形態1の各変形例に記載した構成を適用することも可能である。 (6) The configuration described in each modification of the first embodiment can be applied to the fifth embodiment described above.
 (7)上記した実施形態1~5では、容量配線またはゲート配線がスリット形成部分とスリット非形成部分とで線幅が等しくなるものを示したが、スリット形成部分とスリット非形成部分とで線幅が変化する構成とすることも可能である。 (7) In the first to fifth embodiments described above, the capacitor wiring or the gate wiring has been shown to have the same line width in the slit forming portion and the slit non-forming portion. A configuration in which the width is changed is also possible.
 (8)上記した実施形態1~5では、スリットの形成範囲が一対の架渡し部を超える範囲にわたるものを示したが、スリットの形成範囲が一対の架渡し部の間の距離と等しくなる設定としたり、一対の架渡し部の間の距離よりも短くなる設定とすることも可能である。 (8) In the first to fifth embodiments described above, the slit forming range extends beyond the pair of spanning portions. However, the slit forming range is set to be equal to the distance between the pair of spanning portions. It is also possible to set it to be shorter than the distance between the pair of spanning parts.
 (9)上記した実施形態1~5では、液晶表示装置を構成するバックライト装置の光源として冷陰極管を用いた場合を示したが、熱陰極管やLEDなど他の光源を用いたものも本発明に含まれる。 (9) In the first to fifth embodiments described above, the cold cathode tube is used as the light source of the backlight device that constitutes the liquid crystal display device, but other light sources such as a hot cathode tube and an LED are also used. It is included in the present invention.
 (10)上記した実施形態1~5では、液晶表示装置が備えるバックライト装置として直下型のものを例示したが、エッジライト型のバックライト装置を用いるようにしたものも本発明に含まれる。 (10) In Embodiments 1 to 5 described above, the direct type is exemplified as the backlight device included in the liquid crystal display device, but the present invention includes one using an edge light type backlight device.
 (11)上記した実施形態1~5では、外部光源であるバックライト装置を備えた透過型の液晶表示装置を例示したが、本発明は、外光を利用して表示を行う反射型液晶表示装置にも適用可能であり、その場合はバックライト装置を省略することができる。 (11) In the first to fifth embodiments described above, a transmissive liquid crystal display device including a backlight device as an external light source has been exemplified. However, the present invention is a reflective liquid crystal display that performs display using external light. The present invention can also be applied to a device, in which case the backlight device can be omitted.
 (12)上記した実施形態1~5では、液晶表示装置のスイッチング素子としてTFTを用いたが、TFT以外のスイッチング素子(例えば薄膜ダイオード(TFD))を用いた液晶表示装置にも適用可能であり、カラー表示する液晶表示装置以外にも、白黒表示する液晶表示装置にも適用可能である。 (12) In Embodiments 1 to 5 described above, the TFT is used as the switching element of the liquid crystal display device. In addition to the liquid crystal display device for color display, the present invention can be applied to a liquid crystal display device for monochrome display.
 (13)上記した実施形態1~5では、表示パネルとして液晶パネルを用いた液晶表示装置を例示したが、他の種類の表示パネル(PDPや有機ELパネルなど)を用いた表示装置にも本発明は適用可能である。その場合、バックライト装置を省略することも可能である。 (13) In the first to fifth embodiments described above, the liquid crystal display device using the liquid crystal panel as the display panel is exemplified, but the present invention is also applied to a display device using another type of display panel (PDP, organic EL panel, etc.). The invention is applicable. In that case, the backlight device can be omitted.
 10...液晶表示装置(表示装置)、12...バックライト装置(照明装置)、20...アレイ基板(素子基板)、21...CF基板(対向基板)、22...液晶層、24...TFT(スイッチング素子)、24a...ゲート電極(電極)、26,126,226,326...ゲート配線(第1配線)、33,133,233,333...容量配線(第2配線)、33a...スリット形成部分、33b...スリット非形成部分、35,335,435...ゲート絶縁膜(絶縁層)、43,243...引廻配線(第3配線)、44,144,244,,444...スリット、45,145,245,345,445...架渡し部、46...第2のスリット、47...第2の架渡し部、48...予備配線(第3配線)、145A...第1の組をなす一対の架渡し部(一方の架渡し部)、145B...第2の組をなす一対の架渡し部(他方の架渡し部)、243A...第1引廻配線(第3配線)、243B...第2引廻配線(第4配線)、337...層間絶縁膜(絶縁層)、338...保護膜(絶縁層)、427A...第1ソース配線(第1配線)、427B...第2ソース配線(第2配線)、GS...ガラス基板(基板)、TV...テレビ受信装置 10 ... Liquid crystal display device (display device), 12 ... Backlight device (illumination device), 20 ... Array substrate (element substrate), 21 ... CF substrate (counter substrate), 22 ... Liquid crystal layer, 24 ... TFT (switching element), 24a ... Gate electrode (electrode), 26, 126, 226, 326 ... Gate wiring (first wiring), 33, 133, 233, 333,. .Capacitive wiring (second wiring), 33a ... slit forming portion, 33b ... slit non-forming portion, 35, 335, 435 ... gate insulating film (insulating layer), 43, 243 ... routing Wiring (third wiring), 44, 144, 244, 444 ... slit, 45, 145, 245, 345, 445 ... spanning part, 46 ... second slit, 47 ... first 2 spanning sections, 48 ... preliminary wiring (third wiring), 145A ... a pair of spanning sections (one bridging section) forming the first set, 45B ... a pair of spanning portions (the other spanning portion) forming the second set, 243A ... first routing wiring (third wiring), 243B ... second routing wiring (fourth) Wiring), 337 ... interlayer insulating film (insulating layer), 338 ... protective film (insulating layer), 427A ... first source wiring (first wiring), 427B ... second source wiring (first) 2 wiring), GS ... glass substrate (substrate), TV ... TV receiver

Claims (15)

  1.  第1配線と、
     前記第1配線に並行するとともに前記第1配線に隣り合って配される第2配線と、
     前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第3配線と、
     前記第2配線のうち少なくとも前記第3配線を跨ぐ部分に配されるスリットと、
     前記第3配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される架渡し部と、を備える素子基板。
    A first wiring;
    A second wiring arranged in parallel with the first wiring and adjacent to the first wiring;
    A third wiring that intersects the first wiring and the second wiring through an insulating layer;
    A slit disposed in a portion straddling at least the third wiring among the second wiring;
    A pair of at least a pair of positions sandwiching the third wiring, wherein the first wiring and the second wiring are arranged with respect to the first wiring and the second wiring through an insulating layer; An element substrate comprising: an insulating portion that is insulated and is bridged between the first wiring and the second wiring.
  2.  前記第1配線と前記第2配線とは、交互に並ぶ形で複数ずつ配されている請求項1記載の素子基板。 2. The element substrate according to claim 1, wherein a plurality of the first wirings and the second wirings are arranged alternately.
  3.  前記架渡し部は、前記第1配線と、前記第1配線を挟んで隣り合う一対の前記第2配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている請求項2記載の素子基板。 3. The element substrate according to claim 2, wherein at least a pair of the bridging portions are formed so as to bridge between the first wiring and a pair of the second wirings adjacent to each other with the first wiring interposed therebetween. .
  4.  前記第1配線と前記一対の第2配線のうちの一方の前記第2配線との間を架け渡す一方の前記架渡し部と、前記第1配線と前記一対の第2配線のうちの他方の前記第2配線との間を架け渡す他方の前記架渡し部とは、前記第1配線の延在方向について互いにずれた位置に配されている請求項3記載の素子基板。 One of the bridging portions that bridges between the first wiring and one of the pair of second wirings, and the other of the first wiring and the pair of second wirings 4. The element substrate according to claim 3, wherein the other bridging portion that bridges the second wiring is arranged at a position shifted from each other in the extending direction of the first wiring.
  5.  前記第2配線と前記第2配線を挟んで配される一対の前記第1配線のうちの一方の前記第1配線との間を架け渡す一方の前記架渡し部と、前記第2配線と前記一対の第1配線のうちの他方の前記第1配線との間を架け渡す他方の前記架渡し部とは、前記第2配線の延在方向について互いにずれた位置に配されている請求項3または請求項4記載の素子基板。 One of the bridging portions that bridges between the first wiring of one of the pair of the first wirings arranged across the second wiring and the second wiring, the second wiring, 4. The other bridging portion that bridges between the other first wiring of the pair of first wirings is disposed at a position shifted from each other in the extending direction of the second wiring. Alternatively, the element substrate according to claim 4.
  6.  前記第2配線は、前記スリットが形成されるスリット形成部分と、前記スリットが形成されないスリット非形成部分とからなり、前記スリット形成部分と前記スリット非形成部分とで線幅が等しいものとされる請求項1から請求項5のいずれか1項に記載の素子基板。 The second wiring includes a slit forming portion where the slit is formed and a slit non-forming portion where the slit is not formed, and the slit forming portion and the slit non-forming portion have the same line width. The element substrate according to any one of claims 1 to 5.
  7.  前記架渡し部と前記第3配線とが同じ層に配されており、前記架渡し部及び前記第3配線と、前記第1配線及び前記第2配線との間に介在する前記絶縁層が同一とされている請求項1から請求項6のいずれか1項に記載の素子基板。 The bridging portion and the third wiring are arranged in the same layer, and the insulating layer interposed between the bridging portion and the third wiring and the first wiring and the second wiring is the same The element substrate according to claim 1, wherein:
  8.  前記スリットは、前記第2配線において前記第3配線を挟む位置に配される少なくとも一対の前記架渡し部を超える範囲にわたって形成されている請求項1から請求項7のいずれか1項に記載の素子基板。 The said slit is formed over the range exceeding the at least one pair of said bridge | crossing part arrange | positioned in the position which pinches | interposes the said 3rd wiring in the said 2nd wiring. Element substrate.
  9.  前記第3配線に並行するとともに前記第3配線に隣り合って配され且つ前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第4配線と、
     前記第1配線のうち少なくとも前記第4配線を跨ぐ部分に配される第2のスリットと、
     前記第4配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される第2の架渡し部とを備える請求項1から請求項8のいずれか1項に記載の素子基板。
    A fourth wiring parallel to the third wiring and adjacent to the third wiring and intersecting the first wiring and the second wiring through an insulating layer;
    A second slit disposed in a portion straddling at least the fourth wiring among the first wiring;
    At least a pair is arranged at a position sandwiching the fourth wiring, and the first wiring and the second wiring are arranged with respect to the first wiring and the second wiring through an insulating layer. 9. The element substrate according to claim 1, further comprising a second bridge portion that is insulated and bridges between the first wiring and the second wiring. 10.
  10.  前記第1配線と前記第2配線とは、交互に並ぶ形で複数ずつ配されており、
     前記架渡し部は、前記第1配線と、前記第1配線を挟んで隣り合う一対の前記第2配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されているのに対して、
     前記第2の架渡し部は、前記第2配線と、前記第2配線を挟んで隣り合う一対の前記第1配線との間をそれぞれ架け渡す形で少なくとも一対ずつ形成されている請求項9記載の素子基板。
    A plurality of the first wirings and the second wirings are arranged alternately in a line,
    Whereas the bridging portion is formed at least one pair in a manner of bridging between the first wiring and a pair of adjacent second wirings across the first wiring,
    The at least one pair of said 2nd bridge | crossover part is formed in the form which bridge | crosses between said 2nd wiring and a pair of said 1st wiring adjacent on both sides of said 2nd wiring, respectively. Element substrate.
  11.  前記第1配線または前記第2配線に接続される電極を少なくとも有するスイッチング素子を備える請求項1から請求項10のいずれか1項に記載の素子基板。 The element substrate according to claim 1, further comprising a switching element having at least an electrode connected to the first wiring or the second wiring.
  12.  請求項1から請求項11のいずれか1項に記載の素子基板と、前記素子基板と対向状をなす対向基板と、前記素子基板と前記対向基板との間に封入される液晶層とを備える表示装置。 An element substrate according to any one of claims 1 to 11, a counter substrate facing the element substrate, and a liquid crystal layer sealed between the element substrate and the counter substrate. Display device.
  13.  前記素子基板及び前記対向基板に向けて光を照射する照明装置を備える請求項12記載の表示装置。 The display device according to claim 12, further comprising an illumination device that irradiates light toward the element substrate and the counter substrate.
  14.  請求項12または請求項13に記載された表示装置を備えるテレビ受信装置。 A television receiver comprising the display device according to claim 12 or 13.
  15.  基板上に、第1配線と、前記第1配線に並行するとともに前記第1配線に隣り合って配される第2配線と、前記第1配線及び前記第2配線に対して絶縁層を介しつつ交差する第3配線と、前記第2配線のうち少なくとも前記第3配線を跨ぐ部分に配されるスリットと、前記第3配線を挟む位置に少なくとも一対配されるものであって、前記第1配線及び前記第2配線に対して絶縁層を介して配されることで前記第1配線及び前記第2配線と絶縁されるとともに前記第1配線と前記第2配線との間に架け渡される架渡し部と、を形成する配線形成工程と、
     前記第1配線と前記第3配線との交差部分と、前記第2配線と前記第3配線との交差部分とに短絡が生じているか否かをそれぞれ検査する検査工程と、
     前記第1配線と前記第3配線との交差部分に短絡が生じていた場合には、前記第1配線のうち、前記第3配線を挟み且つ少なくとも一対の前記架渡し部の間に挟まれる部分を切断して前記第1配線から切り離す一方で、前記第1配線とそれに隣り合う前記第2配線との間に架け渡された少なくとも一対の前記架渡し部を、前記第1配線及び前記第2配線に対してそれぞれ短絡させ、さらには前記第2配線において前記スリットを挟んで配される複数の部分のうち前記第1配線に対して少なくとも一対の前記架渡し部により短絡される部分を切断して前記第2配線から切り離すようにし、また前記第2配線と前記第3配線との交差部分に短絡が生じていた場合には、前記第2配線において前記スリットを挟んで配される複数の部分のうち前記第3配線と短絡した部分を切断する、修理工程とを行う素子基板の製造方法。
    On the substrate, the first wiring, the second wiring parallel to the first wiring and adjacent to the first wiring, and the first wiring and the second wiring through an insulating layer At least a pair of third wirings intersecting each other, a slit disposed in at least a portion of the second wiring across the third wiring, and a position sandwiching the third wiring, the first wiring And the second wiring being arranged via an insulating layer so as to be insulated from the first wiring and the second wiring and to be bridged between the first wiring and the second wiring. A wiring forming process for forming a portion;
    An inspection process for inspecting whether or not a short circuit has occurred at the intersection between the first wiring and the third wiring and the intersection between the second wiring and the third wiring;
    When a short circuit occurs at the intersection between the first wiring and the third wiring, a portion of the first wiring that sandwiches the third wiring and is sandwiched between at least a pair of the bridging portions Is cut off from the first wiring, and at least a pair of the bridging portions spanned between the first wiring and the second wiring adjacent to the first wiring are separated from the first wiring and the second wiring. Short-circuiting each of the wirings, and further cutting a portion short-circuited by at least a pair of the bridging portions with respect to the first wiring out of a plurality of portions arranged across the slit in the second wiring. A plurality of portions arranged so as to sandwich the slit in the second wiring when a short circuit occurs at the intersection of the second wiring and the third wiring. Of the above Cutting the wiring and short-circuit portion, a manufacturing method of an element substrate for performing a repair step.
PCT/JP2012/065331 2011-06-22 2012-06-15 Device board, display apparatus, television receiver apparatus, and method for making device board WO2012176701A1 (en)

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JPH10123563A (en) * 1996-10-17 1998-05-15 Sharp Corp Liquid crystal display device and its fault correction method
JP2003156763A (en) * 2001-11-21 2003-05-30 Fujitsu Display Technologies Corp Liquid crystal display unit and its defect repair method
JP2004198718A (en) * 2002-12-18 2004-07-15 Fujitsu Ltd Display device and method for correcting defect thereof
JP2005043639A (en) * 2003-07-22 2005-02-17 Nec Kagoshima Ltd Switching element array substrate, active matrix type display device using the same, and its repairing method
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