JP2022076989A - Wiring board, display panel, and method for repairing defect in wiring board - Google Patents

Abstract

To provide a new connection wiring structure useful for increasing the density of connection wiring.SOLUTION: A wiring board 40 comprises: a substrate 41; a pixel electrode 24; source wiring 27; an output terminal 50 of a source driver 12 for inputting a signal to the source wiring 27; first wiring 43 that is provided on the substrate 41 and connected with the source wiring 27 and the output terminal 50; and second wiring 45 that is provided on the substrate 41 and disposed along the first wiring 43, has the first wiring 43 superimposed thereon with an insulating layer 44 therebetween, and is connected with the first wiring 43 at a first contact C1 and a second contact C2 arranged separated from each other. The first wiring 43 and the second wiring 45 include, between the first contact C1 and the second contact C2, a superimposed part X0 where both are superimposed with each other and a first non-superimposed part X1 and a second non-superimposed part X2 where both are not superimposed with each other.SELECTED DRAWING: Figure 5

Description

The techniques disclosed herein relate to wiring boards, display panels, and methods of repairing defects in wiring boards.

Display panels such as liquid crystal panels used in electronic devices such as smartphones, personal computers, and televisions are required to have both high definition and narrow frame, which are contradictory issues. In the frame area of the display panel, a large number of connection wirings for connecting the display element arranged on the display panel and the driver for driving the display element are arranged, and the number of connection wirings is high-definition of the display image. It increases with. Therefore, in order to realize high definition and narrow frame at the same time, it is necessary to arrange more connection wiring in a narrower frame area. For example, Patent Document 1 discloses a wiring pattern in which short circuits can be suppressed even if the connection wiring pitches are set to the minimum pitch by providing two adjacent connection wirings in two layers, an upper layer and a lower layer, via an insulating layer. ing.

Japanese Unexamined Patent Publication No. 2007-1506049

According to this wiring pattern, the upper layer connection wiring is arranged between two adjacent lower layer connection wirings in a plan view and is not superimposed. Therefore, there was room for improvement from the viewpoint of arranging the connection wiring at a higher density.

The technique disclosed herein has been made in view of the above circumstances, and an object thereof is to provide a new connection wiring structure useful for increasing the density of connection wiring.

(1) One embodiment of the technique disclosed herein is a substrate having an insulating property, a pixel electrode provided on the substrate, a pixel wiring provided on the substrate and connected to the pixel electrode, and the pixel. A signal input unit for inputting a signal to the wiring, a first wiring provided on the board and connected to the pixel wiring and the signal input unit, and an arrangement along the first wiring provided on the board. The first contact is superposed on the first wiring via an insulating layer, and the first contact and the second wiring connected to the first wiring at the second contact are provided. The wiring and the second wiring are a superimposing portion that is superposed on each other between the first contact and the second contact, and a first non-superimposing portion and a first non-superimposing portion that are not superimposing on each other at a position sandwiching the superimposing portion. 2 A wiring board including a non-superimposing portion.

(2) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of the above (1), the first non-superimposing portion is formed between the first contact point and the second contact point. The second non-superimposing portion is a wiring board provided so as to be connected to one contact and to be connected to the second contact between the first contact and the second contact. be.

(3) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of the above (2), the first wiring and the second wiring each have a widened portion wider than the other portions. At the same time, the first contact and the second contact are provided in the widened portion, respectively, and the first wiring and the second wiring are extended from the separated positions of the widened portion and then overlapped with each other. , A wiring board provided with the first non-superimposition portion and the second non-superimposition portion continuously to the widening portion.

(4) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of any one of (1) to (3) above, the first wiring is a first extending along a first direction. A first portion comprising a portion and a second portion and an oblique portion extending along a second direction that intersects the first direction at an angle of less than 90 degrees between the first portion and the second portion. One contact is provided in the first portion, and the second contact is a wiring board provided in the second portion.

(5) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of any one of (1) to (4) above, the second wiring is narrower than the first wiring. The first wiring is a wiring board including protruding portions protruding from both ends of the second wiring in the width direction orthogonal to the longitudinal direction.

(6) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of any one of (1) to (5) above, the second wiring is provided along the longitudinal direction of the second wiring. It is a wiring board that is superimposed on the first wiring over a range of 90% or more.

(7) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of any one of (1) to (6) above, a gate layer, a source layer, the gate layer, and the source layer are provided. The first wiring is composed of the same conductive film as the source layer, the second wiring is composed of the same conductive film as the gate layer, and the insulating layer includes a thin film transistor including a gate insulating layer for insulating. It is a wiring substrate made of the same insulating film as the gate insulating layer.

(8) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of any one of (1) to (7), the first wiring and the second wiring are the first non-superimposition. A wiring board provided with a third non-superimposition portion between the portion and the second non-superimposition portion and at a position separated from the first non-superimposition portion and the second non-superimposition portion. Is.

(9) Further, in an embodiment of the technique disclosed herein, in addition to the configuration of (8), the first wiring and the second wiring include the first non-superimposition portion and the second non-superimposition portion. The first intermediate point and the second intermediate point arranged apart from the first non-superimposing portion and the second non-superimposing portion, and the first intermediate point and the second intermediate point. Between, it has a meandering portion that meanders along a direction that intersects the direction connecting the first intermediate point and the second intermediate point, and is either the first wiring or the second wiring. One includes a first meandering portion that meanders in a substantially U-shape in the meandering portion, and the other of the first wiring and the second wiring is more than the first meandering portion in the meandering portion. The first meandering portion and the second meandering portion include a second meandering portion that meanders in a wide substantially U shape, and one portion of a pair of parallel portions extending substantially in parallel with each other thereof is included in the first meandering portion and the second meandering portion. It is a wiring board that constitutes the superimposing portion by superimposing and at least the other portion of the parallel portions does not superimpose on each other to form the third non-superimposing portion.

(10) Further, in an embodiment of the technique disclosed herein, in addition to any one of the above (1) to (9), a plurality of the pixel electrodes, a plurality of the pixel wirings, and a plurality of the pixel wirings. A wiring board comprising the first wiring and the second wiring, wherein the plurality of the first wiring and the second wiring are arranged in a direction in which at least a part thereof intersects in the longitudinal direction.

(11) Further, one embodiment of the technique disclosed herein includes a wiring board having any one of the configurations (1) to (10) above, and a counter board bonded to the wiring board. It is a display panel provided with.

(12) Further, in one embodiment of the technique disclosed herein, a plurality of the first wirings are short-circuited with respect to the wiring board having the configuration of the above (10), and the adjacent first wirings are short-circuited with each other. Which of the first wiring and the second wiring connected to the first wiring for at least one of the identified short-circuit wiring pairs and the step of specifying the short-circuit wiring pair. A method for repairing a defect in a wiring substrate, which comprises a step of cutting one of them at each of the first non-superimposition portion and the second non-superimposition portion.

(13) Further, in one embodiment of the technique disclosed herein, a plurality of short-circuit tests of the first wiring are performed on the wiring board having the configuration of the above (10) having the configuration of the above (8) or (9). The first wiring and the first wiring are performed with respect to the step of identifying the short-circuit wiring pair short-circuited between the adjacent first wirings and the first wiring of at least one of the identified short-circuit wiring pairs. Wiring including a step of cutting one of the second wirings connected to the wiring at each of the first non-superimposing portion or the second non-superimposing portion and the third non-superimposing portion. This is a method for repairing defects in the board.

According to the technique disclosed herein, it is possible to provide a new connection wiring structure useful for increasing the density of connection wiring.

Schematic plan view of the liquid crystal panel provided in the liquid crystal display device according to the embodiment. Schematic cross-sectional view of the liquid crystal panel Enlarged view of the main part of the array board of FIG. Schematic cross-sectional view of the TFT of FIG. Schematic rear view of the substrate comprising the first wiring and the second wiring in one embodiment. Cross-sectional view taken along the line AA of FIG. BB line sectional view of FIG. Cross-sectional view taken along the line CC of FIG. Schematic plan view of a liquid crystal panel provided in a liquid crystal display device according to another embodiment. Enlarged view of the main part of FIG.

<< Embodiment 1 >>
An embodiment of the technique disclosed herein will be described with reference to FIGS. 1 to 8. FIG. 1 is a plan view of a liquid crystal panel 11 provided in a liquid crystal display device 10 as an example of a display device. A part of each drawing shows an X-axis, a Y-axis, and a Z-axis that intersect each other (orthogonal in this embodiment). In each drawing, the X-axis is the Y-axis in the long side direction of the liquid crystal panel 11. Is in the short side direction, and the Z axis is in the thickness direction (that is, the normal direction of the plate surface of the liquid crystal panel 11). Further, the front side of the paper surface in FIG. 1 is the front side of the liquid crystal panel 11, and the back side of the paper surface is the back side. However, the above direction is only for convenience and should not be interpreted in a limited way.

The liquid crystal panel 11 is an example of a display panel in the present technology, has a rectangular planar shape, and is configured to be able to display an image. The liquid crystal display device 10 includes the liquid crystal panel 11 and a backlight device (lighting device) as an external light source for generating light to irradiate the liquid crystal panel 11 provided on the back side of the liquid crystal panel 11.

As shown in FIG. 2, the liquid crystal panel 11 generally includes a pair of substrates 20, 21 and a liquid crystal layer 22 interposed between the substrates 20, 21.
In the liquid crystal layer 22, a transparent liquid crystal material having fluidity and optical anisotropy (refractive index anisotropy) is enclosed between a pair of substrates 20 and 21, and the peripheral edge thereof is sealed by a sealing material 22A. It is composed of being done. In the liquid crystal layer 22, an electric field is applied to each pixel by the substrates 20 and 21 in the thickness direction, and the orientation of the liquid crystal molecules is changed based on the potential difference. As a result, the transmittance of light from the backlight device can be changed for each pixel (for each pixel portion PX), and a predetermined gradation display can be performed.

The pair of substrates 20, 21 are elements for holding the liquid crystal layer 22 and applying an electric field to the liquid crystal layer 22. Of the pair of boards 20 and 21, the one arranged on the front side (front side) is the CF board 20 (also referred to as the facing board), and the one arranged on the back side (back side) is the array board 21 (also referred to as the facing board). It is also called a wiring board, an active matrix board, etc.). Both the CF substrate 20 and the array substrate 21 include a glass substrate having insulation and heat resistance, and various layers described below are laminated on the inner surface side facing each other, and a polarizing plate is attached to the outer surface side, respectively. It is attached. As shown in FIG. 1, the CF substrate 20 has a short side dimension shorter than that of the array substrate 21. The CF substrate 20 and the array substrate 21 are arranged so that one end (upper here) in the short side direction is aligned, and the array substrate 21 is CF at the other end (lower here) in the short side direction. It protrudes to the other side (here, downward) with respect to the substrate 20. As a result, the array substrate 21 is divided into a facing portion 21A facing the CF board 20 and a non-facing portion 21B not facing the CF board 20. Further, the liquid crystal panel 11 has a display area A1 (a region surrounded by an alternate long and short dash line in FIG. 1) for displaying an image and a non-display area A2 (also referred to as a frame area) which is a portion other than the display area A1. include. A liquid crystal layer 22 is interposed in the display area A1 of the pair of substrates 20 and 21. The display area A1 in the present embodiment is arranged in the central portion of the facing portion 21A, and the non-display area A2 is an outer edge portion that surrounds the display area A1 in a frame shape. However, the shape of the non-display region A2 is not limited to this.

On the front side of the array board 21, gate wiring 26 (also referred to as scanning wiring or second wiring) is provided along the X-axis direction over the display area A1, and source wiring (also referred to as data wiring or the like) is provided along the Y-axis direction. 27 are arranged in a matrix (matrix). The area surrounded by the gate wiring 26 and the source wiring 27 is one pixel portion PX. The pixel unit PX includes a TFT 23 (thin film transistor) as a switching element and a pixel electrode 24. In FIG. 3, for reference, the equivalent circuit of the TFT 23 arranged in one pixel portion PX and the pixel electrode 24 are enlarged and displayed. As shown in FIG. 4, the TFT 23 of this example is a bottom gate type TFT in which the gate electrode 23A is arranged closer to the array substrate 21 than the channel layer 23D, and is provided on the upper layer side of the gate electrode 23A. The source electrode 23B and the drain electrode 23C are provided apart from each other via the gate insulating layer 33 and the channel layer 23D. The gate electrode 23A of the TFT 23 is connected to the gate wiring 26, the source electrode 23B is connected to the source wiring 27, and the drain electrode 23C is connected to the pixel electrode 24. The configuration of the TFT 23 is not limited to this.

The gate electrode 23A of the TFT 23 is formed in the same layer as the gate wiring 26. That is, the gate electrode 23A is made of a conductive film (gate metal film) made of the same material as the gate wiring 26. The source electrode 23B and the drain electrode 23C of the TFT 23 are formed in the same layer as the source wiring 27. That is, the source electrode and the drain electrode are made of a conductive film (source metal film) made of the same material as the source wiring 27. The channel layer 23D in the present embodiment is composed of an oxide semiconductor film made of an oxide semiconductor, and the TFT 23 is an oxide semiconductor TFT. The TFT 23 is driven based on various signals supplied to the gate wiring 26 and the source wiring 27, respectively, and controls the supply of electric potential to the pixel electrode 24 with the driving. The display area A1 in the present embodiment has, for example, a diagonal size of 32 inches, the number of gate wirings 26 installed is "3840", and the number of source wirings 27 installed is "2160". The TFT 23 is covered with a passivation film or the like as a protective film.

As shown in FIG. 1, in the non-display area A2 of the array board 21, a pair of gate circuit units 14 are integrally (monolithically) on the board 21 so that the display area A1 is sandwiched from both sides in the X-axis direction. It is provided. The gate circuit unit 14 includes a gate driver (scanning line drive circuit), and input terminals of the gate driver are connected to a control board via a flexible board 13 or the like described later, and a plurality of outputs of the gate driver. Each of the terminals is connected to each gate wiring 26. As a result, the gate driver transmits, for example, a gate clock signal or the like to each gate wiring 26 based on image data or the like transmitted from the control board.

A flexible substrate 13 is mounted (for example, COG (Chip On Glass) mounting) on the other end (lower side in this case) of the non-opposing portion 21B of the array substrate 21. The flexible substrate 13 of the present embodiment includes a large number of wiring patterns and a source driver 12 on a base material made of a synthetic resin material having insulating properties and flexibility (for example, a polyimide resin or the like). The source driver 12 is composed of an LSI chip including a signal line drive circuit of the TFT 23, and is COF (Chip On) with respect to the flexible substrate 13 so as to be arranged substantially in the center of the array substrate 21 in the long side direction (X-axis direction). Film) Implemented. The source driver 12 includes an input terminal and a plurality of output terminals, the input terminal is connected to a control board, and each of the plurality of output terminals is connected to each source wiring 27 via a lead-out wiring 15 (an example of connection wiring). It is connected to the. The output terminal of the source driver 12 and the lead-out wiring 15 can be suitably electrically connected via an anisotropic conductive film (ACF). Since the source driver 12 has a smaller dimension in the X-axis direction than the display area A1, the lead-out wiring 15 is provided for each of the plurality of source wirings 27 extending from the output terminal of the flexible board 13 to the lower end of the display area A1. It is routed in a fan-shaped manner. The lead-out wiring 15 will be described later. The source driver 12, for example, processes a digital signal such as image data transmitted from a control board, and transmits a gradation voltage signal or the like corresponding to each source wiring 27.

On the inner surface side of the CF substrate 20, a plurality of color filters 28 are arranged in a matrix over the display region A1 in the X-axis direction and the Y-axis direction. The color filter 28 is paired with one pixel electrode 24 on the array substrate 21 side and is arranged at a position where they are superimposed in a plan view. The color filter 28 of this example, blue (B), green (G), and red (R) exhibit three different colors, and these three different color filters 28 form a set of gate wiring 26 (X). They are repeatedly arranged side by side along the axial direction). In the liquid crystal panel 11 of this example, the color filters 28 having the same color are arranged along the source wiring 27 (Y-axis direction). A set of color filters 28 of R, G, and B arranged along the X-axis direction and three pixel electrodes 24 facing each color filter 28 constitute one pixel portion PX. Then, in the liquid crystal panel 11, a set of pixel portions PX of R, G, and B adjacent to each other along the X-axis direction constitutes display pixels capable of color display of a predetermined gradation. The arrangement pitch in the Y-axis direction in the pixel portion PX is, for example, 600 μm or less, typically about 450 to 550 μm (more specifically, for example, about 510 μm), and the arrangement pitch in the X-axis direction is For example, it is set to 300 μm or less, typically about 100 to 200 μm (more specifically, for example, about 170 μm).

On the inner surface side of the CF substrate 20, a black matrix 29 (light-shielding portion between pixels) for partitioning between the color filters 28 of each color is provided. The black matrix 29 is made of a material having a light-shielding property, and has a pixel opening 29A at a position where it overlaps with most of the pixel electrodes 24 by forming a substantially grid-like planar shape. The pixel opening 29A allows the transmitted light of the pixel electrode 24 to be emitted to the outside (front side) of the liquid crystal panel 11. The black matrix 29 is arranged so as to be vertically superimposed on at least the TFT 23, the gate wiring 26, and the source wiring 27 on the array substrate 21 side. Further, it is preferable to provide a spacer on the inner surface side of the counter electrode to maintain the thickness (cell gap) of the liquid crystal layer 22. Further, in both the substrates 20 and 21, an alignment film for orienting the liquid crystal molecules contained in the liquid crystal layer 22 is provided on the innermost surface in contact with the liquid crystal layer 22.

<Connection wiring>
In order to achieve both high definition and narrow frame of the liquid crystal panel 11, it is desired to increase the density of the lead-out wiring 15, that is, to make the lead-out wiring 15 finer and narrower in pitch. However, if the lead-out wiring 15 is made thinner, the resistance of the lead-out wiring 15 becomes higher and disconnection is likely to occur. Therefore, the lead-out wiring 15 according to the present technology includes a plurality of lead-out wirings 15, and a part or all of them has a two-layer structure by two wirings arranged at the same position in a plan view via an insulating layer. By contacting the upper layer wiring and the lower layer wiring at a plurality of places, it functions as one connection wiring. A wiring board 40 including a connection wiring 42 having such a two-layer structure will be described.

That is, as shown in FIGS. 5 to 8, the wiring board 40 includes a connection wiring 42 on the board 41. The connection wiring 42 includes a first wiring 43, an insulating layer 44, and a second wiring 45. FIG. 5 is a plan view of the connection wiring 42 formed on the transparent substrate 41 when viewed from the back side of the substrate 41. In order to facilitate understanding, the insulating layer 44 is not displayed and the first wiring is shown. Only 43 and the second wiring 45 are shown. 6 to 8 are cross-sectional views of the wiring board 40, in which a protective film 46 such as a passivation film (PAS film) or an interlayer insulating film is additionally provided on the substrate 41 and the connection wiring 42. There is. Here, the wiring board 40 corresponds to the array board 21 of the liquid crystal panel 11 described above, and the connection wiring 42 corresponds to the lead-out wiring 15. The connection wiring 42 is a conductor that connects the source wiring 27 (an example of the pixel wiring) connected to the pixel electrode 24 provided on the array board 21 and the output terminal 50 (an example of the signal input unit) of the source driver 12. It is a layer. Each of these layers has a laminated structure, and is typically formed on the substrate 41 sequentially from the layer closer to the substrate 41 by a lithography technique (for example, photolithography, radiation lithography, etc.).

The first wiring 43 of the connection wiring 42 is connected to the source wiring 27 and the output terminal 50 of the source driver 12 (see FIG. 3). A plurality of first wirings 43 are provided on the substrate 41, and the plurality of first wirings 43 are arranged apart from each other in the X-axis direction of the array substrate 21. On the other hand, the source driver 12 is a compact LSI chip. Therefore, as described above, the lead-out wiring is arranged in a fan shape as a whole, and extends substantially linearly along the Y-axis direction on the center side and diagonally on the end side. More specifically, among the plurality of first wirings 43, those arranged in the central portion of the array substrate 21 in the X-axis direction extend substantially linearly along the Y-axis direction. On the other hand, the first wiring 43 arranged in the portion other than the central portion in the X-axis direction extends substantially linearly along the Y-axis direction in the vicinity of the connection portion with the source wiring 27 or the output terminal 50, but is Y. The central portion in the axial direction extends in an oblique direction intersecting the Y axis. For example, as shown in FIG. 5, the first wiring 43 arranged in a portion other than the central portion in the X-axis direction includes straight portions P1 at both ends in the Y-axis direction, and an oblique portion P2 (between the straight portions P1). An example of a diagonal part) is included.

Here, as an example, the line width of the first wiring 43 (connection wiring 42) is, for example, about 15 μm or less (typically about 5 to 10 μm, for example, about 6 μm), and two adjacent wires in the diagonal portion P2. The pitch of the first wiring 43 (connection wiring 42) is, for example, 15 μm or less (typically, about 5 to 10 μm, for example, 8 μm).
The line width is a dimension in the width direction of the connection wiring 42 (first wiring 43, second wiring 45). The "width direction" is a direction orthogonal to the longitudinal direction of the connection wiring 42 (first wiring 43, second wiring 45), which coincides with the Y-axis direction in the straight portion P1 and the diagonal portion P2. The direction is orthogonal to the extending direction of each connection wiring 42 (first wiring 43, second wiring 45).

The second wiring 45 is provided so as to be superimposed on the first wiring 43 via the insulating layer 44. The second wiring 45 is not necessarily limited to this, but is provided via the insulating layer 44 on the side closer to the substrate 41 than the first wiring 43. In the wiring board 40 of the present embodiment, the second wiring 45 is provided directly on the substrate 41 (in other words, without interposing another layer), on which the insulating layer 44 and the first wiring 43 are placed. They are stacked in this order. However, another layer may be provided between the substrate 41 and the connection wiring 42 (first wiring 43, insulating layer 44, and second wiring 45). Further, the arrangement of the first wiring 43 and the second wiring 45 with respect to the substrate 41 may be reversed. The insulating layer 44 can be continuously formed in a solid shape so as to extend over the wiring region of the plurality of connecting wirings 42 to be arranged.

The second wiring 45 is arranged along the first wiring 43 in most of the portions thereof, and is provided apart from the arrangement path of the first wiring 43. In the first contact C1 and the second contact C2, the second wiring 45 is provided. It is connected to the first wiring 43. Specifically, the first wiring 43 and the second wiring 45 include widening portions P3 in which the line width is widened at both ends of the second wiring 45 in the longitudinal direction, as shown in FIG. The widened portion P3 in the present embodiment is formed in the straight portion P1 of the connecting wiring 42, and is not formed in the diagonal portion P2 in which the pitch between the adjacent connecting wirings 42 tends to be small. Further, the pitch between the adjacent source wirings 27 is wider than the pitch between the adjacent output terminals 50 of the source driver 12. Therefore, the widening portion P3 formed in the straight line portion P1 on the side of the source wiring 27 has a relatively large widening dimension, and the widening portion P3 formed in the straight line portion P1 on the output terminal 50 side has a relatively small widening dimension. I am doing it. As shown in FIG. 6, the insulating layer 44 arranged between the first wiring 43 and the second wiring 45 in the widened portion P3 is provided with a contact hole H1 penetrating in the thickness direction. By inserting the first wiring 43 formed in a later process from the second wiring 45 and the insulating layer 44 into the contact hole H1, the first wiring 43 and the second wiring 45 are connected through the contact hole H1. In this way, the first contact C1 is provided on the widened portion P3 on the source wiring 27 side, and the second contact C2 is provided on the widened portion P3 on the output terminal 50 side of the source driver 12. Although not limited to this, the width of the contact hole H1 may be the same as the line width of the second wiring 45 in the portion other than the widened portion P3.

Here, the first wiring 43 and the second wiring 45 in the connection wiring 42 are located between the first contact C1 and the second contact C2 so as to sandwich the superposed portion X0 and the superposed portion X0. A first non-superimposed portion X1 and a second non-superimposed portion X2 that do not superimpose on each other are provided. It should be noted that superimposition and non-superimposition are distinguished by whether the second wiring 45 is superposed on the first wiring 43 or non-superimposing in the longitudinal direction of the connection wiring 42. Therefore, as shown in FIG. 5 and the like, the protruding portion of the first wiring 43 formed by the first wiring 43 protruding from both ends in the width direction with respect to the second wiring 45 is relative to the second wiring 45. Although it is non-superimposed, it does not correspond to any of the first non-superimposed portion X1 and the second non-superimposed portion X2 referred to here. Further, even if the first wiring 43 is arranged in a single layer (single layer structure), there is a portion in which the second wiring 45 becomes a single layer corresponding to the single layer portion of the first wiring 43. If not, such a first wiring 43 does not correspond to any of the first non-superimposing portion X1 and the second non-superimposing portion X2 referred to here.

In the present embodiment, the oblique portion P2 constitutes an overlapping portion X0 on which the first wiring 43 and the second wiring 45 overlap over the entire length in the longitudinal direction thereof. A first non-superimposing portion X1 and a second non-superimposing portion X2 are provided on the side of the diagonal portion P2 of the straight line portion P1 with respect to the first contact C1 and the side of the oblique portion P2 with respect to the second contact C2, respectively. ing. In the first non-superimposing portion X1 and the second non-superimposing portion X2, the first single-layer portion S1 and the second wiring, respectively, in which the first wiring 43 does not overlap with the second wiring 45 and exists as a single-layer conductor film. The 45 is provided as a pair with the second single layer portion S2 which exists as a single layer conductor film without overlapping with the first wiring 43. The portions extending along the Y-axis direction of the first single-layer portion S1 and the second single-layer portion S2 are separated from each other in the X-axis direction.

Further, the first non-superimposing portion X1 in the present embodiment is provided so as to be connected to the first contact C1 between the first contact C1 and the second contact C2. More specifically, the first contact C1 is provided in the widened portion P3 on the side of the source wiring 27. The first single layer portion S1 and the second single layer portion S2 in the first non-superimposing portion X1 are obliquely separated from each other in the X-axis direction at the end portion of the widening portion P3 on the side toward the diagonal portion P2. It is extended toward the partial P2. Here, the dimension of the widened portion P3 in the X-axis direction is sufficiently larger than the line width of the first wiring 43 and the second wiring 45 (for example, 2.5 times or more, typically about 3 to 5 times). Further, the widened portion P3 on the side of the source wiring 27 has a larger dimension in the X-axis direction than the dimension in the Y-axis direction. Therefore, in the first non-superimposing portion X1, the first single layer portion S1 and the second single layer portion S2 can be lengthened in the Y-axis direction. Therefore, in the first non-superimposing portion X1, both the first single layer portion S1 and the second single layer portion S2 extend linearly along the Y-axis direction up to the diagonal portion P2 or an extension line thereof. ..

The second non-superimposing portion X2 in the present embodiment is provided between the first contact C1 and the second contact C2 so as to be connected to the second contact C2. More specifically, the second contact C2 is provided in the widening portion P3 on the side of the output terminal 50. The first single layer portion S1 and the second single layer portion S2 are extended toward the diagonal portion P2 from a position separated in the X-axis direction at the end portion of the widening portion P3 on the diagonal portion P2 side. There is. Here, the dimension of the widened portion P3 in the X-axis direction is sufficiently larger than the line width of the first wiring 43 and the second wiring 45 (for example, 2.5 times or more, typically about 2.5 to 4 times). ). Further, the widened portion P3 on the side of the output terminal 50 has a larger dimension in the Y-axis direction than the dimension in the X-axis direction. Therefore, it is desirable that the second non-superimposing portion X2 is compactly formed in the Y-axis direction. Therefore, in the second non-superimposing portion X2, one of the second single layer portions S2 extends linearly along the Y-axis direction up to the oblique portion P2. The other first single layer portion S1 extends linearly along the Y-axis direction by the same length as the second single layer portion S2, and then is refracted toward the second single layer portion S2. The first wiring 43 overlaps with the second wiring 45. By doing so, the dimension of the straight line portion P1 on the side of the output terminal 50 in the Y-axis direction can be kept short.

Regarding the above connection wiring 42, in the second wiring 45, at least 90% or more of the portion along the longitudinal direction of the second wiring 45 is the first wiring 43 from the viewpoint of resistance reduction effect, redundancy assurance, yield improvement, and the like. It is good to overlap. As a result, the resistance of the connection wiring 42 can be effectively reduced, and the continuity can be ensured by the second wiring 45 when the first wiring 43 is disconnected. The second wiring 45 has a sufficiently long dimension (length) along the longitudinal direction as compared with the line width. Therefore, in the second wiring 45, a portion of 95% or more along the longitudinal direction, further 98% or more may be overlapped with the first wiring 43, and the total length (100%) along the longitudinal direction is preferably the first. It is preferable that the wiring 43 is superimposed. Further, although not limited to this, in the second wiring 45 of the present embodiment, as shown in FIGS. 5 to 7, the dimension (line width) W2 in the width direction is the width direction of the first wiring 43. It is preferable that the dimension (line width) is equal to or smaller than the first wiring 43. In the wiring board 40 of the present embodiment, in a plan view, the first wiring 43 extends from the second wiring 45 on both sides in the width direction, for example, by dimension t, and the second wiring 45 is the first with respect to the entire circumference thereof. The shape is one size smaller than the wiring 43 (for example, by the dimension t).

The first wiring 43 and the second wiring 45 described above are conductive films having electrical conductivity. From the viewpoint that the first wiring 43 and the second wiring 45 can have high electrical conductivity, for example, copper (Cu), titanium (Ti), aluminum (Al), Cr (chromium), molybdenum (Mo), and the like. Any one metal selected from highly conductive metals such as Ta (tantal) and tungsten (W), alloys of the metals (may include intermetal compounds; the same shall apply hereinafter), and two kinds. It may be composed of an alloy or the like containing the above. The first wiring 43 and the second wiring 45 may be a single-layer film made of a metal material having one kind of composition or a laminated film made of a metal material having two or more kinds of compositions.

When the wiring board 40 includes the TFT 23 in addition to the connection wiring 42, the connection wiring 42 may be connected to the TFT 23. In such a case, of the first wiring 43 and the second wiring 45, the wiring arranged on the side closer to the substrate 41 (second wiring 45 in this example) is the gate electrode 23A of the TFT 23, the source electrode 23B, and the drain. It is preferable to manufacture the electrode 23C in the same process as the electrode (gate electrode 23A in this example) arranged closer to the substrate 41. Further, of the first wiring 43 and the second wiring 45, the wiring arranged on the far side of the substrate 41 (the first wiring 43 in this example) includes the gate electrode 23A of the TFT 23, the source electrode 23B, and the drain electrode 23C. Of these, it is preferable to manufacture the electrodes (source electrode 23B and drain electrode 23C in this example) arranged closer to the substrate 41 in the same process. Although not limited to this, the thickness of the first wiring may be approximately 6 μm or more and 10 μm or less (for example, about 8 μm), and the thickness of the second wiring may be approximately 6 μm or more and 10 μm or less (for example, about 8 μm). good.

In the case of this example, for example, the second wiring 45 may be a conductive film having the same composition as the gate wiring 26 and the gate electrode 23A by forming the second wiring 45 in the same process as the gate wiring 26 and the gate electrode 23A of the TFT 23. Further, the first wiring 43 may be a conductive film having the same composition as the source wiring 27, the source electrode 23B and the drain electrode 23C by forming the first wiring 43 in the same process as the source wiring 27, the source electrode 23B and the drain electrode 23C. Of the first wiring 43 and the second wiring 45, the wiring arranged on the side closer to the substrate 41 (second wiring 45 in this example) has a relatively high melting point such as Ta (tantalum) or W (tungsten). It is recommended to use the metal of. Further, of the first wiring 43 and the second wiring 45, the wiring arranged on the side farther from the substrate 41 (first wiring 43 in this example) is Al (aluminum) or Cr (aluminum) or Cr (from the viewpoint of avoiding signal deterioration). It may be composed of a metal having a relatively low resistance such as chromium). As described above, the wiring arranged on the side far from the substrate 41 (first wiring 43 in this example) is wider than the wiring arranged on the near side (second wiring 45 in this example). The resistance of the connection wiring 42 can be efficiently reduced.

The insulating layer 44 is an insulating film having poor electrical conductivity (typically, insulating). The protective film 46 is also generally composed of an insulating film having poor electrical conductivity (typically, insulating). The insulating layer 44 and the protective film 46 can be made of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) or an insulating organic material such as an acrylic resin (for example, PMMA). Considering that the insulating layer 44 is arranged between the first wiring 43 and the second wiring 45, the insulating layer 44 may be manufactured in the same process as the gate insulating layer 33. In other words, the insulating layer 44 may be an insulating film having the same composition as the gate insulating layer 33, and may be made of an insulating inorganic material (for example, silicon nitride). On the other hand, the protective film 46 may be either an insulating inorganic material or an insulating organic material (for example, acrylic resin), and for example, a layer made of an insulating organic material is laminated on a layer made of an insulating inorganic material. May be. Although not limited to this, the thickness of the insulating layer may be approximately 425 nm or more and 575 nm or less (for example, about 500 nm), and the thickness of the protective film may be approximately 170 nm or more and 230 nm or less (for example, about 200 nm). good.

The channel layer 23D of the TFT 23 is a semiconductor film made of a semiconductor material. The semiconductors constituting the channel layer 23D include elemental semiconductors mainly composed of Group V elements such as silicon, compound semiconductors in which Group III and Group V or Group II and Group VI elements are combined, and In-Ga-Zn-O. Examples thereof include oxide semiconductors such as (indium gallium zinc oxide). Above all, the channel layer 23D may be composed of an In—Ga—Zn—O semiconductor from the viewpoint of having high field effect mobility and the like. Here, the In—Ga—Zn—O-based semiconductor is a ternary composite oxide containing In (indium), Ga (gallium), and Zn (zinc), and may be amorphous. It may be crystalline. The thickness of the channel layer 23D is appropriately determined by a desired TFT design, and is not limited to this, and as an example, it is exemplified that the thickness is approximately 127.5 nm or more and 172.5 nm or less (for example, about 150 nm). To.

Here, in the connection wiring 42 described above, the overlapped portion X0 may be provided between the first contact C1 and the second contact C2 without providing the first non-superimposed portion X1 and the second non-superimposed portion X2. Conceivable. Even for the connection wiring without such non-superimposed portions X1 and X2, if the fine line is used, the increase in resistance is suppressed as compared with the case where one wiring of the upper layer or the lower layer is used, and the wiring of one layer is broken. Even in this case, there is an advantage that the disconnection can be avoided by the other wiring. However, if one connection wiring is composed of two wirings, an upper layer and a lower layer, a new problem that the occurrence rate of short-circuit defects with adjacent connection wirings may be doubled may occur. In addition, according to the study by the present inventors, although the reason is not clear, the lock-in type infrared thermography, which is widely used in the product inspection of the display panel when the two wirings of the upper layer and the lower layer are superimposed, is used. It has become clear that a new problem may arise in which it becomes difficult to identify the defective part.

Lock-in infrared thermography is a method for identifying defective parts due to short circuits, leaks, etc. of miniaturized and laminated electronic components and units. According to this analysis method, a thermal image is recorded while applying a thermal load synchronized with the pulse signal to the wiring, and minute heat generation points (coordinates) caused by defects such as short circuits or leaks are detected non-destructively. be. Defects such as short circuits or leaks on the array board can be corrected by repair technology using a laser repair device before bonding to the CF board, achieving a reduction in the defective product rate and an improvement in yield. Can be done. However, the wiring board having a two-layer structure does not generate heat when a voltage is applied, even if the connection wiring is determined to be defective by lighting inspection or electrical characteristic evaluation. Therefore, for such connection wiring, even if it is determined by lighting inspection or electrical characteristic evaluation that the connection wiring has a defect such as a short circuit or a leak, the coordinates of the defect location cannot be specified by lock-in infrared thermography. .. Therefore, it is necessary to repair the defect after identifying the defective portion by observing the connection wiring along the connection wiring with a microscope or the like. When such an inspection is performed on a connection wiring having a long length in the longitudinal direction, it is very difficult to lose sight of the connection wiring 42 to be inspected on the way because the observation field of view needs to be changed many times. It was.

<How to repair defects in wiring boards>
On the other hand, according to the wiring board 40 having the configuration disclosed herein, regarding the manufactured wiring board 40 (specifically, for example, the array board 21), first, (1) a plurality of first wiring 43 (that is, that is). A leak inspection (short circuit test) of the connection wiring 42) is performed, and if a leak is found in any of the plurality of connection wirings 42, a set of connection wirings 42 (short-circuit wirings) in which the adjacent connection wirings 42 are short-circuited are short-circuited. Perform the step of identifying the pair). Then, for (2) at least one connection wiring 42 of the specified short-circuit wiring pair, either the first wiring 43 or the second wiring 45 connected to the first wiring 43 is connected. The step of cutting is executed in each of the first non-superimposition portion X1 and the second non-superimposition portion X2.

More specifically, for example, when there is a leak in the portion of one of the first wirings 43 in the adjacent connection wiring 42, as shown in FIG. 8, the first non-superimposing portion X1 and the second non-superimposing portion X2 The first single layer portion S1 in the above is cut, for example, at the position indicated by the alternate long and short dash line. A laser cutter may be used to cut the single layer portions S1 and S2. As a result, it is possible to insulate the wiring on the defective side (that is, the first wiring 43) and ensure continuity with the remaining wiring (that is, the second wiring 45), and defects such as short circuits or leaks in the connection wiring 42 can be ensured. Can be easily modified. Further, for example, when there is a leak in the portion of the second wiring 45 in the adjacent connection wiring 42, the second single layer portion S2 in the first non-superimposing portion X1 and the second non-superimposing portion X2 may be cut, respectively. .. As a result, the wiring on the defective side (that is, the second wiring 45) can be insulated, and the remaining wiring (that is, the first wiring 43) can ensure continuity, and defects such as short circuits or leaks in the connection wiring 42 can be ensured. Can be easily modified. As a result, the correction rate of the wiring board 40 and the liquid crystal panel 11 can be improved to improve the yield. It should be noted that which of the first wiring 43 and the second wiring 45 has a leak can be determined, for example, by electrical characteristic evaluation. If it is not possible to determine whether there is a leak in the first wiring 43 or the second wiring 45 by the electrical characteristic evaluation, the single layer portion S1 or S2 is cut for one of the wirings that are likely to have a leak, and the leak occurs. If it is not repaired, the cut portion may be repaired (connection processing) and the single layer portion S2 or S1 may be cut for the other wiring.

<Composition and action>
The wiring substrate 40 according to the above embodiment includes a substrate 41 (array substrate 21) having an insulating property, a pixel electrode 24 provided on the substrate 41, and a source wiring 27 (provided on the substrate 41 and connected to the pixel electrode 24). The pixel wiring), the output terminal 50 (signal input unit) for inputting a signal to the source wiring 27, the first wiring 43 provided on the board 41 and connected to the source wiring 27 and the output terminal 50, and the board 41. The first wiring 43 is provided in the first contact C1 and the second contact C2, which are arranged along the first wiring 43, overlapped with the first wiring 43 via the insulating layer 44, and are arranged apart from each other. The second wiring 45 connected to the above is provided.

In such a configuration, the first wiring 43 is bypassed by the second wiring 45, and a connection wiring 42 having a two-layer structure including the first wiring 43 and the second wiring 45 is constructed. According to such a connection wiring 42, the line resistance thereof is reduced as in the wiring having a line width obtained by adding the first wiring 43 and the second wiring 45. As a result, it is possible to suppress an increase in line resistance even when the first wiring 43 and the second wiring 45 are made into fine lines (for example, the line width is about 15 μm or less). Further, the first wiring 43 and the second wiring 45 are insulated by the insulating layer 44, and are formed in another process. Therefore, even if either one of the first wiring 43 and the second wiring 45 is disconnected at the time of making a fine line, the function as the connection wiring 42 can be fulfilled if the other is continuous. As a result, it is possible to reduce the defect rate when the fine line is formed. Further, since the second wiring 45 is arranged at a position overlapping with the first wiring 43, the ratio of the first wiring 43 and the second wiring 45 to the substrate is reduced. As a result, the density of the connection wiring 42 can be increased without excessively increasing the line resistance.

Further, according to the above configuration, the first non-superimposing portion X1 and the second non-superimposing portion X2 can be realized by a simple pattern by using the widening portion P3 of the first contact C1 and the second contact C2. .. Further, this makes it possible to provide a connection wiring structure suitable for defect correction while suppressing the possibility of disconnection due to a complicated wiring pattern. Further, since the first single layer portion S1 or the second single layer portion S2 to be cut are separated from each other, it is possible to suppress the situation where the other is cut at the time of cutting. Even with such a configuration, it is possible to easily correct defects such as short circuits or leaks.

Further, according to the above configuration, the first wiring 43 is between the straight lines P1 and P1 (first and second parts) extending along the X axis (first direction) and these straight lines P1 and P1. Includes an oblique portion P2 (oblique portion) extending along a second direction intersecting the X-axis at an angle of less than 90 degrees, the first contact C1 being provided on one straight portion P1 and a second. The contact C2 is provided on the other straight portion P1. The superimposing portion X0 is provided on the diagonal portion P2. Since it is necessary to make the line width narrower and the pitch of the adjacent connection wiring 42 smaller in the diagonal portion P2 than in the straight portion P1, the superimposing portion X0 having the above characteristics is set in the diagonal portion P2. The arrangement is suitable because the advantages of the techniques disclosed herein can be more clearly demonstrated.

In the above embodiment, the first wiring 43 has a linear portion P1 (first portion) on the side of the source wiring 27 extending along the Y-axis direction (first direction) and a linear portion on the side of the output terminal 50 of the source driver. It includes P1 (second portion) and includes an oblique portion P2 (oblique portion) extending along a second direction that intersects the Y-axis direction at an angle of less than 90 degrees between these linear portions P1. The first contact C1 is provided in the straight line portion P1 on the side of the source wiring 27, and the second contact C2 is provided in the straight line portion P1 on the side of the output terminal 50. In the connection wiring 42 that aggregates a plurality of source wirings 27 into the output terminal 50 of the wiring of the source driver 12, the pitch between the adjacent connection wirings 42 is oblique to, for example, the pitch in the straight line portion P1 on the side of the output terminal 50. The pitch in the portion P2 is inevitably narrower. Therefore, by adopting such a configuration, the first contact C1 and the second contact C2 can be arranged in the straight line portion P1 having a large pitch, and the contact area can be easily secured to be wide. Further, a bypass by the second wiring 45 can be provided to the first wiring 43 over the entire length of the diagonal portion P2. As a result, even when the line width of the connection wiring 42 of the diagonal portion P2 is made narrower than before (or than the straight portion P1), it is possible to suppress an increase in resistance due to the fine line of the connection wiring 42. The advantages of the individually disclosed techniques can be more effectively demonstrated.

In the above embodiment, the second wiring 45 is narrower than the first wiring 43, and the first wiring 43 includes protruding portions protruding from both ends of the second wiring 45 in the width direction orthogonal to the longitudinal direction. According to such a configuration, the first wiring 43 arranged over the entire length of the connection wiring 42 can be formed wider, and the first wiring 43 can be made to have a lower resistance. Further, for example, when the wiring board 40 is manufactured by the photolithography technique, when the first wiring 43 is made to enter the contact hole H1 of the insulating layer 44 as a layer separated from the substrate, the portion having entered the contact hole H1 and the insulating layer 44 It is preferable in that it is easy to secure continuity with the portion arranged on the surface and the line thinning of the first wiring 43 can be suppressed. Further, when the first wiring 43 is made of a material having a lower resistance than that of the second wiring 45, it is preferable in that the resistance of the first wiring 43 can be further reduced.

In the above embodiment, the second wiring 45 is superimposed on the first wiring 43 over a range of 90% or more along the longitudinal direction of the second wiring 45. According to such a configuration, the resistance reducing effect and the disconnection preventing effect of the second wiring 45 are preferably exhibited, which is preferable.

In the above embodiment, the first wiring 43 includes a TFT 23 including a gate electrode 23A (gate layer), a source electrode 23B (source layer), and a gate insulating layer 33 that insulates the gate electrode 23A and the source electrode 23B. The second wiring 45 is made of the same conductive film as the gate electrode 23A, and the insulating layer 44 is made of the same insulating film as the gate insulating layer 33. According to such a configuration, the first wiring 43, the second wiring 45, and the insulating layer 44 can be formed on the substrate 41 in accordance with the manufacture of the TFT 23, which is suitable.

<< Embodiment 2 >>
The wiring board 240 according to the second embodiment will be described with reference to FIGS. 9 and 10. The wiring board 240 of the second embodiment is different from the first embodiment in that a third non-superimposed portion X3 is provided between the first non-superimposed portion X1 and the second non-superimposed portion X2. Other configurations may be the same as those in the first embodiment, and the description of the same configurations, actions and effects will be omitted.

For example, with respect to the wiring board 40 shown in FIG. 1, the wiring length may be significantly different between the connection wiring 42 arranged in the central portion in the X-axis direction and the connection wiring 42 arranged on both ends. As an example, the connection wiring 42 arranged at the center position in the X-axis direction has a linear distance of about 11 mm to the output terminal 50 to be connected, whereas the end in the display area A1 in the X-axis direction. The connection wiring 42 arranged at the position has a linear distance of about 328 mm to the output terminal 50 to be connected. Therefore, with respect to the plurality of wiring boards 40, the sheet resistance may vary depending on the wiring length, and the seat resistance of the connection wiring 42 arranged at the end position is higher than that of the connection wiring 42 arranged at the center position. Can be high. Further, the connection wiring 42 arranged at the center position has a small degree of aggregation in the X-axis direction up to the output terminal 50, and is adjacent to the connection wiring 42 as compared with the connection wiring 42 arranged at the end position. It is possible to secure a relatively wide pitch between. Therefore, as shown in FIG. 9, in order to reduce the variation in resistance between the plurality of connection wirings 242, it is possible to increase the resistance value by meandering the wiring pattern of the connection wiring 242 arranged in the central portion. I'm also sick.

Therefore, in the wiring board 240 of the present embodiment, the first wiring 243 and the second wiring 245 are located between the first non-superimposing portion X1 and the second non-superimposing portion X2, as shown in FIG. A third non-superimposed portion X3 that does not superimpose on each other is provided at a position separated from the first non-superimposed portion X1 and the second non-superimposed portion X2. More specifically, the connection wiring 242 (that is, the first wiring 243 and the second wiring 245) has the first non-superimposition portion X1 between the first non-superimposition portion X1 and the second non-superimposition portion X2. The first intermediate point M1 and the second intermediate point M1 and the second intermediate point M1 and the second intermediate point M2 are arranged between the first intermediate point M1 and the second intermediate point M2 arranged apart from each other and the second intermediate point M1 and the second intermediate point M2. It has a meandering portion M3 that meanders along a direction intersecting with a direction connecting the two intermediate points M2. Then, one of the first wiring 243 and the second wiring 245 (here, the first wiring 243) includes a first meandering portion M31 meandering in a substantially U-shape in the meandering portion M3. Further, the other of the first wiring 243 and the second wiring 245 (here, the second wiring 245) meanders in a U shape wider than the first meandering portion M31 in the meandering portion M3. The part M32 is included. The first meandering portion M31 and the second meandering portion M32 each form a superposed portion X01 in which one portion of a pair of parallel portions extending substantially parallel to each other overlaps with each other and forms a parallel portion. The third non-superimposed portion X3 is formed by not superimposing at least the other portion thereof on each other. In the third non-superimposing portion X3, the first wiring 243 does not overlap with the second wiring 245 and exists as a single-layer conductor film, and the second wiring 245 has the first wiring 243. A second single-layer portion S2 that exists as a single-layer conductor film without being superimposed is provided.

<How to repair defects in wiring boards>
According to the wiring board 40 of the first embodiment, if either the first wiring 43 or the second wiring 45 has a defect such as a leak, the first wiring 43 or the second wiring 43 or the second wiring having a defect from the connection wiring 42 has a defect. The wiring 45 can be modified by disconnecting the first non-superimposing portion X1 and the second non-superimposing portion X2. However, if the first non-superimposing portion X1 and the second non-superimposing portion X2 are arranged at both ends of the second wiring 45 in order to correct a defect that may occur in a wide range in the first wiring 43 and the second wiring 45, the correction causes The length of the insulated wiring also becomes long, which may cause a problem that the resistance greatly differs between the adjacent connection wirings 42.

On the other hand, according to the wiring board 240 having the above configuration, the third non-superimposing portion X3 is provided between the first non-superimposing portion X1 and the second non-superimposing portion X2, and the first non-superimposing portion X1 and the first non-superimposing portion X1 are provided. 3 The defective first wiring 243 or second wiring 245 is separated from the connection wiring 242 between the non-superimposition portion X3 or between the third non-superimposition portion X3 and the second non-superimposition portion X2 ( Can be insulated). This makes it possible to reduce the difference in resistance between adjacent connection wirings 242 and repair defects. At this time, it is preferable to conduct the first wiring 243 and the second wiring 245 by a laser repair device at the ends of the first non-superimposition portion X1 and the second non-superimposition portion X2 following the third non-superimposition portion X3.

Further, the third non-superimposed portion X3 may be provided at a plurality of locations between the first non-superimposed portion X1 and the second non-superimposed portion X2. In this case, there is a defect between one third non-superimposition portion X3 and the other third non-superimposition portion X3 arranged next to the third non-superimposition portion X3 along the longitudinal direction of the connection wiring 242. The existing first wiring 243 or second wiring 245 can be separated (insulated). Thereby, the difference in resistance between the adjacent connection wirings 242 can be further reduced, and the defect can be repaired. Whether there is a defect in the first wiring 243 or the second wiring 245 and whether there is a defect between the non-superimposing portions X1, X3, X2 is determined by, for example, an electrical characteristic evaluation (for example, a charge amount). It can be judged by evaluation). If it is not possible to determine from the electrical characteristic evaluation whether there is a leak in the first wiring 243 or the second wiring 245 and which non-superimposing portion X1, X3, X2 has a defect, the leak Cut the single layer part S1 or S2 for the non-superimposing parts X1, X3, X2 arranged at the positions sandwiching the wiring with high possibility, and if the leak is not repaired, repair (connect) the cut part and the other. The single layer portion S2 or S1 for the portion may be cut.

<< Other Embodiments >>
The techniques disclosed herein are not limited to those disclosed in the above embodiments, and for example, the following aspects are also included in the technical scope disclosed herein. In addition, the techniques disclosed herein can be implemented in various modified embodiments without departing from their essence.

(1) In each of the above-described embodiments, the case where the connection wiring of the two-layer structure according to the present technology is a source leader is exemplified, but the connection wiring may be, for example, a gate leader, or other wiring. May be.

(2) In the above-described second embodiment, the connection wiring is meandered repeatedly to the left and right in the form of a substantially U shape along the X-axis direction, and extends along the Y-axis direction. The composition of is not limited to this. For example, the number of folds of the substantially U-shape of the meandering portion is not limited, and can be appropriately set according to a desired degree of resistance increase. Further, the connection wiring may include a portion extending along an oblique direction intersecting the X-axis direction and the Y-axis direction while repeatedly meandering left and right in the X-axis direction. For example, the oblique portion P2 includes a meandering portion. But it may be.

(3) In the above-described embodiment, the first wiring and the second wiring constituting the connection wiring are composed of conductor films having different compositions from each other, but the first wiring and the second wiring constituting the connection wiring are used. May be composed of both conductor films having the same composition.

(4) In the above-described embodiment, an example in which the two-layer structure connection wiring according to the present technology is applied to all the source leader wires arranged on the substrate has been disclosed, but the two-layer structure connection wiring according to the present technology has been disclosed. May be applied to any one or more of all the wiring arranged on the board. Further, a region having a two-layer structure of the connection wiring (in other words, a position to be bypassed by the second wiring and its length) can be appropriately set.

(5) In the above-described embodiment, the case where both the first wiring and the second wiring constituting the connection wiring are composed of a conductor film made of metal is shown, but the first wiring and the second wiring are at least a part. Alternatively, the entire semiconductor film may include a low resistance region or a transparent electrode film.

(6) In each of the above-described embodiments, the case where the wiring board includes a bottom gate type TFT having a single gate structure is shown, but the configuration of the TFT is not limited to this. The TFT may be, for example, a TFT having a dual gate structure in which two gate electrodes, a front gate electrode and a back gate electrode, are arranged on a layer having the same distance from the substrate, or two gate electrodes above and below the channel layer. It may be a TFT or the like having a double gate structure. Further, as the material of the semiconductor film (channel layer), amorphous silicon or low-temperature polysilicon can be used in addition to the oxide semiconductor. When low-temperature polysilicon is used as the material of the semiconductor film, it is preferable that the TFT is a top gate type in which the gate electrode is arranged on the upper layer side of the channel layer.

(7) In each of the above-described embodiments, the case where the connection wiring is directly connected to the source wiring is shown, but the switch circuit unit (RGB switch circuit unit) and the ESD protection circuit unit are connected between the connection wiring and the source wiring. Etc. may intervene. The switch circuit unit has a function of distributing a signal supplied from the terminal unit side to a plurality of source wirings connected to pixel units having different colors. Therefore, in a configuration in which the connection wiring is connected to the switch circuit portion, the number of terminals and connection wirings installed can be smaller than the number of source wirings installed.

(8) In addition to the above-described embodiments, the connection position of the flexible substrate with respect to the array substrate in the X-axis direction and the arrangement of the terminal portion in the X-axis direction of the array substrate can be appropriately changed. In that case, the shape and arrangement of the connection wiring on the array board are also appropriately changed according to the mounting mode of the flexible board.

(9) In each of the above-described embodiments, the case where only one flexible board is mounted on the array board is shown, but a configuration in which a plurality of flexible boards are mounted on the array board may be used. Even in that case, the shape and arrangement of the connection wiring on the array board are also appropriately changed according to the mounting mode of the flexible board.

(10) In each of the above-described embodiments, the configuration in which the flexible substrate on which the driver is COF-mounted is COB-mounted on the array substrate is shown, but even if the driver is COG (Chip On Glass) mounted on the array substrate. good. In that case, the driver is mounted on the array board at a position closer to the display area than the mounting area of the flexible board. The terminal portion connected to the connection wiring will be arranged in the driver mounting area.

(11) In addition to the above-described embodiments, the specific configuration of the pixel electrodes can be appropriately changed. For example, the shape of the pixel electrode may be a rectangle (square or rectangle), a rhombus, a parallelogram, or the like, and these may be arranged in the same orientation (orientation) on the substrate, or may be arranged in different orientations (the shape may be different). For example, it may be staggered.

(12) In each of the above-described embodiments, the case where the color filter has three colors of R, G, and B is illustrated, but the color filter includes, for example, four colors (for example, R, G, and B) other than the three colors. White) or the like. In this case, the ratio of the longitudinal dimension to the lateral dimension in the pixel electrode can be appropriately set.

(13) In addition to the above-described embodiments, specific wiring routes such as specific screen size and resolution of the liquid crystal panel, display mode, pixel electrode configuration, connection wiring, source wiring, and gate wiring, and The line width, pitch, etc. can be changed as appropriate. Further, the ratio of the length of the second wiring overlapping with the first wiring can be appropriately changed.

(14) The defect repair method of the wiring board of the above-described embodiment may be carried out at any timing after forming the connection wiring having a two-layer structure. For example, it can be carried out before bonding the wiring board and the CF board, which can easily carry out defect repair by the laser repair device. In addition, after forming the connection wiring of the two-layer structure, it is preferable to carry out at the time of lighting inspection or the like.

(15) In the above embodiment, a liquid crystal display device using a liquid crystal panel as a display panel is exemplified, but the display panel includes a PDP (plasma display panel), an organic EL (Electro-Luminescence) panel, and an EPD (microcapsule type electricity). It may be another type of display panel such as a migration type display panel), a MEMS (Micro Electro Mechanical Systems) display panel, or a display panel with a touch sensor. The same applies to the display device. Further, the backlight may be omitted for the display device provided with the organic EL panel.

11 ... Liquid crystal panel, 12 ... Source driver, 13 ... Flexible board, 14 ... Gate circuit section, 15 ... Lead wiring, 20 ... CF board, 21 ... Array board, 22 ... Liquid crystal layer, 23 ... TFT, 23A ... Gate electrode, 23B ... source electrode, 23C ... drain electrode, 23D ... channel layer, 24 ... pixel electrode, 27 ... source wiring, 33 ... gate insulating layer, 40, 240 ... wiring board, 41 ... board, 42, 242 ... connection wiring, 43. , 243 ... 1st wiring, 44 ... Insulation layer, 45,245 ... 2nd wiring, 50 ... Output terminal, C1 ... 1st contact, C2 ... 2nd contact, M1 ... 1st intermediate point, M2 ... 2nd intermediate point , M31 ... 1st meandering part, M32 ... 2nd meandering part, M3 ... meandering part, P1 ... straight part, P2 ... diagonal part, P3 ... widening part, X0, X01 ... superimposing part, X1 ... first non-superimposing part, X2 ... 2nd non-superimposing part, X3 ... 3rd non-superimposing part

Claims (13)

Insulating substrate and
Pixel electrodes provided on the substrate and
Pixel wiring provided on the substrate and connected to the pixel electrodes,
A signal input unit for inputting a signal to the pixel wiring,
A first wiring provided on the substrate and connected to the pixel wiring and the signal input unit,
The first contact and the second contact, which are provided on the substrate and are arranged along the first wiring, are superimposed on the first wiring via an insulating layer, and are arranged apart from each other, are attached to the first wiring. The second wiring to be connected and
Equipped with
The first wiring and the second wiring are formed between the first contact and the second contact.
The overlapping part that overlaps with each other,
At the positions sandwiching the superposed portion, a first non-superimposed portion and a second non-superimposed portion that do not superimpose on each other,
Wiring board. The first non-superimposing portion is provided between the first contact point and the second contact point so as to be connected to the first contact point.
The wiring board according to claim 1, wherein the second non-superimposing portion is provided between the first contact and the second contact so as to be connected to the second contact. The first wiring and the second wiring each have a widened portion wider than the other portions, and the first contact and the second contact are provided in the widened portion, respectively.
The first wiring and the second wiring extend from the separated positions of the widened portion and then overlap each other so that the first non-superimposed portion and the second non-superimposed portion are continuously connected to the widened portion. The wiring board according to claim 2. The first wiring is
The first and second parts extending along the first direction,
Includes an oblique portion extending along a second direction that intersects the first direction at an angle of less than 90 degrees between the first part and the second part.
The wiring board according to claim 1 or 2, wherein the first contact is provided in the first portion, and the second contact is provided in the second portion. The second wiring is narrower than the first wiring, and the first wiring includes a protruding portion protruding from both ends of the second wiring in a width direction orthogonal to the longitudinal direction, according to claim 1 or 2. The wiring board described. The wiring board according to claim 1 or 2, wherein the second wiring is superimposed on the first wiring over a range of 90% or more along the longitudinal direction of the second wiring. A thin film transistor including a gate layer, a source layer, and a gate insulating layer that insulates the gate layer and the source layer.
The first wiring is composed of the same conductive film as the source layer, and is composed of the same conductive film.
The second wiring is composed of the same conductive film as the gate layer, and is composed of the same conductive film.
The wiring board according to claim 1 or 2, wherein the insulating layer is formed of the same insulating film as the gate insulating layer. The first wiring and the second wiring are located between the first non-superimposing portion and the second non-superimposing portion, at positions separated from the first non-superimposing portion and the second non-superimposing portion. The wiring board according to claim 1 or 2, further comprising a third non-superimposing portion that does not superimpose on each other. The first wiring and the second wiring are
Between the first non-superimposing portion and the second non-superimposing portion, with the first intermediate point and the second intermediate point arranged apart from the first non-superimposing portion and the second non-superimposing portion. ,
A meandering portion between the first intermediate point and the second intermediate point, which meanders along a direction intersecting the direction connecting the first intermediate point and the second intermediate point.
Have,
One of the first wiring and the second wiring includes a first meandering portion that meanders in a substantially U-shape in the meandering portion.
The other of the first wiring and the second wiring includes a second meandering portion in the meandering portion, which meanders in a substantially U shape wider than the first meandering portion.
The first meandering portion and the second meandering portion are
One of the pair of parallel portions extending substantially in parallel with each other overlaps with each other to form the superimposed portion.
The wiring board according to claim 8, wherein at least the other portion of the parallel portions does not overlap with each other to form the third non-superimposition portion. A plurality of the pixel electrodes, a plurality of the pixel wirings, and a plurality of the first wirings and the second wirings are provided.
The wiring board according to any one of claims 1, 2, 3, and 9, wherein the plurality of the first wiring and the second wiring are arranged in a direction in which at least a part thereof intersects in the longitudinal direction. The wiring board according to any one of claims 1, 2, 3, 9, and 10.
A display panel comprising an opposed board attached to the wiring board. A step of performing a short-circuit test of a plurality of the first wirings of the wiring board according to claim 10 to identify a short-circuit wiring pair short-circuited between the adjacent first wirings.
For the first wiring of at least one of the specified short-circuit wiring pairs, one of the first wiring and the second wiring connected to the first wiring is provided with the first non-superimposing portion and the first non-superimposing portion. The step of cutting at each of the second non-superimposing portions and
How to repair defects in wiring boards, including. The wiring board according to claim 8, further comprising the plurality of the pixel electrodes, the plurality of the pixel wirings, the plurality of the first wiring and the second wiring, and the plurality of the first wiring and the said. The second wiring is a short-circuit wiring pair in which a plurality of the first wirings are short-circuited on a wiring board arranged in a direction in which at least a part thereof intersects in the longitudinal direction, and the first wirings adjacent to each other are short-circuited. And the process of identifying
For the first wiring of at least one of the specified short-circuit wiring pairs, either one of the first wiring and the second wiring connected to the first wiring may be the first non-superimposing portion or the first non-superimposing portion. The step of cutting at each of the second non-superimposing portion and the third non-superimposing portion,
How to repair defects in wiring boards, including.

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