WO2012176031A1 - Method of fabrication of a semiconductor substrate and a semiconductor substrate - Google Patents
Method of fabrication of a semiconductor substrate and a semiconductor substrate Download PDFInfo
- Publication number
- WO2012176031A1 WO2012176031A1 PCT/IB2012/001129 IB2012001129W WO2012176031A1 WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1 IB 2012001129 W IB2012001129 W IB 2012001129W WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- substrate
- donor substrate
- constituted
- strained
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 223
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims description 68
- 239000000463 material Substances 0.000 claims abstract description 193
- 238000000034 method Methods 0.000 claims abstract description 57
- 230000001965 increasing effect Effects 0.000 claims abstract description 10
- 230000008602 contraction Effects 0.000 claims abstract description 8
- 230000001939 inductive effect Effects 0.000 claims abstract description 4
- 238000009877 rendering Methods 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 46
- 239000010703 silicon Substances 0.000 claims description 44
- 150000002500 ions Chemical class 0.000 claims description 43
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 27
- 238000002513 implantation Methods 0.000 claims description 12
- 238000005498 polishing Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000012141 concentrate Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 284
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 40
- 229910052796 boron Inorganic materials 0.000 description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 16
- 238000004064 recycling Methods 0.000 description 15
- 230000007547 defect Effects 0.000 description 12
- 229910052732 germanium Inorganic materials 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 238000002048 anodisation reaction Methods 0.000 description 8
- 229910052729 chemical element Inorganic materials 0.000 description 8
- -1 hydrogen ions Chemical class 0.000 description 8
- 235000019592 roughness Nutrition 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000003792 electrolyte Substances 0.000 description 6
- 239000011148 porous material Substances 0.000 description 6
- 230000006835 compression Effects 0.000 description 5
- 238000007906 compression Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910021426 porous silicon Inorganic materials 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000008366 buffered solution Substances 0.000 description 1
- 238000003795 desorption Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000010070 molecular adhesion Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Definitions
- the method further comprises a seventh step consisting .in reusing the donor substrate resulting from the sixth step and including the porous support layer for the fabrication of a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material; - the seed layer has, after the third step, a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer in the relaxed state; - the third material is silicon, the second material is SiGe, and the first material is silicon;
- FIG. 2 is a diagrammatic representation of an electrochemical anodization method
- FIG. 3 is a diagrammatic representation of another embodiment of the electrochemical anodization method
- the first material and the second material have different lattice parameters in the relaxed state.
- the results of the treatment enabling the support layer 2 to be made porous depend on various parameters, such as the type and the level of doping, the crystal orientation of the material of the layer, the current density, the composition and the concentration of the electrolyte, the temperature and the anodization time.
- the seed layer 3 has a lattice parameter equal to the lattice parameter of the material of the seed layer 3 in the relaxed state, or
- the seed layer 3' having in one embodiment a thickness in the range
- the method includes a sixth step E6 consisting in transferring at least part of the strained layer 5 constituted of the third material from the donor substrate 1 to a receiver substrate 8.
- Bonding the donor substrate 1 and the receiver substrate 8 is generally preceded by cleaning the surfaces of the substrates to enable improved molecular bonding.
- the confinement structure 23 comprising the confinement layer 25 is generally produced by epitaxial growth and is formed during the first step E1 of formation of the donor substrate 1.
- the confinement structure is generally disposed in the seed layer 3.
- a confinement layer is produced in one or more materials adapted to attract the ions introduced into the substrate towards said confinement layer during this temperature increasing heat treatment.
- Typical heat treatment temperatures are in the range 200°C to 700°C.
- the seed layer 3' constituted of the second material remains relaxed or in a state close to a relaxed state (as defined above) before its reuse, in contrast to the first embodiment.
- the seventh step E7 of reusing the donor substrate 1 includes the steps consisting in repeating the fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer 5 constituted of the third material.
- the donor substrate 1 still includes, after the sixth step E6, part of the strained layer 5, i.e. not all of the latter has been transferred after the sixth step E6.
- the method includes the steps consisting in applying cyclically the second, third, fourth, fifth, sixth and seventh steps for the fabrication of a plurality of receiver substrates including a strained layer 5 of the third material from a donor substrate 1 formed in the first step.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1155574 | 2011-06-23 | ||
FR1155574A FR2977070A1 (fr) | 2011-06-23 | 2011-06-23 | Procede de fabrication d'un substrat semi-conducteur comprenant du silicium poreux, et substrat semi-conducteur |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012176031A1 true WO2012176031A1 (en) | 2012-12-27 |
Family
ID=46456941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2012/001129 WO2012176031A1 (en) | 2011-06-23 | 2012-06-11 | Method of fabrication of a semiconductor substrate and a semiconductor substrate |
Country Status (3)
Country | Link |
---|---|
FR (1) | FR2977070A1 (zh) |
TW (1) | TW201301372A (zh) |
WO (1) | WO2012176031A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7464631B2 (ja) | 2019-07-02 | 2024-04-09 | ソイテック | 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3024587B1 (fr) | 2014-08-01 | 2018-01-26 | Soitec | Procede de fabrication d'une structure hautement resistive |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040115900A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
US20060118870A1 (en) * | 2004-12-08 | 2006-06-08 | Samsung Electronics Co., Ltd. | Structure of strained silicon on insulator and method of manufacturing the same |
US20060124961A1 (en) * | 2003-12-26 | 2006-06-15 | Canon Kabushiki Kaisha | Semiconductor substrate, manufacturing method thereof, and semiconductor device |
US20060144323A1 (en) * | 2004-12-30 | 2006-07-06 | Samsung Electronics Co., Ltd. | Substrate with locally integrated single crystalline silicon layer and method of fabricating the same |
-
2011
- 2011-06-23 FR FR1155574A patent/FR2977070A1/fr active Pending
-
2012
- 2012-05-16 TW TW101117426A patent/TW201301372A/zh unknown
- 2012-06-11 WO PCT/IB2012/001129 patent/WO2012176031A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040115900A1 (en) * | 2002-12-13 | 2004-06-17 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance |
US20060124961A1 (en) * | 2003-12-26 | 2006-06-15 | Canon Kabushiki Kaisha | Semiconductor substrate, manufacturing method thereof, and semiconductor device |
US20060118870A1 (en) * | 2004-12-08 | 2006-06-08 | Samsung Electronics Co., Ltd. | Structure of strained silicon on insulator and method of manufacturing the same |
US20060144323A1 (en) * | 2004-12-30 | 2006-07-06 | Samsung Electronics Co., Ltd. | Substrate with locally integrated single crystalline silicon layer and method of fabricating the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7464631B2 (ja) | 2019-07-02 | 2024-04-09 | ソイテック | 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造 |
Also Published As
Publication number | Publication date |
---|---|
FR2977070A1 (fr) | 2012-12-28 |
TW201301372A (zh) | 2013-01-01 |
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