WO2012176031A1 - Procédé de fabrication d'un substrat semi-conducteur et substrat semi-conducteur - Google Patents

Procédé de fabrication d'un substrat semi-conducteur et substrat semi-conducteur Download PDF

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Publication number
WO2012176031A1
WO2012176031A1 PCT/IB2012/001129 IB2012001129W WO2012176031A1 WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1 IB 2012001129 W IB2012001129 W IB 2012001129W WO 2012176031 A1 WO2012176031 A1 WO 2012176031A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
donor substrate
constituted
strained
Prior art date
Application number
PCT/IB2012/001129
Other languages
English (en)
Inventor
Christophe Figuet
Oleg Kononchuk
Original Assignee
Soitec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec filed Critical Soitec
Publication of WO2012176031A1 publication Critical patent/WO2012176031A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Definitions

  • the method further comprises a seventh step consisting .in reusing the donor substrate resulting from the sixth step and including the porous support layer for the fabrication of a new receiver substrate including at least part of a strained layer constituted of a third semiconductor material; - the seed layer has, after the third step, a lattice parameter having a maximum difference of 0.5% in absolute value relative to the lattice parameter of the material of the seed layer in the relaxed state; - the third material is silicon, the second material is SiGe, and the first material is silicon;
  • FIG. 2 is a diagrammatic representation of an electrochemical anodization method
  • FIG. 3 is a diagrammatic representation of another embodiment of the electrochemical anodization method
  • the first material and the second material have different lattice parameters in the relaxed state.
  • the results of the treatment enabling the support layer 2 to be made porous depend on various parameters, such as the type and the level of doping, the crystal orientation of the material of the layer, the current density, the composition and the concentration of the electrolyte, the temperature and the anodization time.
  • the seed layer 3 has a lattice parameter equal to the lattice parameter of the material of the seed layer 3 in the relaxed state, or
  • the seed layer 3' having in one embodiment a thickness in the range
  • the method includes a sixth step E6 consisting in transferring at least part of the strained layer 5 constituted of the third material from the donor substrate 1 to a receiver substrate 8.
  • Bonding the donor substrate 1 and the receiver substrate 8 is generally preceded by cleaning the surfaces of the substrates to enable improved molecular bonding.
  • the confinement structure 23 comprising the confinement layer 25 is generally produced by epitaxial growth and is formed during the first step E1 of formation of the donor substrate 1.
  • the confinement structure is generally disposed in the seed layer 3.
  • a confinement layer is produced in one or more materials adapted to attract the ions introduced into the substrate towards said confinement layer during this temperature increasing heat treatment.
  • Typical heat treatment temperatures are in the range 200°C to 700°C.
  • the seed layer 3' constituted of the second material remains relaxed or in a state close to a relaxed state (as defined above) before its reuse, in contrast to the first embodiment.
  • the seventh step E7 of reusing the donor substrate 1 includes the steps consisting in repeating the fifth and sixth steps of the fabrication method to fabricate a new receiver substrate including at least part of a strained layer 5 constituted of the third material.
  • the donor substrate 1 still includes, after the sixth step E6, part of the strained layer 5, i.e. not all of the latter has been transferred after the sixth step E6.
  • the method includes the steps consisting in applying cyclically the second, third, fourth, fifth, sixth and seventh steps for the fabrication of a plurality of receiver substrates including a strained layer 5 of the third material from a donor substrate 1 formed in the first step.

Abstract

L'invention concerne un procédé de fabrication consistant à former un substrat donneur (1) comprenant une couche support (2) et une couche de germe contrainte (3), rendre poreuse la couche support (2), traiter le substrat donneur (1) pour déformer en allongement ou en contraction la couche support poreuse (2') constituée du premier matériau, ladite déformation induisant un relâchement dans la couche de germe (3'), augmenter l'épaisseur de la couche de germe (3'), former une couche contrainte (5) en contact avec ladite couche de germe (3') et transférer au moins une partie de la couche contrainte (5) du substrat donneur (1) à un substrat récepteur (8).
PCT/IB2012/001129 2011-06-23 2012-06-11 Procédé de fabrication d'un substrat semi-conducteur et substrat semi-conducteur WO2012176031A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1155574 2011-06-23
FR1155574A FR2977070A1 (fr) 2011-06-23 2011-06-23 Procede de fabrication d'un substrat semi-conducteur comprenant du silicium poreux, et substrat semi-conducteur

Publications (1)

Publication Number Publication Date
WO2012176031A1 true WO2012176031A1 (fr) 2012-12-27

Family

ID=46456941

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2012/001129 WO2012176031A1 (fr) 2011-06-23 2012-06-11 Procédé de fabrication d'un substrat semi-conducteur et substrat semi-conducteur

Country Status (3)

Country Link
FR (1) FR2977070A1 (fr)
TW (1) TW201301372A (fr)
WO (1) WO2012176031A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7464631B2 (ja) 2019-07-02 2024-04-09 ソイテック 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3024587B1 (fr) * 2014-08-01 2018-01-26 Soitec Procede de fabrication d'une structure hautement resistive

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040115900A1 (en) * 2002-12-13 2004-06-17 Taiwan Semiconductor Manufacturing Company Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
US20060118870A1 (en) * 2004-12-08 2006-06-08 Samsung Electronics Co., Ltd. Structure of strained silicon on insulator and method of manufacturing the same
US20060124961A1 (en) * 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
US20060144323A1 (en) * 2004-12-30 2006-07-06 Samsung Electronics Co., Ltd. Substrate with locally integrated single crystalline silicon layer and method of fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040115900A1 (en) * 2002-12-13 2004-06-17 Taiwan Semiconductor Manufacturing Company Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance
US20060124961A1 (en) * 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
US20060118870A1 (en) * 2004-12-08 2006-06-08 Samsung Electronics Co., Ltd. Structure of strained silicon on insulator and method of manufacturing the same
US20060144323A1 (en) * 2004-12-30 2006-07-06 Samsung Electronics Co., Ltd. Substrate with locally integrated single crystalline silicon layer and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7464631B2 (ja) 2019-07-02 2024-04-09 ソイテック 高周波アプリケーション用の埋め込みポーラス層を含む半導体構造

Also Published As

Publication number Publication date
TW201301372A (zh) 2013-01-01
FR2977070A1 (fr) 2012-12-28

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