WO2012174871A1 - 一种锗基nmos器件及其制备方法 - Google Patents

一种锗基nmos器件及其制备方法 Download PDF

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WO2012174871A1
WO2012174871A1 PCT/CN2012/071390 CN2012071390W WO2012174871A1 WO 2012174871 A1 WO2012174871 A1 WO 2012174871A1 CN 2012071390 W CN2012071390 W CN 2012071390W WO 2012174871 A1 WO2012174871 A1 WO 2012174871A1
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substrate
metal
oxide
layer
germanium
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French (fr)
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黄如
李志强
安霞
郭岳
张兴
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0277—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming conductor-insulator-semiconductor or Schottky barrier source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/165—Tunnel injectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the embodiment of the invention belongs to the field of ultra-large scale integrated circuit (ULSI) process manufacturing technology, and particularly relates to a germanium-based MOS device structure and a preparation method thereof.
  • ULSI ultra-large scale integrated circuit
  • BACKGROUND OF THE INVENTION Under the impetus of Moore's Law, traditional silicon-based MOS devices face many challenges and limitations while continuously increasing integration: such as mobility degradation, carrier velocity saturation, and DIBL effect, among which mobility degradation becomes an influence device.
  • One of the key factors for further improvement in performance In order to solve the problem caused by device size reduction, high mobility channel materials must be used.
  • ⁇ -based Schottky MOS transistors have become one of the research hotspots: First, the electron and hole mobility of germanium materials is higher than that of silicon materials, and the fabrication process of germanium channel devices is compatible with traditional CMOS processes; The source-drain structure replaces the traditional highly doped source and drain, which not only avoids the problem of low solid solubility and fast diffusion of impurities in the germanium material, but also reduces the source-drain resistivity. Therefore, fluorenyl Schottky MOS transistors are expected to break through the limitations of conventional silicon-based devices to achieve excellent device performance.
  • ⁇ -based Schottky MOS transistors also have problems to be solved: a large number of dangling bonds and metal (or metal telluride) present at the interface between the source-drain and the substrate of the fluorenyl Schottky MOS transistor are generated in the forbidden band.
  • the metal induced band gap state (MIGS) causes the Fermi level to be pinned near the valence band, resulting in a large electron barrier.
  • the larger electron barrier limits the performance improvement of the ⁇ -based Schottky MOS transistor: the large electron barrier of the source/channel limits the current drive capability of the device during the on-state; The low hole barrier causes the leakage current of the device to increase; at the same time, the larger electron barrier causes the electrons at the source to enter the channel mainly in a tunneling manner, resulting in a large subthreshold slope of the device. Therefore, the height of the electron barrier becomes one of the decisive factors affecting the performance of the ⁇ -based Schottky MOS transistor. Summary of the invention
  • the embodiment of the present invention attenuates the Fermi level pin by depositing a cerium oxide (Ge0 2 ) and a metal oxide double-layer dielectric film between the source and drain regions and the substrate.
  • the tie effect reduces the electron barrier and improves the performance of the bismuth-based Schottky MOS transistor.
  • Steps 1 to 1) specifically include:
  • the germanium-based substrate of the step 1 - 1) includes a bulk germanium substrate, a germanium-insulated insulating substrate (GOI) or an epitaxial germanium substrate, and the like.
  • the metal oxide of the step 1 - 2) uses a material having a low oxygen atomic areal density, and the ratio of the oxygen atomic areal density to the Ge0 2 oxygen atomic areal density of the dielectric material is required to be less than 0.8, such as strontium oxide (SrO), barium oxide (BaO). ), radium oxide (RaO), etc.
  • the metal film of the step 1 - 3 ) is an aluminum film or other low work function metal film.
  • This method can weaken the Fermi level pinning effect and reduce the electron barrier, thereby improving the performance of the ⁇ -based Schottky MOS device.
  • a thin layer of metal oxide is deposited on the Ge0 2, since the density of oxygen atoms at the interface surface of the metal oxide, Ge0 2 oxygen atoms at the interface moves to its interface is lower than the metal oxide Ge0 2, resulting in A dipole directed by Ge0 2 to the metal oxide is generated at the interface, and the electric field generated by the dipole contributes to the adjustment of the Schottky electron barrier.
  • Ge0 2 can form a Ge substrate.
  • the metal induced band gap state (MIGS) is generated in the band, thereby achieving the purpose of further weakening the Fermi level pinning effect and adjusting the Schottky barrier height.
  • the oxygen atomic areal density of the metal oxide is related to the radius of the metal cation: the larger the metal cation radius, the smaller the oxygen atomic areal density.
  • the radium ion (RaO) and other materials have a metal ion radius greater than ⁇ . ⁇ , and the oxygen atomic areal density ratio at the interface with Ge0 2 is less than 0.8, which in turn produces a strong dipole-adjusted Schottky barrier.
  • this embodiment can more effectively adjust the Schottky barrier and improve device performance.
  • FIG. 1(j) are flowcharts showing the preparation of a fluorenyl Schottky transistor according to an embodiment of the present invention.
  • FIG. 1 is a flow chart of a method of fabricating a germanium based Schottky transistor in accordance with a preferred embodiment of the present invention.
  • the preferred embodiment of the invention produces a germanium-based Schottky transistor method comprising the steps of:
  • Step 1 Provide a ruthenium based substrate.
  • an N-type semiconductor germanium substrate 1 As shown in Fig. 1 (a), an N-type semiconductor germanium substrate 1, wherein the substrate 1 can be a body germanium, a germanium-insulated insulating (G0I) or an epitaxial germanium substrate.
  • the substrate 1 can be a body germanium, a germanium-insulated insulating (G0I) or an epitaxial germanium substrate.
  • Step 2 Make a P-well region. Depositing a silicon oxide layer and a silicon nitride layer on the germanium substrate, first defining a P well region by photolithography and reactively etching away silicon nitride in the P well region, and then ion-implanting a P-type impurity such as boron, etc., and then annealing Into the P-well 2, and finally remove the implant mask, as shown in Figure 1 (b).
  • Step 3 Implement trench isolation.
  • a silicon oxide and silicon nitride layer is first deposited on the germanium, and then lithography is defined and reactive silicon etching is used to etch silicon nitride, silicon oxide, and germanium to form trenches.
  • a chemical vapor deposition (CVD) method is used to deposit a silicon oxide backfill isolation trench, and finally a chemical mechanical polishing technique (CMP) is used to smooth the surface to achieve isolation between devices.
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing technique
  • Device isolation is not limited to shallow trench isolation (STI), but techniques such as field oxide isolation can also be used.
  • Step 4 forming a gate dielectric layer on the active region.
  • the gate dielectric layer may be made of a high-k dielectric, cerium oxide, cerium oxynitride or the like. Before depositing the gate dielectric, it is generally necessary to perform surface passivation treatment with PH 3 , H 3 , and F plasma, or deposit an interfacial layer such as silicon (Si), aluminum nitride (A1N;), or antimony oxide ( Y 2 0 3 ) and so on.
  • a germanium substrate yttria ⁇ 2 0 3) as an interface layer
  • ALD atomic layer deposition
  • Step 5 forming a gate on the gate dielectric layer.
  • the gate may be a polysilicon gate, a metal gate, a FUSI gate or a full germanium gate.
  • a metal gate is formed by depositing titanium nitride (TiN), and then lithographically defined and etched to form a gate structure, as shown in FIG. 1 (e) ) as shown.
  • Step 6 Prepare the side walls on both sides of the grid.
  • the side can be prepared by depositing SiO 2 or Si 3 N 4 and etching
  • the wall may also deposit Si 3 N 4 and Si0 2 in sequence to form a double-sided wall structure.
  • a sidewall structure 6 is formed on both sides of the gate by depositing Si0 2 and using dry etching.
  • Step 7 Form a thin layer of Ge0 2 in the source and drain regions.
  • This thin layer can be obtained by ALD, RF sputtering, thermal oxidation, and ozone oxidation.
  • the ALD deposition mode is preferred, and the Ge0 2 thickness is about 0.5 to 4 as shown in Fig. 1 (g).
  • Step 8 Depositing a metal oxide film of the source and drain regions. It is required that the ratio of the oxygen atom density at the interface of the dielectric material to the Ge0 2 interface oxygen atom density is less than 0.8, such as strontium oxide (SrO;), barium oxide (BaO;), radium oxide (RaO), etc., the preferred embodiment of the present embodiment uses strontium oxide (SrO). ).
  • This layer of material can also be obtained by ALD deposition, which has a thickness of about 0.5 to 4 nm, as shown in Figure 1 (h).
  • Step 9 Prepare a metal source and drain.
  • a low work function metal film such as aluminum (Al), titanium (Ti), ytterbium (Y) or the like may be deposited on the semiconductor substrate by physical vapor deposition such as evaporation or sputtering.
  • the preferred embodiment is aluminum having a thickness ranging from 100 ⁇ to 1 ⁇ , which is defined by lithography and etched to obtain a metal source drain, as shown in Fig. 1(i).
  • Step 10 Form contact holes and metal wires.
  • an oxide layer is deposited by CVD, lithography defines an opening position and etches silicon dioxide to form a contact hole; then a metal layer such as Al Al-Ti is sputtered, and a wiring pattern is formed by photolithography and etched to form a metal. The wiring pattern is finally metallized to obtain the metal wiring layer 10, as shown in Fig. 1 (j).
  • Embodiments of the present invention provide a germanium-based MOS device structure and a method of fabricating the same. This method can not only reduce the barrier height of the electrons in the Schottky-based MOS source and drain, but also improve the performance of the Schottky-based MOS transistor, and the preparation process is simple and fully compatible with silicon CMOS technology. Compared with the prior art, the semiconductor device structure and the method of fabricating the same can improve the performance of the bismuth-based Schottky MOS transistor simply and effectively.
  • the present invention has been described in detail by the preferred embodiments of the present invention. It is understood that the above description is only a preferred embodiment of the present invention, and that the device structure of the present invention can be made certain without departing from the spirit of the invention.
  • the source/drain structure may also adopt a lifted, recessed source/drain structure or other new structures such as a double gate, a FinFET ⁇ gate, a triple gate, a fence, etc.; the preparation method thereof is not limited to the contents disclosed in the embodiment, Equivalent variations and modifications made in accordance with the claims of the present invention are intended to be within the scope of the present invention.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

发明提供了一种锗基肖特基NMOS晶体管，包括在衬底（1）与源、漏区之间淀积二氧化锗层（7）和金属氧化物层，具体为：在衬底（1）上淀积一层二氧化锗，在二氧化锗层（7）上淀积一层金属氧化物，金属源、漏区位于金属氧化物层上。发明还提供了一种锗基肖特基NMOS晶体管的制备方法。这降低了晶体管的源、漏处的电子的势垒高度，改善了电流开关比，提升了晶体管的性能，而且制作工艺与硅CMOS技术完全兼容，保持了工艺简单的优势。

Description

一种锗基 NMOS器件及其制备方法
相关申请的交叉引用
本申请要求于 2011年 6月 23日提交至中国国家知识产权局的中国专利申请（申 请号为： 201110170991.4) 的优先权， 其全部内容通过引用合并于此。 技术领域
本发明实施例属于超大规模集成电路 （ULSI) 工艺制造技术领域， 具体涉及一 种锗基 MOS器件结构及其制备方法。 背景技术 在摩尔定律的推动下， 传统硅基 MOS器件在不断提高集成度的同时也面临诸多 挑战和限制： 如迁移率退化、 载流子速度饱和以及 DIBL效应等， 其中迁移率退化成 为影响器件性能进一步提升的关键因素之一。 为了解决器件尺寸缩小所带来的问题， 必须采用高迁移率沟道材料。 目前， 锗基肖特基 MOS晶体管成为了研究热点之一： 首先， 锗材料的电子和空穴迁移率比硅材料高， 而且锗沟道器件的制备工艺与传统 CMOS工艺兼容；同时肖特基源漏结构替代传统的高掺杂源漏不仅避免了锗材料中杂 质固溶度低和扩散快的问题， 而且还能减小源漏电阻率。 因此， 锗基肖特基 MOS晶 体管有望突破传统硅基器件的限制而获得优良的器件性能。
然而， 锗基肖特基 MOS晶体管也存在亟待解决的问题： 锗基肖特基 MOS晶体 管源漏与衬底的界面处存在的大量悬挂键以及金属 (或金属锗化物)在锗禁带中产生 的金属诱导带隙态 （MIGS) 使费米能级被钉扎在价带附近， 导致电子势垒较大。 较 大的电子势垒限制了锗基肖特基 MOS晶体管性能的提升： 开态时源 /沟道较大的电 子势垒限制了器件的电流驱动能力； 而关态时漏 /沟道的较低的空穴势垒导致器件的 泄漏电流增大； 同时， 较大的电子势垒使源端的电子主要以隧穿的方式进入沟道， 导 致器件的亚阈值斜率变大。 因此， 电子势垒高度成为影响锗基肖特基 MOS晶体管 性能的决定因素之一。 发明内容
针对上述锗基肖特基 MOS晶体管存在的问题， 本发明实施例通过在源漏区与 衬底间淀积二氧化锗 (Ge02)和金属氧化物双层介质薄膜来减弱费米能级钉扎效应，降 低电子势垒， 改善锗基肖特基 MOS晶体管的性能。
下面简述本发明实施例的锗基肖特基 MOS晶体管的一种制备方法，步骤如下：
1—1) 在锗基衬底上制作 MOS结构；
1-2) 淀积源漏区域的 Ge02和金属氧化物薄层；
1-3) 溅射低功函数金属薄膜， 刻蚀形成金属源漏；
1— 4) 形成接触孔、 金属连线。
步骤 1一 1) 具体包括：
2— 1)在衬底上制作隔离区；
2— 2)淀积栅介质层以及栅；
2— 3)形成栅结构；
2— 4)形成侧墙结构。
所述步骤 1一 1 )的锗基衬底包括体锗衬底、锗覆绝缘衬底 (GOI)或外延锗衬底等。 所述步骤 1一 2) 的金属氧化物采用低氧原子面密度的材料， 要求此介质材料氧 原子面密度与 Ge02氧原子面密度比小于 0.8， 如氧化锶 (SrO)、 氧化钡 (BaO)、 氧化镭 (RaO)等。
所述步骤 1一 3 ) 的金属薄膜为铝膜或其他低功函数金属膜。
与现有技术相比， 本发明实施例的有益效果是：
此方法可以减弱费米能级钉扎效应， 降低电子势垒，进而改善锗基肖特基 MOS 器件的性能。 首先， 在 Ge02上淀积一薄层金属氧化物， 由于金属氧化物界面处的氧 原子面密度比 Ge02的低， Ge02界面处的氧原子向金属氧化物界面一侧移动， 导致在 界面处产生由 Ge02指向金属氧化物方向的偶极子， 而偶极子产生的电场有助于肖特 基电子势垒的调节； 其次， 在众多介质中， Ge02能与 Ge衬底形成较好的界面接触， 有效钝化锗表面的悬挂键， 降低界面态密度； 再者， 在金属源漏与衬底之间的金属氧 化物和 Ge02， 可以阻挡金属或金属锗化物在锗禁带中产生金属诱导带隙态（MIGS), 从而达到进一步减弱费米能级钉扎效应、 调节肖特基势垒高度的目的。
一般金属氧化物与 Ge02界面处的氧原子面密度比越小， 产生的偶极子越强， 势 垒调节越显著。而金属氧化物的氧原子面密度与金属阳离子的半径有关： 金属阳离子 半径越大， 氧原子面密度越小。 本发明实施例采用的氧化锶 (SrO)、 氧化钡 (BaO)、 氧 化镭 (RaO)等材料的金属离子半径都大于 Ι.ΐΑ, 与 Ge02界面处的氧原子面密度比小 于 0.8， 进而产生较强的偶极子调节肖特基势垒。 与采用单层绝缘介质材料如氧化铝 (A1203) 等相比， 本实施方案能更有效地调节肖特基势垒， 提升器件性能。 附图说明
图 1 (a)—图 1 (j ) 为本发明实施例提出的制备锗基肖特基晶体管的流程图。 图中： 1 衬底； 2— P阱区域； 3—隔离区； 4 栅极介质层； 5—金属栅； 6—侧 墙结构； 7— Ge02薄层； 8—绝缘氧化物薄膜； 9一金属源漏； 10 金属连线层。 具体实施方式 下面结合附图和具体实施方式对本发明实施例作进一步详细描述：
图 1为本发明一优选实施例制作锗基肖特基晶体管的方法流程图。本发明的此优 选实施例制作锗基肖特基晶体管的方法包括如下步骤：
步骤 1 : 提供一块锗基衬底。 如图 1 (a)所示， 一块 N型半导体锗衬底 1， 其中 衬底 1可采用体锗、 锗覆绝缘 （G0I) 或外延锗衬底等。
步骤 2: 制作 P阱区域。 在锗衬底上淀积氧化硅和氮化硅层， 首先通过光刻定义 P阱区域并反应离子刻蚀掉 P阱区域的氮化硅， 然后离子注入 P型杂质如硼等， 再退 火驱入制作 P阱 2， 最后去掉注入掩蔽层， 完成后如图 1 (b) 所示。
步骤 3 : 实现沟槽隔离。 如图 1 (c) 中隔离区 3， 首先在锗片上淀积氧化硅和氮 化硅层，然后通过光刻定义并利用反应离子刻蚀技术刻蚀氮化硅、氧化硅以及锗形成 沟槽， 再利用化学气相淀积（CVD)方法淀积氧化硅回填隔离槽， 最后采用化学机械 抛光技术（CMP)将表面磨平，实现器件间的隔离。器件隔离不局限于浅槽隔离（STI)， 也可以采用场氧隔离等技术。
步骤 4: 在所述有源区上形成栅极介质层。 栅介质层可以采用高 K介质、 二氧化 锗、 氮氧化锗等材料。 在淀积栅介质之前， 一般需要用 PH3、 H3以及 F等离子体等 进行表面钝化处理， 或淀积一层界面层如硅 (Si)、 氮化铝 (A1N；)、 氧化钇 (Y203)等。 本 优选实施例先在锗衬底上制作一薄层氧化钇 (Υ203)作为界面层， 然后采用原子层淀积 (ALD) 方法得到氧化铪 (Hf02) 栅介质层 4， 如图 1 (d) 所示。
步骤 5 : 在所述栅极介质层上形成栅极。 栅可以采用多晶硅栅、 金属栅、 FUSI 栅或全锗化物栅等， 本实施例采用淀积氮化钛 （TiN) 制备金属栅， 然后光刻定义并 刻蚀形成栅结构， 如图 1 (e) 所示。
步骤 6: 在栅极两侧制备侧墙。 可以通过淀积 Si02或 Si3N4并刻蚀的方式制备侧 墙， 也可依次淀积 Si3N4和 Si02形成双侧墙结构。 如图 1 (0所示， 本实施例采用淀 积 Si02并采用干法刻蚀的方法， 在栅的两侧形成侧墙结构 6
步骤 7: 形成源漏区域的 Ge02薄层。 此薄层可以通过 ALD、 射频溅射、 热氧化 和臭氧氧化等方式获得。 此处优选 ALD淀积方式， Ge02厚度约为 0.5~4 如图 1 (g) 所示。
步骤 8: 淀积源漏区域的金属氧化物薄膜。 要求此介质材料界面氧原子密度与 Ge02界面氧原子密度比小于 0.8， 如氧化锶 (SrO；)、 氧化钡 (BaO；)、 氧化镭 (RaO)等， 本实施优选例采用氧化锶 (SrO)。 此层材料同样可以通过 ALD淀积的方式得到， 其厚 度约为 0.5~4nm， 如图 1 (h) 所示。
步骤 9: 制备金属源漏。 可以采用物理气相淀积方式如蒸镀或溅射， 在半导体衬 底上淀积一层低功函数金属薄膜如铝 (Al)、 钛 (Ti)、 钇 (Y)等。 本优选实施例为铝， 其 厚度范围在 100ηιη~1μιη， 通过光刻定义并刻蚀得到金属源漏， 如图 1 (i) 所示。
步骤 10: 形成接触孔、 金属连线。 首先用 CVD淀积氧化层， 光刻定义出开孔位 置并刻蚀二氧化硅形成接触孔； 然后溅射金属层如 Al Al-Ti等， 再光刻定义出连线 图形并刻蚀形成金属连线图形， 最后进行金属化处理， 获得金属连线层 10， 如图 1 (j) 所示。
本发明实施例提出了一种锗基 MOS器件结构及其制备方法。 此方法不但可以 降低锗基肖特基 MOS源漏处电子的势垒高度， 提升锗基肖特基 MOS晶体管的性 能， 而且制备工艺简单并与硅 CMOS技术完全兼容。 与现有技术相比， 所述半导体 器件结构及其制备方法能简单有效地提升锗基肖特基 MOS晶体管的性能。 以上通过优选实施例详细描述了本发明， 本领域的技术人员应当理解， 以上所述 仅为本发明的优选实施例，在不脱离本发明实质的范围内，可以对本发明的器件结构 做一定的变形或修改，例如源漏结构也可采用提升、凹陷源漏结构或其他新结构如双 栅、 FinFET Ω栅、 三栅和围栅等； 其制备方法也不限于实施例中所公开的内容， 凡 依本发明权利要求所做的均等变化与修饰， 皆应属本发明的涵盖范围。

Claims

权 利 要 求
1、 一种锗基肖特基 MOS晶体管， 其特征在于， 在衬底与源、 漏区之间淀 积二氧化锗层和金属氧化物层， 具体为： 在衬底上淀积一层二氧化锗， 在二氧化 锗层上淀积一层金属氧化物， 金属源、 漏位于金属氧化物层上。
2、 如权利要求 1所述的锗基肖特基 MOS晶体管， 其特征在于， 所述二氧 化锗层的厚度范围为 0.5~4匪。
3、 如权利要求 1所述的锗基肖特基 MOS晶体管， 其特征在于， 所述金属 氧化物界面氧原子密度与 Ge02界面氧原子密度比小于 0.8。
4、 如权利要求 1所述的锗基肖特基 MOS晶体管， 其特征在于， 所述金属 氧化物层的厚度范围为 0.5~4nm。
5、 如权利要求 3所述的锗基肖特基 MOS晶体管， 其特征在于， 所述金属 氧化物选自氧化锶、 氧化钡或氧化镭。
6、 一种锗基肖特基 MOS晶体管的制备方法， 步骤如下：
1—1) 在锗基衬底上制作 MOS结构；
1-2) 淀积源、 漏区域的 Ge02和金属氧化物层；
1-3) 溅射低功函数金属薄膜， 刻蚀形成金属源、 漏；
1— 4) 形成接触孔、 金属连线。
7、 如权利要求 6所述的方法， 其特征在于， 步骤 1一 1) 具体包括：
2— 1) 在衬底上制作隔离区；
2—2) 淀积栅介质层以及栅；
2—3) 形成栅结构；
2—4) 形成侧墙结构。
8、 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 1 ) 的锗基衬底包 括体锗衬底、 锗覆绝缘衬底或外延锗衬底。
9、 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 2) 金属氧化物材 料的界面氧原子密度与 Ge02界面氧原子密度比小于 0.8， 优选氧化锶、 氧化钡 或氧化镭。
10、 如权利要求 6所述的方法， 其特征在于， 所述步骤 1一 3 ) 的金属薄膜 为铝膜或其他低功函数金属膜。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
CN102227001B (zh) * 2011-06-23 2013-03-06 北京大学 一种锗基nmos器件及其制备方法
CN103137460B (zh) * 2011-11-23 2016-02-10 中国科学院微电子研究所 一种分子尺度界面SiO2的形成和控制方法
CN107578994B (zh) 2011-11-23 2020-10-30 阿科恩科技公司 通过插入界面原子单层改进与iv族半导体的金属接触
CN102655112B (zh) 2012-04-18 2014-08-06 北京大学 实现锗基mos器件有源区之间隔离的方法
CN102881562A (zh) * 2012-10-11 2013-01-16 北京大学 一种锗基衬底的表面钝化方法
CN102903625B (zh) * 2012-10-18 2015-11-04 北京大学 锗基衬底表面钝化方法
KR20140121617A (ko) * 2013-04-08 2014-10-16 삼성전자주식회사 반도체 장치 및 그 제조 방법
JP6133991B2 (ja) * 2013-08-30 2017-05-24 国立研究開発法人科学技術振興機構 ゲルマニウム層上に酸化ゲルマニウムを含む膜を備える半導体構造およびその製造方法
CN103646865A (zh) * 2013-12-25 2014-03-19 中国科学院微电子研究所 在Ge衬底制备超薄氧化锗界面修复层的方法
US9449885B1 (en) 2015-06-19 2016-09-20 International Business Machines Corporation High germanium content FinFET devices having the same contact material for nFET and pFET devices
CN105336694B (zh) * 2015-10-13 2018-03-30 北京大学 一种锗基cmos的制备方法
US10068981B2 (en) * 2016-03-02 2018-09-04 Lam Research Corporation Rare earth metal surface-activated plasma doping on semiconductor substrates
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
DE112017005855T5 (de) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe
US10797137B2 (en) 2017-06-30 2020-10-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for reducing Schottky barrier height and semiconductor device with reduced Schottky barrier height
US11133226B2 (en) 2018-10-22 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. FUSI gated device formation
CN111463133B (zh) * 2020-04-17 2023-01-17 中国科学院微电子研究所 Ge基NMOS晶体管及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017705A (ja) * 2001-06-29 2003-01-17 Toshiba Corp 電界効果トランジスタ及び半導体装置の製造方法
EP1763084A2 (en) * 2005-09-09 2007-03-14 Fujitsu Limited Field-effect transistor and method for fabricating the same
CN101866953A (zh) * 2010-05-26 2010-10-20 清华大学 低肖特基势垒半导体结构及其形成方法
CN102227001A (zh) * 2011-06-23 2011-10-26 北京大学 一种锗基nmos器件及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
US6782610B1 (en) * 1999-05-21 2004-08-31 North Corporation Method for fabricating a wiring substrate by electroplating a wiring film on a metal base
US6833556B2 (en) * 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP2005026563A (ja) * 2003-07-04 2005-01-27 Renesas Technology Corp 半導体装置
CN1886826A (zh) * 2003-10-22 2006-12-27 斯平内克半导体股份有限公司 动态肖特基势垒mosfet器件及其制造方法
US7598134B2 (en) * 2004-07-28 2009-10-06 Micron Technology, Inc. Memory device forming methods
US7700452B2 (en) * 2007-08-29 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel transistor
FR2921750B1 (fr) * 2007-10-02 2014-07-25 Commissariat Energie Atomique Formation selective d'un compose comprenant un materiau semi-conducteur et un materiau metallique dans un substrat, a travers une couche d'oxyde de germanium
KR101527535B1 (ko) * 2008-10-21 2015-06-10 삼성전자주식회사 반도체 소자의 형성 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017705A (ja) * 2001-06-29 2003-01-17 Toshiba Corp 電界効果トランジスタ及び半導体装置の製造方法
EP1763084A2 (en) * 2005-09-09 2007-03-14 Fujitsu Limited Field-effect transistor and method for fabricating the same
CN101866953A (zh) * 2010-05-26 2010-10-20 清华大学 低肖特基势垒半导体结构及其形成方法
CN102227001A (zh) * 2011-06-23 2011-10-26 北京大学 一种锗基nmos器件及其制备方法

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