WO2012162934A1 - 阱区的形成方法和半导体基底 - Google Patents

阱区的形成方法和半导体基底 Download PDF

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Publication number
WO2012162934A1
WO2012162934A1 PCT/CN2011/077634 CN2011077634W WO2012162934A1 WO 2012162934 A1 WO2012162934 A1 WO 2012162934A1 CN 2011077634 W CN2011077634 W CN 2011077634W WO 2012162934 A1 WO2012162934 A1 WO 2012162934A1
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Prior art keywords
region
well region
semiconductor
forming
isolation structure
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Ceased
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PCT/CN2011/077634
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN2011900000552U priority Critical patent/CN202513135U/zh
Priority to US13/381,636 priority patent/US8815698B2/en
Publication of WO2012162934A1 publication Critical patent/WO2012162934A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a method of forming a well region and a semiconductor substrate. Background technique
  • a semiconductor substrate 100 is provided.
  • the semiconductor substrate 100 includes: a first isolation structure 111 and a second isolation.
  • the structure 112, the third isolation structure 113, the fourth isolation structure 114, and the fifth isolation structure 115 are used to isolate the active region.
  • a photoresist 120 is formed on the semiconductor substrate 100 outside the active region between the second isolation structure 112 and the third isolation structure 113.
  • doping ion 140 implantation is performed. Referring to FIG.
  • a first well region 151 is formed in an active region between the second isolation structure 112 and the third isolation structure 113.
  • the depth of the first well region 151 is generally greater than that of the isolation structure. depth.
  • the size of isolation structures continues to decrease. Therefore, in the process of forming the first well region 151, due to the small size of the isolation structure, partial doping ions may undergo lateral scattering, that is, partially doped ions may pass through the second isolation structure 112 and the third isolation.
  • a first excess doped region 161 is formed in the upper middle portion, and a second excess doped region 162 is also formed in the upper middle portion of the third isolation structure 113 toward the side of the fourth isolation structure 114, and the first excess doped region 161
  • the doping type of the second excess doping region 162 is the same as the doping type of the first well region 151.
  • the photoresist 120 is removed to obtain a semiconductor device including a first well region 151, a first excess doped region 161, and a second excess doped region 162.
  • the same method can be used in the active region between the first isolation structure 111 and the second isolation structure 112, the active region between the third isolation structure 113 and the fourth isolation structure 114, A second well region 152 is simultaneously formed in the active region between the four isolation structures 114 and the fifth isolation structure 115.
  • a third excess doping region 163 is also generated in the upper middle portion of the side of the second isolation structure 112 toward the third isolation structure 113, and the third isolation structure 113 is formed in the third isolation structure 113.
  • a fourth excess doped region 164 is formed in a middle upper portion of a side facing the second isolation structure 112, and a fifth excess doped region 165 is formed in a middle upper portion of a side of the fourth isolation structure 114 toward the third isolation structure 113, A sixth excess doped region 166 is generated in a middle upper portion of the fourth isolation structure 114 toward a side of the fifth isolation structure 115, and the third excess doping region 163, the fourth redundant doping region 164, and the fifth plurality
  • the doping type of the remaining doped region 165 and the sixth redundant doping region 166 is the same as the doping type of the second well region 152.
  • the doping types of the first well region 151 and the second well region 152 are different.
  • the first well region 151 is N-type ion doped
  • the second well region 152 is P-type ion doped
  • the first excess doped region 161 and the second redundant doped region 162 are N-type ion doped
  • the third super-doped region 163, the fourth super-doped region 164, the fifth super-doped region 165, and the sixth super-doped region 166 are P-type ion doped.
  • the fifth excess doped region 165 does not substantially affect the threshold voltage of the semiconductor device between the third isolation structure 113 and the fourth isolation structure 114, and the sixth excess doping region 166 is substantially not The threshold voltage of the semiconductor device between the fourth isolation structure 114 and the fifth isolation structure 115 is affected.
  • the threshold voltage of the semiconductor device between the first isolation structure 111 and the second isolation structure 112 may vary. Also, since the doping type of the third super-doped region 163 is different from that of the first well region 151, and the doping type of the fourth super-doped region 164 is different from that of the first well region 151, the second isolation structure 112 The doping type of the third isolation 162 and the second isolation region 152 are different, and thus the threshold voltage of the semiconductor device between the third isolation structure 113 and the fourth isolation structure 114 also changes. The change in threshold voltage is bound to affect the performance of the semiconductor device.
  • the problem to be solved by the present invention is to provide a method of forming a well region and a semiconductor substrate which removes dopant ions which are laterally diffused through the isolation structure, thereby ensuring stabilization of the threshold voltage of the semiconductor device.
  • the present invention provides a method for forming a well region, including:
  • Selecting at least one of the active regions to form a first well region in the selected active region is covered with a mask, and the remaining active regions are etched to form a recess; a semiconductor material is epitaxially grown to fill the recess.
  • the method of forming the well region further includes: forming a second well region in the semiconductor material, wherein the second well region and the first well region doping type are different.
  • the semiconductor substrate material and the semiconductor material are both Si, SiGe, SiC or
  • the depth of the groove is less than or equal to the depth of the isolation structure.
  • the present invention also provides a method for forming a well region, including:
  • the etching the active region comprises: forming a mask on a portion of the active regions, etching the remaining active regions.
  • the well region formed in the active region includes a first well region and a second well region,
  • the doping types of the first well region and the second well region are different.
  • the semiconductor substrate material and the semiconductor material are both Si, SiGe, SiC or
  • the depth of the groove is less than or equal to the depth of the isolation structure.
  • the present invention also provides a semiconductor substrate, including:
  • the semiconductor substrate includes an isolation structure to isolate at least two active regions; a modified semiconductor region, the modified semiconductor region being embedded in at least a portion of the active region, the modified semiconductor region material Unlike the semiconductor substrate material, and the upper surface of the modified semiconductor region is at least flush with the upper surface of the active region.
  • a lower surface of the modified semiconductor region is higher than a lower surface of the isolation structure.
  • the semiconductor substrate material is Si, SiGe, SiC or Ge.
  • the modified semiconductor region material is Si, SiGe, SiC or Ge.
  • the present invention has the following advantages:
  • An embodiment of the present invention after forming a well region in an active region, covering the active region with a mask, removing a semiconductor substrate including excess doped regions, and re-growing a semiconductor containing no excess doped regions At the bottom of the village, the phenomenon that the threshold voltage of the semiconductor device changes due to the excess doped region is avoided, and the threshold voltage of the semiconductor device is stabilized.
  • Another embodiment of the present invention removes a semiconductor substrate including excess doped regions after forming a well region in the active region without damaging the well region, and then regrown without excessive doping
  • the semiconductor substrate of the impurity region avoids the phenomenon that the threshold voltage of the semiconductor device changes due to the excess doped region, and the threshold voltage of the semiconductor device is stabilized.
  • the present invention also provides a semiconductor substrate comprising a semiconductor substrate and a modified semiconductor region of different doping types, wherein the number of excess doped regions is reduced or removed in the semiconductor substrate, thereby ensuring subsequent preparation
  • the threshold voltage of the semiconductor device is stable.
  • FIG. 6 are schematic diagrams showing the structure of a semiconductor device fabricated in the prior art
  • FIG. 7 is a schematic flow chart of a method for forming a well region according to Embodiment 1 of the present invention.
  • FIG. 8 to FIG. 16 are cross-sectional views showing an intermediate structure of a method of forming a well region according to a first embodiment of the present invention.
  • FIG. 17 is a schematic flow chart of a method for forming a well region according to Embodiment 2 of the present invention.
  • 18 to 22 are cross-sectional views showing an intermediate structure of a method of forming a well region according to a second embodiment of the present invention.
  • FIG. 23 is a schematic structural view of a semiconductor substrate according to Embodiment 3 of the present invention. detailed description
  • the present invention provides a method for forming two well regions, one is to cover the active region with a mask after forming a well region in the active region, and to include excess doping outside the active region.
  • the semiconductor substrate of the impurity region is removed, and then the semiconductor substrate without excess doped regions is re-grown; the other is that after the well region is formed in the active region, all or part of the well is not destroyed under the premature destruction of the well region.
  • the present invention also provides a semiconductor substrate comprising a semiconductor substrate having different doping types and a modified semiconductor region, wherein the number of excess doped regions is reduced or removed in the semiconductor substrate, The threshold voltage of the semiconductor device to be subsequently prepared is stabilized.
  • the method for forming the well region includes: S11, forming an isolation region in a semiconductor substrate to isolate the active region;
  • S12 selecting at least one of the active regions, forming a first well region in the selected active region; 513, covering the selected active region with a mask, etching the remaining active regions to form a recess;
  • step S11 is performed to form an isolation region on the semiconductor substrate 200 to isolate the active region.
  • the material of the semiconductor substrate 200 may be a silicon substrate (Si), a silicon-based substrate (SiGe), a silicon carbide substrate (SiC), or a germanium (Ge).
  • the isolation region is defined by an isolation structure, which may be a shallow trench isolation structure or a partial silicon oxide isolation structure.
  • the number of the isolation structures may be any integer greater than or equal to two.
  • the specific preparation method of the isolation structure is well known to those skilled in the art and will not be described herein.
  • the isolation structure in the embodiment includes five shallow trench isolation structures, respectively: a first shallow trench isolation structure 211, a second shallow trench isolation structure 212, and a third shallow trench isolation structure. 213.
  • the first shallow trench isolation structure 211 and the second shallow trench isolation structure are used to isolate the first active region
  • the second shallow trench isolation structure 212 and the third shallow trench isolation structure 213 are used to isolate the second
  • the source region, the third shallow trench isolation structure 213 and the fourth shallow trench isolation structure 214 are used to isolate the third active region
  • the fourth shallow trench isolation structure 214 and the fifth shallow trench isolation structure 215 are used for isolation.
  • step S12 at least one of the active regions is selected, and a first well region is formed in the selected active region.
  • the first active region, the third active region, and the fourth active region are selected. It should be noted that, in other embodiments of the present invention, there may be other different options, such as: selecting one active region, two active regions, or all active regions, and the like.
  • a photoresist 220 is formed on the unselected second active region, as shown in FIG.
  • the photoresist 220 may cover the second active region, all or part of the second shallow trench isolation structure 212 and/or all or part of the third shallow trench isolation structure 213, the photoresist 220 It is also possible to cover only the second active region as long as the photoresist 220 does not cover the selected active region.
  • doping ion 240 implantation is performed, as shown in FIG. Wherein, when the doping type of the first well region is P-type, the doping ions 240 may be In ions, IB ions or BF 2 ions; when the doping type of the first well region is N-type, The dopant ions 240 may be As ions, P ions or Sb ions.
  • the photoresist 220 is removed, and a first well region 251 is formed in each of the selected first active region, the third active region, and the fourth active region. See Figure 11.
  • the present embodiment forms the first excess doping region in the middle portion of the second isolation structure 212 toward the third isolation structure 213 while forming the first well region 251. 261.
  • excess doped regions may also appear on the sidewalls of the third isolation structure 213, the fourth isolation structure 214, and the second isolation structure 212, not shown in FIG.
  • step S13 is performed to cover the selected first active region, the third active region, and the fourth with a mask.
  • the source region etches the remaining second active region to form a recess.
  • a mask 270 is first formed on the first active region, the third active region, and the fourth active region.
  • the mask 270 can be obtained by any conventional vacuum coating technique.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • silicon nitride (Si 3 N 4 ) is formed by a low pressure chemical vapor deposition (LPCVD) process under high temperature (about 750 degrees Celsius) via ammonia gas and two-way silane.
  • the mask 270 may cover part or all of the first shallow trench isolation structure 211, part or all of the second shallow trench isolation structure 212 while completely covering the selected three active regions. Some or all of the third shallow trench isolation structure 213, some or all of the shallow trench isolation structure 214, some or all of the isolation structure 215, but the mask 270 cannot cover the unselected active regions.
  • a second active region of the mask 270 is not selectively etched to form a recess 280.
  • the selective etching in the embodiment may adopt a selective plasma etching method, which is well known to those skilled in the art, and thus will not be described herein.
  • the depth of the recess 280 should be greater than or equal to the first plurality The depth of the remaining doped region 261 or the second excess doped region 262.
  • the depth of the recess 280 should also be less than or equal to the depth of the shallow trench isolation structure, as shown in FIG. Since the upper surface of the well region is generally higher than the lower surface of the isolation structure, the lower surface of the excess doped region is lower than the upper surface of the well region a face, thus ensuring that the depth of the groove 280 is less than or equal to the depth of the isolation structure and greater than or equal to the depth of the first excess doped region 261 or the second excess doped region 262, the groove 280
  • the lower surface may be higher than the upper surface of the first well region 251, and may be equal to the upper surface of the first well region 251, and may also be lower than the upper surface of the first well region 251.
  • step S14 is performed. As shown in FIG. 14, the semiconductor material 290 is epitaxially grown to fill the recess 280 to form a modified semiconductor region.
  • the epitaxially grown semiconductor material 290 may be Si, SiGe, SiC or Ge.
  • the material of the conductor base 200 is different.
  • the epitaxial growth method is a selective epitaxial growth method in which the semiconductor material 290 is grown only in the recess 280. This technique is well known to those skilled in the art and will not be described herein.
  • the upper surface of the semiconductor material 290 in the recess 280 is separated from the shallow trench.
  • the upper surface is flush, such that a modified semiconductor region filled with semiconductor material 290 is formed within recess 208.
  • the flush can be either exactly in the same horizontal plane in the strict sense, or there can be errors within the allowable range of the process parameters.
  • the present embodiment may further form a second well region 252 in the semiconductor material 290, that is, a second well region 252 is formed in the remaining second active region.
  • the second well region 252 and the first well region 251 are of different types, that is, when the first well region 251 is N-type, the second well region 252 is P-type; when the first well region 251 is In the P-type, the second well region 252 is N-type.
  • the preparation method of the second well region is specifically referred to step S12, and details are not described herein again.
  • the first excess doped region 261 and the second excess doped region 262 different in doping type from the second well region 252 are removed, thereby being in the second well.
  • the threshold voltage of the semiconductor device formed on the region 252 is not affected by the lateral diffusion of the dopant ions, ensuring the stability of its performance.
  • FIG. 17 is a schematic flow chart showing a method of forming a well region according to the embodiment, and the method for forming the well region includes:
  • step S21 in the embodiment is the same as the step S11 in the first embodiment, and the step S24 is the same as the step S14 in the first embodiment.
  • the difference between the embodiment and the first embodiment is only the step S22 and the step S23. S23 will be described in detail.
  • step S21 is performed. Referring to Fig. 18, the present embodiment forms five shallow trench isolation structures on the semiconductor substrate 310 to isolate the four active regions.
  • Step S21 in this embodiment is the same as step S11 in the first embodiment, and finally forms the first shallow trench isolation.
  • the first shallow trench isolation structure 311 and the second shallow trench isolation structure 312 are used to isolate the first active region
  • the second shallow trench isolation structure 312 and the third shallow trench isolation structure 313 are used to isolate the second.
  • the active region, the third shallow trench isolation structure 313 and the fourth shallow trench isolation structure 314 are used to isolate the third active region
  • the fourth shallow trench isolation structure 314 and the fifth shallow trench isolation structure are used for isolation Four active areas.
  • step S22 is performed. Referring to FIG.
  • a first well region 351 is formed in the first active region and the third active region, and a second well region is formed in the second active region and the fourth active region. 352, the doping types of the first well region 351 and the second well region 352 are different.
  • the first well region 351 or the second well region 352 may be formed in all active regions; A first well region 351 is formed in one active region, and a second well region 352 is formed in the remaining active region, depending on the requirements for subsequent formation of the semiconductor device.
  • the specific forming method of the first well region 351 and the second well region 352 is the same as that of the first embodiment, and details are not described herein again.
  • the depth of the first well region and the depth of the second well region may or may not be equal.
  • the depth of the well region refers to the vertical distance between the upper surface of the well region and the upper surface of the shallow trench isolation structure.
  • the present embodiment also faces the first shallow trench isolation structure 312 in the process of forming the first well region 351 and the second well region 352.
  • the trench isolation structure 311—the upper middle portion of the side forms a first excess doping region 361, and the second shallow trench isolation structure 312 forms a second excess doping toward the upper middle portion of the third shallow trench isolation structure 313—the side
  • the region 362 is in the middle of the third shallow trench isolation structure 313 facing the second shallow trench isolation structure 312
  • a third excess doped region 363 is formed on the upper portion
  • a fourth excess doped region 364 is formed on the upper portion of the third shallow trench isolation structure 313 toward the fourth shallow trench isolation structure 314 - in the fourth shallow trench
  • the isolation structure 314 forms a fifth excess doped region 365 toward the middle upper portion of the third shallow trench isolation structure 313, and the fourth shallow trench isolation structure 314 faces the upper portion of the fifth shallow trench isolation structure 315.
  • Forming a sixth excess doped region 366, and doping types of the first redundant doped region 361, the fourth redundant doped region 364, and the fifth redundant doped region 365 are doped with the second well region 352
  • the types of the second excess doped region 362, the third redundant doped region 363, and the sixth redundant doped region 366 are the same as those of the first well region 351.
  • Step S23 is performed to etch each of the active regions to form a first recess 371, a second recess 372, a third recess 373, and a fourth recess 374, as shown in FIG.
  • the depth of the groove is less than or equal to the depth of its corresponding well region.
  • the depth of the W-groove refers to the vertical distance between the upper surface of the trench and the upper surface of the shallow trench isolation structure.
  • the depth of each groove is less than or equal to the depth of its corresponding well region.
  • the specific etching method of each groove is the same as that in the first embodiment, and details are not described herein again.
  • the depth of the groove is less than or equal to the depth of the shallow trench isolation structure, as shown in FIG. 20 .
  • step S24 is performed. Referring to Fig.
  • a semiconductor material 390 is epitaxially grown to fill each of the trenches to form a modified semiconductor region.
  • the semiconductor material 390 may be further planarized.
  • the epitaxially grown semiconductor material 390 may be Si, SiGe, SiC or Ge.
  • the semiconductor material 390 may be the same material as the semiconductor substrate 300 or may be different from the material of the semiconductor substrate 300.
  • the steps of planarizing the semiconductor material 390 in the trenches in this embodiment are the same as those in the first embodiment, and are not described herein again.
  • the semiconductor substrate including all the unnecessary doped regions is uniformly etched without using a mask, and the etching does not damage the formed
  • the well region structure is then epitaxially grown to obtain a semiconductor substrate including a well region but not including an excess doped region.
  • all of the semiconductor devices are not affected by the lateral diffusion of the dopant ions. Therefore, the present implementation method is more compact, lower in cost, and can ensure the stability of the threshold voltage of all semiconductor devices.
  • a mask may be formed on a portion of the well region to selectively etch the remaining well region to form a recess.
  • the embodiment provides a semiconductor substrate, including: a semiconductor substrate 400, the semiconductor substrate 400 includes an isolation structure to isolate the active region;
  • the material of the semiconductor substrate 400 in this embodiment may be Si, SiGe, SiC or Ge.
  • the semiconductor substrate includes a first isolation structure 411, a second isolation structure 412, a third isolation structure 413, and a fourth isolation structure 414,
  • the first active region 431, the second active region 432, and the third active region 433 are isolated, and each of the isolation structures is a shallow trench isolation structure.
  • the number of the isolation structures may be any integer of 2 or more, and the isolation structure may also be other isolation structures, such as a partial silicon oxide isolation structure.
  • a portion of the active region may further include a first well region (not shown), and the remaining active region may further include a second well region (not shown).
  • the doping types of the first well region and the second well region are different, and upper surfaces of the first well region and the second well region are lower or flush with the lower surface of the modified semiconductor region 420 .
  • the material of the modified semiconductor region 420 in this embodiment may also be Si, SiGe, SiC or Ge, but the material of the modified semiconductor region 420 is different from the material of the semiconductor substrate 400, such as: When the material of 400 is Si, the material of the modified semiconductor region 420 may be SiGe, SiC or Ge, but the material of the modified semiconductor region 420 may not be Si.
  • the lower surface of the modified semiconductor region 420 is higher than the lower surface of each of the isolation structures, thereby avoiding damage to the well regions that have been formed between the isolation structures.
  • the modified semiconductor region 420 in this embodiment is embedded in all of the active regions. In other embodiments of the present invention, the modified semiconductor region 420 may be embedded only in a portion of the active region, and the remaining number of the active regions is still a semiconductor village different from the material of the modified semiconductor region 420. Bottom 400.
  • the upper surface of the modified semiconductor region 420 in this embodiment is flush with the upper surface of the active region. In other embodiments of the invention, the upper surface of the 420 modified semiconductor region may also be higher than the upper surface of the active region.
  • the semiconductor substrate described above can be specifically prepared by the method of Embodiment 1 or Embodiment 2, so that some or all of the excess doped regions are removed from the semiconductor substrate, and the stability of the threshold voltage of the corresponding semiconductor device is ensured.

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Abstract

一种半导体技术领域的阱区的形成方法和半导体基底，一种所述方法包括：在半导体衬底上形成隔离区，以隔离有源区；选定至少一个所述有源区，在选定的所述有源区内形成第一阱区；以掩模覆盖选定的所述有源区，刻蚀剩余的所述有源区，以形成凹槽；外延生长半导体材料，以填充所述凹槽。另一种所述方法包括：在半导体衬底内形成隔离区，以隔离有源区；在所述有源区内形成阱区；刻蚀所述有源区，以形成凹槽，所述凹槽的深度小于或等于所述阱区的深度；外延生长半导体材料，以填充所述凹槽。所述半导体基底，包括：材料不同的半导体衬底和修正半导体区。本发明去除了穿过隔离结构进行横向扩散的掺杂离子，保证了半导体器件的阈值电压稳定。

Description

阱区的形成方法和半导体基底
本申请要求于 2011 年 5 月 31 日提交中国专利局、 申请号为 201110144978.1、 发明名称为"阱区的形成方法和半导体基底"的中国专利申请 的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术领域， 特别涉及一种阱区的形成方法和半导体基 底。 背景技术
在半导体制造技术中， 形成阱区是必不可少的工艺。 下面结合附图说明现有技术中阱区的形成方法， 所述方法具体包括： 参见图 1所示， 提供半导体村底 100, 所述半导体村底 100包括： 第一隔离 结构 111、 第二隔离结构 112、 第三隔离结构 113、 第四隔离结构 114和第五隔离 结构 115 , 所述隔离结构用于隔离有源区。 参见图 2所示， 在所述第二隔离结构 112和所述第三隔离结构 113之间的有 源区之外的半导体村底 100上形成光刻胶 120。 参见图 3所示， 进行掺杂离子 140注入。 参见图 4所示， 在所述第二隔离结构 112和所述第三隔离结构 113之间的有 源区内形成第一阱区 151 , 第一阱区 151的深度一般大于所述隔离结构的深度。 然而随着半导体器件尺寸的不断减小， 隔离结构的尺寸也随之不断减小。 因此在形成第一阱区 151的过程中， 由于隔离结构的尺寸很小， 部分掺杂离子 会发生横向扩散（lateral scattering ) , 即部分掺杂离子会穿过第二隔离结构 112 和第三隔离结构 113 , 从而在第二隔离结构 112朝向第一隔离结构 111的一侧的 中上部产生第一多余掺杂区域 161 , 在第三隔离结构 113朝向第四隔离结构 114 的一侧的中上部也产生第二多余掺杂区域 162,且第一多余掺杂区域 161和第二 多余掺杂区域 162的掺杂类型与第一阱区 151的掺杂类型相同。
参见图 5所示， 去除所述光刻胶 120, 得到包括第一阱区 151、 第一多余掺 杂区域 161和第二多余掺杂区域 162的半导体器件。
参见图 6所示， 采用同样方法可在第一隔离结构 111和第二隔离结构 112之 间的有源区内、第三隔离结构 113和第四隔离结构 114之间的有源区内、第四隔 离结构 114和第五隔离结构 115之间的有源区内同时形成第二阱区 152。
类似地，在形成第二阱区 152的过程中， 同样会在第二隔离结构 112朝向第 三隔离结构 113的一侧的中上部产生第三多余掺杂区域 163、 在第三隔离结构 113朝向第二隔离结构 112的一侧的中上部产生第四多余掺杂区域 164、 在第四 隔离结构 114朝向第三隔离结构 113的一侧的中上部产生第五多余掺杂区域 165、 在第四隔离结构 114朝向第五隔离结构 115的一侧的中上部产生第六多余 掺杂区域 166, 且第三多余掺杂区域 163、 第四多余掺杂区域 164、 第五多余掺 杂区域 165和第六多余掺杂区域 166的掺杂类型与第二阱区 152的掺杂类型相 同。
所述第一阱区 151和所述第二阱区 152的掺杂类型不同。 如： 第一阱区 151 为 N型离子掺杂， 第二阱区 152为 P型离子掺杂， 则： 第一多余掺杂区域 161和 第二多余掺杂区域 162为 N型离子掺杂， 第三多余掺杂区域 163、第四多余掺杂 区域 164、 第五多余掺杂区域 165和第六多余掺杂区域 166为 P型离子掺杂。
由于第五多余掺杂区域 165、 第六多余掺杂区域 166和第二阱区 152的掺杂 类型相同，因此第五多余掺杂区域 165基本不会对第三隔离结构 113和第四隔离 结构 114之间的半导体器件的阈值电压产生影响，第六多余掺杂区域 166也基本 不会对第四隔离结构 114和第五隔离结构 115之间的半导体器件的阈值电压产 生影响。
但是由于第一多余掺杂区域 161与第二阱区 152的掺杂类型不同，因此第一 隔离结构 111和第二隔离结构 112之间的半导体器件的阈值电压会发生变化。同 样， 由于第三多余掺杂区域 163与第一阱区 151的掺杂类型不同，且第四多余掺 杂区域 164与第一阱区 151的掺杂类型不同， 因此第二隔离结构 112和第三隔离 162与第二阱区 152的掺杂类型不同，因此第三隔离结构 113和第四隔离结构 114 之间的半导体器件的阈值电压也会发生变化。阈值电压的变化势必影响半导体 器件的性能。
因此，如何在形成阱区的过程中， 减小掺杂离子的横向扩散引起的半导体 器件阈值电压变化就成为亟待解决的问题。 发明内容
本发明解决的问题是提供一种阱区的形成方法和半导体基底，去除穿过隔 离结构进行横向扩散的掺杂离子， 保证了半导体器件的阈值电压稳定。
为解决上述问题， 本发明提供了一种阱区的形成方法， 包括：
在半导体村底上形成隔离区， 以隔离有源区；
选定至少一个所述有源区， 在选定的所述有源区内形成第一阱区； 以掩模覆盖选定的所述有源区， 刻蚀剩余的所述有源区， 以形成凹槽； 外延生长半导体材料， 以填充所述凹槽。
可选地，所述阱区的形成方法还包括：在所述半导体材料中形成第二阱区 所述第二阱区和所述第一阱区掺杂类型不同。
可选地 ,
可选地， 所述半导体村底材料与所述半导体材料均为 Si、 SiGe、 SiC 或
Gec
可选地，在以隔离结构界定所述隔离区时， 所述凹槽的深度小于或等于所 述隔离结构的深度。
为解决上述问题， 本发明还提供了一种阱区的形成方法， 包括：
在半导体村底上形成隔离区， 以隔离有源区; 在所述有源区内形成阱区
刻蚀所述有源区， 以形成凹槽， 所述凹槽的深度小于或等于所述阱区的深
外延生长半导体材料， 以填充所述凹槽
可选地，所述刻蚀所述有源区包括：在部分数目的所述有源区上形成掩模, 刻蚀剩余的所述有源区。 可选地 ,
可选地， 所述在所述有源区内形成的阱区包括第一阱区和第二阱区， 所述 第一阱区和第二阱区的掺杂类型不同。
可选地， 所述半导体村底材料和所述半导体材料均为 Si、 SiGe、 SiC 或
Ge。
可选地，在以隔离结构界定所述隔离区时， 所述凹槽的深度小于或等于所 述隔离结构的深度。 为解决上述问题， 本发明还提供了一种半导体基底， 包括：
半导体村底， 所述半导体村底包括隔离结构， 以隔离至少两个有源区； 修正半导体区， 所述修正半导体区嵌于至少部分数目的所述有源区中， 所 述修正半导体区材料与所述半导体村底材料不同，且所述修正半导体区的上表 面至少与所述有源区的上表面齐平。
可选地， 所述修正半导体区的下表面高于所述隔离结构的下表面。 可选地， 所述半导体村底材料为 Si、 SiGe、 SiC或 Ge。
可选地， 所述修正半导体区材料为 Si、 SiGe、 SiC或 Ge。 与现有技术相比， 本发明具有以下优点：
1 )本发明一个实施例在有源区内形成阱区后， 采用掩模覆盖所述有源区， 将包括多余的掺杂区域半导体村底去除，进而重新生长不含多余掺杂区域的半 导体村底，从而避免了多余的掺杂区域引起的半导体器件阈值电压发生变化的 现象， 保证了半导体器件的阈值电压稳定。
2 )本发明另一个实施例在有源区内形成阱区后， 在不破坏所述阱区的前 提下，将包括多余的掺杂区域的半导体村底去除， 进而重新生长不包含多余掺 杂区域的半导体村底，从而避免了多余的掺杂区域引起的半导体器件阈值电压 发生变化的现象， 保证了半导体器件的阈值电压稳定。
3 )本发明还提供了一种半导体基底， 其包括掺杂类型不同的半导体村底 和修正半导体区， 该半导体基底中由于减少或去除了多余掺杂区域的数目， 因 此也能保证后续制备的半导体器件阈值电压的稳定。 附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1至图 6是现有技术制作半导体器件的结构示意图；
图 7是本发明实施例一提供的阱区的形成方法的流程示意图；
图 8至图 16是本发明实施例一提供的阱区的形成方法的中间结构的剖面 图；
图 17是本发明实施例二提供的阱区的形成方法的流程示意图；
图 18至图 22是本发明实施例二提供的阱区的形成方法的中间结构的剖面 图；
图 23是本发明实施例三提供的半导体基底的结构示意图。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。 在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明 还可以采用其他不同于在此描述的其它方式来实施，因此本发明不受下面公开 的具体实施例的限制。
正如背景技术部分所述，现有技术中随着半导体器件尺寸的不断减小， 包 括隔离结构的半导体器件在形成掺杂区的过程中，部分掺杂离子会穿过隔离结 构发生横向扩散， 最终影响了半导体器件的阈值电压。 针对上述缺陷， 本发明提供了两种阱区的形成方法， 一个是在有源区内形 成阱区后， 采用掩模覆盖所述有源区， 将所述有源区之外包括多余的掺杂区域 半导体村底去除， 进而重新生长不含多余掺杂区域的半导体村底； 另一个是在 有源区内形成阱区后，在不破坏所述阱区的前提下，将全部或部分阱区上包括 多余的掺杂区域的半导体村底去除，进而重新生长不包含多余掺杂区域的半导 体村底。上述两种方法都避免了多余的掺杂区域引起的半导体器件阈值电压发 生变化的现象， 保证了半导体器件的阈值电压稳定。 根据上述两种方法， 本发 明还得到了一种半导体基底，其包括掺杂类型不同的半导体村底和修正半导体 区， 该半导体基底中由于减少或去除了多余掺杂区域的数目， 因此也能保证后 续制备的半导体器件阈值电压的稳定。
下面结合附图进行详细说明。
实施例一
图 7示出了本实施例提供的阱区的形成方法的流程示意图， 所述阱区的形 成方法包括： S11 , 在半导体村底内形成隔离区， 以隔离有源区；
S12, 选定至少一个所述有源区， 在选定的所述有源区内形成第一阱区； 513, 以掩模覆盖选定的所述有源区， 刻蚀剩余的所述有源区， 以形成凹 槽；
514, 外延生长半导体材料， 以填充所述凹槽形成修正半导体区。 图 8至图 16示出了本实施例阱区的形成方法的中间结构的剖面图， 下面 结合图 7和图 8至图 16对本实施例进行详细描述。 结合图 7和图 8, 执行步骤 S11 , 在半导体村底 200上形成隔离区， 以隔 离有源区。
具体的，所述半导体村底 200的材料可以是硅村底（ Si )、错硅村底（ SiGe )、 碳化硅村底（SiC )或锗村底（Ge )等。
具体地， 所述隔离区由隔离结构界定， 所述隔离结构可以为浅沟槽隔离结 构或者局部氧化硅隔离结构。所述隔离结构的数目可以为大于或等于 2的任意 整数。所述隔离结构的具体制备方法对于本领域的技术人员是熟知的，在此不 再赘述。
为筒单起见，本实施例中所述隔离结构包括 5个浅沟槽隔离结构，分别为： 第一浅沟槽隔离结构 211、第二浅沟槽隔离结构 212、第三浅沟槽隔离结构 213、 第四浅沟槽隔离结构 214和第五浅沟槽隔离结构 215。 其中， 第一浅沟槽隔离 结构 211 和第二浅沟槽隔离结构用于隔离第一有源区， 第二浅沟槽隔离结构 212和第三浅沟槽隔离结构 213用于隔离第二有源区，第三浅沟槽隔离结构 213 和第四浅沟槽隔离结构 214 用于隔离第三有源区， 第四浅沟槽隔离结构 214 和第五浅沟槽隔离结构 215用于隔离第四有源区。 接着执行步骤 S12, 选定至少一个所述有源区， 在选定的所述有源区内形 成第一阱区。 本实施例中选定第一有源区、 第三有源区和第四有源区。 需要说明的是， 在本发明的其他实施例中， 还可以有其他不同的选择， 如： 选择一个有源区、 两个有源区或所有的有源区等。 首先， 在未选定的第二有源区上形成光刻胶 220, 参见图 9所示。 其中， 所述光刻胶 220可以覆盖第二有源区、 全部或部分的第二浅沟槽隔离结构 212 和 /或全部或部分的第三浅沟槽隔离结构 213,所述光刻胶 220也可以仅仅覆盖 第二有源区， 只要所述光刻胶 220不覆盖选定的有源区即可。 然后， 进行掺杂离子 240注入， 参见图 10所示。 其中， 当第一阱区的掺 杂类型为 P型时， 所述掺杂离子 240可以为 In离子、 IB离子或 BF2离子； 当所述 第一阱区的掺杂类型为 N型时， 所述掺杂离子 240可以为 As离子、 P离子或 Sb 离子。
在进行掺杂离子注入后，去除所述光刻胶 220,此时在选定的第一有源区、 第三有源区内和第四有源区内分别形成了第一阱区 251 , 参见图 11所示。 基 于与背景技术所描述相同的原因， 本实施例在形成第一阱区 251的同时，也会 在第二隔离结构 212朝向第三隔离结构 213—侧的中上部形成第一多余掺杂区 域 261、 在第三隔离结构 213朝向第二隔离结构 212—侧的中上部形成第二多 余掺杂区域 262, 具体参见图 11。 当然， 在第三隔离结构 213、 第四隔离结构 214和第二隔离结构 212的各侧壁上也会出现多余掺杂区域， 图 11中未示出。 接着执行步骤 S13, 以掩模覆盖选定的第一有源区、 第三有源区和第四有 源区， 刻蚀剩余的第二有源区， 以形成凹槽。 参见图 12所示， 首先在所述第一有源区、 第三有源区和第四有源区上形 成掩模 270。 其中， 所述掩模 270可以利用任何常规真空镀膜技术获得。 例如 原子层沉积（ALD )、 物理气相沉积（PVD )、 化学气相沉积（CVD )、 等离子 体增强型化学气相沉积 （PECVD ) 工艺。 本实施例中利用低压化学气相沉积 ( LPCVD ) 工艺， 在高温（约 750摄氏度）条件下， 经由氨气和二路硅烷反 应生成氮化硅（Si3N4 )。
需要说明的是， 所述掩模 270在完全覆盖选定的三个有源区的同时，还可 以覆盖部分或全部第一浅沟槽隔离结构 211、 部分或全部第二浅沟槽隔离结构 212、 部分或全部第三浅沟槽隔离结构 213、 部分或全部浅沟槽隔离结构 214、 部分或全部隔离结构 215, 但所述掩模 270不能覆盖未选定的有源区。
参见图 13所示， 选择性刻蚀未覆盖所述掩模 270的第二有源区， 以形成 凹槽 280。
本实施例中所述选择性刻蚀具体可采用选择性等离子刻蚀方法，该方法对 本领域的技术人员是熟知的，故在此不再赘述。为了在形成凹槽 280的过程中， 将所述第一多余掺杂区域 261和所述第二多余掺杂区域 262去除， 所述凹槽 280 的深度应该大于或等于所述第一多余掺杂区域 261 或第二多余掺杂区域 262的深度。
此外， 为了不破坏所述浅沟槽隔离结构， 所述凹槽 280的深度还应该小于 或等于所述浅沟槽隔离结构的深度， 具体参见图 13所示。 由于阱区的上表面 一般高于隔离结构的下表面，所述多余掺杂区域的下表面低于所述阱区的上表 面，因此在保证凹槽 280的深度小于或等于隔离结构深度且大于或等于所述第 一多余掺杂区域 261 或第二多余掺杂区域 262深度的情况下， 所述凹槽 280 的下表面可能高于所述第一阱区 251的上表面， 也可能等于所述第一阱区 251 的上表面， 还可能低于所述第一阱区 251的上表面。
接着执行步骤 S14, 参见图 14所示， 外延生长半导体材料 290, 以填充所 述凹槽 280形成修正半导体区。
其中， 外延生长的所述半导体材料 290可以为 Si、 SiGe、 SiC或 Ge。 所 导体村底 200的材料不相同。
所述外延生长方法为选择性外延生长方法， 即只在凹槽 280内生长半导体 材料 290, 该技术对于本领域的技术人员是熟知的， 在此不再赘述。
参见图 15所示， 之后， 本实施例还需要采用干法或湿法刻蚀以去除所述 方法 ), 使所述凹槽 280内的半导体材料 290的上表面与所述浅沟槽隔离结构 的上表面齐平，从而，在凹槽 208内形成了填满半导体材料 290的修正半导体 区。所述的齐平既可以是严格意义上的完全位于同一水平面，也可以存在工艺 参数允许范围内的误差。
进一步地， 参见图 16所示， 本实施例还可以在所述半导体材料 290中形 成第二阱区 252, 即在剩余的第二有源区内形成第二阱区 252。 所述第二阱区 252和所述第一阱区 251掺杂类型不同， 即当第一阱区 251为 N型时， 所述第 二阱区 252为 P型； 当第一阱区 251为 P型时， 所述第二阱区 252为 N型。 第二阱区的制备方法具体参考步骤 S12, 在此不再赘述。
至此完成第一阱区 251和第二阱区 252的制备。
本实施例在形成第一阱区 251的过程中，将与第二阱区 252掺杂类型不同 的第一多余掺杂区域 261和第二多余掺杂区域 262去除， 从而在第二阱区 252 上形成的半导体器件的阈值电压不会受到掺杂离子横向扩散的影响，保证了其 性能的稳定性。
实施例二
图 17示出了本实施例提供的阱区的形成方法的流程示意图，所述阱区的形 成方法包括：
S21 , 在半导体村底上形成隔离区， 以隔离有源区；
522, 在所述有源区内形成阱区；
523 , 刻蚀所述有源区， 以形成凹槽， 所述凹槽的深度小于或等于所述阱 区的深度；
524, 外延生长半导体材料， 以填充所述凹槽形成修正半导体区。
本实施例中步骤 S21与实施例一中步骤 S11相同， 步骤 S24与实施例一 中步骤 S14相同， 本实施例与实施例一的区别仅在于步骤 S22和步骤 S23 , 下 面主要对步骤 S22和步骤 S23进行详细说明。 首先执行步骤 S21 , 参见图 18所示， 本实施例在半导体村底 310上形成 五个浅沟槽隔离结构， 以隔离四个有源区。
本实施例中步骤 S21与实施例一中步骤 S11相同，最终形成第一浅沟槽隔 离结构 311、 第二浅沟槽隔离结构 312、 第三浅沟槽隔离结构 313、 第四浅沟 槽隔离结构 314和第五浅沟槽隔离结构 315。 其中， 第一浅沟槽隔离结构 311 和第二浅沟槽隔离结构 312 用于隔离第一有源区， 第二浅沟槽隔离结构 312 和第三浅沟槽隔离结构 313 用于隔离第二有源区， 第三浅沟槽隔离结构 313 和第四浅沟槽隔离结构 314 用于隔离第三有源区， 第四浅沟槽隔离结构 314 和第五浅沟槽隔离结构用于隔离第四有源区。 接着执行步骤 S22, 参见图 19所示， 在第一有源区和第三有源区内形成 第一阱区 351 , 且在第二有源区和第四有源区内形成第二阱区 352, 第一阱区 351和第二阱区 352的掺杂类型不同。 此处仅为举例， 在此不应限制本发明的 保护范围， 在本发明的其他实施例中， 可以在所有有源区内都形成第一阱区 351或第二阱区 352; 也可以只在一个有源区内形成第一阱区 351 , 在剩余有 源区内形成第二阱区 352, 具体情况根据后续形成半导体器件的要求而定。
其中， 所述第一阱区 351和第二阱区 352的具体形成方法同实施例一，在 此不再赘述。 第一阱区的深度和第二阱区的深度可以相等， 也可以不相等。 所 述阱区的深度是指阱区的上表面与所述浅沟槽隔离结构上表面之间的垂直距 离。
再次参见图 19, 基于与背景技术所描述相同的原因， 本实施例在形成第 一阱区 351和第二阱区 352的过程中，也会在第二浅沟槽隔离结构 312朝向第 一浅沟槽隔离结构 311—侧的中上部形成第一多余掺杂区域 361 , 在第二浅沟 槽隔离结构 312朝向第三浅沟槽隔离结构 313—侧的中上部形成第二多余掺杂 区域 362, 在第三浅沟槽隔离结构 313朝向第二浅沟槽隔离结构 312—侧的中 上部形成第三多余掺杂区域 363 , 在第三浅沟槽隔离结构 313朝向第四浅沟槽 隔离结构 314—侧的中上部形成第四多余掺杂区域 364 , 在第四浅沟槽隔离结 构 314 朝向第三浅沟槽隔离结构 313 —侧的中上部形成第五多余掺杂区域 365 , 在第四浅沟槽隔离结构 314朝向第五浅沟槽隔离结构 315—侧的中上部 形成第六多余掺杂区域 366,且第一多余掺杂区域 361、第四多余掺杂区域 364 和第五多余掺杂区域 365的掺杂类型与第二阱区 352的掺杂类型相同，第二多 余掺杂区域 362、 第三多余掺杂区域 363和第六多余掺杂区域 366的掺杂类型 与第一阱区 351的掺杂类型相同。 执行步骤 S23 , 参见图 20所示， 刻蚀每个所述有源区， 以形成第一凹槽 371、 第二凹槽 372、 第三凹槽 373和第四凹槽 374, 每个所述凹槽的深度小于 或等于其对应的阱区的深度。所述 W槽的深度是指 槽的上表面与所述浅沟槽 隔离结构上表面之间的垂直距离。 本实施例中为了不破坏第一阱区 351和第二阱区 352的结构，所以保证每 个凹槽的深度小于或等于其对应的阱区的深度。每个凹槽的具体刻蚀方法同实 施例一， 在此不再赘述。 此外， 为了不破坏所述浅沟槽隔离结构， 所述凹槽的深度还小于或等于所 述浅沟槽隔离结构的深度， 具体参见图 20所示。 最后执行步骤 S24, 参见图 21所示， 外延生长半导体材料 390, 以填充每 个所述 槽形成修正半导体区。 参见图 22所示， 本实施例也可以对所述半导体材料 390进一步进行平坦 化处理。 其中， 外延生长的所述半导体材料 390可以为 Si、 SiGe、 SiC或 Ge。 所 述半导体材料 390既可以与所述半导体村底 300的材料相同，也可以与所述半 导体村底 300的材料不相同。 本实施例中对 槽内的半导体材料 390 进行平坦化处理的步骤与实施例 一相同， 在此不再赘述。 本实施例在形成第一阱区 351和第二阱区 352后， 无需掩模的作用， 统一 对所有包括多余掺杂区域的半导体村底进行刻蚀，且所述刻蚀不损坏已形成的 阱区结构， 然后对刻蚀区域进行外延生长，得到包括阱区但不包括多余掺杂区 域的半导体村底。在后续形成半导体器件后， 所有的半导体器件都不会受到掺 杂离子横向扩散作用的影响。 因此本实施方法更筒单、 成本更低、 且能保证所 有半导体器件阈值电压的稳定性。 在本发明的另一个实施例中，在所述有源区内形成阱区之后， 可以在部分 数目的阱区上形成掩模，从而对剩余的阱区进行选择性刻蚀以形成凹槽，且保 证凹槽的深度小于对应阱区的深度； 然后外延生长半导体材料， 以填充每个所 述凹槽； 最后去除所述掩模。此种实现方式可以实现对部分数目的阱区对应的 多余掺杂区域进行去除，消除该部分多余掺杂区域的横向扩散造成的对应半导 体器件的阈值电压影响。 实施例三 参见图 23所示， 本实施例提供了一种半导体基底， 包括： 半导体村底 400, 所述半导体村底 400包括隔离结构， 以隔离有源区； 由上述实施例的方法中形成的修正半导体区 420, 所述修正半导体区 420 嵌于至少部分数目的所述有源区中，所述修正半导体区 420材料与所述半导体 村底 400材料不同，且所述修正半导体区 420的上表面至少与所述有源区的上 表面齐平。 本实施例中所述半导体村底 400的材料可以为 Si、 SiGe、 SiC或 Ge。 为了便于说明和理解， 在其中一个实施例中， 如图 23所示， 所述半导体 村底包括第一隔离结构 411、 第二隔离结构 412、 第三隔离结构 413和第四隔 离结构 414, 以隔离第一有源区 431、 第二有源区 432和第三有源区 433, 且 每个所述隔离结构为浅沟槽隔离结构。 需要说明的是，在本发明的其他实施例 中， 所述隔离结构的数目可以为 2以上的任意整数， 所述隔离结构也可以为其 他隔离结构， 如局部氧化硅隔离结构等。 其中， 部分数目的所述有源区内还可以包括第一阱区 （图中未示出）， 剩 余的所述有源区内还可以包括第二阱区 （图中未示出）， 所述第一阱区和所述 第二阱区的掺杂类型不同，且所述第一阱区和所述第二阱区的上表面低于或齐 平于所述修正半导体区 420的下表面。 本实施例中所述修正半导体区 420的材料也可以为 Si、 SiGe、 SiC或 Ge, 但所述修正半导体区 420的材料与所述半导体村底 400的材料不相同，如： 当 半导体村底 400为的材料为 Si 时，所述修正半导体区 420的材料可以为 SiGe、 SiC或 Ge, 但所述修正半导体区 420的材料不能是 Si。 本发明的实施例中，修正半导体区 420的下表面高于各个所述隔离结构下 表面， 这样可以避免将隔离结构之间已经形成的阱区破坏。 本实施例中所述修正半导体区 420嵌于所有的所述有源区中。在本发明的 其他实施例中， 所述修正半导体区 420可以仅嵌于部分数目的所述有源区中， 剩余数目的所述有源区中仍是与修正半导体区 420 材料不同的半导体村底 400。 本实施例中所述修正半导体区 420的上表面与所述有源区的上表面齐平。 在本发明的其他实施例中，所述 420修正半导体区的上表面还可以高于所述有 源区的上表面。 上述的半导体基底具体可采用实施例一或实施例二的方法制备得到，从而 半导体基底中去除了部分或全部的多余掺杂区域，保证了对应半导体器件阈值 电压的稳定性。 虽然本发明己以较佳实施例披露如上，但本发明并非限定于此。任何本领 域技术人员， 在不脱离本发明的精神和范围内， 均可作各种更动与修改， 因此 本发明的保护范围应当以权利要求所限定的范围为准。

Claims

权 利 要 求
1. 一种阱区的形成方法， 包括：
在半导体村底内形成隔离区， 以隔离有源区； 选定至少一个所述有源区， 在选定的所述有源区内形成第一阱区； 其特征在于， 所述阱区的形成方法还包括： 以掩模覆盖选定的所述有源区， 刻蚀剩余的所述有源区， 以形成凹槽； 外延生长半导体材料， 以填充所述凹槽。
2.根据权利要求 1 所述的阱区的形成方法， 其特征在于， 还包括： 在所 述半导体材料中形成第二阱区， 所述第二阱区和所述第一阱区掺杂类型不同。
3. 根据权利要求 1所述的阱区的形成方法， 其特征在于， 所述半导体村 底材料与所述半导体材料相同或不同。
4.根据权利要求 3所述的阱区的形成方法， 其特征在于， 所述半导体村 底材料与所述半导体材料均为 Si、 SiGe、 SiC或 Ge。
5.根据权利要求 1 所述的阱区的形成方法， 其特征在于， 在以隔离结构 界定所述隔离区时， 所述凹槽的深度小于或等于所述隔离结构的深度。
6.一种阱区的形成方法， 包括：
在半导体村底内形成隔离区， 以隔离有源区； 在所述有源区内形成阱区；
其特征在于， 还包括： 刻蚀所述有源区， 以形成凹槽， 所述凹槽的深度小于或等于所述阱区的深 度；
外延生长半导体材料， 以填充所述凹槽。
7.根据权利要求 6所述的阱区的形成方法， 其特征在于， 所述刻蚀所述 有源区包括： 在部分数目的所述有源区上形成掩模， 刻蚀剩余的所述有源区。
8.根据权利要求 6所述的阱区的形成方法， 其特征在于， 所述半导体村 底材料与所述半导体材料相同或不同。
9.根据权利要求 6所述的阱区的形成方法， 其特征在于， 所述在所述有 源区内形成的阱区包括第一阱区和第二阱区，所述第一阱区和第二阱区的掺杂 类型不同。
10. 根据权利要求 6所述的阱区的形成方法， 其特征在于， 所述半导体村 底材料和所述半导体材料均为 Si、 SiGe、 SiC或 Ge。
11.根据权利要求 6所述的阱区的形成方法， 其特征在于， 在以隔离结构 界定所述隔离区时， 所述凹槽的深度小于或等于所述隔离结构的深度。
12. 一种半导体基底， 包括： 半导体村底，所述半导体村底包括隔离结构， 以隔离至少两个有源区；其特征在于，所述半导体基底还包括：修正半导体区， 所述修正半导体区嵌于至少部分数目的所述有源区中，所述修正半导体区材料 与所述半导体村底材料不同，且所述修正半导体区的上表面至少与所述有源区 的上表面齐平。
13. 根据权利要求 12所述的半导体基底， 其特征在于， 所述修正半导体 区的下表面高于所述隔离结构的下表面。
14.根据权利要求 12所述的半导体基底， 其特征在于， 所述半导体村底 材料为 Si、 SiGe、 SiC或 Ge。
15. 根据权利要求 12所述的半导体基底， 其特征在于， 所述修正半导体 区材料为 Si、 SiGe、 SiC或 Ge。
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