TW202145357A - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TW202145357A
TW202145357A TW110102258A TW110102258A TW202145357A TW 202145357 A TW202145357 A TW 202145357A TW 110102258 A TW110102258 A TW 110102258A TW 110102258 A TW110102258 A TW 110102258A TW 202145357 A TW202145357 A TW 202145357A
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layer
silicon
fin
crystal
doped region
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TW110102258A
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TWI792157B (zh
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周鴻儒
高珮玲
廖晨瑄
張志仲
郭俊銘
許哲源
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台灣積體電路製造股份有限公司
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Abstract

本文的實施例為一種在鰭部隔離區製造期間減少鰭部氧化的方法。 上述方法包括：提供一半導體基底，具有一n型摻雜區及一p型摻雜區形成於半導體基底的頂部上；磊晶生長一第一層於p型摻雜區上； 磊晶生長不同於第一層的一第二層於n型摻雜區上；磊晶生長一第三層於第一層與第二層的上表面上，其中第三層薄於第一層及第二層。上述方法更包括蝕刻第一層、第二層及第三層，以形成鰭部結構於半導體基底上，且在鰭部結構之間形成一隔離區。

Description

半導體結構及其製造方法
本發明實施例係關於一種半導體技術，且特別是關於一種半導體結構及其製造方法。
在鰭式場效電晶體（fin field effect transistors, finFET）中形成隔離區的過程中，鰭部氧化會導致鰭部寬度損失，這又導致電晶體效能下降及良率損失。矽鍺鰭部結構在鰭部結構之間形成隔離區的期間對於鰭部寬度損失特別敏感。
一種半導體結構，包括：一半導體基底；一第一鰭部結構，形成於半導體基底上，包括一第一磊晶層以及薄於第一磊晶層的一第二磊晶層；一第二鰭部結構，形成於半導體基底上，包括不同於第一磊晶層的一第三磊晶層及第二磊晶層，其中第二磊晶層薄於第三磊晶層；以及一隔離區，位於第一鰭部結構與第二鰭部結構之間。
一種半導體結構，包括：一晶體基底；一第一電晶體結構，包括一第一晶體鰭部結構形成於晶體基底上，其中第一晶體鰭部結構包括晶體基底的一p型摻雜區、磊晶生長於p型摻雜區上的一矽層以及磊晶生長於矽層上的一第一矽蓋層；一第二電晶體結構，包括一第二晶體鰭部結構形成於晶體基底上，其中第二晶體鰭部結構包括晶體基底的一n型摻雜區、磊晶生長於n型摻雜區上的一矽鍺層以及磊晶生長於矽鍺層上的一第二矽蓋層；一隔離堆疊，形成於第一晶體鰭部結構與第二晶體鰭部結構之間。
一種半導體結構之製造方法，包括：提供一半導體基底，其具有一n型摻雜區及一p型摻雜區形成於半導體基底的頂部上；磊晶生長一第一層於p型摻雜區上；磊晶生長不同於第一層的一第二層於n型摻雜區上；磊晶生長一第三層於第一層及第二層的上表面上，其中第三層薄於第一層及第二層；蝕刻第一層、第二層及第三層以形成多個鰭部結構於半導體基底上；以及形成一隔離區於鰭部結構之間。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以所定義本發明。舉例來說，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本揭露內容於各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的，而非自行指定所探討的各個不同實施例及/或配置之間的關係。
再者，於空間上的相關用語，例如＂下方＂、＂之下＂、＂下＂、＂上方＂、＂上＂等等於此處係用以容易表達出本說明書中所繪示的圖式中元件或特徵部件與另外的元件或特徵部件的關係。這些空間上的相關用語除了涵蓋圖式所繪示的方位外，還涵蓋裝置於使用或操作中的不同方位。此裝置可具有不同方位（旋轉90度或其他方位）且此處所使用的空間上的相關符號同樣有相應的解釋。
如本文所使用的用語“名義”係指在產品或製程的設計階段設定的部件或製程操作步驟的特性或參數所需值或目標值（連同高於及/或低於所需值的範圍）。數值範圍通常為製造製程或公差造成的微小變化。
在一些實施例中，用語 “大約”及“實質上”可表示給定數量值的5%內變化（舉例來說，該值的±1%、±2%、±3%、±4%、±5%）。這些數值僅為示例，並非侷限於此。應當理解，用語“大約”及“實質上”可指根據本文所教示，由所屬技術領域中具有通常知識者解釋該值的百分比。
如本文所使用的用語“垂直”是指名義上垂直於基底的表面。
鰭式場效電晶體（finFET）中的鰭部隔離係透過製造設置於鰭部結構之間的鰭部隔離區而獲得實現。鰭部隔離區可對應於定義鰭部結構之後所形成的淺溝槽隔離（shallow trench isolation, STI）區。鰭部結構可透過任何合適的方法進行圖案化。舉例來說，可使用一或多道光學微影製程來圖案化鰭部結構，上述光學微影製程包括雙重圖案化製程或多重圖案化製程。雙重圖案化或多重圖案化製程可將光學微影與自對準製程結合，從而允許形成圖案，例如其間距小於使用單一直接光學微影製程所能獲得的間距。舉例來說，在一些實施例中，形成一犧牲層於一基底上方，並使用光學微影製程對其進行圖案化。使用自對準製程於圖案化的犧牲層側邊形成間隔層。接著去除犧牲層，然後可使用餘留的間隔層圖案化出鰭部結構。
作為示例說明而未侷限於此，鰭部隔離區的製造可包括多重操作步驟，例如：（i）沉積一襯層材料於鰭部結構上；（ii）沉積主體隔離材料於襯層材料上；（iii）進行主體隔離材料的後沉積處理；（iv）進行主體隔離材料的平坦化操作步驟；以及（iv）進行凹進（recess）操作步驟，以去除主體隔離材料的多餘部分。前述製程中的每一者可包括額外的次操作步驟。舉例來說，主要隔離材料的沉積後處理可包括在濕蒸汽中進行退火操作步驟，以提高沉積的隔離材料的質量。 在一些實施例中，隔離材料可為氧化矽或氧化矽類的材料，其更包括氮及氫。
在後沉積處理期間，鰭部結構的弱點位置（例如，鰭部結構的頂部角落，鰭部結構的上表面與側壁表面會合處）被濕蒸汽所氧化。鰭部氧化係自鰭部結構的表面朝向其中心往內進行。若不控制，則氧化過程可形成氧化層，有效地減少鰭部結構的未氧化部分。在後續的鰭部隔離材料的凹進操作步驟中，鰭部結構的氧化部分可能會無意間去除。因此，鰭部結構的寬度縮減。在一些實施例中，若氧化不均勻，則會在鰭部結構上形成凹坑缺陷。缺陷的形成及鰭部寬度的損失會導致電晶體的效能下降及效能變異，兩者都不利於製造的良率。
本文所述的實施例為一種在鰭部隔離區的形成期間減少鰭部氧化的方法。在一些實施例中，結晶矽蓋層覆蓋鰭部結構的上表面，以防止鰭部在隔離區的形成期間氧化。矽晶體蓋層可不作為犧牲材料，並且可成為電晶體結構的一部分。因此，需要控制矽晶體蓋層的厚度及品質。
第1圖係製造方法100的流程圖，其說明了根據一些實施例之位於晶體鰭部結構的上表面上的晶體蓋層的形成製程，用以防止在後續的鰭部隔離製造期間的鰭部氧化。可在方法100的各種操作步驟之間進行其他製造操作步驟，且僅出於清楚及便於說明的目的可省略其他製造操作步驟。這些不同的操作步驟也在本揭露的精神及範圍內。再者，此處所揭露的可能不需要由所有操作步驟來進行。另外，一些操作步驟可同時進行，或者以不同於第1圖所示順序進行。在一些實施例中，除了當前描述的操作步驟之外或代替當前描述的操作步驟，可進行一或多個其他操作步驟。為了說明的目的，將配合第2-12圖中所示的實施例說明方法100。提供說明方法100的圖式僅出於說明性目的，且未按比例繪製。另外，這些圖式可能無法反映真實結構、特徵或膜層的實際幾何形狀。為了說明性目的，可能會故意增加一些結構、薄膜或幾何形狀。
請參照第1圖，方法100開始於操作步驟110及生長矽磊晶層於內部形成有n型井區及p型井區的半導體基底上的製程。作為示例說明而未侷限於此，第2圖中繪示出了根據操作步驟110的一半導體基底，第2圖為半導體基底200的局部立體示意圖，包括p型井區210及n型井區220形成於其局部的上表面上。
在一些實施例中，半導體基底200為塊材半導體晶圓或絕緣體上覆半導體（semiconductor on insulator, SOI）晶片的頂層，例如絕緣體上覆矽。再者，半導體基底200可由矽（Si）或另一種元素半導體，例如（i）鍺（Ge）；（ii）化合物半導體，包括碳化矽（SiC）、砷化鎵（GaAs）、磷化鎵（GaP）、磷化銦（InP）、砷化銦（InAs）及/或銻化銦（InSb）；（iii）合金半導體，包括矽鍺（SiGe）、砷化鎵磷（GaAsP）、砷化鋁銦（AlInAs）、砷化鋁鎵（AlGaAs）、砷化鎵銦（GaInAs）、磷化鎵銦（GaInP）及/或砷化鎵銦磷化物（GaInAsP）；或（iv）其組合形成。在一些實施例中，半導體基底200具有晶體微結構，例如，其不為非晶質或多晶。
出於示例性目的，方法100中半導體基底200係以矽晶體具有上表面平行於（100）晶面作為說明。基於本文的揭露內容，可使用如上所述的其他材料。這些材料也在本揭露的精神及範圍內。
可透過使用適當的摻雜物摻雜半導體基底200的頂部來形成摻雜井區（舉例來說，p型井區210及n型井區220）。作為示例說明而未侷限於此，可透過離子佈植機以約5×1016 atoms/cm3 至1×1019 atoms/cm3 的濃度佈植硼（B），以形成p型井區210。相應地，可透過離子佈植機以5×1016 atoms/cm3 至1×1019 atoms/cm3 的濃度砷（As）、銻（Sb）或磷（P），以形成n井區220。上述摻雜物種的佈植深度範圍可在約100nm至500nm之間。換句話說，摻雜的p型井區210及n型井區220的深度T的範圍約在100nm至500nm之間。p型井區210及n型井區220的“邊界”由虛線表示。作為示例說明而未侷限於此，p型井區210及n型井區220可能未延伸於半導體基底200的整個上表面上。舉例來說，可形成多個p型井區210及n型井區220。在一些實施例中，摻雜井區的形成更包括在離子佈植之後進行的活化退火（activation anneal），以確保能活化半導體晶格內的摻雜物。
根據操作步驟110，生長一矽磊晶層230於半導體基底200上。在一些實施例中，矽磊晶層230生長至厚度約在300 Å至1000Å之間。作為示例說明而未侷限於此，可利用化學氣相沉積製程來沉積矽磊晶層230。矽磊晶層230的生長中所使用的原料氣體包括但不限於矽烷（SiH4 ）、四氯化矽（SiCl4 ）、三氯矽烷（trichlorosilane, TCS）或二氯矽烷（SiH2 Cl2 或DSC（dichlorosilane））。可以氫氣（H2 ）作為反應氣體，以減少上述原料氣體。取決於所使用的氣體，磊晶生長期間的沉積溫度可約在700℃至1250℃的範圍。舉例來說，相較於具有更多氯原子的原料氣體（例如，SiCl4 或TCS），具有更少氯原子的原料氣體（例如，DSC）可能需要更低的形成溫度。前述氣體的範圍及類型僅供作示例，並未侷限於此。在一些實施例中，生長矽磊晶層230以覆蓋半導體基底200的整個上表面。然而，並未侷限於此，且可透過使用圖案化的罩幕層來生長矽磊晶層230於半導體基底200的所需區域上。根據一些實施例，矽磊晶層230繼承相同於矽半導體基底200的晶體取向（crystallographic orientation），因為上述基底有效地作為矽磊晶層230的種子層。此意指矽磊晶層230的上表面230S 也平行於（ 100）晶面。
在一些實施例中，矽磊晶層230可是本質的（例如，未摻雜的）或摻雜的。矽磊晶層230可在生長形成期間或在生長之後進行摻雜。再者，矽磊晶層230可摻雜有相同或不同於下方摻雜井區類型的摻雜物，且摻雜有相同或不同的摻雜物濃度。
請參照第1及3圖，方法100繼續進行至操作步驟120及形成一開口300於矽磊晶層230內以露出n型井區220的上表面的製程。在一些實施例中，使用光學微影及蝕刻操作步驟形成開口300。作為示例說明而未侷限於此，可施加光阻塗層（未繪示）於矽磊晶層230上。隨後光阻可根據所需的圖案進行曝光及顯影。舉例來說，所需的圖案可為開口，其對準於n型井區220，露出半導體基底200的上表面。可利用濕式清潔去除光阻的未曝光區，因而留下顯影後的光阻的所需圖案於p型井區210上方的矽磊晶層230上。顯影的光阻隨後可作為蝕刻罩幕。異向性乾蝕刻製程可局部去除矽磊晶層230的露出部分，以形成開口300。保護由顯影後光阻所覆蓋的矽磊晶層230區域（例如，位於p型井區210的頂部）不受蝕刻化學的影響，因此不會被移除。一旦在矽磊晶層230內形成開口300，便以濕式清潔去除餘留的顯影後的光阻。矽磊晶層230中的蝕刻部分為上述製程的結果，如第3圖所示的開口300。
在一些實施例中，當露出n型井區220的上表面時，停止乾式蝕刻製程。作為示例說明而未侷限於此，可使用蝕刻停止層來示意蝕刻製程終止。作為示例說明而未侷限於此，可在形成矽磊晶層230之前形成一碳摻雜層於摻雜井區的上表面內，以作為蝕刻停止層及摻雜物擴散阻障層。或者，由於摻雜矽的蝕刻速率可不同於本質矽的蝕刻速率，因此可使用n型井區220的n型摻雜物濃度來示意蝕刻製程終止。
請第1圖，方法100繼續進行至操作步驟130及生長矽鍺磊晶層於露出的n型井區220上而填充開口300的製程。在一些實施例中，以異質磊晶製程生長矽鍺磊晶層。第4圖係繪示出生長矽鍺磊晶層400於開口300內的n型井區220上之後的結構。在一些實施例中，平坦化操作步驟，例如化學機械研磨（chemical mechanical polishing, CMP），研磨矽鍺磊晶層400，使矽鍺磊晶層400及矽磊晶層230的上表面實質上為共平面，如第4圖所示。作為示例說明而未侷限於此，用於矽鍺磊晶層生長的前驅物氣體可包括（i）SiH4 、Si2 H6 、SiH2 Cl2 、GeH4 或HCl以及（ii）H2 、N2 或Ar的組合。在一些實施例中，可在矽鍺磊晶層400的生長之前沉積一緩衝層（未繪示），以抑制由於生長的矽鍺與下方半導體基底200之間的晶格失配所產生的生長缺陷。再者，開口300可在生長矽鍺磊晶層400之前進行預處理，以去除於蝕刻製程期間所形成的原生氧化物層。
如同矽磊晶層230的情形一般，矽鍺磊晶層400使用半導體基底200作為種子層。因此，矽鍺磊晶層400“繼承”與半導體基底200相同的晶體取向，且其上表面400S 平行於（100）矽晶面。
請參照第1圖，方法100繼續進行至操作步驟140及生長一矽晶體蓋層於矽磊晶層230及矽鍺磊晶層400上的製程。在一些實施例中，矽晶體蓋層的生長係於能夠處理多個晶圓的多批次爐管內進行。在一些實施例中，將要處理的晶圓堆疊於爐管內並進行化學氧化物去除（chemical oxide removal, COR）製程，此製程去除位於矽磊晶層230及矽鍺磊晶層400的上表面所形成的原生氧化物。化學氧化物去除（COR）製程使用氫氟酸（HF）與氨（NH3 ）混合物。一旦矽磊晶層230的上表面230S 及矽鍺磊晶層400的上表面400S 各自不含原生氧化物，便開始生長矽晶體蓋層。在一些實施例中，於約在300℃至400℃之間的溫度下使用二氯矽烷（SiH2 Cl2 或DSC）及氫（H2 ）來生長矽晶體蓋層。第5圖係繪示出生長一矽晶體蓋層500於矽磊晶層230及矽鍺磊晶層400上。在一些實施例中，矽晶體蓋層500具有與下方矽磊晶層230及矽鍺磊晶層400相同的晶體取向。舉例來說，矽晶體蓋層500的上表面平行於（100）晶面。
在一些實施例中，矽晶體蓋層500在鰭部隔離區的形成期間保護矽磊晶層230及矽鍺磊晶層400的上表面而免於遭受氧化。根據一些實施例，矽晶體蓋層500的厚度約在2nm。厚度小於2 nm的矽晶體蓋層無法提供鰭部足夠的氧化防護，而厚度大於2nm的矽晶體蓋層則會降低電晶體的效能。原因在於如前所述，矽晶體蓋層500並非作為犧牲層，故會成為電晶體結構的一部分。因此，矽晶體蓋層500需要具備足夠厚度以防止鰭部氧化，並且必須足夠薄以避免影響電晶體的效能。
請參照第1圖，方法100繼續進行至操作步驟150及形成鰭部結構的製程。如前所述，可透過任何合適的方法來圖案化出鰭部結構。舉例來說，可使用一或多道光學微影製程（包括雙重圖案化製程或多重圖案化製程）來圖案化出鰭部結構。雙重圖案化或多重圖案化製程可將光學微影製程與自對準製程結合，從而允許形成圖案，例如其間距小於使用單一直接光學微影製程所能獲得的間距。舉例來說，在一些實施例中，形成一犧牲層於一基底上方，並使用光學微影製程對其進行圖案化。使用自對準製程於圖案化的犧牲層側邊形成間隔層。接著去除犧牲層，然後可使用餘留的間隔層圖案化出鰭部結構。根據一些實施例，第6圖係繪示出最終圖案化操作步驟，用以形成鰭部結構，操作步驟中圖案化層610及620設置於矽晶體蓋層500上。在一些實施例中，圖案化層610包括氧化矽，且圖案化層620包括氮化矽（Si3 N4 ）。
圖案化層610及620（透過上述光學微影製程所定義）的尺寸依序定義了鰭部結構700及710的寬度W、長度L以及間距，如第7圖所示。蝕刻製程的持續時間可用來定義鰭部結構700及710的高度H。作為示例說明而未侷限於此，寬度W可約在5nm至10nm的範圍，而鰭部結構700及710的高度H可約在35nm至120nm的範圍。長度L的調整係取決於後續製造操作步驟中形成的閘極結構（其垂直於鰭部結構（例如，沿x方向））的數量、間距及尺寸。 在一些實施例中，可在半導體基底200的其他位置（例如，鄰近鰭部結構700及710）中形成額外的鰭部結構（類似鰭部結構700及710）。
在一些實施例中，鰭部結構700包括位於n型井區220上的矽鍺磊晶層400，而鰭部結構710包括位於p型井區210上的矽磊晶層230。根據一些實施例，p型finFET可形成於具有矽鍺通道區的鰭部結構700上，而n型finFET可形成於具有矽通道區的鰭部結構710上。然而，並未侷限於此，且可在具有矽通道區的鰭部結構710上形成p型finFET及n型finFET。
請參照第1圖，方法100繼續進行至操作步驟160及沉積隔離材料於鰭部結構700及710之間的製程。請參照第8圖，沉積隔離材料包括沉積一襯層800於鰭部結構700及710上。根據一些實施例，第8圖係鰭部結構700及710沿第7圖所示的切割線AB的剖面示意圖。作為示例說明而未侷限於此，襯層800作為隔離材料的黏著層。再者，襯層800作為鰭部結構700及710的側壁表面抗氧化的保護層。作為示例說明而未侷限於此，襯層800可透過順應性沉積製程（例如，電漿輔助原子層沉積（plasma-enhanced atomic layer deposition, PEALD））進行沉積，厚度約在3nm。作為示例說明而未侷限於此，襯層800可為氧化矽或氧化矽類的介電材料。
隨後，沉積一隔離材料900（例如，主要隔離材料）以圍繞鰭部結構700及710，如第9圖所示。在一些實施例中，隔離材料900沉積至一厚度900T ，其約3倍於鰭部結構700及710的高度H（例如，900T 〜H×3）。舉例來說，若高度H約在120nm，則厚度900T 約在360nm。根據一些實施例，利用流動式化學氣相沉積（flowable chemical vapor deposition）製程（例如，流動式CVD）來沉積隔離材料900，以確保隔離材料900填滿鰭部結構700及710之間的空間而不會形成縫隙或孔洞。在一些實施例中，隔離材料900為氧化矽類的介電材料，其可包括氮及氫。為了進一步改善其介電和結構特性，對隔離材料900進行濕式蒸汽退火（例如，100%水分子），溫度約在800℃至1200℃之間。在進行濕式蒸汽退火期間，隔離材料900會緻密化且增加其氧含量。
根據一些實施例，矽晶體蓋層500防止鰭部結構700及710於“弱點”位置A處發生氧化，例如鰭部結構700及710的頂部角落，其位於兩個不同的晶面會合處，其中晶面（100）沿著鰭部結構的上表面，而晶面（110）沿著鰭部結構的側壁表面。鰭部結構700及710的頂部角落形成轉變點，在濕式蒸汽退火期間，氧可擴散通過並氧化鰭部結構700及710。生長於鰭部結構700及710的上表面上的矽晶體蓋層500將弱點從位置A“遷移”至位置B，並將其從鰭部結構的上表面“移離”。之所以能夠如此係由於磊晶生長會複製下方的晶體結構（及取向）。舉例來說，原子排列起來就好像原子排列為下方晶體層的延續一樣。在矽晶體蓋層500及鰭部結構700為異質磊晶生長的情形下，矽晶體蓋層500將與下方矽鍺磊晶層400具有相同對稱性，但由於矽鍺底層與矽晶體蓋層之間的晶格失配，故矽原子之間的距離並不相同。然而，由於矽晶體蓋層500的厚度限制（例如，約2nm）與鰭部結構700的寬度限制（例如，約在5nm至10nm之間），故可抑制與晶格失配相關的缺陷。
隨後，如第10圖所示，以化學機械研磨（CMP）製程來研磨隔離材料900，直至露出鰭部結構700及710上的圖案化層620。 在一些實施例中，圖案化層620作為上述化學機械研磨（CMP）製程的研磨停止層。如第11圖所示，化學機械研磨（CMP）製程的修整可去除圖案化層620並露出圖案化層610。在一些實施例中，透過包括磷酸（H3 PO4 ）的濕式蝕刻化學，選擇性去除餘留的圖案化層620。
請參照第1圖，方法100繼續進行至操作步驟170及相對於鰭部結構700及710的隔離材料900進行凹進的製程，如第12圖所示。在一些實施例中，凹進操作步驟也“回縮（pull back）”襯層800，這是因為在隔離材料900的凹進製程中使用的乾式蝕刻化學劑也對襯層800具有選擇性。在一些實施例中，凹進製程包括但未侷限於氟碳化合物化學劑。上述凹進製程的結果為鰭部結構700及710的上部露出，而下部仍保持埋入於隔離材料900內。再者，方法100中所述的任何氧化製程期間形成於鰭部狀結構700及710的側壁上的任何氧化物將於上述凹進操作步驟期間被去除。
根據一些實施例，第13圖係形成閘極堆疊1300於鰭部結構700及710上之後的局部立體示意圖。在一些實施例中，閘極堆疊1300包括一閘極電極1310及夾設於閘極電極1310與鰭部結構700及710之間的一閘極介電堆疊1320。閘極堆疊1300順沿著每個鰭部結構700及710以及對應的源極/汲極磊晶區（未繪示）而形成電晶體結構。舉例來說，如先前所述，形成於鰭部結構700上的電晶體結構為p型finFET，而形成於鰭部結構710上的電晶體結構為n型finFET。在一些實施例中，用於鰭部結構700的閘極堆疊1300可包括與用於鰭部結構710的閘極堆疊1300不同的金屬層。
本文所述的實施例係一種在鰭部隔離區的製造期間防止鰭部發生氧化的方法。根據一些實施例，上述方法包括在形成的鰭部結構的上表面上沉積矽晶體層，以作為覆蓋層，防止在隔離區的製造期間發生鰭部氧化。在一些實施例中，矽晶體蓋層不為犧牲層，且可整合於電晶體結構內。在一些實施例中，磊晶生長矽晶體層至約2nm的厚度，且具有一上表面平行於（100）矽晶面。
在一些實施例中，一種半導體結構包括：一半導體基底，具有一第一鰭部結構及一第二鰭部結構形成於一半導體基底上。第一鰭部結構包括一第一磊晶層及比第一磊晶層薄的一第二磊晶層。第二鰭部結構包括不同於第一磊晶層的一第三磊晶層及第二磊晶層，其中第二磊晶層比第三磊晶層薄。半導體結構更包括：一隔離區，位於第一鰭部結構與第二鰭部結構之間。
在一些實施例中，一種半導體結構包括：一晶體基底及具有一第一晶體鰭部結構形成於晶體基底上的一第一電晶體結構。第一晶體鰭部結構包括晶體基底的一p型摻雜區、磊晶生長於p型摻雜區上的一矽層以及磊晶生長於矽層上的一第一矽蓋層。半導體結構更包括一第二電晶體結構，具有形成於晶體基底上的一第二晶體鰭部結構。第二晶體鰭部結構包括晶體基底的一n型摻雜區、磊晶生長於n型摻雜區上的一矽鍺層以及磊晶生長於矽鍺層上的一第二矽蓋層。另外，半導體結構包括一隔離堆疊，形成於第一晶體鰭部結構與第二晶體鰭部結構之間。
在一些實施例中，一種半導體結構之製造方法包括：提供一半導體基底，其具有一n型摻雜區及一p型摻雜區形成於半導體基底的頂部上；磊晶生長一第一層於p型摻雜區上；磊晶生長不同於第一層的一第二層於n型摻雜區上；磊晶生長一第三層於第一層及第二層的上表面上，其中第三層比第一層及第二層薄。上述方法更包括蝕刻第一層、第二層及第三層以形成多個鰭部結構於半導體基底上；以及形成一隔離區於鰭部結構之間。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神及保護範圍內，且可於不脫離本揭露之精神及範圍內，當可作更動、替代與潤飾。
100:方法 110,120,130,140,150,160,170:操作步驟 200:半導體基底 210:p型井區 220:n型井區 230:矽磊晶層 230S ,400S :上表面 300:開口 400:矽鍺磊晶層 500:矽晶體蓋層 610,620:圖案化層 700,710:鰭部結構 800:襯層 900:隔離材料 900T :厚度 1300:閘極堆疊 1310:閘極電極 1320:閘極介電堆疊 A,B:位置 H:高度 L:長度 T:深度 W:寬度
第1圖係繪示出根據一些實施例之形成矽晶體蓋層於半導體鰭部結構上的製造方法流程圖，用以防止形成鰭部隔離區期間的鰭部氧化。 第2至6圖係繪示出根據一些實施例之基底於鰭部結構上形成有矽晶體蓋層的製造期間的立體示意圖。 第7至12圖係繪示出根據一些實施例之鰭部結構上形成有矽晶體蓋層於鰭部隔離區製造期間的剖面示意圖。 第13圖係繪示出根據一些實施例之p型及n型電晶體的局部立體示意圖。
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100:方法
110,120,130,140,150,160,170:操作步驟

Claims (20)

  1. 一種半導體結構，包括： 一半導體基底； 一第一鰭部結構，形成於該半導體基底上，包括： 一第一磊晶層；以及 一第二磊晶層薄於該第一磊晶層； 一第二鰭部結構，形成於該半導體基底上，包括： 一第三磊晶層，不同於該第一磊晶層；以及 該第二磊晶層，其中該第二磊晶層薄於該第三磊晶層；以及 一隔離區，位於該第一鰭部結構與該第二鰭部結構之間。
  2. 如請求項1之半導體結構，其中該第二磊晶層為厚度約在2nm的矽晶體蓋層。
  3. 如請求項1之半導體結構，其中該第一磊晶層包括矽，且該第三磊晶層包括矽鍺。
  4. 如請求項1之半導體結構，其中該第二磊晶層具有平行於（100）矽晶面的上表面以及平行於（110）晶面的側壁表面。
  5. 如請求項1之半導體結構，其中該隔離區包括： 一襯層，設置於該第一鰭部結構及該第二鰭部結構的底部與側壁的表面上；以及 一介電材料，設置於該襯層上且位於該第一鰭部結構與該第二鰭部結構之間。
  6. 如請求項1之半導體結構，其中該第一鰭部結構更包括一p型摻雜區，設置於該第一磊晶層下方。
  7. 如請求項1之半導體結構，其中該第二鰭部結構更包括一n型摻雜區，設置於該第三磊晶層下方。
  8. 如請求項1之半導體結構，其中第一鰭部結構及該第二鰭部結構具有相同的高度與寬度。
  9. 一種半導體結構，包括： 一晶體基底； 一第一電晶體結構，包括一第一晶體鰭部結構，形成於該晶體基底上，其中該第一晶體鰭部結構包括： 該晶體基底的一p型摻雜區； 一矽層，磊晶生長於該p型摻雜區上；以及 一第一矽蓋層，磊晶生長於該矽層上； 一第二電晶體結構，包括一第二晶體鰭部結構，形成於該晶體基底上，其中該第二晶體鰭部結構包括： 該晶體基底的一n型摻雜區； 一矽鍺層，磊晶生長於該n型摻雜區上；以及 一第二矽蓋層，磊晶生長於該矽鍺層上；以及 一隔離堆疊，形成於該第一晶體鰭部結構與該第二晶體鰭部結構之間。
  10. 如請求項9之半導體結構，其中該第一矽蓋層覆蓋該矽層的上表面。
  11. 如請求項9之半導體結構，其中該第二矽蓋層覆蓋該矽鍺層的上表面。
  12. 如請求項9之半導體結構，其中該第一矽蓋層的側壁表面實質上對準於該矽層與該p型摻雜區的側壁表面。
  13. 如請求項9之半導體結構，其中該第二矽蓋層的側壁表面實質上對準於該矽鍺層與該n型摻雜區的側壁表面。
  14. 如請求項9之半導體結構，其中該第一矽蓋層薄於該矽層。
  15. 如請求項9之半導體結構，其中該第二矽蓋層薄於該矽鍺層。
  16. 如請求項9之半導體結構，其中該第一矽蓋層與該該第二矽蓋層具有相同的厚度及晶體取向。
  17. 一種半導體結構之製造方法，包括： 提供一半導體基底，其具有一n型摻雜區及一p型摻雜區形成於半導體基底的頂部上； 磊晶生長一第一層於該p型摻雜區上； 磊晶生長不同於該第一層的一第二層於該n型摻雜區上； 磊晶生長一第三層於該第一層及該第二層的上表面上，其中該第三層薄於該第一層及該第二層； 蝕刻該第一層、該第二層及該第三層，以形成多個鰭部結構於該半導體基底上；以及 形成一隔離區於該等鰭部結構之間。
  18. 如請求項17之半導體結構之製造方法，其中蝕刻該第一層、該第二層及該第三層包括蝕刻穿過該半導體基底的該n型摻雜區及該p型摻雜區。
  19. 如請求項17之半導體結構之製造方法，其中磊晶生長該第三層包括於該第二層上進行異質磊晶沉積。
  20. 如請求項17之半導體結構之製造方法，其中磊晶生長該第三層包括生長一矽層，具有2nm的厚度及平行於（100）晶面的上表面。
TW110102258A 2020-02-11 2021-01-21 半導體結構及其製造方法 TWI792157B (zh)

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