CN113257817A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
CN113257817A
CN113257817A CN202110074774.9A CN202110074774A CN113257817A CN 113257817 A CN113257817 A CN 113257817A CN 202110074774 A CN202110074774 A CN 202110074774A CN 113257817 A CN113257817 A CN 113257817A
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layer
silicon
fin
epitaxial layer
fin structure
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Inventor
周鸿儒
张志仲
郭俊铭
许哲源
高珮玲
廖晨瑄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述的实施例是针对一种用于在鳍隔离区的形成期间减少鳍氧化的方法。该方法包括提供具有在半导体衬底的顶部上形成有n‑掺杂区和p‑掺杂区的半导体衬底；以及在p‑掺杂区上外延生长第一层；在n‑掺杂区域上外延生长不同于第一层的第二层；在第一层和第二层的顶表面上外延生长第三层，其中，第三层比第一层和第二层薄。该方法还包括蚀刻第一层，第二层和第三层，以在半导体衬底上形成鳍结构和在鳍结构之间形成隔离区。本申请的实施例提供了半导体结构及其形成方法。

Description

半导体结构及其形成方法
技术领域
本申请的实施例涉及半导体结构及其形成方法。
背景技术
在鳍式场效应晶体管(finFET)中形成隔离区期间，鳍氧化会导致鳍宽度的损失，这事实上还会导致晶体管性能的下降和产量损失。在鳍结构之间的隔离区的形成期间，硅-锗鳍结构对鳍宽度的损失尤其敏感。
发明内容
在一些实施例中，半导体结构包括具有在半导体衬底上形成的第一鳍结构和第二鳍结构的半导体衬底。第一鳍结构包括第一外延层和比第一外延层薄的第二外延层。第二鳍结构包括不同于第一外延层和第二外延层的第三外延层，其中第二外延层比第三外延层薄。半导体结构还包括在第一鳍结构和第二鳍结构之间的隔离区。
在一些实施例中，半导体结构包括晶体衬底和具有形成在晶体衬底上的第一晶体鳍结构的第一晶体管结构。第一晶体鳍结构包括晶体衬底的p-掺杂区，外延生长在p-掺杂区上的硅层，和外延生长在硅层上的第一硅覆盖层。半导体结构还包括具有形成在晶体衬底上的第二晶体鳍结构的第二晶体管结构。第二晶体鳍结构包括晶体衬底的n-掺杂区，外延生长在n-掺杂区上的硅锗层，和外延生长在硅锗层上的第二硅覆盖层。另外，半导体结构包括形成在第一晶体鳍结构和第二晶体鳍结构之间的隔离堆叠件。
在一些实施例中，一种方法包括提供具有在半导体衬底的顶部上形成的n-掺杂区和p-掺杂区的半导体衬底；在p-掺杂区上外延生长第一层；在n-掺杂区上外延生长不同于第一层的第二层；在第一层和第二层的顶面上外延生长第三层，其中第三层比第一和第二层薄。该方法还包括蚀刻第一层，第二层和第三层以在半导体衬底上形成鳍结构，和在鳍结构之间形成隔离区域。
本申请的实施例可以防止鳍损失。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1是根据一些实施例的用于在半导体鳍结构上形成晶体硅覆盖层以防止在鳍隔离区形成期间的鳍氧化的制造方法的流程图。
图2至图6是根据一些实施例的在具有其上形成的晶体硅覆盖层的鳍结构的形成期间的衬底的等距视图。
图7至图12是根据一些实施例的在鳍隔离区形成期间，具有在其上形成的晶体硅覆盖层的鳍结构的截面图。
图13是根据一些实施例的p型和n型晶体管的局部等距视图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
如本文所用，术语“标称”是指在产品或工艺的设计阶段期间设置的，表示部件或工作操作的特征或参数的期望值或目标值，以及高于和/或低于所需值的范围。该值的范围通常是由于制造工艺或公差的微小变化所致。
在一些实施例中，术语“约”和“基本上”可以指示给定量的值在目标值的5％之内变化(例如，目标值的±1％，±2％，±3％，±4％和±5％)。
如本文所用，术语“垂直”是指名义上垂直于衬底的表面。
通过形成设置在鳍结构之间的鳍隔离区来实现鳍式场效应晶体管(finFET)中的鳍隔离。鳍隔离区可以对应于在鳍结构限定之后形成的浅沟槽隔离(STI)区。可以通过任何合适的方法来图案化鳍结构。例如，可以使用包括双重图案化工艺或多重图案化工艺的一种或多种光刻工艺来图案化鳍结构。双重图案化或多重图案化工艺可以将光刻和自对准工艺相结合，从而允许创建的图案具有，例如，小于使用单个、直接光刻工艺所能获得的间距。例如，在一些实施例中，在衬底上方形成牺牲层并使用光刻工艺将其图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且可以使用剩余的间隔件来图案化鳍结构。
作为示例而非限制，鳍隔离区的形成可以包括多种操作，例如：(i)在鳍结构上沉积衬里材料，(ii)在衬里材料上沉积主隔离材料，(iii)主隔离材料的后沉积处理，(iv)主隔离材料的平坦化操作，和(v)凹进操作以去除主隔离材料的不期望的部分。每一个前述工艺可以包括附加的子操作。例如，主隔离材料的后沉积处理可以包括在湿蒸汽中的退火操作，以改善沉积的隔离材料的质量。在一些实施例中，隔离材料可以是氧化硅或基于氧化硅的材料，其进一步包括氮和氢。
在后沉积处理期间，鳍结构的弱点位置—例如，鳍结构的顶表面与侧壁表面相遇的鳍结构的顶角—可以通过湿蒸汽被氧化。鳍氧化从鳍结构的表面向其中心向内进行。如果不受控制，则氧化工艺可以形成有效地减少鳍结构的未氧化部分的氧化层。在随后的鳍隔离材料的凹进操作中，鳍结构的氧化部分可能被无意地去除。因此，减小了鳍结构的宽度。在一些实施例中，如果氧化不均匀，则可能在鳍结构上形成凹坑缺陷。缺陷的形成和鳍宽度的损失会导致晶体管下降的性能和性能的变化，这都不利于制造产量。
本文所述的实施例针对一种用于在鳍隔离区的形成期间减少鳍氧化的方法。在一些实施例中，鳍结构的顶表面被硅晶体覆盖层覆盖以防止隔离区形成期间的鳍氧化。晶体硅覆盖层可以不是牺牲性的，并且晶体硅覆盖层可以成为晶体管结构的一部分。因此，需要控制晶体硅覆盖层的厚度和质量。
图1是制造方法100的流程图，其描述了根据一些实施例的位于晶体鳍结构的顶表面上的晶体覆盖层的形成工艺，以防止在随后的鳍隔离形成期间的鳍氧化。可以在方法100的各种操作之间执行其他制造操作，并且仅为了清楚和便于描述可以将其省略。这些各种操作在本发明的精神和范围内。此外，可能不需要在此提供的所有操作来执行本发明。另外，可以同时或者以与图1所示的不同的顺序执行一些操作。在一些实施例中，除了当前描述的操作之外或代替当前描述的操作，可以执行一个或多个其他操作。为了说明的目的，将参考图2至图12中所示的实施例来描述方法100。提供的用于描述方法100的附图仅为了说明的目的，并且未按比例绘制。此外，这些图可能无法反映真实结构，特征或膜的实际几何形状。为了说明的目的，可能故意增加了一些结构，膜或几何形状。
参考图1，方法100开始于操作110和在其中形成有n-型阱和p-型阱的半导体衬底上生长硅外延层的工艺。作为示例而非限制，图2中示出了根据操作110的半导体衬底，图2是包括形成在其上表面的部分上的p-型阱210和n-型阱220的半导体衬底200的局部等距视图。
在一些实施例中，衬底200是块状半导体晶圆或绝缘体上半导体(SOI)晶圆(例如，绝缘体上硅)的顶层。此外，衬底200可以由硅(Si)或另一种基础的半导体制成，例如，(i)锗(Ge)；以及(ii)化合物半导体，包括碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)和/或锑化铟(InSb)；(iii)合金半导体，包括硅锗(SiGe)、砷化镓磷(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)和/或砷化镓铟磷化物(GaInAsP)；或(iv)其组合。在一些实施例中，衬底200具有晶体微结构，例如，它不是非晶或多晶的。
出于示例的目的，将在晶体硅的顶表面平行于(100)晶面的情况下描述方法100中的衬底200。基于本发明，可以使用如上所述的其他材料。这些材料在本发明的精神和范围内。
可以例如通过适当的掺杂剂掺杂半导体衬底200的顶部来形成掺杂的阱(例如，p-型阱210和n-型阱220)。作为示例而非限制，可以通过离子注入机注入约5×1016原子/cm3至约1×1019原子/cm3浓度的硼(B)，以形成p-型阱210。相应地，可以通过离子注入机注入约5×1016原子/cm3至约1×1019原子/cm3浓度的n-型掺杂剂，例如，As、锑(Sb)、或磷(P)，以形成n-阱220。可以以约100nm至约500nm范围内的深度注入前述种类的掺杂剂。换句话说，掺杂阱210和220的深度T在约100nm和约500nm之间变化。p-型阱210和n-型阱220的“边界”由虚线表示。作为示例而非限制，p-型阱210和n-型阱220可以不在半导体衬底200的整个顶表面上方延伸。例如，可以在半导体衬底200的上表面上形成多个p-型阱210和n-型阱220。在一些实施例中，掺杂阱的形成进一步包括在离子注入之后的激活退火，以确保掺杂剂在半导体晶格内被激活。
根据操作110，在半导体衬底200上生长硅外延层230。在一些实施例中，生长硅外延层230的厚度在约
Figure BDA0002907182750000051
到约
Figure BDA0002907182750000052
之间。作为示例而非限制，可以利用化学气相沉积工艺来沉积硅外延层230。在硅外延层230的生长中，可以使用的源气体包括但不限于硅烷(SiH4)、四氯化硅(SiCl4)、三氯硅烷(TCS)或二氯硅烷(SiH2Cl2或DSC)。可以使用氢气(H2)作为反应气体以减少上述源料气。外延生长期间的沉积温度可以在约700℃至约1250℃的范围内，这取决于所使用的气体。例如，与具有更多氯原子的源气体如SiCl4或TCS相比，具有较少氯原子的源气体(例如，像DSC)可以需要较低的形成温度。前述气体的范围和类型仅作为示例提供，而不是限制性的。在一些实施例中，生长硅外延层230以覆盖半导体衬底200的整个顶表面。然而，这不是限制性的，并且可以通过使用例如图案化的掩模层以在衬底200的期望区域上生长硅外延层230。根据一些实施例，硅外延层230继承与硅衬底200相同的晶体取向，因为该衬底有效地用作硅外延层230的种子层。这意味着硅外延层230的顶表面230S也平行于(100)晶面。
在一些实施例中，硅外延层230可以是本征的(例如，未掺杂的)或掺杂的。硅外延层230可以在生长形成期间或生长之后被掺杂。此外，硅外延层230可以被掺杂有与下面的掺杂阱相同或不同类型的掺杂剂，并且被掺杂有相同或不同的掺杂剂浓度。
参考图1和图3，方法100继续进行操作120和在硅外延层230中形成开口300以暴露n-型阱220的顶表面的工艺。在一些实施例中，通过使用光刻和蚀刻操作形成开口300。作为示例而非限制，可以在硅外延层230上施加光刻胶涂层(未示出)。可以随后根据期望的图案对光刻胶进行曝光和显影；例如，期望的图案可以是与暴露半导体衬底200的顶表面的n-型阱220对准的开口。可以用湿法清洁去除光刻胶的未曝光区域，从而在位于p-型阱210上方的硅外延层23上留下显影的光刻胶的期望图案。显影的光刻胶随后可以用作蚀刻掩模。各向异性干蚀刻工艺可以部分去除硅外延层230的暴露部分以形成开口300。被显影的光刻胶覆盖的硅外延层230的区域(例如，在p-型阱210的顶部上)受到保护，而不受蚀刻化学品的影响，因此不会被去除。一旦在硅外延层230中形成开口300，就用湿法清洁去除剩余的显影的光刻胶。该工艺的结果是蚀刻了硅外延层230中的部分，如图3所示的开口300。
在一些实施例中，当暴露n-阱220的顶表面时，干法蚀刻工艺终止。作为示例而非限制，可以使用蚀刻停止层来表示蚀刻工艺的结束。作为示例而非限制，可以在形成硅外延层230之前，在掺杂阱的顶表面内形成碳掺杂层，以用作蚀刻停止层和掺杂剂扩散阻挡层。可选地，由于掺杂硅的蚀刻速率可以与本征硅的蚀刻速率不同，因此可以使用n-型阱220的n-型掺杂剂浓度来表示蚀刻过程的结束。
参照图1，方法100继续进行操作130和在暴露的n-型阱220上生长硅锗外延层以填充开口300的工艺。在一些实施例中，通过异质外延工艺生长硅锗外延层。图4示出了在n-型阱220上开口300内的生长硅锗外延层400之后的结构。在一些实施例中，如图4所示，诸如化学机械抛光(CMP)的平坦化操作抛光硅锗外延层400以使得硅锗外延层400和硅外延层230的顶表面基本共面。作为示例而非限制，用于硅锗外延层生长的前驱体气体可包括(i)SiH4、Si2H6、SiH2Cl2、GeH4或HCl和(ii)H2、N2或Ar的组合。在一些实施例中，可以在硅锗外延层400的生长之前沉积缓冲层(未示出)以抑制由于生长的硅锗与下面的衬底200之间的晶格失配而导致的生长缺陷。此外，开口300可以在硅锗外延层400的生长之前进行预处理以去除在蚀刻工艺期间形成的本征氧化物层。
如在硅外延层230的情况下，硅锗外延层400使用衬底200作为种子层。因此，硅锗外延层400“继承”与衬底200相同的晶体取向，并且其顶表面400S平行于(100)硅晶面。
在参考图1时，方法100继续操作140和在硅外延层230和硅锗外延层400上生长晶体硅覆盖层的工艺。在一些实施例中，晶体硅覆盖层的生长发生在能够处理多个晶圆的多批次熔炉中。在一些实施例中，待处理的晶圆堆叠在熔炉内并暴露于化学氧化物去除(COR)工艺，该化学氧化物去除工艺去除硅外延层230和硅锗外延层400的顶表面上形成的本征氧化物。在一些实施例中，COR工艺使用混合了氨(NH3)的氢氟酸(HF)。一旦硅外延层230和硅锗外延层400的顶表面230S和400S分别不含本征氧化物，就开始晶体硅覆盖层的生长。在一些实施例中，二氯硅烷(SiH2Cl2或DSC)和氢(H2)用于在约300℃至400℃之间的温度下生长晶体硅覆盖层。图5示出了在硅外延层230和硅锗外延层400上生长的晶体硅覆盖层500。在一些实施例中，晶体硅覆盖层500具有与下面的硅外延层230和硅锗外延层400相同的晶学取向。例如，晶体硅覆盖层500的顶表面平行于(100)晶面。
在一些实施例中，晶体硅覆盖层500在鳍隔离区的形成期间保护硅外延层230和硅锗外延层400的顶表面免受氧化。根据一些实施例，晶体硅覆盖层500的厚度为约2nm。厚度小于2nm的晶体硅覆盖层不能提供足够的保护，以防止鳍氧化，而厚度大于2nm的晶体硅覆盖层则会降低晶体管的性能。这是因为，如之前所述，晶体硅覆盖层500不是牺牲性的，因此晶体硅覆盖层500成为晶体管结构的一部分。从而，晶体硅覆盖层500需要足够厚以防止鳍氧化，并且足够薄以不影响晶体管的性能。
在参考图1时，方法100继续进行操作150和形成鳍结构的工艺。如之前所述，可以通过任何合适的方法来图案化鳍结构。例如，可以使用包括双图案化工艺或多图案化工艺的一种或多种光刻工艺来图案化鳍结构。
双重图案化工艺或多重图案化工艺可以将光刻和自对准工艺相结合，从而允许创建的图案具有，例如，间距小于使用单个直接光刻工艺所能获得的间距。例如，在一些实施例中，在衬底上方形成牺牲层并使用光刻工艺将其图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且可以使用剩余的间隔件来图案化鳍结构。根据一些实施例，图6示出了用于形成鳍结构的最终图案化操作，其中，图案化层610和620设置在晶体硅覆盖层500上。在一些实施例中，图案化层610包括氧化硅并且图案化层620包括氮化硅(Si3N4)。
通过上述光刻工艺限定的图案化层610和620的尺寸依次限定了图7所示的鳍结构700和710的宽度W，长度L和间距。蚀刻工艺的持续时间可以用于限定鳍结构700和710的高度H。作为示例而非限制，宽度W可以在约5nm至约10nm的范围内，而鳍结构700和710的高度H可以在约35nm至约120nm的范围内。取决于随后的制造操作中垂直于鳍结构—例如，沿x方向—形成的栅极结构的数量，间距和尺寸来调节长度L。在一些实施例中，比如鳍结构700和710的附加鳍结构可以形成在衬底200的其他位置中，例如，邻近鳍结构700和710。
在一些实施例中，鳍结构700包括在n-型阱220上的硅锗外延层400，并且鳍结构710包括在p-型阱210上的硅外延层230。根据一些实施例，p-型finFET可以形成在具有硅锗沟道区的鳍结构700上，并且n-型finFET可以形成在具有硅沟道区的鳍结构710上。然而，这不是限制性的，并且p-型和n-型finFET可以形成在具有硅沟道区的鳍结构710上。
在参考图1时，方法100继续进行操作160和在鳍结构700和710之间沉积隔离材料的工艺。在参考图8时，沉积隔离材料包括位于鳍结构700和710的上方的衬层800的沉积。根据一些实施例，图8是沿着图7所示的切割线AB的鳍结构700和710的截面图。作为示例而非限制，衬层800用作隔离材料的粘合层。此外，衬层800作为鳍结构700和710的侧壁表面的保护层，以防止抗氧化。作为示例而非限制，衬层800可以通过诸如等离子体增强原子层沉积(PEALD)的共形的沉积工艺沉积，厚度为约3nm。作为示例而非限制，衬层800可以是氧化硅或基于氧化硅的介电材料。
随后，如图9所示，沉积隔离材料900(例如，主隔离材料)以围绕鳍结构700和710。在一些实施例中，隔离材料900沉积的厚度为900T，该厚度为鳍结构700和710的高度H的约3倍(例如900T～H×3)。例如，如果H为约120nm，则900T为约360nm。根据一些实施例，利用可流动的化学气相沉积工艺(例如，可流动的CVD)沉积隔离材料900，以确保隔离材料900填充鳍结构710和700之间的间隙而不会形成接缝或孔洞。在一些实施例中，隔离材料900是包括例如氮和氢的基于氧化硅的介电材料。为了进一步改善其介电和结构性能，隔离材料900在约800℃至1200℃之间的温度下经受湿蒸汽退火(例如100％水分子)。在湿蒸汽退火期间，隔离材料900致密化并且其氧含量可以增加。
根据一些实施例，晶体硅覆盖层500防止鳍结构700和710在“弱点”位置A的氧化，诸如在两个不同的晶体面相遇的鳍结构700和710的顶角-沿着鳍结构的顶表面的面(100)和沿着鳍的侧壁表面的面(110)。鳍结构700和710的顶角形成过渡点，在湿蒸汽退火期间，氧气可以扩散通过该过渡点并且氧化鳍结构700和710。在鳍结构700和710的顶表面上生长的晶体硅覆盖层500将弱点从位置A“重新定位”到位置B，并将其从鳍结构的顶表面“移开”。之所以能够实现这一点，是因为外延生长会复制下层的晶体结构(和取向)，例如，原子排列就好像它们是下面的晶体层的延续一样。在晶体硅覆盖层500和鳍结构700是异质外延生长的情况下，晶体硅覆盖层500将具有与下面的硅锗外延层400相同的对称性，但是由于硅锗底层和晶体硅覆盖层之间的晶格失配，晶体硅覆盖层500将具有与下面的硅锗外延层400不同硅原子之间的距离。然而，由于晶体硅覆盖层500的有限厚度(例如，约2nm)和鳍结构700的有限宽度(例如，约5nm和约10nm之间)，可以抑制与晶格失配有关的缺陷。
随后，如图10所示，CMP工艺抛光隔离材料900，直到暴露鳍结构700和710上的图案化层620。在一些实施例中，图案化层620用作上述CMP工艺的抛光停止层。如图11所示，CMP修整可以去除图案化层620并暴露出图案化层610。在一些实施例中，通过包括磷酸(H3PO4)的湿法蚀刻化学品来选择性地去除剩余的图案化层620。
在参考图1时，方法100继续进行操作170和如图12所示的相对于鳍结构700和710凹进隔离材料900的工艺。在一些实施例中，凹进操作还“后拉”衬层800。这是因为在隔离材料900的凹进工艺中使用的干法蚀刻化学品也对衬层800是选择性的。在一些实施例中，凹进工艺包括但不限于碳氟化合物化学品。作为上述凹进工艺的结果，鳍结构700和710的顶部被暴露，而底部仍保持嵌入在隔离材料900中。此外，在上述凹进操作期间，将去除在方法100中描述的任何氧化工艺期间在鳍结构700和710的侧壁上形成的任何氧化物。
根据一些实施例，图13是在其上形成栅极堆叠件1300之后的鳍结构700和710的局部等距视图。在一些实施例中，栅极堆叠件1300包括栅电极1310和插在栅电极1310和鳍结构700和710之间栅极介电质堆叠件1320。栅极堆叠件1300以及每个鳍结构700和710和相应的源极/漏极外延区(未示出)形成晶体管结构。例如，如上所述，在鳍结构700上形成的晶体管结构是p-型finFET，并且在鳍结构710上形成的晶体管结构是n-型finFET。在一些实施例中，用于鳍结构700的栅极堆叠件1300可以包括与用于鳍结构710的栅极堆叠件1300不同的金属层。
本文所述的实施例是针对一种用于在鳍隔离区的形成期间防止鳍氧化的方法。根据一些实施例，该方法包括在形成的鳍结构的顶表面上沉积晶体硅层作为覆盖层，以防止在隔离区的形成期间的鳍氧化。在一些实施例中，晶体硅覆盖层不是牺牲性的，并且可以被集成在晶体管结构中。在一些实施例中，晶体硅层外延生长约2nm的厚度，并具有平行于(100)硅晶面的顶表面。
在一些实施例中，半导体结构包括具有在半导体衬底上形成的第一鳍结构和第二鳍结构的半导体衬底。第一鳍结构包括第一外延层和比第一外延层薄的第二外延层。第二鳍结构包括不同于第一外延层和第二外延层的第三外延层，其中第二外延层比第三外延层薄。半导体结构还包括在第一鳍结构和第二鳍结构之间的隔离区。
在一些实施例中，半导体结构包括晶体衬底和具有形成在晶体衬底上的第一晶体鳍结构的第一晶体管结构。第一晶体鳍结构包括晶体衬底的p-掺杂区，外延生长在p-掺杂区上的硅层，和外延生长在硅层上的第一硅覆盖层。半导体结构还包括具有形成在晶体衬底上的第二晶体鳍结构的第二晶体管结构。第二晶体鳍结构包括晶体衬底的n-掺杂区，外延生长在n-掺杂区上的硅锗层，和外延生长在硅锗层上的第二硅覆盖层。另外，半导体结构包括形成在第一晶体鳍结构和第二晶体鳍结构之间的隔离堆叠件。
在一些实施例中，一种方法包括提供具有在半导体衬底的顶部上形成的n-掺杂区和p-掺杂区的半导体衬底；在p-掺杂区上外延生长第一层；在n-掺杂区上外延生长不同于第一层的第二层；在第一层和第二层的顶面上外延生长第三层，其中第三层比第一和第二层薄。该方法还包括蚀刻第一层，第二层和第三层以在半导体衬底上形成鳍结构，和在鳍结构之间形成隔离区域。
在一些实施例中，一种半导体结构，包括：半导体衬底；第一鳍结构，形成在所述半导体衬底上，第一鳍结构包括：第一外延层；和第二外延层，所述第二外延层比所述第一外延层薄；第二鳍结构，形成在所述半导体衬底上，所述第二鳍结构包括：第三外延层，不同于所述第一外延层；和第二外延层，其中，第二外延层比所述第三外延层薄；和隔离区，位于所述第一鳍结构和所述第二鳍结构之间。
在一些实施例中，第二外延层是具有约2nm的厚度的晶体硅覆盖层。在一些实施例中，第一外延层包括硅，并且第三外延层包括硅锗。在一些实施例中，第二外延层具有平行于(100)硅晶面的顶表面和平行于(110)晶面的侧壁表面。在一些实施例中，隔离区包括：衬层，设置在第一鳍结构和第二鳍结构的底部侧壁表面上；和介电材料，设置在衬层上以及第一鳍结构和第二鳍结构之间。在一些实施例中，第一鳍结构还包括设置在第一外延层下方的p-掺杂区。在一些实施例中，第二鳍结构还包括设置在第三外延层下方的n-掺杂区。在一些实施例中，第一鳍和第二鳍具有相等的高度和宽度。
在一些实施例中，一种半导体结构，包括：晶体衬底；第一晶体管结构，包括形成在晶体衬底上的第一晶体鳍结构，其中，第一晶体鳍结构包括：晶体衬底的p-掺杂区；硅层，外延生长在p-掺杂区上；和第一硅覆盖层，外延生长在硅层上；第二晶体管结构，包括形成在晶体衬底上的第二晶体鳍结构，其中，第二晶体鳍结构包括：晶体衬底的n-掺杂区；硅锗层，外延生长在n-掺杂区上；和第二硅覆盖层，外延生长在硅锗层上；和隔离堆叠件，形成在第一晶体鳍结构和第二晶体鳍结构之间。
在一些实施例中，第一硅覆盖层覆盖硅层的顶表面。在一些实施例中，第二硅覆盖层覆盖硅锗层的顶表面。在一些实施例中，第一硅覆盖层的侧壁表面与p-掺杂区和硅层的侧壁表面基本对准。在一些实施例中，第二硅覆盖层的侧壁表面与n-掺杂区和硅锗层的侧壁表面基本对准。在一些实施例中，第一硅覆盖层比硅层薄。在一些实施例中，第二硅覆盖层比硅锗层薄。在一些实施例中，第一硅覆盖层和第二硅覆盖层具有相同的厚度和晶体取向。
在一些实施例中，一种方法，包括：提供半导体衬底，半导体衬底的顶部上形成有n-掺杂区和p-掺杂区；在p-掺杂区上外延生长第一层；在n-掺杂区域上外延生长不同于第一层的第二层；在第一层和第二层的顶表面上外延生长第三层，其中，第三层比第一层和第二层薄；蚀刻第一层、第二层和第三层，以在半导体衬底上形成鳍结构；和在鳍结构之间形成隔离区。
在一些实施例中，蚀刻第一层、第二层和第三层包括蚀刻穿过半导体衬底的所述n-掺杂区和p-掺杂区。在一些实施例中，外延生长第三层包括在第二层上执行异质外延沉积。在一些实施例中，外延生长第三层包括生长硅层，硅层具有约2nm的厚度和平行于(100)晶面的顶表面。
应当理解，“详细描述”部分而不是本发明部分的“摘要”旨在用于解释权利要求。本发明部分的摘要可以阐述发明人所设想的本发明的一个或多个但不是所有可能的实施例，因此，无意以任何方式限制从属权利要求。
前述公开概述了几个实施例的特征，使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员将理解，他们可以容易地将本发明用作设计或修改其他工艺和结构的基础，以实现与本文介绍的实施例相同的目的和/或实现相同的优点。本领域技术人员还将认识到，这样的等效构造不脱离本公开的精神和范围，并且在不脱离本公开的精神和范围的情况下，它们可以在此进行各种改变，替换和变更。

Claims (10)

1.一种半导体结构，包括：
半导体衬底；
第一鳍结构，形成在所述半导体衬底上，所述第一鳍结构包括：
第一外延层；和
第二外延层，所述第二外延层比所述第一外延层薄；
第二鳍结构，形成在所述半导体衬底上，所述第二鳍结构包括：
第三外延层，不同于所述第一外延层；和
所述第二外延层，其中，所述第二外延层比所述第三外延层薄；和
隔离区，位于所述第一鳍结构和所述第二鳍结构之间。
2.根据权利要求1所述的半导体结构，其中，所述第二外延层是具有约2nm的厚度的晶体硅覆盖层。
3.根据权利要求1所述的半导体结构，其中，所述第一外延层包括硅，并且所述第三外延层包括硅锗。
4.根据权利要求1所述的半导体结构，其中所述第二外延层具有平行于(100)硅晶面的顶表面和平行于(110)晶面的侧壁表面。
5.根据权利要求1所述的半导体结构，其中，所述隔离区包括：
衬层，设置在所述第一鳍结构和所述第二鳍结构的底部和侧壁表面上；和
介电材料，设置在所述衬层上以及所述第一鳍结构和所述第二鳍结构之间。
6.根据权利要求1所述的半导体结构，其中，所述第一鳍结构还包括设置在所述第一外延层下方的p-掺杂区。
7.根据权利要求1所述的半导体结构，其中，所述第二鳍结构还包括设置在所述第三外延层下方的n-掺杂区。
8.根据权利要求1所述的半导体结构，其中，所述第一鳍结构和所述第二鳍结构具有相等的高度和宽度。
9.一种半导体结构，包括：
晶体衬底；
第一晶体管结构，包括形成在所述晶体衬底上的第一晶体鳍结构，其中，所述第一晶体鳍结构包括：
所述晶体衬底的p-掺杂区；
硅层，外延生长在所述p-掺杂区上；和
第一硅覆盖层，外延生长在所述硅层上；
第二晶体管结构，包括形成在所述晶体衬底上的第二晶体鳍结构，其中，所述第二晶体鳍结构包括：
所述晶体衬底的n-掺杂区；
硅锗层，外延生长在所述n-掺杂区上；和
第二硅覆盖层，外延生长在所述硅锗层上；和
隔离堆叠件，形成在所述第一晶体鳍结构和第二晶体鳍结构之间。
10.一种形成半导体结构的方法，包括：
提供半导体衬底，所述半导体衬底的顶部上形成有n-掺杂区和p-掺杂区；
在所述p-掺杂区上外延生长第一层；
在所述n-掺杂区域上外延生长不同于所述第一层的第二层；
在所述第一层和所述第二层的顶表面上外延生长第三层，其中，所述第三层比所述第一层和所述第二层薄；
蚀刻所述第一层、所述第二层和所述第三层，以在所述半导体衬底上形成鳍结构；和
在所述鳍结构之间形成隔离区。
CN202110074774.9A 2020-02-11 2021-01-20 半导体结构及其形成方法 Pending CN113257817A (zh)

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