TWI765396B - 超薄鰭式結構及其形成方法 - Google Patents
超薄鰭式結構及其形成方法 Download PDFInfo
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- TWI765396B TWI765396B TW109138177A TW109138177A TWI765396B TW I765396 B TWI765396 B TW I765396B TW 109138177 A TW109138177 A TW 109138177A TW 109138177 A TW109138177 A TW 109138177A TW I765396 B TWI765396 B TW I765396B
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Abstract
本揭示內容描述了一種用於形成具有漸縮底部輪廓的超薄鰭片的方法,以改善結構剛性和閘極控制特性。該方法包含形成鰭式結構,該鰭式結構包含磊晶層部分和被隔離區圍繞的摻雜區部分,使得磊晶層部分的頂部係在隔離區上方。該方法還包含在隔離區上方的磊晶層的頂部上沉積矽基層,並對矽基層進行退火以使矽基層迴焊。該方法還包含蝕刻在隔離區上方的矽基層和鰭式結構以在隔離區上方的鰭式結構中形成第一底部漸縮輪廓,並且對鰭式結構進行退火以在第一底部漸縮輪廓下方和隔離區上方形成第二底部漸縮輪廓。
Description
本發明實施例係有關半導體結構及其形成方法,尤指一種超薄鰭式結構及其形成方法。
鰭式場效電晶體(finFET)可以具有超薄鰭式結構,以改善通道區上的閘極控制。然而,在超薄鰭式結構之間的隔離區形成期間及/或在其他製造製程中,超薄鰭式結構易於彎曲或塌陷。這是因為超薄鰭式結構缺乏較厚鰭式結構的結構完整性。
本發明的一實施例係關於一種半導體結構,包含:一基板,該基板包含在其上形成的複數個基座結構;複數個鰭式結構,在該等基座結構上形成,並且包含:一底部漸縮部分,具有一底部寬度、一中間寬度和一頂部寬度,其中該中間寬度大於該底部寬度及該頂部寬度;及一上部部分,具有一實質上等於或小於該底部漸縮部分的該頂部寬度的一寬度;以及一隔離材料,置於該等基座結構之間。
本發明的一實施例係關於一種半導體結構,包含:一基板,該基板包含在其上形成的複數個基座結構;複數個鰭式結構,在該等基座結構上形成,並且包含一頂部部分、及寬於該頂部部分之一漸縮底部部分,其中該漸縮底部部分之各側壁與該鰭式結構的該頂部部分的側壁表面和該基座結構的側壁表面不共面;以及一隔離材料,位於該等基座結構之間。
一種半導體結構的形成方法,包含:於一基板的一摻雜區上沉積一磊晶層;圖案化該磊晶層和該摻雜區以形成一鰭式結構,該鰭式結構包含一磊晶層部分和一摻雜區部分;於該基板上形成一隔離區,使該磊晶層部分的一頂部部分位於該隔離區上方;於該隔離區上方的該磊晶層的該頂部部份上沉積一矽基層;對該矽基層進行退火以使該矽基層迴焊;蝕刻該隔離區上方的該矽基層和該鰭式結構,以在該隔離區上方的該鰭式結構中形成一第一底部漸縮輪廓;以及對該鰭式結構進行退火以在該第一底部漸縮輪廓下方和該隔離區上方形成一第二底部漸縮輪廓,其中該第一底部漸縮輪廓和第二底部漸縮輪廓共同形成一底部輪廓,該底部輪廓具有一頂部寬度、一中間寬度和一底部寬度的,及其中該中間寬度係大於該頂部寬度和該底部寬度中的各者。
以下揭示內容提供眾多不同的實施例或實例以用於實施本揭露內容之不同特徵。下文中描述組件及排列之特定實例以簡化本揭示內容。此等組件及排列當然僅為例示實施例,且不意欲進行限制。例如,在下文之描述中,第一特徵形成在第二特徵上方或之上可包含其中第一特徵與第二特徵以直接接觸方式形成的實施例,且亦可包含其中在第一特徵與第二特徵之間形成額外特徵而使得第一特徵與第二特徵必非直接接觸之實施例。此外,本揭示內容在多個實例中使用重複的元件符號及/或字母。此重複是為了簡化及清楚之目的,而非意指所論述的各個實施例及/或構造之間的關係。
此外,在此使用諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等空間相對用語用於簡化描述,以描述如附圖中所圖示的一個元件或特徵結構與其他元件或特徵結構的關係。該空間相對用語意欲涵蓋使用或操作中之元件在除了附圖描述的方向以外的不同方向。此裝置亦可被轉向(90°旋轉或其他方位),且本文使用的空間相對用語可據此作類似的解釋。
用語「標稱(nominal)」在此處是指在產品或製程的設計階段期間設定的組件或製程步驟的特性或參數的期望值或目標值,以及高於和/或低於所欲之數值的一範圍值。數值的範圍通常由於製造過程或公差(tolerances)的會有輕微變化。
在部分實施方式中,用語「約」與「實質上」可以指示在該值的5%內變化的給定量的值(例如,±1%、±2%、±3%、±4%與±5%的值)。這些數值僅為例示,並非意欲作為限制。本領域具有通常知識者根據本文的教導,可以將用語「約」與「實質上」解釋為數值的百分比。
在鰭式場效電晶體(finFETs)中使用的超薄鰭式結構(例如,具有在約5nm至約15nm之間的平均寬度)提供了改善通道區上的閘極控制,並減輕了與短通道效應相關的問題。由於這些理由,對於finFETs,使用超薄鰭式結構是有吸引力的。然而,與較厚的鰭式結構(例如厚度約大於20nm)相比,上述提到超薄鰭式結構的優點因本身有限的飽和電流(例如,由於其減少的寬度)而受到減損,並且缺乏結構剛性。例如,超薄鰭式結構在源自周圍層(例如介電質)及/或後續製造操作的機械應力下,可能易於彎曲或塌陷,例如緻密化製程會導致應力在超薄鰭式結構附近累積。
為了解決上述挑戰,本揭露內容涉及一種用於形成具有漸縮底部輪廓的超薄鰭式結構的方法,以改善結構剛性同時保持期望的閘極控制特性。在部分實施例中,可以使用本文描述的方法來製造矽和矽鍺(SiGe) 超薄鰭式結構。此外,可以在p型finFET中形成具有可變濃度的Ge和漸縮底部輪廓的SiGe鰭片,以改善在通道上的閘極控制和在超薄鰭式結構和閘極介電層堆疊之間的介面質量。
根據部分實施例,圖1A為具有底部漸縮輪廓105的超薄鰭式結構100(鰭式結構100)的局部等角視圖,其實質上改善了鰭式結構100的結構剛性。在部分實施例中,在形成未示於圖1中的閘極堆疊之前,在基板115的基座結構110上形成鰭式結構100。
鰭式結構100具有在大約5nm至大約15nm之間的頂部寬度W和在大約40nm至大約70nm之間的總高度H。各個鰭式結構100的高度H是從鰭式結構100和基板115的基座結構110之間的界面測量的,並且包含高度B,其對應於底部漸縮輪廓105的總高度和高度A-在底部漸縮輪廓105上方鰭式結構100的高度。在部分實施例中,高度H實質上等於高度A和B之和(例如,H=A+B),如圖1A所示。在部分實施例中,高度A是介於高度H的大約80%至大約90%之間(例如,80%H≤A≤90%H),高度B是介於高度H的大約10%至大約20%之間(例如,10%H≤B≤20%H)。例如,如果H是介於大約40nm至大約70nm之間,則高度A是介於大約32nm至大約63nm之間,並且高度B(例如,底部漸縮輪廓105的高度) 是介於大約4nm至大約14nm之間。
在部分實施例中,如果高度B小於高度H的大約10%,則底部漸縮輪廓105可能會不夠厚的足以在結構上支撐鰭式結構100。例如,如果高度B小於約10%的高度H。鰭式結構100可能變得易於彎曲或塌陷。另一方面,如果高度B大於約20%的高度H(例如,如果底部漸縮輪廓105佔據鰭式結構100的較大部分),則可以限制底部漸縮輪廓105附近的通道控制。因此,鰭式結構100中的底部漸縮輪廓105的尺寸(例如,高度B)需要被調整,以使得鰭式結構100在機械剛性和電性能之間展現出最佳的平衡。
如圖1A所示,鰭式結構100被隔離材料120隔離,隔離材料120包含介電質材料,諸如氧化矽、含碳的氧化矽、含氫和氮的氧化矽,或任何其他合適的絕緣材料或絕緣層。
基座結構110可以由基板115形成並且可以包含未示於圖1A中的一個或多個摻雜區。例如,基座結構110的頂部部分(例如,在底部漸縮輪廓105下方)可以摻雜有n型或p型摻雜劑,以防止在finFET操作期間鰭式結構100和基板115之間的洩漏電流。在部分實施例中,基板115是一整體半導體晶片或絕緣層上半導體(SOI)晶片的一頂層,例如絕緣體上覆矽。此外,基板115可以由矽或另一種元素的半導體所製成,例如,(i)鍺(Ge);(ii)包含碳化矽(SiC)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)和/或銻化銦(InSb)的化合物半導體;(iii)包含磷砷化鎵(GaAsP)、砷銦化鋁(AlInAs)、砷鎵化鋁(AlGaAs)、砷銦化鎵(GaInAs)、磷銦化鎵(GaInP) 和/或磷砷銦化鎵(GaInAsP)的合金半導體;或(iv)其組合。在部分實施例中,基板115具有晶體微結構,例如其並不是非晶態或多晶態。
出於例示性的目的,基板115和基座結構110將在其頂部表面平行於(100)晶面的晶體矽(Si)的背景下進行描述。基於本文的揭露內容,可以使用如上所述的其他材料或晶體取向,且這些材料在本揭露的精神和範圍內。
根據部分實施例,如圖1A所示,鰭式結構100的底部漸縮輪廓105係形成在隔離材料120的頂部表面上方。
在部分實施例中,鰭式結構100可以包含單個磊晶層或磊晶層的堆疊。例如,鰭式結構100可以包含單個Si磊晶層125(如圖1A所示),單個SiGe磊晶層130(如圖1B所示),或SiGe磊晶層135、140和145的堆疊(如圖1C所示)。在部分實施例中,具有單個Si磊晶層125的鰭式結構100 (如圖1A所示)適合於n型finFETs(例如nFETs)。具有單個SiGe磊晶層130或SiGe磊晶層135、140和145的堆疊的鰭式結構100 (如圖1B和1C所示)適合於p型finFETs(例如pFETs)。在部分實施例中,用於nFETs和pFETs的鰭式結構100(如圖1A-C所示)都可以本文描述的方法形成在同一基板(例如基板115)上形成。
在部分實施例中,如圖1B所示,複數個鰭式結構100為從單個SiGe磊晶層130所製成的pFET鰭式結構。其具有隨高度H以函數變化的原子百分比(at. %)的Ge原子濃度。例如,請參考圖1B,單個SiGe磊晶層130具有隨鰭式結構100的高度A從約10%原子百分比(at. %)至約25%原子百分比變化的鍺濃度,以及隨底部漸縮輪廓105的高度B從約25%原子百分比至約35%原子百分比變化的鍺濃度。在部分實施例中,在由高度A界定的區域內的鍺「峰值(peak)」濃度朝向高度A的底部被定位,例如,在由高度HG
限定的鰭式結構100的區域內,在底部漸縮輪廓105的上方。在部分實施例中,高度HG
係介於鰭式結構100的高度H的約1/3和2/3之間。例如,如果鰭片總高度H為約60nm,則高度HG
可以在約20nm和約40nm之間。
在部分實施例中,圖1D顯示Ge原子百分比隨著圖1B所示的鰭式結構的高度H以函數變化。如前關於圖1B所討論的,在高度A的「邊界」內,峰值Ge原子百分比可在由高度HG
限定的鰭式結構100的區域內可以發現,該高度在鰭式結構100的高度H的約1/3和2/3之間延伸。此外,如前關於圖1D所示和所討論的,在底部漸縮輪廓105內的(例如,沿著高度B)Ge原子百分比甚至還可以更高。透過調整沉積製程的條件,圖1D所示的Ge原子百分比的輪廓可在SiGe磊晶層的生成過程中被實現,其將在後面討論到。
在部分實施例中,與圖1D所示相似的Ge原子百分比輪廓可以由如圖1C所示的包含SiGe磊晶層135、140和145的的鰭式結構100實現。例如,可以不同Ge濃度的生長SiGe磊晶層135、140和145,其複製圖1D所示的Ge輪廓。作為示例而非以此為限制,磊晶層145可以以最低的Ge濃度生長,磊晶層140可以以大於磊晶層145的Ge濃度且以厚度等於大約高度HG
的厚度生長,並且磊晶層135可以大於磊晶層140的Ge濃度並且厚度等於大約高度B生長以形成底部漸縮輪廓105。SiGe磊晶層135、140和145的上述描述不是限制性的,並且可以形成具有兩層取代三層的堆疊。例如,SiGe磊晶層135和140可以結合成單個SiGe磊晶層。附加的SiGe磊晶層也是可能的,並且在本揭露的精神和範圍內。
在部分實施例中,圖2和圖3為包含在圖1A之矩形150中的結構元件的放大截面圖。圖2和圖3所示的特徵同樣適用於圖1B和圖1C所示的鰭式結構100。請參考圖2,底部漸縮輪廓105具有介於約5nm至約15nm之間的頂部寬度Wt,介於約8nm至約20nm之間的中間寬度Wm,以及介於約7nm至18nm之間的底部寬度Wb。在部分實施例中,寬度Wb大於寬度Wt,且寬度Wm大於寬度Wt和寬度Wb,例如Wm>Wb>Wt。在部分實施例中,Wt/Wm之比例介於約0.25至約0.75之間(例如,0.25≤Wt/Wm≤0.75);且Wb/Wm之比例介於約0.35至約0.90之間(例如,0.35≤Wb/Wm≤0.90)。在部分實施例中,Wt/Wm和Wb/Wm之比例分別小於約0.25和0.25,可以在鰭式結構100的漸縮區域中以有限的通道控制產生誇大的漸縮輪廓。在部分實施例中,Wt/Wm和Wb/Wm之比例分別大於約0.75和0.90,可以產生無法為鰭式結構100提供足夠的結構支撐的漸縮輪廓。在部分實施例中,底部漸縮輪廓105的寬度Wt實質上等於或大於圖1所示的鰭式結構100的頂部寬度W(例如Wt ≥ W)。因此,鰭式結構100在鰭式結構100的頂部處可能是狹窄的,並且沿著高度A的寬度增加(例如,W<Wt)。在部分實施例中,沿著高度A的鰭式結構100的寬度是恆定的(例如W=Wt),且在底部漸縮輪廓105的高度B內增加。
在部分實施例中,底部漸縮輪廓105的寬度Wm與基座結構110和鰭式結構100之間的界面間隔大約1nm至約3nm之範圍間的垂直距離C。在部分實施例中,垂直距離C介於高度B(例如,底部漸縮輪廓105的整體高度)的約1/3至約1/2之間。在部分實施例中,低於大約1/3的C/B比將「移動(move)」Wm使其更接近Wb。對於閘極層的沉積,這將產生具有挑戰性的幾何形狀。例如,在Wm和Wb之間的底部漸縮輪廓105的部分上共形地沉積閘極層(例如,high-k介電層,功函數層等)將具有挑戰性,這可能導致在FETs之間非預期的閾值電壓變化。另一方面,高於大約1/2的C/B比將「移動」Wm使其更接近Wt,這將削弱鰭式結構100的結構完整性。
在部分實施例中,基座結構110與鰭式結構100的界面以大約4nm至大約15nm之範圍間的垂直距離D位於隔離材料120的頂部表面上方。
如前所討論,鰭式結構100沿著高度H具有寬和窄部分,以改善其結構剛性。然而,在同樣的閘極偏壓條件下,對於鰭式結構100較寬部分(例如位於Wt、Wm和Wb的位置)的閘極控制可能是具有挑戰性的。根據部分實施例,Ge濃度可用於「局部(locally)」減少鰭式結構100的較寬部分上的Vt並改善閘極控制。這是因為,Ge具有比Si較窄的能隙;因此,與具有較低Ge濃度的區域相比(例如,在鰭式結構100的頂部),具有較高鍺濃度的區(例如,在由高度HG
與底部漸縮輪廓定義的區域)可以具有較低的Vt。因此,增加鰭式結構100的較寬部分的Ge濃度,有效地降低較寬部分內的Vt,且改善通道上的閘極控制。根據部分實施例,在鰭式結構中調整Ge濃度對於finFET的操作是有益的,並確保沿著鰭式結構100的高度H實質上恆定的飽和電流。在部分實施例中,鰭式結構100中富含Ge的區域中的Ge濃度可達到約50%。
根據部分實施例,圖2所示的底部漸縮輪廓105的寬度Wm為用於調整鰭式結構100結構剛性的關鍵結構參數。如前所討論,寬度Wm的範圍從約8nm至約20nm。若寬度Wm小於約8nm,底部漸縮輪廓105的寬度則不足以為鰭式結構100提供足夠的結構支撐。相對地,如果寬度Wm大於約20nm,則即使具有較高的Ge濃度,底部漸縮輪廓105內的通道控制也變得具有挑戰性。
在部分實施例中,透過在圖3中所示的底部漸縮輪廓105的各側上的角度θ1
和θ2
提供寬度Wm的控制。在部分實施例中,約10度至約30度之間的角度θ1
和θ2
提供約8nm至約20nm之間的寬度Wm。因此,小於約10°的角度θ1
和θ2
導致小於約8nm的寬度Wm,而大於約30°的角度θ1
和θ2
導致大於約20nm的寬度Wm。在部分實施例中,透過在鰭式結構100的形成期間和之後使用的蝕刻和退火條件來控制中間寬度Wm以及角度θ1
和θ2
。在部分實施例中,角度θ3
在約120度至約160度的範圍內。
在部分實施例中,角度θ1
和θ2
防止底部漸縮輪廓105的側壁部分與底部漸縮輪廓105上方和下方的鰭式結構100的側壁部分共面。此外,角度θ1
和θ2
防止底部漸縮輪廓105的側壁部分與基座結構110的側壁部分共面,如圖3所示。
圖4為用以形成如圖1所示的鰭式結構100的製造方法的流程圖,可以在方法400的各種操作之間執行其他製造操作,並且僅為了清楚和便於描述可以將其省略。該些各種操作在本揭露的精神和範圍內。另外,可能不需要所有操作來執行本文提供的揭露內容。部分操作可以同時執行,或者以與圖4所示順序不同的順序執行。在部分實施例中,除了當前描述的步驟之外或取代當前描述的操作,可以執行一個或多個其他操作。將參考圖5至圖10描述方法400。提供用於描述方法400的附圖僅出於說明性目的,並且可能未按比例繪製。此外,這些圖可能無法反映真實結構,特徵或薄膜的實際幾何形狀。為了說明的目的,部分結構,薄膜或幾何形狀可能已經刻意增加或省略。
請參考圖4,方法400開始於操作405和在基板的p型區上沉積Si磊晶層的製程,該基板例如圖1A所示的基板115。作為例示而非限制,並且根據方法400的操作405,如圖5所示,可以在基板115的p型區500上直接生長Si磊晶層125。p型區500可以被形成,例如,可以透過使用諸如硼(B)之類的p型摻雜劑的離子植入製程來形成p型區500,並且其摻雜劑濃度在大約5×1016
atom/cm3
至大約1×1019
atom/cm3
的範圍內。可以使用化學氣相沉積(CVD)製程將Si磊晶層125生長至約30nm至約100nm之間的厚度。用於Si磊晶形成的原料氣體可包含矽烷(SiH4
)、四氯化矽(SiCl4
)、三氯矽烷(TCS)或二氯矽烷(SiH2
Cl2
或DSC)。 氫氣(H2
)可用作減少上述原料氣體的反應氣體。磊晶層生長期間的沉積溫度可以在約700℃至約1250℃的範圍內,這取決於所使用的氣體。例如,具有更少氯原子的原料氣體(例如,DSC)可能需要比具有更多氯原子的原料氣體(例如,SiCl4
或TCS)更低的形成溫度。前述氣體的範圍和類型僅作為例示提供,而非限制性的。
請參考圖4,方法400以操作410和對Si磊晶層125和p型區500進行圖案化以繼續在基板115上形成鰭式結構的製程。在部分實施例中,使用圖5所示的硬式光罩結構505透過光刻和蝕刻操作來對Si磊晶層125和p型區500進行圖案化。在部分實施例中,硬式光罩結構505用作蝕刻光罩,並且可以包含一層或多層,例如氧化矽和氮化矽。鰭式結構可以透過任何合適的方法來圖案化。例如,可以使用一種或多種光刻製程來圖案化鰭式結構,所述光刻製程包含雙圖案化製程或多圖案化製程。雙圖案化製程或多圖案化製程可以將光刻製程和自對準製程相結合,從而允許創建圖案,例如,其間距小於使用單個、直接光刻製程所能獲得的間距。在部分實施例中,在基板上方形成犧牲層並使用光刻製程對其進行圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物。然後去除犧牲層,然後可以使用剩餘的間隔物來圖案化鰭式結構。根據部分實施例,圖5示出了用於形成鰭式結構的最終圖案化操作,其中,硬式光罩結構505可以是設置在Si磊晶層125上的其餘間隔物。
根據部分實施例,圖6示出了根據上述操作410形成的所得鰭式結構100。可以根據操作410透過使用附加的硬式光罩結構在基板115上形成附加的鰭式結構100。在部分實施例中,沿y軸和x軸的硬式光罩結構505的寬度和長度界定了圖6中所示的鰭式結構100的寬度和長度。此外,硬式光罩結構505之間的間隔界定鰭式結構100之間的間隔。因此,透過控制硬式光罩結構505的尺寸,可以界定鰭式結構100的尺寸。在部分實施例中,在操作410之後,鰭式結構100的寬度W’在大約7nm至大約18nm之間,其可以與圖2所示的Wb相似或厚於Wb。
請參考圖4,方法400繼續操作415和在鰭式結構100之間沉積隔離材料的製程。沉積隔離材料包含在鰭式結構100上方沉積襯層600,如圖6所示。作為例示而非限制,襯層600用作隔離材料的粘合層。作為例示而非限制,襯層600可以透過共形沉積製程(諸如等離子體增強的原子層沉積(PEALD))以大約2nm至4nm之間的厚度沉積。作為例示而非限制,襯層600可以是氧化矽或基於氧化矽的介電材料。
接著,如圖6所示,將隔離材料120沉積以包圍鰭式結構100。在部分實施例中,隔離材料120以圖1A所示的鰭式結構100的高度H的大約3倍的厚度沉積。根據部分實施例,利用可流動的化學氣相沉積製程(例如,可流動的CVD)沉積隔離材料120,以確保隔離材料120填充鰭式結構100之間的空間而不會形成接縫或空隙。在部分實施例中,隔離材料120是包含例如氮和氫的基於氧化矽的介電材料。為了進一步改善其介電和結構特性,隔離材料120可以在約600℃至1200℃之間的溫度下經受濕蒸汽退火(例如100%水分子)。在濕蒸汽退火期間,隔離材料120緻密化並且其含氧量增加。
接著,化學機械平坦化(CMP)製程拋光隔離材料120,直到暴露鰭式結構100的頂部表面。在前述CMP製程期間,去除了鰭式結構100的頂部表面上的襯層600的部分。如圖7所示,乾蝕刻製程會「拉回(pulls back)」(例如選擇性蝕刻)襯層600和隔離材料120,以暴露鰭式結構100的頂部。這是因為在隔離材料120的蝕刻製程中使用的氣體化學成分對襯層600也是選擇性的。在部分實施例中,蝕刻製程包含但不限於碳氟化合物化學。作為上述蝕刻製程的結果,鰭式結構100的頂部部分被暴露,而底部部分仍保持嵌入隔離材料120中。在部分實施例中,蝕刻隔離材料120,使得凹陷的隔離材料120的頂部表面與基座結構110和Si磊晶層125之間的界面間隔垂直距離R。在部分實施例中,垂直距離R基本上等於圖2所示的垂直距離C(例如,在大約1nm和3nm之間)。換句話說,隔離材料120被蝕刻到大約如圖2所示的寬度Wm的水平。
請參考圖4,方法400繼續進行操作420和「修整(trimming)」(例如蝕刻)鰭式結構100的矽磊晶層125的側壁的製程,該側壁未被隔離材料120覆蓋,例如,通過修整鰭式結構100的暴露部分。在部分實施例中,修整(例如,蝕刻)矽磊晶層125的側壁包含在矽磊晶層125上選擇性地沉積矽基層,迴焊矽基層,使得矽基層在鰭式結構的頂部變薄,並且朝著鰭式結構100的底部變厚,隨後蝕刻矽基層和矽磊晶層125以形成初始或第一漸縮輪廓。
在部分實施例中,矽基層是矽磊晶層,該矽磊晶層以共形方式選擇性地沉積在鰭式結構100的頂部表面和側壁表面上,厚度在約1nm至約2nm之間。其結果是,矽基材料不會在隔離材料120上生長。在部分實施例中,兩階段退火製程包含在約600℃至約700℃之間的溫度下預浸泡約10秒至30秒。接著在約800°C和約1000°C之間的溫度下進行突發式退火約1ms。迴焊製程被配置為在鰭式結構100上重新分佈矽基材料。在部分實施例中,在鰭式結構100的頂部和底部之間重新分佈約0.5nm至約1nm的矽基材料。例如,在迴焊製程之後,基於矽基層的厚度可以在鰭式結構100的底部為約3nm,並且在鰭式結構100的頂部為約1nm。圖7示出了在上述沉積和迴焊製程之後的矽基層700。
對矽基層700和矽磊晶層125有選擇性的後續刻蝕製程開始去除矽基層700。由於在迴焊製程之後矽基層700的非共形分佈,鰭式結構100頂部的矽磊晶層125比鰭式結構100底部的矽磊晶層125更早地暴露於蝕刻化學物質,其中矽基層係較厚的。因此,鰭式結構100的頂部部分比底部部分暴露於蝕刻化學物質的時間更長。就蝕刻化學物質的這種刻意暴露時間差會反應在鰭式結構100中初始或第一漸縮輪廓的形成。所得出的鰭式結構100在圖8中所示。作為例示而非限制,鰭式結構100在如圖8所示的蝕刻製程之後形成圓形的頂角。此外,在蝕刻製程之後,頂部寬度W”與圖6所示的初始頂部寬度W'相比係變窄了(例如,W”<W)。在部分實施例中,W”可以實質上等於或約大於圖1A中所示的W(例如,W”≥W)。
在部分實施例中,較厚的矽基層(例如,厚於約2nm)和較長的迴焊時間可用於產生更明顯的漸縮輪廓(例如,具有較大寬度Wm的底部漸縮輪廓)。然而,這樣的條件會實質地增加總體處理時間和製造成本。另一方面,較薄的矽基層(例如,薄於約2nm)可能不會產生期望的漸縮輪廓(例如,頂部和底部寬度之間的期望的差)。
在部分實施例中,矽基層的厚度和迴焊條件(例如,退火持續時間和溫度)可用於調整鰭式結構100上的頂部和底部側壁覆蓋範圍之間的厚度差並產生所需的漸縮輪廓。更具體地說,上述製程可用於定義圖3中所示的角度θ1
。此外,在部分實施例中,可重複操作420以微調鰭式結構100的所需初始漸縮輪廓和頂部寬度。
在部分實施例中,上述蝕刻製程包含濕式蝕刻和乾式蝕刻的組合。在部分實施例中,濕式蝕刻製程用於主蝕刻(例如,以修整鰭式結構100),而乾式蝕刻製程用於去除在主蝕刻期間形成的副產物。在部分實施例中,蝕刻製程從鰭式結構100去除約10%至20%的矽磊晶材料(例如,在約4nm至約7nm之間)。作為例示而非限制,濕式蝕刻化學可包含稀鹽酸(dHF),氫氧化氨(NH4
OH)和水。乾式蝕刻製程可以包含例如臭氧(O3)等離子體。在部分實施例中,濕式蝕刻製程是等向性的,以確保在主蝕刻期間從所有方向的蝕刻均勻性。
請參考圖4,方法400繼續操作425並且在修整的鰭式結構100上沉積氧化物層。例如,並且在參考圖9中,可以沉積氧化物層900以覆蓋修整的鰭式結構100的頂部和側壁表面和隔離材料120的頂部表面。作為例示而非限制,氧化物層900可以是犧牲閘極氧化物層,例如厚度在大約2nm與大約5nm之間的氧化矽層或氮氧化矽層。在隨後的步驟中,用包含具有高介電常數(例如,介電常數大於約3.9)的材料的閘極介電堆疊代替氧化物層900。
請參考圖4,方法400繼續操作430和執行退火和形成如圖10所示的第二漸縮輪廓的製程。更具體地說,操作430的退火製程界定如圖3所示的角度θ2
和θ3
。這是因為,在操作430的退火製程中,由於來自氧化物層900,襯層600和隔離材料120的氧氣的可用性,鰭式結構100被部分氧化,如圖9中的短黑色箭頭905和長黑色箭頭910所示。由於襯層600和隔離材料120的總厚度大於氧化物層900的厚度,所以對於鰭式結構100被襯層600和隔離材料120覆蓋的部分,比由氧化物層900覆蓋的鰭式結構100的部分更多的氧可用於氧化。因此,由襯層600和隔離材料120覆蓋的鰭式結構100的部分將比由氧化物層900覆蓋的鰭式結構100的部分更多地被氧化。因此,與在由氧化物層900覆蓋的鰭式結構100的部分上相比,在鰭式結構100的襯層600和隔離材料120覆蓋的部分上形成更厚的氧化物將消耗更多來自鰭式結構100的矽材料。同時,在前述退火製程中,隔離材料120如白色箭頭915所示收縮。因此,隔離材料120的高度減少並且隔離材料120有效地凹陷以露出如圖10所示的底部漸縮輪廓105。
在部分實施例中,退火製程類似於關於操作420中的矽基層700的迴焊討論的退火製程。但是,差異在於,例如,在步驟430中,根據部分實施例,突發式退火的溫度範圍可以更大,例如,在大約700℃與大約1100℃之間。另外,在步驟430中的退火製程期間的氧濃度高於在步驟420中描述的退火製程的氧濃度。在部分實施例中,由襯層600和隔離材料120覆蓋的鰭式結構100的部分氧化也可能在如前述關於步驟420中的矽基層700的迴焊所討論的退火製程期間發生。類似地,隔離材料120也可以在步驟430中的退火製程期間凹陷。
基於在操作430中描述的前述氧化製程,如圖10中的虛線圓1000所示的底部漸縮輪廓105的下部上的氧化物層900的部分係生長得比在底部漸縮輪廓105上方的氧化物層900的部分更厚。這是由於在襯層600和隔離材料120附近存在額外的氧,其增強了該區中的氧化反應。同時,隨著隔離材料120相對於鰭式結構100收縮和凹陷,由於透過隔離材料120的凹陷作用去除了氧源,氧化物層900的生長減慢了。因此,底部漸縮輪廓105透過如上所述的蝕刻和氧化製程的組合而形成。
根據部分實施例,可以透過操作430的退火條件來調變圖3中所示的角度θ2
。例如,增加退火溫度(例如,將退火溫度設定為接近約1100℃)及/或退火時間,允許氧化物層900如上所述在鰭式結構100的底部繼續生長。較厚的氧化物層900意味著來自鰭式結構100的Si磊晶層125的消耗更大,其導致更大的θ2
和寬度Wm以及更窄的θ3
。相對地,接近700℃的退火溫度及/或更短的退火時間將產生更薄的氧化物層和更低的Si磊晶層125的消耗,其導致更小的θ2
和寬度Wm以及更寬的θ3
。為了便於描述,氧化物層900和襯層600未於圖1A-1C,圖2和圖3中示出。
在部分實施例中,在操作430之後,如圖10所示,在鰭式結構100上沉積犧牲閘極電極1005。在部分實施例中,犧牲閘極電極1005沒有沿著x方向覆蓋鰭式結構100的整個長度。例如,犧牲閘極電極1005覆蓋鰭式結構100的中間部分,而其餘鰭式結構100暴露。此外,在操作430之後,鰭式結構100的寬度W實質上不改變。在部分實施例中,在操作420和425期間,由於上述蝕刻和退火製程,鰭式結構100的高度從操作410開始連續減小。
在部分實施例中,從氧化物層900(例如,優先選擇對氧化物層900的蝕刻製程)剝離鰭式結構100的暴露部分(例如,鰭式結構100的未被犧牲閘極電極1005覆蓋的部分),並且在其上生長源極/汲極磊晶結構如圖11所示。在部分實施例中,源極/汲極磊晶結構1100是從每個鰭式結構100生長的兩個或更多個磊晶層形成的合併的源極/汲極磊晶結構。在生長的最後階段,兩個或多個磊晶層被允許合併並形成如圖11所示的源極/汲極磊晶結構1100。在部分實施例中,源極/汲極磊晶結構1100包含用於p型finFET的SiGe和用於n型finFET的碳摻雜的Si(Si:C)。
方法400亦可用於形成如圖1B和1C所示的SiGe鰭式結構。例如,在操作405中,可以在基板115的n型區上形成單個SiGe磊晶層或SiGe磊晶層堆疊,以形成如圖1B和1C所示的鰭式結構100。如上所述,其適用於p型finFETs。在部分實施例中,SiGe磊晶層係使用異質磊晶製程生長,例如CVD製程。作為例示而非限制,用於單個SiGe磊晶層或SiGe磊晶堆疊生長的前驅氣體可包含(i)SiH4
,矽乙烷(Si2
H6
)、SiH2
Cl2
、鍺烷(GeH4
)或鹽酸(HCl)和(ii)氫氣(H2
)、氮氣(N2
)或氬氣(Ar)的組合。在部分實施例中,可以在生長SiGe磊晶層之前沉積的緩衝層(未示出)以抑制由於生長的SiGe與下面的基板115之間的晶格不匹配導致的生長缺陷。此外,可以在生長SiGe磊晶層之前對基板115進行預處理,以去除在其上形成的自然氧化物層。
作為例示而非限制,生長期間,可以透過GeH4
的分壓(partial pressure)和其他氣體(如SiH4
、Si2
H6
和SiH2
Cl2
)的分壓來調節生長期間的Ge濃度。例如,生長期間GeH4
的較高分壓或SiH4
、Si2
H6
或SiH2
Cl2
的較低分壓有利於具有較高Ge濃度的SiGe層。GeH4
的較低分壓或SiH4
、Si2
H6
或SiH2
Cl2
的較高分壓有利於具有較低Ge濃度的SiGe層。
根據本公開的各種實施例描述了一種用於形成具有漸縮底部輪廓的超薄鰭片的方法,以改善結構剛性和期望的閘極控制特性。在部分實施例中,可以使用本文描述的方法來製造Si和SiGe超薄鰭片。此外,可以在p型finFETs中形成具有可變Ge濃度和漸縮底部輪廓的SiGe鰭片,以改善對通道的閘極控制。在部分實施例中,SiGe鰭式結構的可變Ge濃度在約10%至約35%的範圍內,越朝向鰭式結構的底部越具有較高的Ge濃度。在部分實施例中,超薄鰭式結構的頂部寬度在約5nm至約15nm之間,而漸縮底部輪廓的寬度在約8nm至約20nm之間。在部分實施例中,透過在圖案化的鰭式結構上沉積和迴焊矽基層,然後以濕式蝕刻和乾式蝕刻製程的組合修整鰭式結構,可以實現第一漸縮輪廓。在部分實施例中,透過在鰭片的修整部分上沉積氧化物層並使鰭式結構經受退火製程來形成第二漸縮輪廓,使該退火製程使鰭式結構的底部比鰭式結構的頂部氧化得更多。
在部分實施例中,半導體結構包含基板,該基板包含在其上形成的基座結構以及在該基座結構上形成的鰭式結構。鰭式結構還包含底部漸縮部分,該底部漸縮部分具有底部寬度,中間寬度和頂部寬度,該中間寬度大於底部寬度和頂部寬度。鰭式結構還包含上部部分,該上部部分的寬度實質上等於或小於底部漸縮部分的頂部寬度。此外,半導體結構包含設置在基座結構之間的隔離材料。
在部分實施例中,半導體結構包含基板,該基板包含在其上形成的基座結構以及在該基座結構上形成的鰭式結構。鰭式結構還包含頂部部分和比頂部部分寬的漸縮底部部分,其中,漸縮底部部分的各側壁與鰭式結構的頂部部分的側壁表面和基座結構的側壁表面不共面。此外,半導體結構包含設置在基座結構之間的隔離材料。
在部分實施例中,一種方法,包含在基板的摻雜區上沉積磊晶層;圖案化磊晶層和摻雜區以形成鰭式結構,該鰭式結構包含磊晶層部分和摻雜區部分。該方法更包含在基板上形成隔離區,使得磊晶層的頂部部分在隔離區上方;在隔離區上方的磊晶層的頂部上沉積矽基層;對矽基層進行退火以使矽基層迴焊;及在隔離區上方蝕刻矽基層和鰭式結構,以在隔離區上方的鰭式結構中形成第一底部漸縮輪廓。該方法更包含使鰭式結構退火以在第一底部漸縮輪廓下方和隔離區上方形成第二底部漸縮輪廓,使得第一底部漸縮輪廓和第二底部漸縮輪廓共同形成具有頂部寬度,中間寬度和底部寬度的底部輪廓。其中中間寬度大於頂部和底部寬度中的各者。
應當理解,詳細描述的部分(不是揭示內容的摘要)旨在用於解釋請求項。揭示內容的摘要部分可能敘述本揭示內容的發明人所思量的一或多個但不是所有的可能實施方式,因此,並不旨在以任何方式限制所附的請求項。
以上概述了數個實施方式的特徵,以便本領域具有通常知識者可較佳地理解本揭示內容的各方面。本領域具有通常知識者將理解,他們可能容易地使用本揭示內容,作為其他製程和結構之設計或修改的基礎,以實現與在此介紹的實施方式之相同的目的,及/或達到相同的優點。本領域具有通常知識者亦會理解,與這些均等的建構不脫離本揭示內容的精神和範圍,並且他們可能在不脫離本揭示內容的精神和範圍的情況下,進行各種改變、替換、和變更。
100:鰭式結構
105:底部漸縮輪廓
110:基座結構
115:基板
120:隔離材料
125:Si磊晶層/矽磊晶層
130:SiGe磊晶層
135:SiGe磊晶層
140:SiGe磊晶層
145:SiGe磊晶層
150:矩形
400:方法
405:操作
410:操作
415:操作
420:操作
425:操作
430:操作
500:p型區
505:硬式光罩結構
600:襯層
700:矽基層
900:氧化物層
905:短黑色箭頭
910:長黑色箭頭
915:白色箭頭
1000:虛線圓
1005:犧牲閘極電極
1100:源極/汲極磊晶結構
A:高度
B:高度
C:垂直距離
D:垂直距離
H:高度
HG
:高度
R:垂直距離
W:寬度
W’:寬度
W’’:頂部寬度
Wt:頂部寬度
Wm:中間寬度
Wb:底部寬度
θ1
:角度
θ2
:角度
θ3
:角度
當結合隨附圖式進行閱讀時,本發明揭露實施例之詳細描述將能被充分地理解。應注意,根據該業界的慣例,各特徵並非按比例繪製且僅用於圖示目的。事實上,為了清楚地說明和討論,可任意增加或減小各特徵之尺寸。
圖1A為根據部分實施例之由矽磊晶層製成具有漸縮底部輪廓之鰭式結構的等角視圖。
圖1B為根據部分實施例之由矽鍺磊晶層製成具有漸縮底部輪廓之鰭式結構的等角視圖。
圖1C為根據部分實施例之由矽磊晶堆疊製成具有漸縮底部輪廓之鰭式結構的等角視圖。
圖1D為根據部分實施例之沿著由單矽鍺磊晶層或矽鍺磊晶堆疊製成具有漸縮底部輪廓之鰭式結構的鍺濃度圖。
圖2和圖3為具有漸縮底部輪廓之鰭式結構的局部截面圖。
圖4為根據部分實施例之形成具有漸縮底部輪廓之鰭式結構的製造方法的流程圖。
圖5至圖10為根據部分實施例之具有漸縮底部輪廓之鰭式結構之製造製程的截面圖。
圖11為根據部分實施例之在具有漸縮底部輪廓之鰭式結構上生長的源極/汲極結構的截面圖。
100:鰭式結構
105:底部漸縮輪廓
110:基座結構
115:基板
120:隔離材料
125:Si磊晶層/矽磊晶層
150:矩形
A:高度
B:高度
H:高度
W:寬度
Claims (10)
- 一種半導體結構,包含:一基板,該基板包含在其上形成的複數個基座結構;複數個鰭式結構,在該等基座結構上形成,並且包含:一底部漸縮部分,具有一底部寬度、一中間寬度和一頂部寬度,其中該中間寬度大於該底部寬度及該頂部寬度;及一上部部分,具有一實質上等於或小於該底部漸縮部分的該頂部寬度的一寬度;以及一隔離材料,置於該等基座結構之間。
- 如請求項1之半導體結構,其中該鰭式結構包含一矽鍺磊晶層,該矽鍺磊晶層具有在該上部部分和該底部漸縮部分之間的一鍺濃度變化。
- 如請求項1之半導體結構,其中該鰭式結構包含複數個矽鍺磊晶層之一堆疊,且其中各矽鍺磊晶層包含不同的一鍺濃度。
- 如請求項1之半導體結構,其中該上部部分之該寬度係介於約5nm至約15nm之間,且該中間寬度係介於約8nm至約20nm之間。
- 如請求項1之半導體結構,其中該底部漸縮部分之該中間寬度由在該上部部分的一側壁表面和該漸縮底部部分的一側壁表面之間測量的該底部漸縮部分的一側壁角所形成。
- 一種半導體結構,包含: 一基板,該基板包含在其上形成的複數個基座結構;複數個鰭式結構,在該等基座結構上形成,並且包含一頂部部分、及寬於該頂部部分之一漸縮底部部分,其中該漸縮底部部分之各側壁與該鰭式結構的該頂部部分的側壁表面和該基座結構的側壁表面不共面;以及一隔離材料,位於該等基座結構之間,其中介於該漸縮底部部分的該側壁與該頂部部分之該側壁表面之間的一漸縮角係介於約10度至約30度之間。
- 如請求項6之半導體結構,其中該漸縮底部部分的相鄰側壁之間形成介於約120度至約160度之間的一角度。
- 一種半導體結構的形成方法,包含:於一基板的一摻雜區上沉積一磊晶層;圖案化該磊晶層和該摻雜區以形成一鰭式結構,該鰭式結構包含一磊晶層部分和一摻雜區部分;於該基板上形成一隔離區,使該磊晶層部分的一頂部部分位於該隔離區上方;於該隔離區上方的該磊晶層的該頂部部份上沉積一矽基層;對該矽基層進行退火以使該矽基層迴焊;蝕刻該隔離區上方的該矽基層和該鰭式結構,以在該隔離區上方的該鰭式結構中形成一第一底部漸縮輪廓;以及對該鰭式結構進行退火以在該第一底部漸縮輪廓下方和該隔離區上方形成一第二底部漸縮輪廓; 其中該第一底部漸縮輪廓和第二底部漸縮輪廓共同形成一底部輪廓,該底部輪廓具有一頂部寬度、一中間寬度和一底部寬度的;及其中該中間寬度係大於該頂部寬度和該底部寬度中的各者。
- 如請求項8之形成方法,其中對該矽基層進行退火包含使該矽基層迴焊,以使得該鰭式結構上的該矽基層的頂部覆蓋率小於該鰭式結構上的該矽基層的底部覆蓋率。
- 如請求項8之形成方法,其中對該鰭式結構進行退火以形成該第二底部漸縮輪廓包含氧化由該隔離區所覆蓋的該鰭式結構。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100144121A1 (en) * | 2008-12-05 | 2010-06-10 | Cheng-Hung Chang | Germanium FinFETs Having Dielectric Punch-Through Stoppers |
US20150008484A1 (en) * | 2012-07-27 | 2015-01-08 | Intel Corporation | High mobility strained channels for fin-based transistors |
US20160359001A1 (en) * | 2015-06-04 | 2016-12-08 | Globalfoundries U.S. 2 Llc | Silicon germanium fin |
US20180053848A1 (en) * | 2016-03-31 | 2018-02-22 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008300384A (ja) * | 2007-05-29 | 2008-12-11 | Elpida Memory Inc | 半導体装置及びその製造方法 |
CN103137475B (zh) * | 2011-11-23 | 2015-09-16 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US9171929B2 (en) | 2012-04-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device and method of making the strained structure |
US9093530B2 (en) | 2012-12-28 | 2015-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin structure of FinFET |
US9318606B2 (en) * | 2013-01-14 | 2016-04-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device and method of fabricating same |
US9159824B2 (en) | 2013-02-27 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with strained well regions |
US9214555B2 (en) | 2013-03-12 | 2015-12-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Barrier layer for FinFET channels |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9548303B2 (en) | 2014-03-13 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET devices with unique fin shape and the fabrication thereof |
US9608116B2 (en) | 2014-06-27 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | FINFETs with wrap-around silicide and method forming the same |
US9219154B1 (en) * | 2014-07-15 | 2015-12-22 | International Business Machines Corporation | Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors |
US9773786B2 (en) | 2015-04-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FETs and methods of forming FETs |
US9564489B2 (en) | 2015-06-29 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple gate field-effect transistors having oxygen-scavenged gate stack |
US9773705B2 (en) * | 2015-06-30 | 2017-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET channel on oxide structures and related methods |
CN106486372B (zh) * | 2015-08-28 | 2021-06-22 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US9929159B2 (en) * | 2016-02-25 | 2018-03-27 | Globalfoundries Inc. | Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins |
US10707208B2 (en) * | 2017-02-27 | 2020-07-07 | International Business Machines Corporation | Fabrication of fin field effect transistors utilizing different fin channel materials while maintaining consistent fin widths |
KR102487548B1 (ko) * | 2017-09-28 | 2023-01-11 | 삼성전자주식회사 | 집적회로 소자 |
US11302535B2 (en) | 2018-06-27 | 2022-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performing annealing process to improve fin quality of a FinFET semiconductor |
US10867862B2 (en) * | 2018-08-31 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor method and device |
DE102019131057A1 (de) | 2018-11-29 | 2020-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung und herstellungsverfahren |
-
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100144121A1 (en) * | 2008-12-05 | 2010-06-10 | Cheng-Hung Chang | Germanium FinFETs Having Dielectric Punch-Through Stoppers |
US20150008484A1 (en) * | 2012-07-27 | 2015-01-08 | Intel Corporation | High mobility strained channels for fin-based transistors |
US20160359001A1 (en) * | 2015-06-04 | 2016-12-08 | Globalfoundries U.S. 2 Llc | Silicon germanium fin |
US20180053848A1 (en) * | 2016-03-31 | 2018-02-22 | International Business Machines Corporation | Fabrication of vertical fin transistor with multiple threshold voltages |
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