CN113054025A - 半导体结构及其形成方法 - Google Patents
半导体结构及其形成方法 Download PDFInfo
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- CN113054025A CN113054025A CN202110108315.8A CN202110108315A CN113054025A CN 113054025 A CN113054025 A CN 113054025A CN 202110108315 A CN202110108315 A CN 202110108315A CN 113054025 A CN113054025 A CN 113054025A
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Abstract
本申请的实施例描述了一种用于形成具有锥形底部轮廓的以改善结构刚度和栅极控制特性的超薄鳍的方法。该方法包括形成鳍结构,该鳍结构包括外延层部分和被隔离区域围绕的掺杂区域部分,使得外延层部分的顶部在隔离区域之上。该方法还包括在隔离区域之上的外延层的顶部上沉积硅基层,并对硅基层进行退火以使硅基层回流。该方法还包括在隔离区域之上蚀刻硅基层和鳍结构以在隔离区域之上的鳍结构中形成第一底部锥形轮廓,并且对鳍结构进行退火以在第一底部锥形下方和隔离区域之上形成第二底部锥形轮廓。根据本申请的实施例,还提供了半导体结构及其形成方法。
Description
技术领域
本申请的实施例涉及半导体结构及其形成方法。
背景技术
鳍式场效应晶体管(finFETs)可以具有用于改善对沟道区域栅极控制的超薄鳍结构。但是,在形成超薄鳍结构之间的隔离区域期间和/或在其他制造工艺期间,超薄鳍结构易于弯曲或塌陷。这是因为超薄鳍结构缺少较厚鳍结构的结构完整性。
发明内容
根据本申请的一个实施例,提供了一种半导体结构,包括:衬底,包括在衬底上形成的基座结构;鳍结构,在基座结构上形成并且包括:底部锥形部分,底部锥形部分具有底部宽度、中间宽度、和顶部宽度,其中中间宽度大于底部宽度和顶部宽度;以及上部部分,上部部分具有宽度基本等于或小于底部锥形部分的顶部宽度;以及位于基座结构之间的隔离材料。
根据本申请的另一个实施例,提供了一种半导体结构,包括:衬底,包括在衬底上形成的基座结构;鳍结构,在基座结构上形成的并且包括顶部部分和比顶部部分宽的锥形底部部分,其中,锥形底部部分的每个侧壁与鳍结构的顶部部分的侧壁表面和基座结构的侧壁表面不共面;以及位于基座结构之间的隔离材料。
根据本申请的又一个实施例,提供了一种形成半导体结构的方法,包括:在衬底的掺杂区域上沉积外延层;对外延层和掺杂区域进行图案化以形成包括外延层部分和掺杂区域部分的鳍结构;在衬底上形成隔离区域,使得外延层部分的顶部区段在隔离区域之上;在隔离区域之上的外延层的顶部部分上沉积硅基层;使硅基层退火以使硅基层回流;在隔离区域之上蚀刻硅基层和鳍结构,以在隔离区域之上的鳍结构中形成第一底部锥形轮廓;以及使鳍结构退火以在第一底部锥形轮廓下方和隔离区域之上形成第二底部锥形轮廓,其中第一底部锥形轮廓和第二底部锥形轮廓共同形成具有顶部宽度、中间宽度、和底部宽度的底部轮廓,以及其中中间宽度大于顶部宽度和底部宽度中的每个。
本申请的实施例提供了超薄鳍结构。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的方面。应该强调的是,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1A是根据一些实施例的具有由硅外延层制成的锥形底部轮廓的鳍结构的等距视图。
图1B是根据一些实施例的具有由硅锗外延层制成的锥形底部轮廓的鳍结构的等距视图。
图1C是根据一些实施例的具有由硅外延堆叠件制成的锥形底部轮廓的鳍结构的等距视图。
图1D是根据一些实施例的沿着具有由单一硅锗外延层或硅锗外延堆叠件制成的锥形底部轮廓的鳍结构的锗浓度图。
图2和图3是具有锥形底部轮廓的鳍结构的局部横截面图。
图4是根据一些实施例的用于形成具有锥形底部轮廓的鳍结构的制造方法的流程图。
图5至图10是根据一些实施例描述的具有锥形底部轮廓的鳍结构的制造工艺的横截面图。
图11是根据一些实施例的在具有锥形底部轮廓的鳍结构上生长的源极/漏极外延结构的横截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。以下描述元件和布置的具体实例以简化本发明。当然,这些仅仅是实例而不旨在限制。例如,在以下描述中,在第二部件上方形成第一部件的工艺可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。如本文中所使用的,在第二部件上形成第一部件的意思是第一部件与第二部件直接接触地形成。另外,本公开可以在各个实例中重复附图标号和/或字母。该重复其本身并未指示所讨论的各个实施例和/或配置之间的关系。
为了便于描述,在此可使用诸如“在...之下”、“在...下方”、“下面的”、“在...之上”、以及“上面的”以及诸如此类的空间关系术语,以描述如图中所示的一个元件或部件与另一元件(多个元件)或部件(多个部件)的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
如本文所用,术语“标称”是指在产品或工艺的设计阶段中设置的,用于组件或工艺操作的特性或参数的期望值或目标值,以及高于或低于该期望值的范围。值的范围可能归因于制造工艺和/或公差的微小变化。
在一些实施例中,术语“约”和“基本上”可以指给定数量的值,该给定数量的值在该值的5%之内变化(例如,为值的±1%、±2%、±3%、±4%、±5%)。这些值仅是示例,并不旨在进行限制。应该理解,术语“约”和“基本上”可以指根据本文的教导,由相关领域的技术人员解释的值的百分比。
用于鳍式场效应晶体管(finFETs)的超薄鳍结构(例如,平均宽度在约5nm和约15nm之间)提供了对沟道区域的改善的栅极控制,并减轻与短沟道效应有关的问题。由于这些原因,超薄鳍结构对于finFETs具有吸引力。然而,与较厚的鳍结构(例如,厚于约20nm)相比,超薄鳍结构的上述益处由于其有限的饱和电流(例如,由于其减小的宽度)而受到损害并且缺乏结构刚性。例如,超薄鳍结构在源自周围层(例如,电介质)的机械应力和/或后续制造操作(例如,致使应力在超薄结构附近累积的致密化工艺)下易于弯曲或塌陷。
为了解决上述挑战,本公开内容涉及一种用于形成具有锥形底部轮廓以用于改善结构刚度的超薄鳍,同时保持期望的栅极控制特性的方法。在一些实施例中,可以使用本文描述的方法来制造硅和硅锗(SiGe)超薄鳍。此外,可以在p型finFETs中形成具有Ge可变浓度和锥形底部轮廓的SiGe鳍,以改善对沟道和超薄鳍结构和栅极介电堆叠件之间的界面质量的栅极控制。
根据一些实施例,图1A是具有底部锥形轮廓105的超薄鳍结构100(鳍结构100)的局部等距视图,该底部锥形轮廓105基本改善了鳍结构100的结构刚度。在一些实施例中,在形成图1中未示出的栅极堆叠件之前,在衬底115的基座结构110上形成鳍结构100。
鳍结构100的顶部宽度W在约5nm至约15nm之间,总高度H在约40nm至约70nm之间。从鳍结构100与衬底115的基座结构110之间的界面测量每个鳍结构100的高度H,并且包括与底部锥形轮廓105的总高度相对应的高度B,以及高度A-底部锥形轮廓105之上的鳍结构100的高度。在一些实施例中,如图1A所示,高度H基本等于高度A和高度B之和(例如,H=A+B)。在一些实施例中,高度A在高度H的约80%至约90%之间(例如,80%H≤A≤90%H),高度B在高度H的约10%至约20%之间(例如,10%H≤B≤20%H)。例如,如果H在约40nm至约70nm之间,则高度A在约32nm至约63nm之间,并且高度B(例如,底部锥形轮廓105的高度)在约4nm至约14nm之间。
在一些实施例中,如果高度B小于高度H的约10%,则底部锥形轮廓105可能不够厚以在结构上支撑鳍结构100。例如,如果高度B小于高度H的约10%,鳍结构100可能变得易于弯曲或塌陷。另一方面,如果高度B大于高度H的约20%(例如,如果底部锥形轮廓105占据鳍结构100的较大部分),则可以限制底部锥形轮廓105附近的沟道控制。因此,鳍结构100中的底部锥形轮廓105的尺寸(例如,高度B)需要被定制,以使得鳍结构100在机械刚度和电性能之间表现出最佳的平衡。
如图1A所示,鳍结构100通过隔离材料120隔离,该隔离材料120包括介电材料,诸如氧化硅、含碳的氧化硅、含氢和氮的氧化硅、或任何其他合适的介电材料或层。
基座结构110可以由衬底115形成并且可以包括图1A中未示出的一个或多个掺杂区域。例如,基座结构110的顶部部分(例如,在底部锥形轮廓105下方)可以掺杂有n型或p型掺杂剂,以防止在finFET操作期间鳍结构100和衬底115之间的泄漏电流。在一些实施例中,衬底115是体半导体晶圆或绝缘体上半导体(SOI)晶圆的顶层,诸如例如绝缘体上硅。此外,衬底115可以由硅或诸如例如,(i)锗(Ge);(ii)一种化合物半导体,包括碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、和/或锑化铟(InSb);(iii)合金半导体,包括砷化镓磷(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)、和/或磷砷化镓铟(GaInAsP);或(iv)它们的组合的另一元素半导体制成。在一些实施例中,衬底115具有晶体微结构,例如,它不是非晶或多晶的。
出于示例目的,将在晶体硅(Si)的顶面平行于(100)晶面的情况下描述衬底115和基座结构110。基于本文的公开内容,可以使用如上所述的其他材料或晶向。这些材料在本公开的精神和范围内。
根据一些实施例,如图1A所示,鳍结构100的底部锥形轮廓105形成在隔离材料120的顶面之上。
在一些实施例中,鳍结构100可以包括单一外延层或外延层的堆叠件。例如,鳍结构100可以包括如图1A所示的单一Si外延层125、如图1B所示的单一SiGe外延层130、或图1C所示的SiGe外延层135、SiGe外延层140和SiGe外延层145的堆叠件。在一些实施例中,图1A中所示的具有单一硅外延层125的鳍结构100适用于n型finFETs(例如,nFETs)。图1B和图1C所示的具有单一SiGe外延层130或SiGe外延层135、SiGe外延层140、和SiGe外延层145的堆叠件的鳍结构100适用于p型finFETs(pFETs)。在一些实施例中,如图1A至图1C所示的用于nFETs和pFETs的鳍结构100都可以使用本文描述的方法形成在同一衬底(例如,衬底115)上。
在一些实施例中,鳍结构100是由单一SiGe外延层130制成的pFET鳍结构,如图1B所示,其Ge原子浓度(原子%)随高度H而变化。例如,参照图1B,单一SiGe外延层130具有沿着鳍结构100的高度A的从约10原子%(原子%)到约25原子%的Ge浓度,并且Ge浓度沿着底部锥形轮廓105的高度B从约25原子%变化至约35原子%。在一些实施例中,由高度A限定的面积内的Ge“峰”浓度朝向高度A的底部定位-例如,在底部锥形轮廓105之上,在由高度HG限定的鳍结构100的面积内。在一些实施例中,高度HG在鳍结构100的高度H的约1/3和2/3之间。例如,如果总鳍高度H为约60nm,则高度HG可以在约20nm至约40nm之间。
在一些实施例中,图1D示出了Ge原子%作为图1B所示的鳍结构100的高度H的函数。如以上关于图1B所讨论的,在高度A的“边界”内,峰Ge原子%可以在由高度HG限定的鳍状结构100的面积内找到,该高度HG在鳍结构100的高度H的大约1/3和2/3之间延伸。附加地,如上所述并且在图1D中所示,Ge原子%在底部锥形轮廓105内(例如,沿着高度B)甚至可以更高。如将在稍好讨论的,通过调整沉积工艺条件,在SiGe外延层的生长过程中可以实现图1D所示的Ge原子%轮廓。
在一些实施例中,对于图1C所示的鳍结构100可以实现与图1D所示相似的Ge轮廓,其包括SiGe外延层135、SiGe外延层140、和SiGe外延层145。例如,可以用不同的Ge浓度来生长SiGe外延层135、SiGe外延层140、和SiGe外延层145,Ge浓度可以复制图1D所示的Ge轮廓。作为示例而非限制,外延层145可以以最低的Ge浓度生长,外延层140可以以大于外延层145的Ge浓度更大的Ge浓度且以等于约高度HG的厚度生长,并且外延层135可以生长以形成底部锥形轮廓105,该底部锥形轮廓105的Ge浓度大于外延层140的Ge浓度,并且其厚度等于约高度B。SiGe外延层135、SiGe外延层140、和SiGe外延层145的上述描述不是限制性的,并且具有可以形成具有两层而不是三层的堆叠件。例如,SiGe外延层135和SiGe外延层140可以结合至单一SiGe外延层。附加的SiGe外延层也是可能的,并且在本公开的精神和范围内。
在一些实施例中,图2和图3是图1A的矩形150中包括的结构元件的放大的横截面图。图2和图3中示出的部件同样适用于图1B和图1C所示的鳍结构100。参考图2,底部锥形轮廓105的顶部宽度Wt在约5nm至约15nm之间,中间宽度Wm在约8nm至约20nm之间,并且底部宽度Wb在约7nm至约18nm之间。在一些实施例中,宽度Wb大于宽度Wt,并且宽度Wm大于宽度Wt和宽度Wb。例如,Wm>Wb>Wt。在一些实施例中,比率Wt/Wm在约0.25至约0.75之间(例如,0.25≤Wt/Wm≤0.75);并且比率Wb/Wm在约0.35至约0.90之间(例如0.35≤Wb/Wm≤0.90)。在一些实施例中,分别小于约0.25和0.35的比率Wt/Wm和Wb/Wm,可以在鳍结构100的锥形面积中产生有限的通道控制的放大的锥形轮廓。在一些实施例中,分别大于约0.75和0.90的比率Wt/Wm和Wb/Wm可产生不能为鳍结构100提供足够的结构支撑的锥形轮廓。在一些实施例中,底部锥形轮廓105的宽度Wt基本等于或大于图1所示的鳍结构100的顶部宽度W(例如,Wt≥W)。因此,鳍结构100在鳍结构100的顶部处可能狭窄并且沿着高度A的宽度增加(例如,W<Wt)。在一些实施例中,鳍结构100沿高度A的宽度是恒定的(例如,W=Wt),并且在底部锥形轮廓105的高度B内增加。
在一些实施例中,底部锥形轮廓105的宽度Wm与基座结构110和鳍结构100之间的界面间隔约1nm至约3nm的竖直距离C。在一些实施例中,竖直距离C在高度B的约1/3与约1/2之间(例如,底部锥形轮廓105的整个高度)。在一些实施例中,低于约1/3的C/B比率将“移动”Wm更接近Wb。对于栅极层的沉积,这将产生挑战性的几何形状。例如,在Wm和Wb之间的底部锥形轮廓105的部分上共形地沉积栅极层(例如,高k介电层、功函层等)将具有挑战性,这可能导致FETs之间的不期望的阈值电压变化。另一方面,高于约1/2的C/B比率将“移动”Wm使其更接近Wt,这将削弱鳍结构100的结构完整性。
在一些实施例中,基座结构110和鳍结构100之间的界面位于隔离材料120的顶面之上的在约4nm至约15nm之间的范围内的竖直距离D。
如上所述,鳍结构100沿高度H具有宽部分和窄部分以改善其结构刚度。但是,在相同的栅极偏置条件下,鳍结构100的较宽部分(例如,在Wt、Wm、和Wb的位置处)的栅极控制可能是挑战性的。根据一些实施例,Ge浓度可以用于“局部”减小鳍结构100的较宽部分上方的Vt并改善栅极控制。这是因为,Ge的带隙比Si窄;因此,与Ge浓度较低的面积(例如,在鳍结构100的顶部)相比,Ge浓度较高的面积(例如,在由高度HG和底部锥形轮廓105限定的面积内)可以具有较低的Vt。因此,增加鳍结构100的较宽部分中的Ge浓度,有效地减小了较宽部分中的Vt并改善了对沟道的栅极控制。根据一些实施例,调整鳍结构中的Ge浓度对于finFET的操作可能是有益的,并且确保沿着鳍结构100的高度H的基本恒定的饱和电流。在一些实施例中,鳍结构100的富Ge面积中的Ge浓度可达到约50%。
根据一些实施例,图2所示的底部锥形轮廓105的宽度Wm是用于调整鳍结构100的结构刚度的关键结构参数。如上所述,宽度Wm的范围可以从约8nm到约20nm。如果宽度Wm小于约8nm,则底部锥形轮廓105的宽度不足以为鳍结构100提供足够的结构支撑。相反地,如果宽度Wm大于约20nm,则底部锥形轮廓105内的沟道控制即使具有较高的Ge浓度变得困难。
在一些实施例中,通过在图3所示的底部锥形轮廓105的每一侧上的角度θ1和θ2来提供宽度Wm的控制。在一些实施例中,在约10°至约30°之间的角度θ1和角度θ2提供在约8nm至约20nm之间的宽度Wm。因此,小于约10°的角度θ1和角度θ2导致小于约8nm的宽度Wm,而大于约30°的角度θ1和角度θ2导致大于约20nm的宽度Wm。在一些实施例中,通过在鳍结构100的形成期间和之后使用的蚀刻和退火条件来控制中间宽度Wm以及角度θ1和角度θ2。在一些实施例中,角度θ3在约120°至约160°的范围内。
在一些实施例中,角度θ1和角度θ2防止底部锥形轮廓105的侧壁部分与鳍结构100的底部锥形轮廓105之上和下方的侧壁部分共平面。此外,角度θ1和角度θ2防止底部锥形轮廓105的侧壁部分与基座结构110的侧壁部分共平面,如图3所示。
图4是用于形成图1A所示的鳍结构100的制造方法400的流程图。可以在方法400的各种操作之间执行其他制造操作,并且仅为了清楚和便于描述可以将其省略。这些各种操作在本公开的精神和范围内。附加地,并非所有操作都可以执行本文提供的公开。一些操作可以同时执行,或者以与图4所示顺序不同的顺序执行。在一些实施例中,除了当前描述的操作之外或代替当前描述的操作,可以执行一个或多个其他操作。将参考图5至图10描述方法400。提供用于描述方法400的附图仅用于说明性目的,并且可能未按比例绘制。附加地,这些图可能无法反映真实结构、部件、或膜的实际几何形状。为了说明的目的,一些结构、膜、或几何形状可能被故意扩大或省略。
参考图4,方法400开始于操作405和在衬底(诸如图1A所示的衬底115)的p型区域上沉积Si外延层的工艺。作为示例而非限制,并且根据方法400的操作405,可以在如图5所示的衬底115的p型区域500上直接生长Si外延层125。可以,例如,通过使用诸如硼(B)的p型掺杂剂并具有从约5×1016原子/cm3至约1×1019原子/cm3的掺杂剂浓度的离子注入工艺形成P型区域500。可以使用化学气相沉积(CVD)工艺将Si外延层125生长至约30nm至约100nm之间的厚度。用于硅外延形成的源气体可以包括硅烷(SiH4)、四氯化硅(SiCl4)、三氯硅烷(TCS)、或二氯硅烷(SiH2Cl2或DSC)。氢气(H2)可用作减少上述源气体的反应气体。取决于所使用的气体,外延层生长期间的沉积温度可以在约700℃至约1250℃的范围内。例如,具有更少氯原子(例如,DSC)的源气体可能比具有更多氯原子的源气体(诸如,SiCl4或TCS)需要更低的形成温度。前述气体的范围和类型仅作为示例提供,而不是限制性的。
参考图4,方法400继续操作410以及对Si外延层125和p型区域500进行图案化以在衬底115上形成鳍结构的工艺。在一些实施例中,使用图5中所示的硬掩模结构505,通过光刻和蚀刻操作来实现对Si外延层125和p型区域500的图案化。在一些实施例中,硬掩模结构505用作蚀刻掩模并且可以包括一层或多层,诸如氧化硅和氮化硅。可以通过任何合适的方法图案化鳍结构。例如,可以使用包括双图案化工艺或多图案化工艺的一个或多个光刻工艺来图案化鳍结构。双图案化或多图案化工艺将光刻工艺和自对准工艺结合在一起,从而允许产生,例如,具有比使用单一、直接的光刻工艺可获得的间距更小的间距的图案。在一些实施例中,在衬底上方形成牺牲层并且使用光刻工艺被图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后,去除牺牲层,并且然后可以使用剩余的间隔件来图案化鳍结构。根据一些实施例,图5示出了用于形成鳍结构的最终图案化操作,其中硬掩模结构505可以是设置在Si外延层125上的剩余间隔件。
根据一些实施例,图6示出了根据上述操作410形成的所得鳍结构100。可以根据操作410通过使用附加的硬掩模结构在衬底115上形成附加的鳍结构100。在一些实施例中,沿着y轴和x轴的硬掩模结构505的宽度和长度限定图6中所示的鳍结构100的宽度和长度。此外,硬掩模结构505之间的间隔限定鳍结构100之间的间隔。因此,通过控制硬掩模结构505的尺寸,可以限定鳍结构100的尺寸。在一些实施例中,在操作410之后,鳍结构100的宽度W’在约7nm至约18nm之间,其可以与图2所示的Wb相似或厚于Wb。
参考图4,方法400继续操作415以及在鳍结构100之间沉积隔离材料的工艺。沉积隔离材料包括如图6所示在鳍结构100上方沉积衬垫层600。作为示例而非限制,衬垫层600用作隔离材料的粘合层。作为示例而非限制,衬垫层600可以通过共形沉积工艺(诸如等离子体增强的原子层沉积(PEALD))以约2nm至4nm之间的厚度沉积。作为示例而非限制,衬垫层600可以是氧化硅或基于氧化硅的介电材料。
随后,如图6所示,沉积隔离材料120以围绕鳍结构100。在一些实施例中,以图1A所示的鳍结构100的高度H的约3倍的厚度沉积隔离材料120。根据一些实施例,利用可流动的化学气相沉积工艺(例如,可流动的CVD)沉积隔离材料120,以确保隔离材料120填充鳍结构100之间的间隙而不会形成接缝或空隙。在一些实施例中,隔离材料120是包括,例如,氮和氢的基于氧化硅的介电材料。为了进一步改善其介电和结构特性,隔离材料120可以在约600℃至1200℃之间的温度下进行湿蒸汽退火(例如,100%水分子)。在湿蒸汽退火期间,隔离材料120致密化并且其氧含量增加。
随后,化学机械平坦化(CMP)工艺抛光隔离材料120,直到暴露出鳍结构100的顶面。在前述CMP工艺期间,去除衬垫层600在鳍结构100的顶面上的部分。如图7所示,干法蚀刻工艺“拉回”(例如,选择性蚀刻)衬垫层600和隔离材料120,以暴露出鳍结构100的顶部部分。这是因为在隔离材料120的蚀刻工艺中使用的气体化学物对衬垫层600也是选择性的。在一些实施例中,蚀刻工艺包括,但不限于,碳氟化合物化学物。作为上述蚀刻工艺的结果,鳍结构100的顶部部分被暴露出,而底部部分仍保持嵌入隔离材料120中。在一些实施例中,隔离材料120被蚀刻,使得凹进的隔离材料120的顶面被基座结构110和Si外延层125之间的界面间隔开竖直距离R。在一些实施例中,竖直距离R基本上等于图2所示的竖直距离C(例如,在约1nm至3nm之间)。换言之,隔离材料120被大致蚀刻至图2所示的宽度Wm的水平。
参考图4,方法400继续操作420,和,例如,通过削减鳍结构100的暴露部分“削减”(例如,蚀刻)鳍结构100的未被隔离材料120覆盖的硅外延层125的侧壁的工艺。在一些实施例中,削减(例如,蚀刻)硅外延层125的侧壁包括在硅外延层125上选择性地沉积硅基层,使硅基层回流使得硅基层在鳍结构100的顶部上变得更薄,而在鳍结构100的底部上变得更厚,并且随后蚀刻硅基层和硅外延层125以形成初始或第一锥形轮廓。
在一些实施例中,硅基层是以共形方式在鳍结构100的顶面和侧壁表面上选择性地沉积硅外延层,其厚度在约1nm至约2nm之间。结果,硅基材料不会在隔离材料120上生长。在一些实施例中,两阶段退火工艺包括在约600℃至约700℃之间的温度下预浸泡约10s至30s,然后在约800℃和约1000℃之间的温度下进行尖峰退火约1ms。回流工艺被配置为在鳍结构100上重新分布硅基材料。在一些实施例中,在鳍结构100的顶部和底部之间重新分布约0.5nm至约1nm的硅基材料。例如,在回流工艺之后,硅基层的在鳍结构100的底部的厚度可以为约3nm,并且硅基层的在鳍结构100的顶部的厚度可以为约1nm。图7示出了在上述沉积和回流工艺之后的硅基层700。
对硅基层700和硅外延层125有选择性的后续刻蚀工艺开始去除硅基层700。由于回流工艺后硅基层700的非共形分布,鳍结构100顶部的硅外延层125比鳍结构100的底部处的硅外延层125更早地暴露于蚀刻化学物,其中硅基层700较厚。因此,鳍结构100的顶部部分比底部部分暴露于蚀刻化学物的时间更长。刻蚀化学物的这种有意的曝光时间差是在鳍结构100中形成初始或第一锥形轮廓的原因。所得的鳍结构100在图8中示出。作为示例而非限制,如图8所示,在蚀刻工艺之后,鳍结构100发展为圆顶角。此外,在蚀刻工艺之后,与图6所示的初始顶部宽度W’相比,顶部宽度W”减小了(例如,W”<W)。在一些实施例中,W”可以基本上等于或大于图1A中所示的W(例如,W”≥W)。
在一些实施例中,较厚的硅基层(例如,厚于约2nm)和较长的回流时间可用于产生更明显的锥形轮廓(例如,具有较大宽度Wm的底部锥形轮廓)。但是,这样的条件会大大增加总体处理时间和制造成本。另一方面,较薄的硅基层(例如,比约2nm薄)可能不会产生期望的锥形轮廓(例如,顶部宽度和底部宽度之间的期望的差)。
在一些实施例中,硅基层的厚度和回流条件(例如,退火持续时间和温度)可用于调整鳍结构100上的顶部和底部侧壁覆盖范围之间的厚度差并产生所需的锥形轮廓。更具体地说,上述工艺可用于限定图3中所示的角度θ1。此外,在一些实施例中,可重复操作420以微调鳍结构100的所需初始锥形轮廓和顶部宽度。
在一些实施例中,前述蚀刻工艺包括湿蚀刻和干蚀刻的组合。在一些实施例中,湿蚀刻工艺用于主蚀刻(例如,以削减鳍结构100),而干蚀刻工艺用于去除在主蚀刻期间形成的副产物。在一些实施例中,蚀刻工艺从鳍结构100去除约10%至20%的硅外延材料(例如,在约4nm至约7nm之间)。作为示例而非限制,湿蚀刻化学物可包括稀盐酸(dHF)、氢氧化氨(NH4OH)、和水。干蚀刻工艺可以包括,例如,臭氧(O3)等离子体。在一些实施例中,湿蚀刻工艺是各向同性的,以确保在主蚀刻期间从所有方向的蚀刻均匀性。
在参照图4时,方法400继续操作425和在削减的鳍结构100上的氧化物层的沉积。例如,并且在参照图9中,可以沉积氧化物层900以覆盖削减的鳍结构100的顶面和侧壁表面和隔离材料120的顶面。作为示例而非限制,氧化物层900可以是牺牲栅极氧化物层,诸如氧化硅层或具有厚度在约2nm至约5nm之间的氮氧化硅层。在随后的操作中,用包括具有高介电常数(例如,介电常数大于约3.9)的材料的栅极介电堆叠件代替氧化物层900。
参考图4,方法400继续操作430并且执行退火工艺以形成图10所示的第二锥形轮廓的工艺。更具体地,操作430的退火工艺限定图3中所示的角度θ2和角度θ3。这是因为,在操作430的退火工艺中,由于来自由如图9中的黑色短箭头905和黑色长箭头910标识氧化物层900、衬垫层600、和隔离材料120的氧气的可用性,鳍结构100被部分氧化。由于衬垫层600和隔离材料120的总厚度大于氧化物层900的厚度,因此可用于鳍结构100的被衬垫层600和隔离材料120覆盖的部分的氧化的氧气比对鳍结构100的被氧化物层900覆盖的部分的氧化的氧气多。因此,鳍结构100的被衬垫层600和隔离材料120覆盖的部分相比于由鳍结构100的被氧化物层900覆盖的部分被氧化得更多。因此,与在鳍结构100的被氧化物层900覆盖的部分上相比,在鳍结构100的被衬垫层600和隔离材料120覆盖的部分上形成较厚氧化物将消耗更多的来自鳍结构100的硅材料。同时,在前述退火工艺期间,隔离材料120如白色箭头915所示收缩。因此,隔离材料120的高度减小并且隔离材料120有效地凹进以露出图10所示的底部锥形轮廓105。
在一些实施例中,退火工艺类似于关于操作420中的硅基层700的回流所讨论的退火工艺。但是,存在差异。例如,在操作430中,根据一些实施例,尖峰退火的温度范围可以更大,例如,在约700℃与约1100℃之间。附加地,在操作430中的退火工艺期间的氧浓度高于在操作420中描述的退火工艺的氧浓度。在一些实施例中,如上文针对操作420中的硅基层700的回流所讨论的退火期间也可能发生由衬垫层600和隔离材料120覆盖的鳍结构100的部分氧化。类似地,在操作430中的退火工艺期间,隔离材料120也可以被凹进。
基于在操作430中描述的前述氧化工艺,底部锥形轮廓105的下部上的氧化物层900的部分,如图10中的虚线圆1000所示,被生长得比底部锥形轮廓105之上的氧化物层900的部分厚。这是由于在衬垫层600和隔离材料120附近存在附加的氧气,该氧气增强了该区域中的氧化反应。同时,随着隔离材料120相对于鳍结构100收缩和凹进,由于通过隔离材料120的凹进作用去除了氧气源,所以氧化物层900的生长减慢。因此,通过如上所述的蚀刻和氧化工艺的组合形成底部锥形轮廓105。
根据一些实施例,可以通过操作430的退火条件来调制图3中所示的角度θ2。例如,增加退火温度(例如,将退火温度设置为更接近于约1100℃)和/或退火时间允许氧化物层900在如上所述的鳍结构100的底部继续生长。较厚的氧化物层900意味着来自鳍结构100的Si外延层125的消耗更大,这导致更大的θ2和宽度Wm以及更窄的θ3。相反,接近700℃的退火温度和/或更短的退火时间将产生较薄的氧化物层和Si外延层125的较低消耗,这导致较小的θ2和宽度Wm以及较宽的θ3。为了易于描述,氧化物层900和衬垫层600未在图1至图1C、图2、和图3示出。
在一些实施例中,在操作430之后,如图10所示,在鳍结构100上沉积牺牲栅电极1005。在一些实施例中,牺牲栅电极1005不沿着x方向覆盖鳍结构100的整个长度。例如,牺牲栅电极1005覆盖鳍结构1005的中间区段,而暴露出其余的鳍结构100。此外,在操作430之后,鳍结构100的宽度W基本上不改变。在一些实施例中,在操作420和操作425期间,由于上述蚀刻工艺和退火工艺,鳍结构100的高度从操作410开始连续减小。
在一些实施例中,(例如,通过对氧化物层900的优先选择蚀刻工艺)从氧化物层900剥离鳍结构100的暴露部分(例如,鳍结构100的未被牺牲栅电极1005覆盖的部分),并且,如图11所示,在其上生长源极/漏极外延结构1100。在一些实施例中,源极/漏极外延结构1100是由从每个鳍结构100生长的两个或多个外延层形成的合并的源极/漏极外延结构。在生长的最后阶段期间,允许两个或多个外延层合并并形成图11所示的源极/漏极外延结构1100。在一些实施例中,源极/漏极外延结构1100包括用于p型finFETs的SiGe和用于n型finFETs的碳掺杂的Si(Si:C)。
方法400还可用于形成图1B和图1C所示的SiGe鳍结构。例如,在操作405中,可以在衬底115的n型区域上形成单一SiGe外延层或SiGe外延堆叠件以形成图1B和图1C所示的鳍结构100,如上所述,适用于p型finFETs。在一些实施例中,利用,例如,CVD工艺的异质外延工艺来生长SiGe外延层。作为示例而非限制,用于单一SiGe外延层或SiGe外延堆叠生长的前体气体可包括(i)SiH4、二碱(Si2H6)、SiH2Cl2、锗烷(GeH4)、或盐酸(HCl),以及(ii)氢(H2)、氮(N2)、或氩气(Ar)的组合。在一些实施例中,可以在生长SiGe外延层之前沉积缓冲层(未示出),以抑制由于生长的SiGe与下面的衬底115之间的晶格失配而导致的生长缺陷。此外,在生长SiGe外延层之前衬底115可以是预先制备的,以去除在其上形成的天然氧化物层。
作为示例而非限制,生长期间的Ge浓度可通过GeH4的分压和生长期间,诸如SiH4、Si2H6、和SiH2Cl2的其他气体的分压来调节。例如,生长期间GeH4的较高分压或SiH4、Si2H6、或SiH2Cl2的较低分压有利于具有较高Ge浓度的SiGe层。GeH4的较低分压或SiH4、Si2H6、或SiH2Cl2的较高分压有利于Ge浓度较低的SiGe层。
根据本公开的各种实施例描述了一种用于形成具有锥形底部轮廓以改善结构刚度和期望的栅极控制特性的超薄鳍的方法。在一些实施例中,可以使用本文描述的方法来制造Si和SiGe超薄鳍。此外,可以在p型finFETs中形成具有Ge可变浓度和锥形底部轮廓的SiGe鳍,以改善对沟道的栅极控制。在一些实施例中,SiGe鳍结构的可变Ge浓度在约10%至约35%的范围内,其中朝向鳍结构的底部的Ge浓度较高。在一些实施例中,超薄鳍结构的顶部宽度在约5nm至约15nm之间,并且底部锥形轮廓的宽度在约8nm至约20nm之间。在一些实施例中,在图案化的鳍结构上沉积和回流硅基层,然后通过湿蚀刻和干蚀刻工艺的组合削减鳍结构,来实现第一锥形轮廓。在一些实施例中,通过在鳍的削减部分上沉积氧化物层并使鳍结构经受使鳍结构的底部部分比鳍结构的顶部部分更多地氧化的退火工艺来形成第二锥形轮廓。
在一些实施例中,一种半导体结构包括在其上形成的基座结构以及在该基座结构上形成的鳍结构的衬底。鳍结构还包括底部锥形部分,该底部锥形部分具有底部宽度、中间宽度、和顶部宽度,该中间宽度大于底部宽度和顶部宽度。鳍结构还包括上部部分,该上部部分的宽度基本等于或小于底部锥形部分的顶部宽度。此外,半导体结构包括设置在基座结构之间的隔离材料。
在一些实施例中,一种半导体结构包括在其上形成的基座结构以及在该基座结构上形成的鳍结构的衬底。该鳍结构还包括顶部部分和比顶部部分宽的锥形底部部分,其中,锥形底部部分的每一侧壁与鳍结构的顶部部分的侧壁表面和基座结构的侧壁表面不共面。此外,半导体结构包括设置在基座结构之间的隔离材料。
在一些实施例中,一种方法包括在衬底的掺杂区域上沉积外延层;图案化外延层和掺杂区域以形成鳍结构,该鳍结构包括外延层部分和掺杂区域部分。该方法还包括在衬底上形成隔离区域,使得外延层部分的顶部区段在隔离区域之上;在隔离区域之上的外延层的顶部部分上沉积硅基层;使硅基层退火以使硅基层回流;以及在隔离区域之上蚀刻硅基层和鳍结构以在隔离区域之上的鳍结构中形成第一底部锥形轮廓。该方法还包括使鳍结构退火以在第一底部锥形轮廓下方和隔离区域之上形成第二底部锥形轮廓,使得第一底部锥形轮廓和第二底部锥形轮廓共同形成具有顶部宽度、中间宽度、和底部宽度的底部轮廓,其中中间宽度大于顶部宽度和底部宽度中的每一个。
根据本申请的一个实施例,提供了一种半导体结构,包括:衬底,包括在衬底上形成的基座结构;鳍结构,在基座结构上形成并且包括:底部锥形部分,底部锥形部分具有底部宽度、中间宽度、和顶部宽度,其中中间宽度大于底部宽度和顶部宽度;以及上部部分,上部部分具有宽度基本等于或小于底部锥形部分的顶部宽度;以及位于基座结构之间的隔离材料。在一些实施例中,鳍结构包括硅外延层。在一些实施例中,鳍结构包括硅锗外延层,硅锗外延层具有在上部部分和底部锥形部分之间变化的锗浓度。在一些实施例中,上部部分包括具有在上部部分的底部区段中的锗峰值浓度的锗浓度梯度。在一些实施例中,底部锥形部分具有比上部部分更大的锗浓度。在一些实施例中,鳍结构包括硅锗外延层的堆叠件,并且其中,每个硅锗外延层包括不同的锗浓度。在一些实施例中,上部部分的宽度在约5nm至约15nm之间,并且中间宽度在约8nm至约20nm之间。在一些实施例中,底部锥形部分的中间宽度由上部部分的侧壁表面和底部锥形部分的侧壁表面之间测量的底部锥形部分的侧壁角度形成。在一些实施例中,侧壁角度在约10°至约30°之间的范围内。
根据本申请的另一个实施例,提供了一种半导体结构,包括:衬底,包括在衬底上形成的基座结构;鳍结构,在基座结构上形成的并且包括顶部部分和比顶部部分宽的锥形底部部分,其中,锥形底部部分的每个侧壁与鳍结构的顶部部分的侧壁表面和基座结构的侧壁表面不共面;以及位于基座结构之间的隔离材料。在一些实施例中,锥形底部部分的侧壁与顶部部分的侧壁表面之间的锥角在约10°至30°之间的范围内。在一些实施例中,锥形底部部分的相邻侧壁形成约120°至约160°之间的角度。在一些实施例中,锥形底部部分包括:高度;顶部宽度;中间宽度;和底部宽度,其中,中间宽度大于顶部宽度和底部宽度中的每个。在一些实施例中,中间宽度在约8nm与20m之间的范围内。在一些实施例中,中间宽度大于顶部宽度和底部宽度,并且底部宽度大于顶部宽度。在一些实施例中,其中中间宽度位于基座结构之上约1nm至约3nm之间。在一些实施例中,锥形底部部分的高度在鳍结构的高度的约10%至约20%之间。
根据本申请的又一个实施例,提供了一种形成半导体结构的方法,包括:在衬底的掺杂区域上沉积外延层;对外延层和掺杂区域进行图案化以形成包括外延层部分和掺杂区域部分的鳍结构;在衬底上形成隔离区域,使得外延层部分的顶部区段在隔离区域之上;在隔离区域之上的外延层的顶部部分上沉积硅基层;使硅基层退火以使硅基层回流;在隔离区域之上蚀刻硅基层和鳍结构,以在隔离区域之上的鳍结构中形成第一底部锥形轮廓;以及使鳍结构退火以在第一底部锥形轮廓下方和隔离区域之上形成第二底部锥形轮廓,其中第一底部锥形轮廓和第二底部锥形轮廓共同形成具有顶部宽度、中间宽度、和底部宽度的底部轮廓,以及其中中间宽度大于顶部宽度和底部宽度中的每个。在一些实施例中,其中使硅基层退火包括使硅基层回流以使得鳍结构上的硅基层的顶部覆盖比位于鳍结构上的硅基层的底部覆盖薄。在一些实施例中,其中,对鳍结构进行退火以形成第二底部锥形轮廓包括:氧化被隔离区域覆盖的鳍结构。
应该理解,详细说明部分,并不是本公开的摘要,旨在用于解释权利要求。公开部分的摘要可以陈述设想的示例性实施例中的一个或多个但不是全部,并且因此,不旨在限于附加的权利要求。
以上论述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体结构,包括:
衬底,包括在所述衬底上形成的基座结构;
鳍结构,在所述基座结构上形成并且包括:
底部锥形部分,所述底部锥形部分具有底部宽度、中间宽度、和顶部宽度,其中所述中间宽度大于所述底部宽度和所述顶部宽度;以及
上部部分,所述上部部分具有宽度基本等于或小于所述底部锥形部分的所述顶部宽度;以及
位于所述基座结构之间的隔离材料。
2.根据权利要求1所述的半导体结构,其中,所述鳍结构包括硅外延层。
3.根据权利要求1所述的半导体结构,其中,所述鳍结构包括硅锗外延层,所述硅锗外延层具有在所述上部部分和所述底部锥形部分之间变化的锗浓度。
4.根据权利要求3所述的半导体结构,其中,所述上部部分包括具有在所述上部部分的底部区段中的锗峰值浓度的锗浓度梯度。
5.根据权利要求3所述的半导体结构,其中,所述底部锥形部分具有比所述上部部分更大的锗浓度。
6.根据权利要求1所述的半导体结构,其中,所述鳍结构包括硅锗外延层的堆叠件,并且其中,每个硅锗外延层包括不同的锗浓度。
7.根据权利要求1所述的半导体结构,其中,所述上部部分的宽度在约5nm至约15nm之间,并且所述中间宽度在约8nm至约20nm之间。
8.根据权利要求1所述的半导体结构,其中,所述底部锥形部分的所述中间宽度由所述上部部分的侧壁表面和所述底部锥形部分的侧壁表面之间测量的所述底部锥形部分的侧壁角度形成。
9.一种半导体结构,包括:
衬底,包括在所述衬底上形成的基座结构;
鳍结构,在所述基座结构上形成的并且包括顶部部分和比所述顶部部分宽的锥形底部部分,其中,所述锥形底部部分的每个侧壁与所述鳍结构的所述顶部部分的侧壁表面和所述基座结构的侧壁表面不共面;以及
位于所述基座结构之间的隔离材料。
10.一种形成半导体结构的方法,包括:
在衬底的掺杂区域上沉积外延层;
对所述外延层和所述掺杂区域进行图案化以形成包括外延层部分和掺杂区域部分的鳍结构;
在所述衬底上形成隔离区域,使得所述外延层部分的顶部区段在所述隔离区域之上;
在所述隔离区域之上的所述外延层的所述顶部部分上沉积硅基层;
使所述硅基层退火以使所述硅基层回流;
在所述隔离区域之上蚀刻所述硅基层和所述鳍结构,以在所述隔离区域之上的所述鳍结构中形成第一底部锥形轮廓;以及
使所述鳍结构退火以在所述第一底部锥形轮廓下方和所述隔离区域之上形成第二底部锥形轮廓,
其中所述第一底部锥形轮廓和所述第二底部锥形轮廓共同形成具有顶部宽度、中间宽度、和底部宽度的底部轮廓,以及
其中所述中间宽度大于所述顶部宽度和所述底部宽度中的每个。
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US20220085167A1 (en) | 2022-03-17 |
US20230378271A1 (en) | 2023-11-23 |
US11189697B2 (en) | 2021-11-30 |
KR102366541B1 (ko) | 2022-02-23 |
TW202139464A (zh) | 2021-10-16 |
US20210313428A1 (en) | 2021-10-07 |
US11862683B2 (en) | 2024-01-02 |
DE102020112030A1 (de) | 2021-10-07 |
KR20210123186A (ko) | 2021-10-13 |
TWI765396B (zh) | 2022-05-21 |
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