WO2012150621A1 - Synthétiseur de fréquence - Google Patents

Synthétiseur de fréquence Download PDF

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Publication number
WO2012150621A1
WO2012150621A1 PCT/JP2011/006147 JP2011006147W WO2012150621A1 WO 2012150621 A1 WO2012150621 A1 WO 2012150621A1 JP 2011006147 W JP2011006147 W JP 2011006147W WO 2012150621 A1 WO2012150621 A1 WO 2012150621A1
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WIPO (PCT)
Prior art keywords
decimal part
output
data
outputs
counter
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PCT/JP2011/006147
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English (en)
Japanese (ja)
Inventor
真由子 藤田
稔 落合
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パナソニック株式会社
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Publication of WO2012150621A1 publication Critical patent/WO2012150621A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division

Definitions

  • the present invention relates to a frequency synthesizer using a PLL (Phase Locked Loop) circuit.
  • PLL Phase Locked Loop
  • a frequency synthesizer using a PLL circuit divides and outputs the frequency of a reference signal (hereinafter sometimes referred to as “reference frequency”).
  • a general frequency synthesizer has a restriction that the output frequency can only be an integer multiple of the reference frequency (the resolution cannot be made finer than the reference frequency).
  • Patent Document 1 the above method has a problem of generating spurious due to a periodic change in the frequency division ratio.
  • spurious can be suppressed by performing delta-sigma modulation. .
  • FIG. 6 shows a frequency synthesizer according to the contents disclosed in Patent Document 1.
  • the phase comparator 103, the low-pass filter 104, the voltage controlled oscillator 101, and the variable frequency divider (integer frequency divider) 102 constitute a PLL circuit that forms a loop.
  • the adder 106 adds the integer part data M and the delta-sigma modulated decimal part data Y, and the added output becomes a signal for switching the frequency division ratio of the variable frequency divider 102.
  • the decimal part control circuit 105 is a circuit that delta-sigma-modulates the decimal part data F input from the decimal part data part 130 and outputs the modulated decimal part data Y.
  • An adder 153 in the decimal part control circuit 105 adds the input decimal part setting data F and the carry signal output from the feedback circuit 152 (the value of the integer part generated by the addition of the decimal part), and performs quadratic integration. Output as an input signal of the device 151.
  • the output of the secondary integrator 151 becomes an output signal of the decimal part control circuit 105 while the decimal part is cut off by the quantizer 150 and also becomes an input signal of the feedback circuit 152.
  • the integrator 151 in the decimal part control circuit 105 has a circuit configuration shown in FIG. 7, and a first integration circuit 201 and a second integration circuit 202 are connected in series.
  • This figure is a block diagram represented by z conversion, and z ⁇ 1 means that a signal delayed by one operation clock is output.
  • signals X 1 , X 2 , and X 3 are mapped as shown in FIG. 8, and a decimal point is present in the bit array.
  • fraction part configuration data F is the carry signal from the D 0 ⁇ D n-1
  • the feedback circuit 152 is mapped to the D n ⁇ D n + 2.
  • the fractional part setting data F in FIG. 8 is the data shifted right by n bits with respect to the decimal point, and corresponds to a value divided by 2n in binary notation.
  • the quantizer 150 performs the quantization operation by taking out the higher-order bits from the decimal part.
  • the decimal part truncated by the quantizer 150 becomes the quantization noise Q, and the output signal Y of the decimal part control circuit 105 is
  • the second term means that the quantization noise Q has a characteristic that the level is small at a low frequency and increases as the frequency becomes high.
  • the low-pass filter 104 in the PLL loop has such a characteristic that the level becomes smaller as the frequency becomes higher, the quantization noise Q included in the output signal of the fractional part control circuit 105 is reduced by the low-pass filter 104. As a result, the quantization noise component appearing at the output of the voltage controlled oscillator 101 is suppressed.
  • the conventional frequency synthesizer described above can output the fractional part setting data F with a decimal number as shown in the equation (1).
  • the denominator at the time of the decimalization is a power of 2
  • the denominator is 2. It is impossible to set a division ratio such as a decimal number that cannot be expressed by a power.
  • the division ratio to be obtained can be expressed by an integer for both the numerator and the denominator. . . It continues with.
  • the present invention is intended to solve such a problem, and even if the division ratio includes a decimal number that cannot be expressed by the number of bits for expressing the decimal number, it is possible to avoid the occurrence of a rounding error and perform accurate frequency division.
  • An object is to realize a frequency synthesizer capable of setting a ratio.
  • a frequency synthesizer includes a voltage controlled oscillator that outputs a signal having a frequency corresponding to an input control voltage, and control data that is input from the voltage controlled oscillator.
  • a signal indicating the comparison result by comparing the phase difference between the variable frequency divider that divides the frequency based on the signal and outputs the divided signal, and the signal from the variable frequency divider and the input reference signal
  • a low-pass filter that outputs a signal after the low-pass filtering, and the output of the low-pass filter is the output of the low-pass filter.
  • the binary output from the decimal part data output unit to the decimal part control circuit is switched according to a desired frequency division ratio.
  • a desired frequency division ratio By switching between the two values, it is possible to represent a decimal that cannot be represented by the number of bits for the decimal part control circuit to represent the decimal.
  • Block diagram of a frequency synthesizer according to an embodiment Time chart showing counter operation status for switching decimal part setting data
  • Block diagram of a frequency synthesizer according to modification 1 Block diagram of a frequency synthesizer according to modification 2
  • Block diagram of a frequency synthesizer according to modification 2 Block diagram of a conventional frequency synthesizer circuit Diagram showing integrator in decimal part control circuit The figure which shows the digital signal which shows the carry part and the decimal part in the decimal part control circuit
  • a phase comparator 3 a low-pass filter 4, a voltage controlled oscillator 1, and a variable frequency divider (integer frequency divider) 2 constitute a PLL circuit that forms a loop.
  • the output from the variable frequency divider 2 and the reference signal are input to the phase comparator 3 and the feedback loop is configured so that the frequencies of the two coincide with each other, the output frequency of the voltage controlled oscillator 1 is set to the reference signal.
  • the frequency is double the frequency of the variable frequency divider.
  • the adder 6 adds the integer part data M and the delta-sigma modulated decimal part data Y.
  • the decimal part control circuit 5 is a circuit that delta-sigma-modulates the input decimal part data F or F + 1.
  • the input decimal part data F and the output of the decimal part control circuit 5 are expressed by the above-described equation (1).
  • the decimal part data output unit 10 includes a binary output unit 20, a decimal part setting data unit 30, and an adder 40.
  • the binary output unit 20 includes an L counter 21, an R counter 22, and a D counter 23, which are frequency division counters, and has a function of generating both 0 and 1 values. It has a function to output either one.
  • the L counter 21 divides the output of the variable frequency divider 2 and generates a reference clock for switching between 0 and 1 value output from the binary output unit 20.
  • the R counter 22 counts down according to the clock input from the L counter 21.
  • the R counter is a counter for determining the length of a period during which a value of 1 is output (hereinafter sometimes referred to as “first period”).
  • the D counter 23 counts down in response to the input of the clock from the L counter 21, and when it reaches a counter set value (for example, 0), it resets itself and resets the R counter 22. As will be described later, the D counter 23 determines a second period during which a value of 0 is output, and may be referred to as a cycle (hereinafter referred to as a “switching period”) of the first period and the second period. ) Is a counter that determines the length.
  • the output (0 or 1) of the R counter 22 is input to the adder 40.
  • the adder 40 outputs the result of adding the input value of 0 or 1 and the decimal part setting data F from the decimal part setting data part 30 to the decimal part control circuit 5.
  • the circuit configuration of the decimal part control circuit 5 is the same as that of the conventional decimal part control circuit 105 shown in the lower part of FIG. 6, and will be described with reference to FIG.
  • the decimal part control circuit 5 (FIG. 6: decimal part control circuit 105) adds an adder 153 that adds the carry (an integer value generated by addition of the decimal part) output from the feedback circuit 152, and quadratic integration of this value.
  • the integrator 151, the quantizer 150 that quantizes the integrator output, and the feedback circuit 152 constitute a loop.
  • the output signal of the adder 153 has the bit arrangement shown in FIG. 8, and the decimal part setting data F is stored in the decimal parts D 0 to D n ⁇ 1 and the carry signal is stored in D n to D n + 2 . Since the number of bits in this array is determined by the specifications required by the system, the number of bits in the integer part and the decimal part is an example.
  • the integrator 151 has the configuration shown in FIG. 7, and includes an integrator circuit 201 that adds the output of the adder 53 delayed by one clock, and an integrator circuit 202 that adds the output delayed by one clock. Connected in series.
  • the quantizer 150 cuts off the fractional part and is realized by extracting the bits after the decimal point of the bit array shown in FIG.
  • the temporal change of the integer part corresponds to the decimal part setting data F, and the period of the decimal part data before quantization and the period of the carry signal output from the decimal part control circuit are the same.
  • the output of the fractional part control circuit 5 is always a constant value if averaged over a period of 2 n + 1 , and the reference clock for the switching period is used as the fractional part control circuit operation clock (variable frequency divider output). If the cycle is 2 n + 1 times, it is possible to make the average frequency division ratio constant in one cycle switching period including the first period for outputting the value 1 and the second period for outputting the value 0. .
  • the L counter 21 in FIG. 1 generates this reference time, and supplies an output obtained by dividing the variable frequency divider output by 2 n + 1 as clock inputs to the R counter 22 and the D counter 23.
  • FIG. 2A shows data transition of the D counter 23, and the number of input clocks is counted until the set value D becomes zero.
  • FIG. 2B shows the output of the D counter 23. When the counter value reaches 0, a pulse is output once. This pulse is used as a reset pulse for the R counter 22.
  • FIG. 2C shows the data transition of the R counter 22, and the number of input clocks is counted until the set value R becomes 0. After the value becomes 0, the data value remains 0 but does not change.
  • the reset signal from the D counter 23 shown in 2 (b) is received, the counter data R is set again and starts changing.
  • FIG. 2 (d) shows the output of the R counter 22, which outputs 1 while the counter data is changing, and when it becomes 0, the output also changes to 0.
  • the input value of the decimal part control circuit 5 is “F + 1”.
  • the input value of the fractional part control circuit 5 is “F”.
  • the output of the fractional part control circuit is expressed by the above-described equation (1), and the level of the quantization noise expressed by the second term increases as the frequency increases, but is reduced by the low-pass filter 4 in the PLL circuit. Therefore, the second term can be ignored.
  • the output Y of the fractional part control circuit 5 is (F + 1) / L while the output of the R counter 22 is in the first period, and the output of the fractional part control circuit 5 is during the second period when the output of the R counter 22 is 0.
  • Y can be regarded as F / L.
  • decimal part data are added to the integer part data M by the adder 6 to set the frequency division ratio of the variable frequency divider 2.
  • the average frequency dividing ratio of the variable frequency divider is M + (F + 1) / L, and the R counter 22 output is 0th.
  • the average frequency division ratio of the variable frequency divider is M + F / L.
  • the decimal part data input to the decimal part control circuit 5 is a repetition of “F + 1” and “F”, and is obtained by dividing the switching period, which is a period for outputting both values once, by the reference time. It is set to be the same as the denominator D of the circumferential ratio N / D (N and D are both integers and N ⁇ D).
  • the decimal part control circuit 5 outputs a decimal number that the decimal part control circuit 5 cannot express originally. Can be handled as if
  • the frequency synthesizer generates a rounding error even if the desired frequency division ratio includes a decimal number (for example, a cyclic decimal number) that the decimal part control circuit 5 cannot express with a power of 2.
  • a decimal number for example, a cyclic decimal number
  • An accurate division ratio can be set while avoiding this.
  • the output from the binary output unit 20 may be always set to 0.
  • the conventional circuit configuration as shown in FIG. 6 can be used as it is.
  • Modification 1 In the embodiment, the value of 0 or 1 is periodically switched by the three counters 21 to 23.
  • the present invention is not limited to such an example realized by hardware such as a counter.
  • a binary output unit 20a configured with software having a count function and switching output according to the number of counts may be used.
  • the binary output unit 20 outputs a binary value of 0 or 1, but the difference between the binary values is not necessarily 1. More generally, 0 and m (m is an integer other than 0) may be output.
  • FIG. 4 shows a binary output unit 20b that realizes such an output.
  • the binary output unit 20b includes a selector 26 and a selector control unit 24 that controls the output of the selector 26.
  • the selector control unit 24 has a function of switching and outputting 0 or 1 at a timing according to a desired frequency division ratio, and includes, for example, the three counters 21 to 23 shown in FIG.
  • FIG. 5 (a) shows a selector 26a that outputs a value of 0 when the output of the selector control unit 24 is 0 and outputs a value of 3 when the output is 1.
  • FIG. 5B shows a selector 26b that outputs a value of 0 when the output of the selector control unit 24 is 0 and outputs a value of 5 when it is 1.
  • the decimal part data input to the decimal part control circuit 5 is a repetition of “F + m” and “F”, and a value obtained by dividing the switching period, which is a period for outputting both values once, by the reference time, It is set to be the same as the denominator D of the frequency division ratio N / D to be set (N and D are both integers and N ⁇ D).
  • the normalized remainder value must be a multiple of m.
  • the length of the switching cycle can be defined as follows.
  • the decimal part data input to the decimal part control circuit 5 is a repetition of “F + m” and “F”, and a value obtained by dividing the switching period, which is a period for outputting both values once, by the reference time.
  • the frequency division ratio N / D to be set may be set to m times the denominator D.
  • the binary output unit 20 is composed of the three counters 21 to 23, but the L counter (frequency dividing counter) 21 is not essential.
  • the L counter 21 is eliminated and the R counter 22 and the D counter 23 have a frequency dividing function.
  • the present embodiment includes the following aspects.
  • the frequency synthesizer is configured to output a signal having a frequency corresponding to an input control voltage and a signal from the voltage control oscillator based on input control data. Divides the frequency and outputs a signal after frequency division, compares the phase difference between the signal from the variable frequency divider and the input reference signal, and outputs a signal indicating the comparison result A phase comparison circuit; and a low-pass filter that filters a signal from the phase comparison circuit and outputs a signal after low-pass filtering, and the output of the low-pass filter is the voltage-controlled oscillator
  • the frequency synthesizer in which a loop of the PLL circuit is formed, binary fractional part data is generated, and any one of the generated binary values is set according to a desired frequency division ratio.
  • Switch to output A fraction part data output unit, a fraction part control circuit that performs delta sigma modulation on the fraction part data from the fraction part data output unit, and outputs the fraction part data after the delta sigma modulation, and the fraction part control circuit
  • An adder that adds the decimal part data output from the input data and the integer part data input thereto and outputs the addition result data to the variable frequency divider as the control data.
  • This configuration can contribute to setting an accurate division ratio while avoiding rounding errors. Also, spurious components can be suppressed by delta-sigma modulation.
  • the desired division ratio is N / D
  • the number of bits indicating the decimal part of the decimal part control circuit is n
  • the absolute value of the difference between the two values is m
  • the sum of the first period in which the decimal part data output unit outputs one of the two values and the second period in which the other value is output is D
  • the decimal part data output unit has a value obtained by dividing the remainder when the frequency division ratio N / D is normalized by 2 n and further divided by m, in the length of either the first period or the second period. It does not matter if set to.
  • the absolute value m of the binary difference may be 1.
  • the desired division ratio is N / D
  • the number of bits indicating the decimal part of the decimal part control circuit is n
  • the absolute value of the difference between the binary values is m
  • the decimal part data output unit is the binary value.
  • the sum of the first period in which one value is output and the second period in which the other value is output is m ⁇ D
  • the fractional data output unit is normal with a frequency division ratio N / D of 2 n
  • the remainder value at the time of conversion may be set to the length of either the first period or the second period.
  • the number of bits indicating the decimal part of the decimal part control circuit is n
  • the output of the variable frequency divider is a clock obtained by dividing the output of the variable frequency divider by 2 to the power of (n + 1) or the output of the variable frequency divider.
  • a clock divided by a value obtained by multiplying by a power of 2 may be used as a reference clock for the decimal part data output unit.
  • This configuration can contribute to a constant average frequency division ratio.
  • the decimal part data output unit includes a decimal part setting data part for outputting decimal part data F, a binary output part for outputting 0 or 1, and decimal part data F output from the decimal part setting data. And an adder that adds 0 or 1 output from the binary output unit and outputs data of the addition result to the decimal part control circuit, wherein the binary output unit includes the variable frequency division A first counter that receives the output clock of the counter, a second counter that receives the output of the first counter and outputs 0 or 1 to the adder until the number of input clocks reaches a set value; A third counter that receives the output of the first counter as input and resets the second counter when the number of clocks reaches a set value may be provided.
  • a value obtained by adding the output of the second counter to an arbitrary bit of the decimal part setting data may be used as the input value of the decimal part control circuit.
  • the frequency synthesizer according to the present invention is useful because it can accurately set a division ratio including a decimal number that cannot be expressed by the number of bits for expressing the decimal number.

Abstract

Un synthétiseur de fréquence selon la présente invention est doté d'une unité de sortie (10) de données de partie décimale (10) qui produit deux valeurs pour des données de partie décimale (F, F+1) et sort l'une ou l'autre des deux valeurs produites par commutation sur la base d'un rapport de division souhaité, d'un circuit de commande (5) de partie décimale qui effectue une modulation delta-sigma pour les données de partie décimale provenant de ladite unité de sortie de données de partie décimale et sort des données de partie décimale après la modulation delta-sigma, et d'un additionneur (6) qui ajoute les données de partie décimale sorties dudit circuit de commande de partie décimale aux données de partie entière (M) entrées et sort les données de résultat additionnées sur un diviseur à fréquence variable (2) en tant que données de commande.
PCT/JP2011/006147 2011-05-02 2011-11-02 Synthétiseur de fréquence WO2012150621A1 (fr)

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JP2011-103017 2011-05-02

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09261048A (ja) * 1995-09-28 1997-10-03 Sanyo Electric Co Ltd 可変分周装置
US5986512A (en) * 1997-12-12 1999-11-16 Telefonaktiebolaget L M Ericsson (Publ) Σ-Δ modulator-controlled phase-locked-loop circuit
JP2002152044A (ja) * 2000-11-16 2002-05-24 Matsushita Electric Ind Co Ltd デルタ・シグマ変調回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09261048A (ja) * 1995-09-28 1997-10-03 Sanyo Electric Co Ltd 可変分周装置
US5986512A (en) * 1997-12-12 1999-11-16 Telefonaktiebolaget L M Ericsson (Publ) Σ-Δ modulator-controlled phase-locked-loop circuit
JP2002152044A (ja) * 2000-11-16 2002-05-24 Matsushita Electric Ind Co Ltd デルタ・シグマ変調回路

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