WO2012113247A1 - Pmos器件叠层结构的制备方法 - Google Patents

Pmos器件叠层结构的制备方法 Download PDF

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WO2012113247A1
WO2012113247A1 PCT/CN2011/082538 CN2011082538W WO2012113247A1 WO 2012113247 A1 WO2012113247 A1 WO 2012113247A1 CN 2011082538 W CN2011082538 W CN 2011082538W WO 2012113247 A1 WO2012113247 A1 WO 2012113247A1
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gate
metal
film
interface
tin
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徐秋霞
李永亮
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/669—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN

Definitions

  • the invention belongs to the field of semiconductor technology, in particular to a preparation method of a PM0S metal gate/high-k gate dielectric stacked structure and a method for adjusting a gate work function in a gate-first process, which is suitable for a high performance nanometer of 32/22 nm and below.
  • CMOS complementary metal oxide semiconductor
  • CMOS integrated circuits As the feature size of CMOS devices continues to shrink according to Moore's law, the development of CMOS integrated circuits has encountered severe challenges.
  • High dielectric constant (K) gate dielectric/metal is used to overcome the problem of small-scale device exponentially increasing gate leakage current, severe polysilicon gate depletion, increased gate resistance, and severe boron penetration of PMOS devices.
  • the gate structure has become the industry consensus to replace the traditional Si0 2 /poly (polysilicon) gate structure.
  • An object of the present invention is to provide a metal gate/high-k gate dielectric stacked structure for a PM0S device and a gate work function adjustment method.
  • the present invention utilizes a physical vapor deposition (PVD) method to deposit a metal gate film over a high-k dielectric, which consists of three metal films: a TiN 1 film is deposited first, and then a thin layer is deposited.
  • PVD physical vapor deposition
  • a metal A1 film followed by deposition of a TiN-2 film, thereby completing the deposition of the entire metal gate; then depositing a barrier metal layer; depositing a polysilicon film and a hard mask, followed by photolithography and hard masking Etching; after de-glue, sequentially etching the polysilicon film/barrier metal layer/metal gate/high-k dielectric/interfacial oxide layer to form a polysilicon film/barrier metal layer/metal gate/high-k gate dielectric/interfacial oxide layer stack structure.
  • the conventional sidewall formation, source/drain implantation and rapid thermal annealing are performed to drive the metal A1 ions to the interface between the high-k gate dielectric film and the interface oxide layer while completing the activation of the source/drain impurities.
  • the Al 0 dipole is generated by the interface reaction, thereby realizing the adjustment of the effective work function of the metal gate of the PM0S device.
  • the adjustment effect is the distance between the deposited thickness of A1, the interface between the A1 layer and the TiN/Hf-based high-k dielectric, that is, the thickness of TiN-1, the heat treatment conditions, and the state near the high-k dielectric/SiO2 interface in the Hf-based K medium.
  • the invention provides a method for preparing a metal gate/high-k gate dielectric stacked structure for a PM0S device and a gate work function adjustment method, the main steps of which are as follows:
  • Step 1) After the conventional L0C0S or STI dielectric isolation is completed, an ultra-thin interface oxide layer or an oxynitride layer is grown on the semiconductor substrate by rapid thermal oxidation or chemical method;
  • Step 2 Formation of a high dielectric constant (K) gate dielectric film, and thermal annealing at 500-105 CTC for 4-120 seconds;
  • Step 3) depositing a metal gate; the metal gate is composed of three layers, followed by TiN 1 /Al/TiN-2, wherein the TiN 1 metal gate has a thickness of 2 - 6 , and the metal A1 film has a thickness of 2 - 5 , TiN - 2 metal gate thickness is 10-20 ⁇ ; step 4) depositing a barrier metal layer;
  • Step 5) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing photolithography and hard mask etching; step 6) removing the glue, masking the hard mask, and sequentially etching the polysilicon film/barrier metal / metal gate / high K gate dielectric / interface Si0 2 form a stacked gate structure;
  • Step 7) forming side wall 1 and source/drain extension regions with low energy ion implantation and large angle implantation;
  • Step 8) forming sidewall 2 and source/drain and ion implantation
  • Step 9) rapid thermal annealing: at 600- 1050 ° C, N 2 annealing to 2-30 seconds; at the completion of the source / drain impurity activated simultaneously, A1 metal ions driven into high-K gate dielectric film and the interfacial oxide interface Upper, through the interface reaction to generate A1-0 dipole, to achieve the adjustment of the effective work function of the metal gate of the PM0S device;
  • Step 11) Contact and metallization: The alloy is annealed in the alloy furnace at 380-430 e C for 30-60 minutes in ⁇ or (N 2 + H 2 ).
  • the device after the conventional L0C0S or STI isolation is cleaned, firstly washed by a conventional method, and then immersed in a hydrofluoric acid/isopropanol/water mixed solution for 2-10 minutes at room temperature. Rinse with deionized water, immediately after immersion in the furnace; hydrofluoric acid: isopropanol: water weight ratio is 0. 2-1. 5%: 0. 01 0. 10%: 1%.
  • the interface nitrogen oxide layer in step 1 may be formed by first injecting nitrogen into Si and then rapidly thermally oxidizing, or rapidly oxidizing to form SiOx, and then N0 nitriding or plasma nitriding to form SiON; SiOx may also be used. 0 3 chemical treatment is formed.
  • the high-k gate dielectric film in step 2 is an Hf-based oxide, which may be HfA10 HfAlON, HfSiAlON or HfLaON, etc., and the high dielectric constant gate dielectric film can be deposited by physical vapor deposition, metal organic chemical vapor deposition. Or formed by an atomic layer deposition process.
  • the metal nitride TiN gate film and the A1 film in the step 3 may be formed by physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition.
  • the barrier metal layer in step 4 may be an A1N or TaN film formed by physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition, and the thickness is 4-10 nm D.
  • the hard mask in step 5 is SiO 2 (0), Si 3 N 4 (N) or a laminated 0/N or 0/N/Oo hard mask using fluorine-based etching.
  • the polysilicon in step 6 is etched by F-based C1 or HBr plus C1, and the TaN/TiN (A1) / high-k gate dielectric stacked gate structure is c1-based reactive ion etching or inductive coupling.
  • Plasma etching is formed or formed by chemical wet etching.
  • the NiSi in the step 10 is completed by sputtering a 20-20 nm Ni film by two-step annealing and selective etching therebetween, and the NiSi film thickness is 15-40.
  • the method provided by the invention is characterized in that a doped metal A1 film is deposited in a metal gate such as TiN, and the metal A1 ion is driven to the interface of the high-k gate dielectric film and the interface oxide layer by heat treatment, and A1 0 is generated by the interface reaction.
  • the dipole realizes the adjustment of the effective work function of the metal gate of the PM0S device.
  • the adjustment effect is the distance between the deposition thickness of A1, the interface between the A1 layer and the TiN/Hf base high K medium, that is, the thickness of TiN-1, the heat treatment conditions, and the near-high K medium/Si0 2 interface in the Hf-based K medium.
  • the state is related to the factor.
  • the invention has good adjustment effect on the effective work function of the metal gate of the PM0S device, is simple and controllable in operation, low in cost, and is fully compatible with the conventional CM0DS process, and is convenient for industrialization of the integrated circuit.
  • Figure 1 is a comparison of the characteristics of the C-V of the poly-Si/TiN 1/Al/TiN-2 metal gate PM0S doped with A1 and without A1 in the TiN metal gate.
  • Figure 2 is a comparison of CV characteristics of poly-Si/TiN-1/Al/TiN-2 metal gate PM0S capacitors with different TiN-1 film thicknesses. detailed description
  • Step 1) Growth of an ultra-thin interface oxide layer or an oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method;
  • Step 2) Formation of a high dielectric constant (K) gate dielectric film at 500 1000 ,, 10- 120 second thermal annealing;
  • Step 3) depositing a metal gate by physical vapor deposition, a thin layer of TiN-1 is deposited by reactive sputtering, followed by sputter deposition of a thin layer of metal Al, followed by reactive sputtering deposition of a layer of TiN. 2;
  • Step 4) depositing a barrier metal layer
  • Step 5) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing photolithography and hard mask etching; step 6) removing the glue, masking the hard mask, and sequentially etching the polysilicon film/barrier metal / metal gate / high K gate dielectric / interface Si0 2 form a stacked gate structure;
  • Step 7) forming low-energy ion implantation and large-angle implantation of the sidewall 1 and the source/drain extension regions;
  • Step 8) forming sidewall 2 and source/drain ion implantation
  • Step 9) rapid thermal annealing annealing in N 2 for 2-30 seconds at 600-1050 ;; driving metal A1 ions to the interface between the high-k gate dielectric film and the interface oxide layer while completing source/drain impurity activation Upper, through the interface reaction to generate A1-0 dipole, to achieve the adjustment of the effective work function of the metal gate of the PM0S device;
  • Step 11) Contact and metallization: Alloy anneal 30 60 minutes in N 2 or (N 2 + H 2 ) in an alloy furnace at a temperature of 380 430 °C.
  • Step 2 SiOx formation of the interface layer: rapid thermal annealing (RTA) in N 2 at 600-80 (TC temperature) for 20-120 seconds to form an oxide layer of 6-8 angstroms;
  • RTA rapid thermal annealing
  • Step 3) Formation of a high dielectric constant (K) gate dielectric film: alternately sputtering an A1 target, an Hf target, and a Si target to form HfSiAlON in a N 2 /Ar atmosphere by a magnetron reactive sputtering process, and a sputtering working pressure 5 X l (T 3 Torr, sputtering power 100-500W, deposited HfSiAlON high K gate dielectric film thickness 10 50 angstroms;
  • Step 4) Ultrasonic cleaning; ultrasonic cleaning with acetone and absolute ethanol for 5-10 minutes, deionized water Rinse, ⁇ ;
  • Step 5) Rapid thermal annealing after deposition of high K medium The sheet is immediately dried and then fed into the furnace at a temperature of 500-1000 CTC for 10-120 seconds.
  • Step 6 Metal gate film deposition: consisting of three layers of TiN-1/Al/TiN-2 metal, wherein the TiN-1 and TiN 2 metal gate films are sputtered in a N 2 /Ar atmosphere by a magnetron reactive sputtering process.
  • a Ti target working pressure 5X 10- 13, N 2 flow 2- 8 sccm
  • sputtering power is 600-1000w
  • TiN- 1 metal gate having a thickness of 2- 5 Ti-N 2 metal gate film having a thickness of 10-20nm A1 2 -5 Sputtering A1 target in Ar atmosphere by magnetron sputtering to form working pressure 5X 10— 13 3 ⁇ 4 Ar flow 20-24 sccm
  • Step 7) Magnetron reactive sputtering deposition of barrier metal layer TaN film, working pressure 5 ⁇ 1 ( ⁇ 13 ⁇ 2 flow rate 2-8 sccm, sputtering power 600-1000w, thickness 4- 8nm
  • Step 8) Low-pressure chemical vapor deposition of a polysilicon film and a SiO 2 hard mask, followed by photolithography and etching using a fluorine-based etch hard mask.
  • Step 9) removing the glue, masking the hard mask, sequentially etching the polysilicon film/TaN/TiN (A1) metal gate/high' ⁇ gate dielectric HfSiAlON/interface Si0 2 to form a stacked gate structure;
  • the polycrystalline silicon is etched by F-based C1 or HBr plus C1, and the TaN/TiN (A1) metal gate/high-k gate dielectric HfSiAlON/interfacial Si0 2 stack is formed by C1-based reactive ion etching or inductively coupled plasma etching. Formed, or formed by chemical wet etching.
  • Step 10) conventionally forming side wall 1 and source/drain extension regions with low energy ion implantation and large angle implantation;
  • step 11) conventionally forming sidewall spacers 2 and source/drain and ion implantation;
  • Step 12) Rapid thermal annealing annealing at 600-1050 ° C for 2-30 seconds; while driving the thermal activation of the source/drain impurities, driving the metal A1 ions to the high-k gate dielectric film and the interface oxide layer On the interface, an A1-0 dipole is generated through the interface reaction to realize the adjustment of the effective work function of the metal gate of the PM0S device;
  • Step 11) Contact and metallization: The alloy is annealed in N 2 or (N 2 +H 2 ) at a temperature of 380 430 ° C for 30-60 minutes.
  • V FB flat band voltage
  • TiN-1 is a C-V characteristic of a 2 nm sample. If it is thick, the adjustment function of the gate work function is weakened, as shown in Fig. 2, TiN-1 is the C-V characteristic of the 4 nm sample.
  • the TiN-1 has a good CV characteristic for the 3 samples, no leakage, and the flat band voltage is also larger.
  • Table 2 gives a comparison of the characteristic parameters of samples with different TiN-1 film thicknesses, and the electrode structure is the same as Poly-Si/TaN/TiN-1/A1 3 ⁇ /TiN-2/Hf SiA10N/Si0 2 .

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

PMOS器件叠层结构的制备方法
本申请要求了 2011年 2月 25 日提交的、 申请号为 201110046360. 1、 发明名称 为 "PM0S器件叠层结构的制备和栅功函数调节方法"的中国专利申请的优先权， 其 全部内容通过弓 I用结合在本申请中。 技术领域
本发明属于半导体技术领域，特别是涉及先栅工艺中一种 PM0S金属栅 /高 K栅介 质叠层结构的制备和栅功函数的调节方法，适合于 32/22纳米及以下技术代高性能纳 米互补型金属氧化物半导体 （CMOS)器件的应用。 背景技术
随着 CMOS器件的特征尺寸按 Moore定律持续缩小， CMOS集成电路的发展遇到了 严峻的挑战。 为克服小尺寸器件成指数规律急增的栅漏电流、 严重的多晶硅栅耗尽、 增大的栅电阻及 PM0S器件严重的硼穿透等问题， 采用高介电常数 （K)栅介质 /金属 栅结构代替传统的 Si02/poly (多晶硅） 栅结构已成为业界的共识。 但是金属栅集成 到高 K栅介质上仍有许多问题急待解决， 如热稳定性问题， 界面态问题， 特别是费米 钉扎效应使纳米 CMOS 器件需要的适当低的阈值电压的获得面临很大挑战， 尤其是 PM0S器件， 因为 PM0S器件需要的高的功函数更难达到。 发明内容
本发明的目的在于提出一种用于 PM0S器件的金属栅 /高 K栅介质叠层结构的制备 和栅功函数调节方法。
为实现上述目的， 本发明利用物理汽相淀积 （PVD) 方法， 在高 K介质上面淀积 金属栅膜， 它由 3层金属膜组成： 先淀积 TiN 1膜， 然后淀积一薄层金属 A1膜， 接 着再淀积一层 TiN- 2膜， 这样完成整个金属栅的淀积； 然后淀积势垒金属层； 淀积多 晶硅膜和硬掩模， 接着进行光刻和硬掩膜的刻蚀； 去胶后， 依次刻蚀多晶硅膜 /势垒 金属层 /金属栅 /高 K介质 /界面氧化层形成多晶硅膜 /势垒金属层 /金属栅 /高 K栅介质 /界面氧化层叠层栅结构。 然后进行常规的侧墙形成、源 /漏注入及快速热退火， 在完 成源 /漏杂质激活的同时，将金属 A1离子驱动到高 K栅介质薄膜与界面氧化层间界面 上， 通过界面反应生成 Al 0偶极子， 从而实现了对 PM0S器件金属栅有效功函数的调 节。其调节效果与 A1的淀积厚度、 A1层与 TiN/ Hf基高 K介质界面的距离， 即 TiN - 1 的厚度、 热处理条件以及 Hf基高 K介质中接近高 K介质 / Si02界面处的状态等因数 有关。
本发明提供的用于 PM0S器件的金属栅 /高 K栅介质叠层结构的制备和栅功函数调 节方法， 其主要步骤如下：
步骤 1 )在完成常规的 L0C0S或 STI介质隔离后， 用快速热氧化或化学法在半导 体衬底上生长超薄界面氧化层或氮氧化层；
步骤 2) 高介电常数 （K) 栅介质薄膜的形成， 并于 500- 105CTC下， 4-120秒热 退火；
步骤 3) 淀积金属栅； 所述金属栅由 3层组成， 依次为 TiN 1/Al/TiN- 2， 其中 TiN 1金属栅厚度为 2 - 6 ， 金属 A1膜厚度为 2- 5匪， TiN- 2金属栅厚度为 10- 20誦； 步骤 4) 淀积势垒金属层；
步骤 5) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 6) 去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /势垒金属 /金属栅 /高 K栅 介质 /界面 Si02形成叠层栅结构；
步骤 7) 形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入；
步骤 8) 形成侧墙 2和源 /漏和离子注入；
步骤 9)快速热退火： 于 600- 1050°C下， 于 N2退火 2-30秒； 在完成源 /漏杂质激 活的同时， 将金属 A1离子驱动到高 K栅介质薄膜与界面氧化层界面上， 通过界面反 应生成 A1-0偶极子， 实现对 PM0S器件金属栅有效功函数的调节；
步骤 10) NiSi硅化物形成；
步骤 11 ) 接触和金属化： 380- 430eC温度下， 在合金炉内于 ^或 （N2+H2 ) 中合 金退火 30-60分。
所述的方法中， 步骤 1之前对完成常规 L0C0S或 STI隔离后的器件进行清洗， 先 采用常规方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡 2-10分钟， 去 离子水冲洗， 甩干后立即进炉； 氢氟酸：异丙醇： 水的重量比为 0. 2-1. 5%: 0. 01 0. 10%: 1%。
所述的方法中， 步骤 1 中界面氮氧化层可采用先注入氮到 Si中再快速热氧化形 成， 或先快速热氧化形成 SiOx, 再用 N0氮化或等离子氮化形成 SiON; SiOx也可用 03化学处理形成。
所述的方法中， 步骤 2中高 K栅介质膜为 Hf基氧化物， 可以是 HfA10 HfAlON, HfSiAlON或 HfLaON等， 所述高介电常数栅介质膜可通过物理气相淀积、 金属有机化 学气相沉积或原子层淀积工艺形成。
所述的方法中， 步骤 3中的金属氮化物 TiN栅薄膜和 A1薄膜可通过物理气相淀 积、 金属有机化学气相沉积或原子层淀积工艺形成。
所述的方法中， 步骤 4中的势垒金属层可以是 A1N或 TaN薄膜， 通过物理气相 淀积、 金属有机化学气相沉积或原子层淀积工艺形成， 厚度 4- 10nmD
所述的方法中，步骤 5中的硬掩膜是 Si02 ( 0)、 Si3N4 (N)或其叠层 0/N或 0/N/Oo 硬掩膜采用氟基刻蚀。
所述的方法中， 步骤 6中多晶硅采用 F基加 C1基或 HBr加 C1基刻蚀， TaN/TiN (A1 ) /高 K栅介质叠层栅结构釆用 C1基反应离子刻蚀或感应偶合等离子刻蚀形成， 或采用化学湿法腐蚀形成。
所述的方法中， 步骤 10中的 NiSi由溅射 8- 20nm Ni薄膜后， 通过两步退火和其 间的选择腐蚀完成， NiSi膜厚 15- 40
本发明提供的方法， 其特点是在 TiN等金属栅中淀积掺杂金属 A1膜， 通过热处 理， 将金属 A1离子驱动到高 K栅介质薄膜与界面氧化层界面上， 通过界面反应生成 A1 0偶极子， 实现对 PM0S器件金属栅有效功函数的调节。 其调节效果与 A1的淀积 厚度、 A1层与 TiN/ Hf 基高 K介质界面的距离， 即 TiN- 1的厚度、 热处理条件以及 Hf基高 K介质中接近高 K介质 / Si02界面处的状态等因数有关。优化这些参量， 可以 获得合适的有效栅功函数， 以期获得合适低的阈值电压。 本发明对 PM0S器件金属栅 有效功函数的调节效果好， 操作简便可控， 成本低， 与常规 CM0DS工艺完全兼容， 便 于集成电路产业化。 附图说明：
图 1是 TiN金属栅中掺 A1和不掺 A1的 poly- Si/TiN 1/Al/TiN- 2金属栅 PM0S电 容 C- V特性比较。
图 2是不同 TiN- 1薄膜厚度的 poly- Si/TiN- 1/Al/TiN- 2金属栅 PM0S电容 C V特 性比较。 具体实施方式
本发明提供的用于 PM0S器件的金属栅 /高 K栅介质叠层结构的制备和栅功函数调 节方法， 在完成常规的 L0C0S或 STI介质隔离后， 其主要步骤如下：
步骤 1 )用快速热氧化或化学法在半导体衬底上生长超薄界面氧化层或氮氧化层； 步骤 2) 高介电常数 （K) 栅介质薄膜的形成， 并于 500 1000Ό下， 10- 120秒热 退火；
步骤 3) 淀积金属栅： 采用物理汽相淀积完成， 先反应溅射淀积一薄层 TiN-l， 接着溅射淀积一薄层金属 Al， 然后再反应溅射淀积一层 TiN 2;
步骤 4) 淀积势垒金属层；
步骤 5) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 6) 去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /势垒金属 /金属栅 /高 K栅 介质 /界面 Si02形成叠层栅结构；
步骤 7 ) 形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入；
步骤 8) 形成侧墙 2和源 /漏离子注入；
步骤 9 )快速热退火： 于 600- 1050Ό下， 于 N2中退火 2-30秒； 在完成源 /漏杂质 激活的同时， 将金属 A1离子驱动到高 K栅介质薄膜与界面氧化层间界面上， 通过界 面反应生成 A1- 0偶极子， 实现对 PM0S器件金属栅有效功函数的调节；
步骤 10 ) iSi硅化物形成；
步骤 11 ) 接触和金属化： 380 430°C温度下， 在合金炉内于 N2或 (N2+H2) 中合 金退火 30 60分。
以下对本发明作进一步的介绍。
步骤 1 ) 清洗： 在器件隔离形成后， 进行界面氧化层形成前的清洗， 先采用常规 方法清洗， 然后按重量比氢氟酸：异丙醇：水 =0. 3 0. 8%: 0. 01-0. 08%: 1%混合溶液在室 温下浸泡 2-10分， 去离子水冲洗， N2中甩千后立即进炉；
步骤 2)界面层 SiOx形成：在 600- 80(TC温度下，在 N2中快速热退火（RTA) 20- 120 秒， 生成 6-8埃的氧化层；
步骤 3 ) 高介电常数（K)栅介质薄膜的形成： 采用磁控反应溅射工艺在 N2/Ar气 氛中交替溅射 A1靶、 Hf靶和 Si靶淀积形成 HfSiAlON,溅射工作压强为 5 X l(T3Torr， 溅射功率为 100- 500W, 淀积形成的 HfSiAlON高 K栅介质薄膜厚 10 50埃；
步骤 4) 超声清洗； 采用丙酮、 无水乙醇先后各超声清洗 5-10分钟， 去离子水 冲洗， ^中甩千；
步骤 5) 淀积高 K介质后快速热退火： 片子甩干后立即进炉， 温度 500- lOOCTC, 时间 10-120秒。
步骤 6)金属栅薄膜淀积：由 TiN- 1/Al/TiN- 2三层金属组成，其中 TiN-1和 TiN 2 金属栅薄膜采用磁控反应溅射工艺在 N2/Ar气氛中溅射 Ti靶形成，工作压强 5X 10—13 , N2流量 2- 8 sccm, 溅射功率为 600-1000w TiN- 1金属栅厚度为 2- 5 Ti-N 2 金属栅厚度为 10-20nm A1薄膜 2-5 采用磁控溅射工艺在 Ar气氛中溅射 A1靶形 成工作压强 5X 10— 13 ¾ Ar流量 20- 24 sccm, 溅射功率为 100- 500w
步骤 7) 磁控反应溅射淀积势垒金属层 TaN薄膜， 工作压强 5Χ 1(Γ13 Ν2流量 2-8 sccm, 溅射功率为 600- 1000w， 厚度 4- 8nm
步骤 8)低压化学汽相淀积多晶硅膜和 Si02硬掩模， 然后进行光刻和釆用氟基刻 蚀硬掩膜。
步骤 9)去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /TaN/TiN (A1)金属栅 /高 ' Κ 栅介质 HfSiAlON/界面 Si02形成叠层栅结构；
其中多晶硅采用 F基加 C1基或 HBr加 C1基刻蚀， TaN/TiN (A1 )金属栅 /高 K栅 介质 HfSiAlON/界面 Si02叠层结构采用 C1基反应离子刻蚀或感应偶合等离子刻蚀形 成， 或采用化学湿法腐蚀形成。
步骤 10) 常规形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入； 步骤 11) 常规形成侧墙 2和源 /漏和离子注入；
步骤 12) 快速热退火： 于 600- 1050°C下， 于^中退火 2-30秒； 在完成源 /漏杂 质热激活的同时， 将金属 A1离子驱动到高 K栅介质薄膜与界面氧化层界面上， 通过 界面反应生成 A1-0偶极子， 实现对 PM0S器件金属栅有效功函数的调节；
步骤 13) NiSi硅化物形成： 由溅射 8- 15 Ni薄膜后， 通过两步退火和其间的 选择腐蚀完成， NiSi膜厚 15- 30
步骤 11) 接触和金属化： 380 430°C温度下， 在合金炉内于 N2或 （N2+H2) 中合 金退火 30-60分。
由图 1可见， 当在 TiN- 1膜和 TiN-2膜之间加入 3nm A1膜后， 平带电压 （VFB) 向正方向大幅度移动， VFB的增加量为 0. 135V, 表明 PM0S器件的有效栅功函数得到大 幅度增加， 满足了 PM0S器件对栅功函数的要求。而且掺 A1样品的栅介质等效厚度大 幅度减薄 （电容增大）， 从 34埃减薄到 23埃， 这对提高器件驱动能力和增强栅控能 力都十分有利。 参数见表 1。
由图 2可见， 对同样的 A1薄膜厚度 （3nm)， TiN- 1膜的厚度不同， 平带电压向 正方向移动的幅度不同， TiN- 1膜的厚度需要优化， 如薄了， 栅漏电会增加， 见图 2 中 TiN- 1为 2nm样品的 C- V特性可知。 如厚了， 栅功函数调节能力减弱， 见图 2中 TiN-1为 4nm样品的 C- V特性可知。 TiN- 1为 3議样品的 C V特性较好， 没有漏电， 且平带电压也更大些。表 2给出了 TiN- 1膜厚度不同的样品的特征参数比较， 其电极 结构同为 Poly- Si/TaN/TiN- 1/A1 3誦 /TiN- 2/Hf SiA10N/Si02。
以上参照本发明的实施例对本发明予以了说明。但是， 这些实施例仅仅是为了说 明的目的， 而并非为了限制本发明的范围。 本发明的范围由所附权利要求及其等价物 限定。 不脱离本发明的范围， 本领域技术人员可以做出多种替换和修改， 这些替换和 修改都应落在本发明的范围之内。
表 1
Figure imgf000008_0001
表 2
Figure imgf000008_0002

Claims

权 利 要 求
1、 一种 PM0S器件叠层结构的制备和栅功函数调节方法， 包括如下步骤：
1 )在完成常规的 L0C0S或 STI介质隔离后，在半导体衬底上生长界面氧化层或氮 氧化层；
2) 高介电常数 (K) 栅介质薄膜的形成， 并于 500- 102(TC下， 4- 120秒热退火；
3) 淀积金属栅， 所述金属栅由三层组成， 依次为 TiN-1/Al/TiN- 2;
4) 淀积势垒金属层；
5) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀；
6) 去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /势垒金属 /金属栅 /高 K栅介质 / 界面 Si02形成叠层栅结构；
7) 形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入；
8) 形成侧墙 2和源 /漏离子注入；
9 ) 快速热退火： 于 600- 105CTC下， 于 N2中退火 2-30秒； 在完成源 /漏杂质激活 的同时， 将金属 A1离子驱动到高 K栅介质薄膜 /界面氧化层界面上， 通过界面反应生 成 A1-0偶极子， 实现对 PM0S器件金属栅有效功函数的调节；
10) NiSi硅化物形成；
11 )接触和金属化： 380- 430Ό温度下， 在合金炉内于 ^或 （N2+H2) 中合金退火 30-60分。
2、根据权利要求 1所述的方法， 其中， 步骤 1之前对完成常规的 L0C0S或 STI隔 离后的器件进行清洗， 先采用常规方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室 温下浸泡 2- 10分钟， 去离子水冲洗， 甩干后立即进炉； 氢氟酸:异丙醇：水的重量比为 0. 2 1· 5%: 0. 01-0. 10%: 1%。
3、 根据权利要求 1所述的方法， 其中， 步骤 1 中是釆用快速热氧化或化学法生 长界面氧化层或氮氧化层； 界面氮氧化层可采用先注入氮到 Si中再快速热氧化形成， 或先快速热氧化形成 SiOx, 再用 Ό氮化或等离子氮化形成 SiON; SiOx可用 03化学处 理形成。
4、 根据权利要求 1所述的方法， 其中， 步骤 2 中高 K栅介质膜是 Hf基高 K栅介 质， 可以是 HfA10、 HfA10N\ Hf SiAlON或 HfLaON, 所述高介电常数栅介质膜通过物理 气相淀积、 金属有机化学气相沉积或原子层淀积工艺形成。
5、 根据权利要求 1所述的方法， 其中， 步骤 3中的金属栅中， TiN 1金属栅厚度 为 2- 6nm, 金属 A1 膜厚度为 2-5議， TiN- 2金属栅厚度为 10- 20腿。
6、 根据权利要求 1所述的方法， 其中， 步骤 3中金属氮化物栅薄膜和 A1薄膜采 用物理气相淀积、 金属有机化学气相沉积或原子层淀积工艺形成。
7、 根据权利要求 1所述的方法， 其中， 步骤 4中势垒金属层是 TaN或 A1N， 厚度 4-lOnm, 采用物理气相淀积、 金属有机化学气相沉枳或原子层淀积工艺形成。
8、 根据权利要求 1所述的方法， 其中， 步骤 5中的硬掩膜是 Si02 ( 0)、 Si3N4 (N) 或其叠层 0/N或 0/N/0; 硬掩膜采用氟基刻蚀。
9、 根据权利要求 1所述的方法， 其中， 步骤 6中多晶硅采用 F基加 C1基或 HBr 加 C1基刻蚀， TaN/TiN (Al ) /高 K栅介质 /界面 Si02叠层结构采用 C1基反应离子刻蚀 或感应偶合等离子刻蚀形成， 或采用化学湿法腐蚀形成。
10、 根据权利要求 1所述的方法， 其中， 步骤 10中的 NiSi由溅射 8- 20nm i薄 膜后， 通过两步退火和其间的选择腐蚀完成， NiSi膜厚 15-40nm。
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