WO2012086379A1 - 増幅回路及び無線通信装置 - Google Patents
増幅回路及び無線通信装置 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0222—Continuous control by using a signal derived from the input signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
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- H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
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- H—ELECTRICITY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/504—Indexing scheme relating to amplifiers the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
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- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3209—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion the amplifier comprising means for compensating memory effects
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- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3224—Predistortion being done for compensating memory effects
Definitions
- the present invention relates to an amplifier circuit and a wireless communication device.
- a desired input / output characteristic may not be obtained due to nonlinear distortion characteristics of the amplifier.
- HPA high power amplifier
- a complex IQ baseband signal having a low frequency before being converted into a radio signal is disclosed in Patent Document 1.
- FIG. 2 it is necessary to perform predistortion that cancels out the nonlinear distortion characteristic of the amplifier in advance using digital signal processing.
- a model or an inverse model (distortion compensation model) of the amplifier is estimated, and distortion in the amplifier is compensated based on the model.
- Non-Patent Document 1 proposes a distortion compensation model for an amplifier in consideration of the memory effect.
- the memory effect generated in the amplifier 100 is caused by a plurality of nonlinear elements NL (memory terms 0 to L 1 + L having different characteristics over time). It is expressed as a composite of 2 ).
- the characteristics of each of the plurality of nonlinear elements NL are expressed as in Expression (2).
- the nonlinear characteristic (input / output characteristic) of each nonlinear element NL is defined based on the input signal u [n ′] to the amplifier 100.
- each nonlinear element NL is given an input signal u [n ′].
- the delay element D is connected to the preceding stage of each nonlinear element NL of the memory terms 1 to L 1 + L 2 , and the input signal u [n ′] given to each nonlinear element NL is temporally related.
- Each has a different signal. That is, each nonlinear element NL of the memory terms 1 to L 1 + L 2 represents the memory effect in the amplifier.
- the power supply voltage (drain signal) of the amplifier is modulated using the input signal of the amplifier, and the power consumption of the amplifier is dynamically changed according to the size of the input signal (power supply (Referred to as Patent Document 2, Non-Patent Documents 2 and 3).
- Patent Document 2 Non-Patent Documents 2 and 3
- the power supply modulation method when the voltage of the input signal is small, the power consumption of the amplifier is suppressed, and the power efficiency is improved. In this way, a highly efficient amplification technique can be provided.
- ET operation envelope tracking operation
- the present invention has been made in connection with the solution of the above problems.
- the present inventor has obtained a new idea that a memory effect that has not been recognized in amplifiers should be considered. That is, in the conventional model, as apparent from the equation (1), only the memory effect that occurs between the input and output of the amplifier is considered as the memory effect.
- the power supply voltage (drain voltage) of the amplifier 100 changes according to the envelope signal of the input signal. That is, in the envelope tracking drive method, a transmission signal (or a signal obtained by shaping the transmission signal) is input to the amplifier while adjusting the power supply voltage supplied to the amplifier according to the input signal power.
- the amplifier whose power supply voltage changes as in the envelope tracking drive system is a two-input system.
- signals input through a plurality of different paths such as an amplifier input-output path and an amplifier power supply-output path are combined in the amplifier. Therefore, the signal input to the amplifier is affected by the frequency characteristics and the memory effect in each path, and the amplifier output may be greatly distorted.
- the present invention provides an amplifier for amplifying a signal, a variable power supply for changing a power supply voltage or a power supply current supplied to a power supply port of the amplifier according to a change in an envelope of the signal, and distortion of the amplifier.
- a distortion compensation unit that performs compensation, and the distortion compensation unit performs processing for compensating for a memory effect that occurs in a path from the power supply port to the signal output port of the amplifier. It is.
- the signal used to obtain the envelope does not need to be a signal amplified by an amplifier (for example, u [n] in the embodiment) itself, but a signal before distortion compensation (for example, x [n in the embodiment). ]).
- the distortion compensation unit compensates for a memory effect generated in a path from the signal input port to the signal output port of the amplifier and a memory effect generated in a path from the power supply port to the signal output port. It is preferable to carry out the treatment.
- both the memory effect generated in the path from the signal input port to the signal output port of the amplifier and the memory effect generated in the path from the power supply port to the signal output port of the amplifier can be compensated. it can.
- the distortion compensation unit includes an estimation unit that estimates a model of the amplifier, and is based on the model estimated by the estimation unit (either an inverse model or a normal model; the same applies hereinafter).
- the model represents at least a memory effect that occurs in a path from the power supply port to the signal output port. It is more preferable that the model also expresses a memory effect that occurs in a path from the signal input port to the signal output port.
- the distortion compensation unit includes an estimation unit that estimates a model of the amplifier, and performs distortion compensation based on the model estimated by the estimation unit.
- the amplifier includes: It is modeled as a combination of a plurality of element amplifiers, and each of the plurality of element amplifiers in the model includes an input signal input to the signal input port and the power source supplied from the variable power source. A voltage or the power supply current is applied, and a combination of outputs of the plurality of element amplifiers in the model corresponds to an output of the amplifier.
- Each of the plurality of element amplifiers in the model includes the signal input Nonlinear characteristics based on the input signal input to the port and the power supply voltage or power supply current supplied from the variable power supply Are defined, the plurality of elements amplifiers in the model, respectively, be given the power supply voltage or the supply current at different times is preferable.
- Each of the plurality of element amplifiers in the model is modeled as a combination of a plurality of nonlinear elements, and each of the plurality of nonlinear elements has an input signal input to the signal input port. And a combination of outputs of the plurality of nonlinear elements corresponds to the output of the element amplifier, and the plurality of nonlinear elements are respectively based on the input signal and the power supply voltage or the power supply current.
- nonlinear characteristics are defined, and the plurality of nonlinear elements are preferably given the input signals at different times, respectively.
- the amplifier model estimated by the distortion compensator can be based on the later-described equation (10) described as the embodiment.
- the “amplifier model based on Expression (10)” includes a model directly corresponding to Expression (10) and its inverse model (Expression (12)), and further an expression obtained by modifying Expression (10).
- a model based on (Equation (15) etc.) is also included.
- the distortion compensator has a memory effect generated in a path from the power supply port to the signal output port, and a memory generated in a path from the signal output port of the distortion compensator to the signal output port of the amplifier. It is preferable to perform a process for compensating for the effect.
- the amplifier model estimated by the distortion compensator can be based on the later-described equation (15) described as the embodiment.
- the “amplifier model based on equation (15)” includes a model directly corresponding to equation (15) and its inverse model (equation (17)), and further an equation obtained by modifying equation (15).
- a model based on (Equation (18) etc.) is also included.
- the amplifier inverse model estimated by the distortion compensator can be based on the following equation (18) described as an embodiment.
- the present invention includes an amplifier that amplifies a signal and a distortion compensation unit that performs distortion compensation of the amplifier, and the distortion compensation unit is other than the signal input port of the amplifier.
- An amplifier circuit that performs processing for compensating for a memory effect that occurs in a path from an input port to a signal output port. According to the present invention, it is possible to compensate for the memory effect that occurs in the path from the input port other than the signal input port of the amplifier to the signal output port.
- an amplifier for amplifying a signal, and a variable power source for changing a power supply voltage or a power supply current supplied to a power supply port of the amplifier according to a change in an envelope of the signal.
- an estimator for estimating the model of the amplifier, and a distortion compensator for performing distortion compensation based on the model estimated by the estimator, wherein the amplifier in the model has a signal input of the amplifier
- a non-linear characteristic is defined based on an input signal input to a port and the power supply voltage or the power supply current supplied from the variable power supply.
- the amplifier has a two-input system.
- the signal input to the amplifier is affected by the frequency characteristics and the memory effect in each path, and the amplifier output is greatly distorted. Therefore, as in the present invention described above, an amplifier model in which nonlinear characteristics are defined based on the input signal input to the signal input port and the power supply voltage or the power supply current supplied from the variable power supply is adopted.
- the characteristics of each of the plurality of routes can be appropriately expressed, and a better model than the conventional one can be obtained.
- the model can be more specifically an amplifier model based on a later-described equation (4) described as an embodiment.
- the amplifier in the model is modeled as a combination of a plurality of nonlinear elements, and each of the plurality of nonlinear elements is given an input signal input to the signal input port, A combination of outputs of a plurality of nonlinear elements corresponds to the output of the amplifier, and each of the plurality of nonlinear elements has a nonlinear characteristic defined based on the input signal and the power supply voltage or the power supply current.
- the plurality of nonlinear elements may be given the input signals at different times, respectively. In this case, at least the memory effect of the path from the signal input port to the output signal port is represented. Of course, the memory effect of the path from the power supply port to the output signal port is also considered.
- model can be more specifically an amplifier model based on the later-described formula (7) described as an embodiment.
- a wireless communication system including the amplifier circuit according to any one of (1) to (14) for amplification of a transmission signal or amplification of a reception signal. Device.
- the present invention according to the above items (1) to (9) and the present invention according to the item (15) that refers to the items (1) to (9), in the path from the power supply port to the signal output port. Memory effects can be compensated.
- the signal output port is reached from an input port other than the signal input port of the width device. It is possible to compensate for memory effects that occur in the path.
- an amplifier model in which only one path is considered Compared with the case where a plurality of paths are considered, an appropriate amplifier model is obtained.
- FIG. 2 is a detailed circuit diagram of the amplifier circuit shown in FIG. 1.
- A is a figure which defines the nonlinear characteristic of ET amplifier which does not consider a memory effect
- (b) is a block diagram of the amplifier model which considered the 2nd memory effect.
- FIG. 6 is a characteristic diagram showing a nonlinear conversion characteristic of an input signal-power supply voltage. It is a block diagram of the amplifier circuit using the 1st modification of an ET amplifier model. It is a block diagram of the amplifier circuit using the 2nd modification of an ET amplifier model.
- FIG. 7 is a detailed circuit diagram of the amplifier circuit shown in FIG. 6. It is an experimental result which shows the unnecessary radiation in the amplifier circuit of FIG. It is a block diagram of an amplifier circuit of a source modulation system. It is a block diagram of the conventional amplifier circuit. It is a block diagram which shows the conventional amplifier model.
- FIG. 1 shows an amplifier circuit 1 according to the embodiment.
- the amplifier circuit 1 is mounted on a radio communication apparatus such as a radio base station apparatus and is used for amplifying a transmission signal.
- the amplifier circuit 1 may be used for amplification of the received signal.
- the amplifier circuit 1 includes a high output amplifier (HPA) 2, a variable power supply 3, and a distortion compensation unit 4.
- the amplifier 2 is for amplifying an input signal, and includes a signal input port 2a for inputting a signal and a signal output port 2b for outputting a signal.
- the amplifier 2 further includes a power supply port 2c to which a power supply voltage (drain voltage) V [n] is supplied.
- the power supply port 2c is an input port other than the signal input port 2a.
- This amplification circuit 1 is an envelope tracking drive system.
- the variable power supply 3 changes the power supply voltage V [n] supplied to the power supply port 2c of the amplifier 2 according to the envelope signal of the signal x [n]. That is, the amplifier 2 and the variable power supply 3 constitute an amplifier (hereinafter referred to as an ET amplifier) 200 that performs an envelope tracking operation.
- the power supply voltage supplied to the amplifier 2 changes according to the envelope of the signal x [n], so that the amplifier 2 can be operated with high efficiency.
- variable power supply 3 is not limited to changing the power supply voltage (drain voltage) V [n], but may change the power supply current (drain current).
- the variable power supply 3 is described as changing the power supply voltage. However, in the following description, it is functionally equivalent even if a part of “power supply voltage” is replaced with “power supply current”.
- the amplifier circuit 1 includes a power detection unit 5 and a power-voltage conversion unit 6 for the signal x [n].
- the power detection unit 5 detects and outputs the power value (envelope signal of the signal x [n]) of the signal x [n] (complex IQ baseband signal).
- the power-voltage conversion unit 6 has a function of converting the power detected by the power detection unit 5 into a power supply voltage value supplied to the amplifier 2.
- the power-voltage conversion unit 6 outputs the converted power supply voltage value (envelope voltage value) to the variable power supply 3.
- the variable power supply 3 dynamically changes the voltage V [n] supplied to the power supply port 2c of the amplifier 2 according to the converted power supply voltage value (envelope voltage value).
- the distortion compensation unit 4 includes an estimation unit 7 that estimates a model of the ET amplifier 200, and a distortion compensation processing unit 8 that performs predistortion processing on the signal x [n].
- the estimation unit 7 of the present embodiment is configured as an inverse characteristic estimation unit 7 that estimates an inverse model indicating the inverse characteristic of the ET amplifier 200 as a model of the ET amplifier 200. The details of the model estimated by the estimation unit 7 and the estimation method will be described later.
- the distortion compensation processing unit 8 acquires an inverse model of the ET amplifier 200 estimated by the estimation unit 7, performs distortion compensation processing on the signal x [n] based on the inverse model, and performs a signal after distortion compensation. u [n] is output. By using the signal u [n] compensated with a characteristic opposite to the distortion characteristic of the ET amplifier 200 as an input signal to the ET amplifier 200 having the distortion characteristic, the amplifier output y [n] in which the distortion is suppressed is obtained. Obtainable.
- the amplifier circuit 1 of FIG. 1 depicts only main components among the components of the amplifier circuit 1, and has the circuit configuration shown in FIG. 2 in detail.
- timing adjustment units 31 a and 31 b are provided in front of the distortion compensation unit 4 and / or the power-voltage conversion unit 6.
- the timing adjustment units 31a and 31b perform timing adjustment in order to match the time from the input (x [n]) of the amplifier circuit to the amplifier output through each path.
- DACs 32 and 32 for converting a digital signal into an analog signal are provided on the output side of the distortion compensator 4, and an analog IQ baseband signal converted by the DAC 32 is orthogonally modulated by an orthogonal modulator 33. .
- the signal after quadrature modulation is up-converted by the frequency converter 34.
- the signal after up-conversion is supplied to one or a plurality of drive amplifiers 35a and 35b and amplified.
- the outputs of the drive amplifiers 35a and 35b are given to the amplifier 2 constituting the ET amplifier 200.
- the drive amplifiers 35a and 35b are supplied with a power supply voltage from a fixed power supply having a fixed voltage instead of a variable power supply.
- the drive amplifiers 35a and 35b are also supplied with a power supply voltage from the variable power supply 3 in the same manner as the amplifier 2. May be supplied.
- the output signal y (t) of the amplifier 2 is detected by the coupler 36 and is supplied to the frequency conversion unit 38 via the variable attenuator (1 / G) 37.
- the frequency converter 38 downconverts the signal.
- the signal after the frequency conversion is given to the ADC 40 through a filter (low-pass filter or band-pass filter) 39.
- the ADC converts an analog signal into a digital signal and provides the output to the signal processing unit 41.
- the signal processing unit 41 performs signal processing such as digital quadrature demodulation and gives a digital IQ baseband signal to the distortion compensation unit 4.
- the amplifier circuit 1 is actually configured as shown in FIG. 2. However, in the following description, it can be explained only on the assumption of the configuration of FIG. To do.
- * [n] is a signal of digital complex baseband IQ expression sampled at time n ⁇ T when the sampling interval is T (seconds).
- * (T) indicates an analog signal at time t.
- the signal is exclusively indicated by * [n].
- x [n] is an input signal before distortion compensation by the distortion compensator 4
- x I [n] is a real part (I-channel) of x [n]
- x Q [ n] is the imaginary part (Q-channel) of x [n].
- x [n] x I [n] + i ⁇ x Q [n].
- u [n] is an input signal after distortion compensation by the distortion compensator 4
- u I [n] is a real part (I-channel) of u [n]
- u ′ [n] is a replica signal for inverse characteristic estimation
- u I ′ [n] is a real part (I-channel) of u ′ [n]
- y [n] is an output signal of the amplifier 2
- y I [n] is a real part (I-channel) of y [n]
- the nonlinear characteristic of the amplifier is defined according to the input signal u [n] to the amplifier.
- the nonlinear characteristic of the ET amplifier 200 in which the power supply voltage V [n] changes according to the envelope signal is defined as the following formula (4) using the power supply voltage (drain voltage) V [n]. To do.
- first memory effect a memory effect
- second memory effect The nonlinear characteristic of the amplifier when there is no (hereinafter referred to as “second memory effect”) is shown. Therefore, the model of the ET amplifier 200 when not considering both the first memory effect and the second memory effect is as shown in FIG.
- the delay element 12 is provided on the line of the input signal u [n ′′] to the nonlinear element 10 corresponding to the amplifier 2 constituting the ET amplifier 200, and the input signal u A power supply voltage V [n ′′] corresponding to [n ′′] is supplied from the variable power supply 11 (corresponding to the variable power supply 3 in FIG. 1) to the nonlinear element 10. That is, the nonlinear element 10 shown in FIG.
- the output Y ′′ 0,0 [n ′′ ⁇ M 1 ] is an input signal u [n ′′ ⁇ M 1 ] that is an input to the signal input port 2 a of the ET amplifier 200 and the power supply of the amplifier 2 that constitutes the ET amplifier 200.
- a power supply voltage V [n ′′] that is an input to the port 2c.
- the delay element 12 is provided on the line of the input signal u [n ′′].
- the delay element is expressed on the line on the variable power supply 11 side. That is, in equation (5), if ⁇ M 1 ⁇ 0, the delay of u [n ′′] is larger, and if ⁇ M 1 > 0, the delay of V [n ′′] is greater. Is big.
- the model of the ET amplifier 200 is expressed by the following equation (6) ).
- Y ′ 0 [n ′′ ⁇ M 1 ] Output signal k of the ET amplifier 200 k: Order l ′′: Relative delay L 1 generated with respect to the input signal u [n ′′] of the ET amplifier 200 in the signal amplification path: Signal amplification Maximum value of relative preceding samples in path L 2 : Maximum value of relative delay samples in signal amplification path M 1 : Maximum value of relative preceding samples in power path K 1 "-L1 , ⁇ M1 is the maximum order of the characteristics of the ET amplifier 200, and the subscripts are a coefficient related to the relative delay (signal amplification path) l ′′ ⁇ L 1 and a coefficient H k related to the relative delay (power supply path) ⁇ M 1 , l "-
- the above equation (7) represents a nonlinear element in which the first memory effect is expressed in the ET amplifier 200. That is, the equation (7) is similar to FIG. 11 and the equation (3) in that the ET amplifier 200 includes L 1 + L 2 +1 (one non-memory term for the first memory effect and one for the first memory effect). This is expressed by the synthesis of a non-linear element having L 1 + L 2 memory terms. A plurality of (L 1 + L 2 +1) nonlinear elements may have different nonlinear characteristics.
- the nonlinear element in which the first memory effect is expressed is referred to as an “element amplifier”.
- an element amplifier a plurality of (L 1 + L 2 +1) nonlinear elements constituting the element amplifier are each given an input signal input to the signal input port 2a.
- the synthesized output corresponds to the output of the element amplifier.
- the nonlinear characteristics of the plurality of nonlinear elements are defined by the input signal u and the power supply voltage V, unlike the nonlinear elements shown in FIG. 11 and Equation (3).
- the plurality of non-linear elements in one element amplifier respectively, the input signals at different times n '+ L 1 -M 1 ⁇ n' -L 2 -M 1 u [n '+ L 1 -M 1] ⁇ ⁇ u [n '-L 2 -M 1] is given. Further, the plurality of non-linear elements in one element amplifier, respectively, given a power supply voltage V of the common time n '-l' [n '-l '].
- FIG. 3B shows a model of the ET amplifier 200 using the element amplifier 20 (an amplifier model in which the first and second memory effects are considered). Further, the ET amplifier model of FIG. 3B is expressed by the following equations (8) and (9).
- the ET amplifier model is modeled as a combination of a plurality of element amplifiers 20.
- This ET amplifier model has M 1 + M 2 +1 (one element amplifier 20a which is a non-memory term for the second memory effect and one element amplifier 20b which is a memory term for the second memory effect is M 1 + M 2.
- the plurality of elements amplifier 20, delay element 22 via a (corresponding to the delay element 12 in FIG. 3 (a)), respectively, 'the input signal u in -M 1 [n' common time n -M 1] is Given.
- the delay element 22 is provided on the line of the input signal u [n ′ ].
- the delay element 22 is provided on the line on the variable power source 21 side. It may be expressed by putting
- Each of the plurality of element amplifiers 20 is supplied with a power supply voltage V supplied from a variable power supply 21 (corresponding to the variable power supply 3 in FIG. 1).
- the power supply voltage V [n ′] at time n ′ is applied to the element amplifier 20a, which is a non-memory term for the second memory effect, among the plurality of element amplifiers 20, whereas the second memory effect is applied.
- the plurality of elements amplifier 20b is a memory section, -1 ⁇ n '-M 1 -M 2 of the power source voltage V [n' -1] where 'time n delayed from' time n ⁇ ⁇ ⁇ V [ n '-M 1 -M 2] is given.
- the delay elements 23 are connected to the preceding stage of the plurality of element amplifiers 20b, which are memory terms, and the power supply voltages applied to the element amplifiers 20 are different from each other in time.
- the input signal u given to each element amplifier 20 [n '-M 1], the time n' whereas those of -M 1, the power supply voltage V (power supplied to each element amplifier 20 the input to the port) are those 'from the time n' times n of -M 1 -M 2. That is, in the ET amplifier model shown in FIG. 3 (b), the ET amplifier model output, a certain time n 'input signal u in -M 1 [n' -M 1] , the time n '-M 1 and the time n '[-1 -M 1 power supply voltage V n] at different times from the' ⁇ V [n '-M 1 -M 2], has become what is reflected.
- Equation (9) is According to the following equation (10) replaced by: here, y [n]: Output signal of ET amplifier 200 k: Order l: Relative delay generated with respect to input signal u [n] of ET amplifier 200 in the signal amplification path m: Input signal u of ET amplifier 200 in the power supply path Relative delay L 1 generated for [n]: maximum value of relative preceding samples in signal amplification path L 2 : maximum value of relative delay samples in signal amplification path M 1 : in power supply path Maximum value of relative preceding samples M 2 : Maximum value of relative delay samples in power supply path K m, l : Maximum order of characteristics of ET amplifier 200, and subscript is relative delay (signal amplification) coefficients for path) l, and the coefficient H k of the relative delay (power supply path) m, l, m: a complex coefficient representing the characteristic of the ET amplifier 200, subscripts coefficient on the relative delay (signal amplification paths) l Relative delay (power supply
- Equation (10) it means that the output of the ET amplifier model at time n is affected by the input signal u and the power supply voltage V at times other than time n.
- the input signal and the power supply voltage V include those that are temporally different from each other. More specifically, the output of the ET amplifier model at time n, a plurality (L 1 + L 2 +1 pieces) input signal u at time n + L 1 ⁇ n-L 2 of [n + L 1] ⁇ u [n ⁇ L 2 ] and the power supply voltage V [n ⁇ 1m] at (L 1 + L 2 +1) ⁇ (M 1 + M 2 +1) times are reflected. Note that (L 1 + L 2 +1) is the number of taps in the delay model showing the first memory effect, and (M 1 + M 2 +1) is the number of taps in the delay model showing the second memory effect.
- the inverse characteristic estimator 7 is based on the inverse model that the inverse characteristic estimator 7 currently has with respect to the output y [n] from the ET amplifier 2 (the output whose gain has been reduced corresponding to the ET amplifier gain). Distortion compensation is performed to obtain an estimated value u ′ [n] of the input signal to the ET amplifier 2. Then, the inverse characteristic estimation unit 7 obtains an error between the actual input signal u [n] and the estimated value u ′ [n], and optimizes the inverse model so that the error is minimized. Turn into. The inverse model obtained in this way is copied to the distortion compensation processing unit 8 and used for the distortion compensation processing in the distortion compensation processing unit 8.
- the input signal estimated value u ′ [n] obtained by the inverse characteristic estimation unit 7 is expressed by the following equation (12) from the equation (11).
- the inverse characteristic estimation unit 7 can obtain the input signal estimated value u ′ [n] based on the power supply voltage V at a plurality of times and the amplifier output y at a plurality of times. That is, the inverse characteristic estimation unit 7 can estimate an inverse model based on the power supply voltage V at a plurality of times and the amplifier output y at a plurality of times.
- FIG. 5 shows a configuration of the amplifier circuit 1 based on the ET amplifier model according to the first modification.
- the amplifier circuit of FIG. 5 is the same as the circuit of FIG.
- the power-voltage conversion unit 6 of the amplifier circuit 1 in FIG. 5 performs not the linear conversion but the nonlinear conversion as shown in FIG. 4 as the conversion from the power of the signal x [n] to the power supply voltage V [n].
- the non-linear conversion of FIG. 4 in the range where the input signal x [n] is small, the increase in the power supply voltage V [n] with respect to the increase in the input signal x [n] is suppressed, and in the range where the input signal x [n] is large.
- the increase in the power supply voltage V [n] with respect to the increase in the input signal x [n] is increased.
- the power supply voltage V [n] can be expressed by a power series as shown in the following equation (13).
- s degree K ′ m, l : maximum order h ′ s, l, m : complex coefficient
- h k, l, m is a complex coefficient representing the characteristics of the ET amplifier 200, and the subscripts are a coefficient related to the relative delay (signal amplification path) l, a relative delay (power supply path) m, and a coefficient related to the order k.
- the ET amplifier model shown in equation (10) can be expressed using the input signal x [n] before distortion compensation and the input signal u [n] after distortion compensation, as in the following equation (15).
- K ′ m, l is the maximum order of the characteristics of the ET amplifier 200, and the subscripts are a coefficient related to the relative delay (signal amplification path) l and a coefficient related to the relative delay (power supply path) m.
- the output of the ET amplifier model at time n is affected by the distortion-compensated input signal u and the distortion-compensated input signal x at times other than time n.
- the distortion-compensated input signal u and the distortion-compensated input signal x include signals that are temporally different from each other. More specifically, the output of the ET amplifier model at time n is a plurality of (L 1 + L 2 +1) times n + L 1 ... T-L 2 after distortion compensation input signal u [n + L 1 ]. u [n ⁇ L 2 ] and (L 1 + L 2 +1) ⁇ (M 1 + M 2 +1) predistortion input signals x [n ⁇ 1m] at the time are reflected. .
- the inverse model (inverse characteristic of the distortion characteristic of the ET amplifier 200) used in the distortion compensation processing unit 8 in FIG. 5 is as shown in Expression (16).
- 200 is a complex coefficient representing an inverse characteristic of 200, and the subscripts are a coefficient related to a relative delay (signal amplification path) l, a coefficient related to a relative delay (power supply path) m, and an order k
- the input signal estimated value u ′ [n] obtained by the inverse characteristic estimating unit 7 in FIG. 5 is expressed by the following equation (17) from the equation (16).
- the inverse characteristic estimation unit 7 in FIG. 5 calculates the input signal estimated value u ′ [n] based on the pre-distortion signal x at a plurality of times and the amplifier output y at a plurality of times. Can be sought. That is, the inverse characteristic estimation unit 7 can estimate an inverse model based on the pre-distortion signal x at a plurality of times and the amplifier output y at a plurality of times. In the case of the amplifier circuit of FIG. 5, it is possible to estimate an amplifier model (inverse model) considering the second memory effect without directly using the power supply voltage.
- the nonlinear characteristic of the ET amplifier 200 but also the nonlinear characteristic of the drive amplifier shown in FIG. 2 can be compensated by the distortion compensator 4. That is, in the case of the amplifier circuit 1 of FIG. 5, not only can the first memory effect and the second memory effect of the ET amplifier 200 be compensated, but also other amplifiers between the signal output port 8a of the distortion compensation unit 4 and the ET amplifier 200.
- the nonlinear characteristic (first memory effect) of the (drive amplifiers 35a and 35b) can also be compensated. This is because the amplifier circuit 1 of FIG. 5 uses x and y instead of V and y for the estimation of the reverse characteristic.
- the distortion compensator 4 in FIG. 5 uses the signal output port 8a of the distortion compensator 4 to the signal output port of the amplifier.
- the first memory effect generated in each of the amplifiers 2, 35a and 35b on the first path reaching 2b can be compensated.
- FIG. 6 shows a configuration of the amplifier circuit 1 based on the ET amplifier model according to the second modification.
- the amplifier circuit of FIG. 6 is the same as the circuits of FIG. 1 and FIG.
- Equation (18) shows that the output of the ET amplifier model (not the inverse model) at time n is the distortion-compensated input signal u and amplifier output signal y (actually, the distortion-compensated input signal x ).
- the distortion-compensated input signal u and the output signal y include those that are temporally different from each other.
- the inverse characteristic estimation unit 7 in FIG. 6 can obtain the input signal estimated value u ′ [n] based on the amplifier output y. That is, the inverse characteristic estimation unit 7 can estimate the inverse model based on the amplifier output y without using the power supply voltage V or the signal x before distortion compensation.
- the adjacent channel leakage power ratio (ACLR) is preferably ⁇ 10 dBc or less (the distortion signal is 10% or less of the main signal).
- FIG. 7 shows a detailed circuit configuration of the amplifier circuit 1 of FIG. The circuit in FIG. 7 is almost the same as the circuit shown in FIG. 2, but in FIG. 7, the input of V [n] to the inverse characteristic estimation unit 7 is unnecessary.
- FIG. 8 shows a result of an experiment in which distortion compensation is performed using an inverse model estimated based on Equation (18). As shown in FIG. 8, unnecessary radiation outside the signal band is suppressed in the embodiment using Equation (18), compared to the case where distortion compensation is not performed and the conventional method using the conventional amplifier model. And good results were obtained.
- Equation (10) the same deformation as that performed to obtain Equation (11), Equation (12), Equation (15), Equation (16), Equation (17), and Equation (18),
- Equation (20) an equation obtained by modifying the equation (20) is obtained.
- FIG. 9 shows a source modulation type amplifier circuit 1.
- the amplifier circuit 1 of FIG. 9 is different from the amplifier circuit 1 of FIG. 1 in that the output of the variable power source 3 is connected to the port 2d on the source side of the amplifier 2 instead of the power port (drain) 2c of the amplifier 2. It is a point.
- a fixed power source to which a fixed voltage (or a fixed current) is supplied is connected to the power supply port 2 c of the amplifier 2.
- the voltage (current) on the source side of the amplifier 2 is controlled in accordance with the change in the envelope of the signal x.
- the source-side port 2d of the amplifier 2 serves as a signal input port instead of the power supply port 2c. That is, the source modulation type amplifier circuit 1 has a first path from the signal input port 2a to the signal output port 2b of the amplifier 2 and a second path from the source side port 2d to the signal output port 2b. .
- the memory effect occurs in the second path as well as the first path, so that the first and second memory effects are compensated for in the same manner as described with reference to FIGS. be able to.
- the source modulation type amplifier circuit 1 of FIG. 9 is different from that of FIG. 1 only in the port to which the variable power supply voltage V is applied, and therefore, the equation indicating the amplifier model is the same as the equation described above.
- the amplifier circuit 1 is not limited to the envelope tracking drive method, but may be an EER (Envelope Elimination and Restoration) method.
- the distortion compensator 4 is not limited to the one that estimates the inverse model of the amplifier and performs distortion compensation using the estimated inverse model, but estimates and estimates the positive model of the amplifier (the distortion characteristic of the amplifier itself). The inverse characteristics of the amplifier may be obtained from the obtained positive model, and distortion compensation may be performed using the inverse characteristics.
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Abstract
Description
特に、増幅したい無線信号の周波数が高い場合には、非線形特性を補正して増幅器を線形化するために、無線信号に変換する前の周波数の低い複素IQベースバンド信号に対して、特許文献1に示すように、デジタル信号処理を用いて事前に増幅器の非線形歪特性を打ち消す前置歪補償(predistortion)を施す必要がある。
歪補償の処理では、前記増幅器のモデルもしくは逆モデル(歪補償モデル)が推定され、そのモデルに基づいて増幅器における歪が補償される。
y[n]:増幅器100の出力信号
k:次数
l:増幅器100の入力信号u[n]に対する相対遅延
L1:相対的な先行サンプル数の最大値
L2:相対的な遅延サンプル数の最大値
Kl:増幅器の特性の最大次数であり、添え字は、相対遅延lに関する係数
hk、l:増幅器100の特性を表す複素係数であり、添え字は、相対遅延lに関する係数及び次数kに関する係数
ここで、複数の非線形素子NLそれぞれの特性は、式(2)のように表される。
式(2)に示すように、各非線形素子NLの非線形特性(入出力特性)は、増幅器100への入力信号u[n’]に基づいて定義されている。
k:次数
l’:入力信号u[n’]に対する相対遅延
L1:相対的な先行サンプル数の最大値
L2:相対的な遅延サンプル数の最大値
Kl'-L1:非線形素子の特性の最大次数であり、添え字は相対遅延l’-L1に関する係数
hk,l'-L1:非線形素子NLの特性を表す複素係数であり、添え字は相対遅延l’-L1に関する係数及び次数kに関する係数
つまり、メモリ項1~メモリ項L1+L2の各非線形素子NLが、増幅器におけるメモリ効果を表現したものとなっている。
なお、式(3a)は、式(2)及び図11より直接的に導かれるモデルであり、式(3b)は、式(3a)を、n=n’-L1,l=l’-L1で置き換えたものである。
しかし、増幅器を高効率化するために、エンベロープトラッキング(Envelope Tracking)駆動方式を採用すると、入力信号のエンベロープ信号に応じて、増幅器100の電源電圧(ドレイン電圧)が変化する。つまり、エンベロープトラッキング駆動方式では、入力信号電力に応じて増幅器に供給される電源電圧を調整しつつ、送信信号(又は送信信号を波形整形した信号)を増幅器に入力することになる。このように、エンベロープトラッキング駆動方式のように電源電圧が変化する増幅器は、2入力系となっている。
上記本発明によれば、増幅器の信号入力ポート以外の他の入力ポートから信号出力ポートに至る経路で発生するメモリ効果を補償することができる。
そこで、上記の本発明のように、信号入力ポートに入力される入力信号及び前記可変電源から供給される前記電源電圧又は前記電源電流、に基づいて非線形特性が定義された増幅器モデルを採用することで、複数の各経路の特性を適切に表現でき、従来よりも良好なモデルが得られる。
この場合、少なくとも、信号入力ポートから出力信号ポートに至る経路のメモリ効果が表現されたモデルとなる。なお、電源ポートから出力信号ポートに至る経路のメモリ効果を考慮することも当然に許容される。
上記の(10)項に係る本発明、ならびに、(10)項を引用する(15)項に係る本発明によれば、幅器の信号入力ポート以外の他の入力ポートから信号出力ポートに至る経路で発生するメモリ効果を補償することができる。
上記の(11)~(14)項に係る本発明、並びに、(11)~(14)項を引用する(15)項に係る本発明によれば、一経路のみが考慮された増幅器モデルに比べて、複数経路が考慮されている分、適切な増幅器モデルとなる。
[1.増幅回路]
図1は、実施形態に係る増幅回路1を示している。この増幅回路1は、無線基地局装置などの無線通信装置に搭載され、送信信号の増幅を行うために用いられる。なお、増幅回路1は、受信信号の増幅に用いても良い。
増幅器2は、さらに、電源電圧(ドレイン電圧)V[n]が供給される電源ポート2cを備えている。増幅器2において、電源ポート2cは、信号入力ポート2a以外の他の入力ポートとなっている。
電力検出部5は、信号x[n](複素IQベースバンド信号)の電力値(信号x[n]のエンベロープ信号)を検出し、出力する。電力-電圧変換部6は、電力検出部5により検出された電力を、増幅器2へ供給される電源電圧値に変換する機能を有している。電力-電圧変換部6は、変換された電源電圧値(エンベロープ電圧値)を可変電源3に出力する。可変電源3は、変換された電源電圧値(エンベロープ電圧値)に応じて、増幅器2の電源ポート2cに供給される電圧V[n]を動的に変化させる。
本実施形態の推定部7は、ET増幅器200のモデルとして、ET増幅器200の逆特性を示す逆モデルを推定する逆特性推定部7として構成されている。なお、推定部7によって推定されるモデルの詳細及びその推定方法については、後述する。
まず、*[n]は、サンプリング間隔T(秒)としたときに、時刻n×Tにサンプリングしたデジタル複素ベースバンドIQ表現の信号である。また、*(t)は、時刻tにおけるアナログ信号を示す。ただし、本実施形態では、歪補償部4におけるデジタル信号領域における歪補償処理を取り扱うため、信号は、専ら、*[n]で示される。
具体的には、x[n]は、歪補償部4による歪補償前の入力信号であり、xI[n]は、x[n]の実部(I-channel)であり、xQ[n]は、x[n]の虚部(Q-channel)である。すなわち、x[n]=xI[n]+i×xQ[n]である。
u[n]は、歪補償部4による歪補償後の入力信号であり、uI[n]は、u[n]の実部(I-channel)であり、uQ[n]は、u[n]の虚部(Q-channel)である。すなわち、u[n]=uI[n]+i×uQ[n]である。
y[n]は、増幅器2の出力信号であり、yI[n]は、y[n]の実部(I-channel)であり、yQ[n]は、y[n]の虚部(Q-channel)である。すなわち、y[n]=G×(yI[n]+i×yQ[n])である。
従来の増幅器モデルでは、式(2)に示すように、増幅器への入力信号u[n]に応じて増幅器の非線形特性が定義されていた。
これに対し、エンベロープ信号に応じて電源電圧V[n]が変化するET増幅器200の非線形特性を、電源電圧(ドレイン電圧)V[n]を用いて、次の式(4)のように定義する。
Y”l"、m"[n”-M1]:ET増幅器200の出力信号
k:次数
l”:信号増幅経路において、ET増幅器200の入力信号u[n”]に対して生じる相対遅延
m”:電源経路において、ET増幅器200の入力信号u[n”]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
Kl"-L1、m"-M1:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、及び相対遅延(電源経路)m”-M1に関する係数
Hk、l"-L1,m"-M1:ET増幅器200の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、相対遅延(電源経路)m”-M1、及び次数kに関する係数
V[n”-l”-m”]:電源電圧
u[n”-l”-M1]:歪補償後の入力信号
したがって、第1メモリ効果及び第2メモリ効果の双方を考慮しない場合のET増幅器200のモデルは、図3(a)のようになる。
Y’0[n”-M1]:ET増幅器200の出力信号
k:次数
l”:信号増幅経路において、ET増幅器200の入力信号u[n”]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
Kl"-L1,-M1:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、及び、相対遅延(電源経路)-M1に関する係数
Hk、l"-L1,-M1:ET増幅器200の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、相対遅延(電源経路)-M1、及び次数kに関する係数
V[n”-l”]:電源電圧
u[n”-l”-M1]:歪補償後の入力信号
ただし、要素増幅器では、複数の非線形素子は、図11及び式(3)に示される非線形素子とは異なり、入力信号u及び電源電圧Vによって非線形特性が定義されている。なお、一つの要素増幅器における複数の非線形素子には、それぞれ、異なる時間n'+L1-M1・・・n'-L2-M1における入力信号u[n'+L1-M1]・・・u[n'-L2-M1]が与えられる。また、一つの要素増幅器における複数の非線形素子には、それぞれ、共通の時間n'-l'の電源電圧V[n'-l']が与えられる。
図3(b)は、要素増幅器20を用いたET増幅器200のモデル(第1及び第2メモリ効果が考慮された増幅器モデル)を示している。
また、図3(b)のET増幅器モデルは、次の式(8)(9)のように表される。
y[n’-M1]:ET増幅器200の出力信号
k:次数
l’:信号増幅経路において、ET増幅器200の入力信号u[n’]に対して生じる相対遅延
m”:電源経路において、ET増幅器200の入力信号u[n’]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
M2:電源経路における、相対的な遅延サンプル数の最大値
Kl',-M1:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)l’に関する係数、及び、相対遅延(電源経路)-M1に関する係数
Hk,l',m"-M1:ET増幅器200の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)l’に関する係数、相対遅延(電源経路)m”-M1、及び次数kに関する係数
V[n’-l’-m”],V[(n-M1)-l’-(m”-M1)]:電源電圧
u[n’-l’-M1],u[(n’-M1)-l’]:歪補償後の入力信号
複数の要素増幅器20には、遅延素子22(図3(a)の遅延素子12に対応)を介して、それぞれ、共通の時間n'-M1における入力信号u[n'-M1]が与えられる。なお、図3(b)においては、入力信号u[n']のライン上に遅延要素22が設けられているが、図3(a)と同様に、可変電源21側のライン上に遅延要素を入れて表現してもよい。
ただし、複数の要素増幅器20のうち、第2メモリ効果についての非メモリ項である要素増幅器20aには、時刻n'の電源電圧V[n’]が与えられるのに対し、第2メモリ効果についてのメモリ項である複数の要素増幅器20bには、時刻n'から遅れた時刻n'-1・・・n'-M1-M2の電源電圧V[n'-1]・・・V[n'-M1-M2]が与えられる。このため、メモリ項である複数の要素増幅器20bの前段には、それぞれ遅延素子23が接続されており、各要素増幅器20に与えられる電源電圧は、時間的にそれぞれ異なるものとなっている。
つまり、図3(b)に示すET増幅器モデルでは、ET増幅器モデル出力には、ある時刻n'-M1における入力信号u[n'-M1]と、その時刻n'-M1及びその時刻n'-M1とは異なる時刻における電源電圧V[n'-1]・・・V[n'-M1-M2]と、が反映されたものとなっている。
したがって、ET増幅器モデルの実際の出力は、複数(L1+L2+1個)の時刻n'+L1-M1・・・n'-L2-M1における入力信号u[n'+L1-M1]・・・u[n'-L2-M1]が反映されているとともに、入力信号uのそれぞれの時刻n'+L1-M1・・・n'-L2-M1についてさらに複数(M1+M2+1個)の時刻における電源電圧が考慮されたものとなる。
y[n]:ET増幅器200の出力信号
k:次数
l:信号増幅経路において、ET増幅器200の入力信号u[n]に対して生じる相対遅延
m:電源経路において、ET増幅器200の入力信号u[n]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
M2:電源経路における、相対的な遅延サンプル数の最大値
Km,l:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び、相対遅延(電源経路)mに関する係数
Hk,l,m:ET増幅器200の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
V[n-l-m]:電源電圧
u[n-l]:歪補償後の入力信号
より具体的には、時刻nにおけるET増幅器モデルの出力は、複数(L1+L2+1個)の時刻n+L1・・・n-L2における入力信号u[n+L1]・・・u[n-L2]と、(L1+L2+1)×(M1+M2+1)個の時刻における電源電圧V[n-l-m]と、が反映されたものとなる。なお、(L1+L2+1)は、第1メモリ効果を示す遅延モデルにおけるタップ数であり、(M1+M2+1)は、第2メモリ効果を示す遅延モデルにおけるタップ数である。
式(10)に示すET増幅器モデルに基づくと、図1の歪補償処理部8において用いられる逆モデル(ET増幅器200の歪特性の逆特性)は、式(11)の通りである。
増幅器逆モデル(補償部):
hinvk,l,m:ET増幅器200の逆特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
Kcm、l ≧ K’m,l
となる。
逆特性推定部7が求める入力信号推定値u’[n]は、式(11)より、次の式(12)の通り表される。
図5は、第1変形例に係るET増幅器モデルに基づく増幅回路1の構成を示している。なお、図5の増幅回路において、特に説明しない点については、図1の回路と同様である。
図5の増幅回路1の電力-電圧変換部6は、信号x[n]の電力から電源電圧V[n]への変換として、線形変換ではなく、図4に示すような非線形変換を行う。図4の非線形変換は、入力信号x[n]が小さい範囲では、入力信号x[n]の増加に対する電源電圧V[n]の増加を抑えておき、入力信号x[n]が大きい範囲では、入力信号x[n]の増加に対する電源電圧V[n]の増加を大きくするものである。
hk,l,m:ET増幅器200の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
K’m,l:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び相対遅延(電源経路)mに関する係数
より具体的には、時刻nにおけるET増幅器モデルの出力は、複数(L1+L2+1個)の時刻n+L1・・・t-L2における歪補償後入力信号u[n+L1]・・・u[n-L2]と、(L1+L2+1)×(M1+M2+1)個の時刻における歪補償前入力信号x[n-l-m]と、が反映されたものとなる。
増幅器逆モデル(補償部):
Kcm,l:ET増幅器200の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び相対遅延(電源経路)mに関する係数
hinvk,l,m:ET増幅器200の逆特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
図5の増幅回路の場合、電源電圧を直接的に用いなくても、第2メモリ効果を考慮した増幅器モデル(逆モデル)の推定が可能となっている。
これは、図5の増幅回路1では、逆特性の推定にVとyではなく、xとyを用いているためである。逆特性の推定にxとyとを用いると、推定される逆特性は、xとyの間に存在するすべての増幅器を対象としたものになる。
したがって、図5の前記歪補償部4は、電源ポート2cから信号出力ポート2bに至る第2経路で発生する第2メモリ効果のほか、歪補償部4の信号出力ポート8aから増幅器の信号出力ポート2bに至る第1経路上にある各増幅器2,35a,35bで発生する第1メモリ効果、を補償することができる。
図6は、第2変形例に係るET増幅器モデルに基づく増幅回路1の構成を示している。なお、図6の増幅回路において、特に説明しない点については、図1及び図5の回路と同様である。
なお、歪が小さい増幅器2としては、隣接チャネル漏洩電力比(Adjacent Channel Leakage Ratio:ACLR)が、-10dBc以下(歪信号が主信号の10%以下)であるのが好ましい。
図7は、図6の増幅回路1の詳細な回路構成を示している。図7の回路は、図2に示す回路とほぼ同様であるが、図7では、逆特性推定部7へのV[n]の入力が不要となっている。
前述の実施形態では、第1メモリ効果及び第2メモリ効果の双方を考慮したET増幅器のモデルを示したが、以下では、第2メモリ効果だけを考慮した増幅器モデルを示す。
第2メモリ効果だけを考慮した増幅器モデルは、図3(b)において、複数の要素増幅器20それぞれの入出力経路(u[n’-M1]からY’m"[n’-M1]に至る経路)におけるメモリ効果(第1メモリ効果)がないと考えればよい。
図9は、ソースモジュレーション方式の増幅回路1を示している。図9の増幅回路1が、図1の増幅回路1と異なる点は、可変電源3の出力が、増幅器2の電源ポート(ドレイン)2cではなく、増幅器2のソース側のポート2dに接続されている点である。また、増幅器2の電源ポート2cには、固定電圧(又は固定電流)が供給される固定電源が接続されている。
このソースモジュレーション方式の増幅回路1においては、電源ポート2cに代えて、増幅器2のソース側のポート2dが、信号の入力ポートになっている。
つまり、ソースモジュレーション方式の増幅回路1では、増幅器2の信号入力ポート2aから信号出力ポート2bに至る第1経路のほか、ソース側ポート2dから信号出力ポート2bに至る第2経路を有している。ソースモジュレーション方式の増幅回路1においても、メモリ効果は、第1経路のほか第2経路でも発生するため、図1~図6に関して説明したのと同様に、第1及び第2メモリ効果を補償することができる。
なお、図9のソースモジュレーション方式の増幅回路1は、可変電源電圧Vが与えられるポートが図1とは異なるだけであるため、増幅器モデルを示す式は、記述の式と同様のものとなる。
なお、今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した意味ではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味、及び範囲内でのすべての変更が含まれることが意図される。
例えば、増幅回路1は、エンベロープトラッキング駆動方式に限られず、EER(Envelope Elimination and Restoration)方式であってもよい。
また、歪補償部4は、増幅器の逆モデルを推定して、推定された逆モデルを用いて歪補償を行うものに限られず、増幅器の正モデル(増幅器の歪特性そのもの)を推定し、推定された正モデルから増幅器の逆特性を求め、その逆特性を用いて歪補償を行っても良い。
2 増幅器
2a 信号入力ポート
2b 信号出力ポート
2c 電源ポート
3 可変電源
4 歪補償部
5 電力検出部
6 電力-電圧変換部
7 推定部
8 歪補償処理部
10 非線形素子
20 要素増幅器
Claims (15)
- 信号を増幅する増幅器と、
前記信号のエンベロープの変化に応じて、前記増幅器の電源ポートに供給される電源電圧又は電源電流を変化させる可変電源と、
前記増幅器の歪補償を行う歪補償部と、
を備え、
前記歪補償部は、前記電源ポートから前記信号出力ポートに至る経路で発生するメモリ効果を補償する処理を行う
ことを特徴とする増幅回路。 - 前記歪補償部は、前記増幅器の信号入力ポートから信号出力ポートに至る経路で発生するメモリ効果、及び、前記電源ポートから前記信号出力ポートに至る経路で発生するメモリ効果、を補償する処理を行う
請求項1記載の増幅回路。 - 前記歪補償部は、前記増幅器のモデルを推定する推定部を備えるとともに、前記推定部によって推定された前記モデルに基づいて歪補償を行うものであり、
前記モデルは、少なくとも、前記電源ポートから前記信号出力ポートに至る経路で発生するメモリ効果、が表現されたものである
請求項1又は2記載の増幅回路。 - 前記歪補償部は、前記増幅器のモデルを推定する推定部を備えるとともに、前記推定部によって推定された前記モデルに基づいて歪補償を行うものであり、
前記モデルにおいて、前記増幅器は、複数の要素増幅器を合成したものとしてモデル化されており、
前記モデルにおける前記複数の要素増幅器には、それぞれ、前記信号入力ポートに入力される入力信号、及び、前記可変電源から供給される前記電源電圧又は前記電源電流が与えられ、
前記モデルにおける前記複数の要素増幅器の出力を合成したものが、前記増幅器の出力に対応しており、
前記モデルにおける前記複数の要素増幅器は、それぞれ、前記信号入力ポートに入力される入力信号及び前記可変電源から供給される前記電源電圧又は前記電源電流、に基づいて非線形特性が定義されており、
前記モデルにおける前記複数の要素増幅器には、それぞれ、異なる時間における前記電源電圧又は前記電源電流が与えられる
請求項1~3のいずれか1項に記載の増幅回路。 - 前記モデルにおける前記複数の要素増幅器は、それぞれ、複数の非線形素子を合成したものとしてモデル化されており、
前記複数の非線形素子には、それぞれ、前記信号入力ポートに入力される入力信号が与えられ、
前記複数の非線形素子の出力を合成したものが前記要素増幅器の出力に対応しており、
前記複数の非線形素子は、それぞれ、前記入力信号及び前記電源電圧又は前記電源電流に基づいて非線形特性が定義されており、
前記複数の非線形素子には、それぞれ、異なる時間における前記入力信号が与えられる
請求項4記載の増幅回路。 - 前記歪補償部は、前記増幅器のモデルを推定する推定部を備えるとともに、前記推定部によって推定された前記モデルに基づいて歪補償を行うものであり、
前記モデルは、下記式に基づく増幅器モデルである請求項1~5のいずれか1項に記載の増幅回路。
y[n]:前記増幅器の出力
k:次数
l:前記増幅器の信号入力ポートから信号出力ポートに至る経路(以下、「信号増幅経路」という)において、前記増幅器の入力信号u[n]に対して生じる相対遅延
m:前記増幅器の電源ポートから信号出力ポートに至る経路(以下、「電源経路」という)において、前記増幅器入力信号u[n]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
M2:電源経路における、相対的な遅延サンプル数の最大値
Km,l:前記増幅器の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び、相対遅延(電源経路)mに関する係数
Hk,l,m:前記増幅器の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
V[n-l-m]:電源電圧
u[n-l]:歪補償後の入力信号 - 前記歪補償部は、前記電源ポートから前記信号出力ポートに至る経路で発生するメモリ効果、及び、前記歪補償部の信号出力ポートから前記増幅器の信号出力ポートに至る経路で発生するメモリ効果、を補償する処理を行う
請求項1~6のいずれか1項に記載の増幅回路。 - 前記歪補償部は、前記増幅器のモデルを推定する推定部を備えるとともに、前記推定部によって推定された前記モデルに基づいて歪補償を行うものであり、
前記モデルは、下記式に基づく増幅器モデルである請求項1~7のいずれか1項に記載の増幅回路。
y[n]:前記増幅器の出力
k:次数
l:前記増幅器の信号入力ポートから信号出力ポートに至る経路(以下、「信号増幅経路」という)において、前記増幅器の入力信号u[n]に対して生じる相対遅延
m:前記増幅器の電源ポートから信号出力ポートに至る経路(以下、「電源経路」という)において、前記増幅器入力信号u[n]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
M2:電源経路における、相対的な遅延サンプル数の最大値
K’m,l:前記増幅器の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び相対遅延(電源経路)mに関する係数
hk,l,m:前記増幅器の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
x[n-l-m]:歪補償前の信号
u[n-l]:歪補償後の信号 - 前記歪補償部は、前記増幅器の逆モデルを推定する推定部を備えるとともに、前記推定部によって推定された前記逆モデルに基づいて歪補償を行うものであり、
前記逆モデルは、下記式に基づく増幅器逆モデルである請求項1~8のいずれか1項に記載の増幅回路。
u’[n]:前記増幅器の入力信号u[n]の推定値
k:次数
l:前記増幅器の信号入力ポートから信号出力ポートに至る経路(以下、「信号増幅経路」という)において、前記増幅器の入力信号u[n]に対して生じる相対遅延
m:前記増幅器の電源ポートから信号出力ポートに至る経路(以下、「電源経路」という)において、前記増幅器入力信号u[n]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
M2:電源経路における、相対的な遅延サンプル数の最大値
Kcm,l:前記増幅器の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、及び相対遅延(電源経路)mに関する係数
hinvk,l,m:前記増幅器の逆特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)lに関する係数、相対遅延(電源経路)m、及び次数kに関する係数
y[n-l-m],y[n-l]:前記増幅器の出力 - 信号を増幅する増幅器と、
前記増幅器の歪補償を行う歪補償部と、
を備え、
前記歪補償部は、前記増幅器の信号入力ポート以外の他の入力ポートから信号出力ポートに至る経路で発生するメモリ効果、を補償する処理を行う
ことを特徴とする増幅回路。 - 信号を増幅する増幅器と、
前記信号のエンベロープの変化に応じて、前記増幅器の電源ポートに供給される電源電圧又は電源電流を変化させる可変電源と、
前記増幅器のモデルを推定する推定部を備えるとともに、前記推定部によって推定された前記モデルに基づいて歪補償を行う歪補償部と、
を備え、
前記モデルにおける前記増幅器は、前記増幅器の信号入力ポートに入力される入力信号及び前記可変電源から供給される前記電源電圧又は前記電源電流、に基づいて非線形特性が定義されている
ことを特徴とする増幅回路。 - 前記モデルは、下記式に基づく増幅器モデルである請求項11記載の増幅回路。
Y”l",m"[n”-M1]:前記モデルにおける前記増幅器の出力
k:次数
l”:前記増幅器の信号入力ポートから信号出力ポートに至る経路(以下、「信号増幅経路」という)おいて、前記増幅器の入力信号u[n”]に対して生じる相対遅延
m”:前記増幅器の電源ポートから信号出力ポートに至る経路(以下、「電源経路」という)において、前記増幅器の入力信号u[n”]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
M1:電源経路における、相対的な先行サンプル数の最大値
Kl"-L1,m"-M1:前記増幅器の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、及び相対遅延(電源経路)m”-M1に関する係数
Hk,l"-L1,m"-M1:前記増幅器の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、相対遅延(電源経路)m”-M1、及び次数kに関する係数
V[n”-l”-m”]:電源電圧
u[n”-l”-M1]:歪補償後の入力信号 - 前記モデルにおける前記増幅器は、複数の非線形素子を合成したものとしてモデル化されており、
前記複数の非線形素子には、それぞれ、前記信号入力ポートに入力される入力信号が与えられ、
前記複数の非線形素子の出力を合成したものが前記増幅器の出力に対応しており、
前記複数の非線形素子は、それぞれ、前記入力信号及び前記電源電圧又は前記電源電流に基づいて非線形特性が定義されており、
前記複数の非線形素子には、それぞれ、異なる時間における前記入力信号が与えられる
請求項11又は12記載の増幅回路。 - 前記モデルは、下記式に基づく、増幅器モデルである請求項13記載の増幅回路。
Y’0[n’-M1]:前記増幅器モデルの出力
k:次数
l’:増幅器の信号入力ポートから信号出力ポートに至る経路(以下、「信号増幅経路」という)において、増幅器の入力信号u[n’]に対して生じる相対遅延
L1:信号増幅経路における、相対的な先行サンプル数の最大値
L2:信号増幅経路における、相対的な遅延サンプル数の最大値
M1:増幅器の電源ポートから信号出力ポートに至る経路(以下、「電源経路」という)における、相対的な先行サンプル数の最大値
Kl"-L1,-M1:前記増幅器の特性の最大次数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、及び、相対遅延(電源経路)-M1に関する係数
Hk,l"-L1,-M1:前記増幅器の特性を表す複素係数であり、添え字は、相対遅延(信号増幅経路)l”-L1に関する係数、相対遅延(電源経路)-M1、及び次数kに関する係数
V[n”-l”]:電源電圧
u[n”-l”-M1]:歪補償後の入力信号 - 請求項1,10,又は11に記載の増幅回路を、送信信号の増幅、又は受信信号の増幅のために備えた無線通信装置。
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US13/993,960 US9257943B2 (en) | 2010-12-22 | 2011-11-30 | Amplifier circuit and wireless communication equipment |
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EP2728743A1 (en) | 2014-05-07 |
JPWO2012086379A1 (ja) | 2014-05-22 |
CN103270695B (zh) | 2016-11-16 |
TW201240334A (en) | 2012-10-01 |
EP2728742B1 (en) | 2015-08-05 |
US9257943B2 (en) | 2016-02-09 |
CN103270695A (zh) | 2013-08-28 |
JP5907073B2 (ja) | 2016-04-20 |
EP2658118B1 (en) | 2015-06-03 |
EP2728744A1 (en) | 2014-05-07 |
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EP2658118A4 (en) | 2014-04-16 |
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