WO2012071861A1 - 一种时分双工基站的时钟备份方法及系统 - Google Patents

一种时分双工基站的时钟备份方法及系统 Download PDF

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Publication number
WO2012071861A1
WO2012071861A1 PCT/CN2011/074590 CN2011074590W WO2012071861A1 WO 2012071861 A1 WO2012071861 A1 WO 2012071861A1 CN 2011074590 W CN2011074590 W CN 2011074590W WO 2012071861 A1 WO2012071861 A1 WO 2012071861A1
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Prior art keywords
clock
standard
primary
standby
module
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PCT/CN2011/074590
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English (en)
French (fr)
Inventor
马磊
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中兴通讯股份有限公司
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Publication of WO2012071861A1 publication Critical patent/WO2012071861A1/zh

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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W56/00Synchronisation arrangements
    • H04W56/001Synchronization between nodes

Definitions

  • the present invention relates to a communication backbone or, in particular, to a clock backup method and system for a TDD (Time Division Duplex) base station.
  • TDD Time Division Duplex
  • the uplink and downlink communications between the TDD base station and the terminal use different time slots of the same frequency channel, separating the receiving and transmitting channels with time. It is required that the base station transmits a signal to the terminal during a certain period of time, and another time period terminal sends a signal to the base station.
  • the TDD base station has a higher time offset between the base stations, but the premise is to ensure the reliability of the clock. Therefore, it is necessary to increase the clock backup function.
  • the traditional method is to add another clock source as a backup or in the same base station.
  • the upper deck uses two sets of clock systems to back up each other.
  • the above schemes have the following disadvantages:
  • a primary object of the present invention is to provide a clock backup method and system for a TDD base station, which solves the problem of low system reliability caused by an increase in backup cost and a non-complete backup scheme.
  • a clock backup method for a time division duplex base station including the steps of: using a primary clock used by a first time division duplex base station and a first time received by a first time division duplex base station Synchronizing the standard clock source, synchronizing the standby clock used by the first time division duplex base station with the second standard clock source received by the second time division duplex base station; detecting whether the primary clock or the first standard clock source is abnormal; If an abnormality occurs, the abnormal primary clock or the first standard clock source is switched to the standby clock.
  • the step of switching the abnormal primary clock to the standby clock includes: outputting the first edge of the primary clock after the time when the primary clock is abnormal, turning off the primary clock, and after turning off the primary clock When the first correct clock signal of the alternate clock is on the mega-edge, the alternate clock is substituted for the primary clock.
  • the method further includes: outputting the first edge of the standby clock after the time when the primary clock returns to normal, turning off the standby clock, and after the time when the standby clock is turned off When the first correct clock signal of the main clock is on the wrong edge, it switches back to the main clock.
  • the step of switching back to the main clock further includes: controlling the main clock to synchronize with the first standard clock source by using the phase difference data after the switching time and the phase difference data of the first standard clock source.
  • the step of switching the abnormal first standard clock source to the standby clock includes: switching the first standard clock source with an abnormality to the standby clock when the first standard clock source is abnormal, and using the active clock with the standby clock The clock is synchronized.
  • the step of synchronizing the primary clock with the standby clock further includes: controlling the primary clock to synchronize with the standby clock using the phase difference data of the primary clock and the standby clock after the switching time.
  • the method further includes: when the first standard clock source returns to a normal time, switching the standby clock to the first standard clock source that is restored to normal, and the primary clock is The first standard clock source is synchronized.
  • the step of synchronizing the primary clock with the first standard clock source further includes: controlling the primary clock to synchronize with the first standard clock source using the phase difference data after the switching time and the phase difference data of the first standard clock source.
  • the second standard clock source received by the second time division duplex base station is synchronized with the backup clocks of the plurality of first time division duplex base stations.
  • a clock backup system for a time division duplex base station including: a primary clock module configured to generate a primary clock used by a first time division duplex base station; and an alternate clock module configured to Generating a standby clock used by the first time division duplex base station; the first standard clock source module, located at the first time division duplex base station, configured to generate a standard clock source synchronized with the primary clock and synchronized with the primary clock; The second standard clock source module is located on the second time division duplex base station, configured to generate a standard clock source synchronized with the standby clock, and synchronized with the standby clock; the detection module is set to detect the primary use Whether the clock module or the first standard clock source module is abnormal.
  • the detecting module includes: a first detecting submodule configured to detect whether an abnormality occurs in the main clock; and a first switching submodule configured to output the first mega-edge of the main clock after the time when the main clock is abnormal, and close The primary clock, and the first correct clock signal transition edge of the standby clock after the time when the primary clock is turned off, replaces the primary clock with the primary clock.
  • the detecting module further includes: a second detecting submodule configured to detect whether an abnormality occurs in the first standard clock source; and a second switching submodule configured to set a first standard of an abnormality when an abnormality occurs in the first standard clock source
  • the clock source switches to the alternate clock and synchronizes the primary clock with the alternate clock.
  • the second standard clock source module uses at least one of the following: Global Positioning System, Global Navigation Satellite System, Beidou or Galileo.
  • the backup clock on the first base station is synchronized with the standard clock source on the second base station, and the backup clock is used as a backup of the standard clock source and the primary clock on the first base station, thereby ensuring correct clock output.
  • FIG. 2 is a preferred embodiment of a clock backup system for a TDD base station according to an embodiment of the present invention.
  • FIG. 3 is another structural block diagram of a clock backup system of a TDD base station according to an embodiment of the present invention.
  • FIG. 4 is another flowchart of a clock backup method of a TDD base station according to an embodiment of the present invention;
  • FIG. 5 is still another structural block diagram of a clock backup system of a TDD base station according to an embodiment of the present invention.
  • BEST MODE FOR CARRYING OUT THE INVENTION will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.
  • Embodiment 1 is a flowchart of a preferred method for clock backup of a TDD base station according to an embodiment of the present invention, which includes the following steps:
  • the abnormal primary clock or the first standard clock source is switched to the standby clock.
  • the backup clock on the first base station is synchronized with the standard clock source on the second base station, and the backup clock is used as a backup of the standard clock source and the primary clock on the first base station, thereby ensuring The correct clock output signal reduces the hardware overhead on the first base station and reduces the system cost.
  • Jtb in the preferred embodiment, the standard clock source and the main clock are simultaneously backed up at the same time, thereby further improving the reliability of the system.
  • the step of switching the abnormal primary clock to the standby clock comprises: outputting the first edge of the primary clock after the time when the primary clock is abnormal, turning off the primary clock, and turning off the primary clock When the first correct clock signal of the alternate clock is changed after the moment, the alternate clock is substituted for the primary clock.
  • seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured.
  • the clock backup method of the TDD base station according to the embodiment of the present invention further includes: outputting the first hop of the standby clock after the time when the primary clock returns to normal after the primary clock of the abnormality is switched to the backup clock.
  • the step of switching back to the primary clock further comprises: controlling the primary clock to synchronize with the first standard clock source by using the phase difference data after the switching time and the phase difference data of the first standard clock source. The accuracy of the main clock is further guaranteed.
  • the step of switching the abnormal first standard clock source to the standby clock comprises: switching the first standard clock source with an abnormality to the standby clock when the first standard clock source is abnormal, and using the primary clock The clock is synchronized with the alternate clock.
  • seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured.
  • the accuracy of the master clock is ensured by synchronizing the master clock with the standby clock (where the standby clock replaces the standard clock source with an abnormality as the new reference clock).
  • the step of synchronizing the primary clock with the standby clock further comprises: using the phase difference data of the primary clock and the standby clock after the switching time to control the synchronization between the primary clock and the standby clock.
  • the phase difference data is used to control the synchronization of the primary clock and the standby clock (where the standby clock replaces the abnormal standard clock source as a new reference clock), further ensuring the accuracy of the primary clock.
  • the clock backup method of the TDD base station provided by the embodiment of the present invention further includes: when the first standard clock source returns to a normal time, after the first standard clock source with the abnormality is switched to the standby clock Switching the standby clock to the first standard clock source that is restored to normal, and synchronizing the primary clock with the first standard clock source.
  • the seamless switching is implemented by the above switching mode. The stability of the data transmission.
  • the accuracy of the main clock is ensured by synchronizing the main clock with the first standard clock source that is restored to normal.
  • the main clock is synchronized with the first standard clock source.
  • the step further includes: controlling the main use time by using the phase difference data of the main clock and the first standard clock source after the switching time Synchronizing with the first standard clock source, further ensuring the accuracy of the primary clock.
  • the second standard clock source received by the second time division duplex base station is synchronized with the standby clock of the plurality of first time division duplex base stations, The cost reduction is further ensured.
  • 2 is a block diagram of a preferred system for a clock backup method of a TDD base station according to an embodiment of the present invention.
  • a clock backup system for a time division duplex base station includes: a primary clock module 202 configured to generate a first time division double The primary clock used by the base station; the standby clock module 204 is configured to generate a backup clock used by the first time division duplex base station; the first standard clock source module 206 is located at the first time division duplex base station, and is configured to generate and The standard clock source for the main clock synchronization is synchronized with the main clock; the second standard clock source module 208 is located at the second time division duplex base station, and is set to generate a standard clock source synchronized with the standby clock and synchronized with the standby clock.
  • the detecting module 210 is configured to detect whether an abnormality occurs in the primary clock module 202 or the first standard clock source module 206.
  • the abnormal primary clock module 202 or the first standard clock source module 206 is switched to the standby.
  • Clock module 204 the backup clock on the first base station is synchronized with the standard clock source on the second base station, and the backup clock is used as a backup of the standard clock source and the primary clock on the first base station, thereby ensuring The correct clock output signal reduces the hardware overhead on the first base station and reduces the system cost.
  • Jtb in the preferred embodiment, the standard clock source and the main clock are simultaneously backed up at the same time, thereby further improving the reliability of the system.
  • the detecting module 210 includes: a first detecting submodule 2101, configured to detect whether an abnormality occurs in the main clock; and the first switching submodule 2102 is configured to output the first clock of the main clock after the time when the main clock is abnormal.
  • the mega-edge, the main clock is turned off, and the standby clock is replaced by the standby clock when the first correct clock signal mega-edge of the standby clock after the time when the main clock is turned off.
  • seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured.
  • the detecting module 210 is further configured to: after switching the primary clock in which the abnormality occurs to the standby clock, output the first edge of the standby clock after the time when the primary clock returns to normal, turn off the standby clock, and turn off.
  • the first correct clock signal of the primary clock after the time of the standby clock is changed, the clock is switched back to the primary clock.
  • seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured.
  • the detecting module 210 is further configured to use the phase difference data after the switching time and the phase difference data of the first standard clock source to control the master clock to synchronize with the first standard clock source.
  • the detection module 210 further includes: a second detection submodule 2103, configured to detect whether an abnormality occurs in the first standard clock source; and the second switching submodule 2104 is set to When the first standard clock source is abnormal, the first standard clock source with an abnormality is switched to the standby clock, and the active clock is used. Synchronize with the alternate clock. In the preferred embodiment, seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured. At the same time, the accuracy of the master clock is ensured by synchronizing the master clock with the standby clock (where the standby clock replaces the first standard clock source with an abnormality as the new reference clock).
  • the detecting module 210 is further configured to use the phase difference data of the primary clock and the standby clock after the switching time to control the synchronization of the primary clock with the standby clock.
  • the phase difference data is used to control the synchronization of the primary clock and the standby clock (where the standby clock replaces the abnormal standard clock source as a new reference clock), further ensuring the accuracy of the primary clock.
  • the detecting module 210 is further configured to switch the standby clock to the first standard clock source that returns to normal after the first standard clock source returns to the normal clock after the first standard clock source with the abnormality is switched to the standby clock.
  • the master clock is synchronized with the first standard clock source.
  • seamless switching is achieved by the above switching mode, and the stability of data transmission is ensured.
  • the accuracy of the main clock is ensured by synchronizing the main clock with the first standard clock source that is restored to normal.
  • the detecting module 210 is further configured to use the phase difference data after the switching time and the phase difference data of the first standard clock source to control the master clock to synchronize with the first standard clock source. Further, the accuracy of the active clock is further ensured.
  • the second standard clock source received by the second time division duplex base station is synchronized with the standby clocks of the plurality of first time division duplex base stations, thereby further ensuring cost.
  • the standard clock source module uses GPS (Global Position System), GLONASS (Global Navigation Satellite System), BD (Beidou) or GALILEO (Galileo).
  • the main clock module 202 The clock signal generated by the voltage-controlled crystal oscillator output frequency is counted, for example, the standard clock source synchronization module 3042 in Embodiment 3.
  • the standby clock module 204 uses the IEEE (Institution for Electrical and Electronic Engineers, IEEE) as in Embodiment 3.
  • the first standard clock source module 206 can employ the second standard clock source receiving module 3045 as in Embodiment 3 for receiving the standard.
  • the clock source, the master clock module 202 passes the time in the embodiment 3.
  • the clock source detection selection module 3044 is locked with a standard clock source received by the second standard clock source receiving module 3045.
  • the second standard clock source module 208 is locked with the standard clock source received by the first standard clock source receiving module 3021 in Embodiment 3 by using the IEEE 1588 main module 3022 in Embodiment 3, thereby being
  • the slave module 3041 of the IEEE 1588 to which the master module 3022 of 1588 is connected is locked with the standard clock source, that is, the slave clock module 204 is synchronized with the second standard clock source module 208.
  • the detecting module 210 uses the output clock detection selection module 3043 and the clock source detection selection module 3044 in Embodiment 3.
  • the clock signals of the primary clock and the standby clock are usually second pulses, and the reference clocks that generate the primary clock or the standby clock are collectively referred to as a clock frequency.
  • FIG. 3 is another structural block diagram of a clock backup system of a TDD base station according to an embodiment of the present invention.
  • the clock backup system of the TDD base station of the present invention includes a base station or a network timing server 302 and a TDD base station 304, where
  • the base station or network timing server 302 includes a first standard clock source receiving module 3021 and a main module 3022 of IEEE 1588;
  • the TDD base station 304 includes a slave module 3041 of IEEE 1588, a standard clock source synchronization module 3042, an output clock detection selection module 3043, and a clock source.
  • the detection selection module 3044 and the second standard clock source receiving module 3045 are detected.
  • the first standard clock source receiving module 3021 and the TDD base station of the base station or network timing server 302 includes a first standard clock source receiving module 3021 and a main module 3022 of IEEE 1588;
  • the TDD base station 304 includes a slave module 3041 of IEEE 1588, a standard clock source synchronization module 3042, an output clock detection selection module 3043, and a clock source.
  • the second standard clock source receiving module 3045 of 304 is configured to receive the same standard clock source
  • the main module 3022 of IEEE 1588 is set to be locked to a standard clock source
  • the slave module 3041 of the IEEE 1588 includes a backup clock, which is set to be locked with the main module 3022 of the IEEE 1588;
  • the standard clock source synchronization module 3042 includes a main clock, which is set to lock the main clock and the reference signal, and transparently transmit the reference signal;
  • the detection selection module 3043 is configured to detect whether the primary clock is available, not to switch to the standby clock, and to detect the phase difference data of the clock signal of the primary clock and the reference signal, and report the data to the phase difference data.
  • the standard clock source synchronization module 3042 outputs an available clock signal to other modules of the TDD base station;
  • the clock source detection selection module 3044 is configured to detect whether the standard clock source receiving module is available, and if not available, switch to the standby clock.
  • the standard clock source synchronization module 3042 includes a main clock, and the component thereof includes a phase detector, a synchronization algorithm module, a control output module, and a voltage controlled crystal oscillator.
  • the phase detector detects the clock signal and the reference signal generated by the voltage output of the voltage controlled crystal oscillator.
  • the phase difference data is reported to the synchronization algorithm module for processing, and the calculated frequency offset adjustment value is applied to the voltage controlled crystal oscillator by the control output module in a voltage form, and the clock signal generated by the counting is indirectly adjusted by adjusting the output frequency of the voltage controlled crystal oscillator.
  • a reference signal which may be a standard clock source or a clock signal output by the IEEE 1588 Slave module 3041, that is, a standby clock.
  • the standard clock source synchronization module 3042 can transparently transmit the reference signal.
  • the IEEE 1588 Slave module 3041 includes a backup clock, and the component includes a field parsing module, a time stamp module, a synchronization algorithm module, and a clock output module.
  • the field parsing module and the time stamp module jointly complete the time stamp extraction and send the synchronization time to the synchronization algorithm module.
  • the result obtained is used to adjust the clock signal of the clock output module, thereby locking the standby clock with the clock signal output by the IEEE 1588 Master (main) module. Since the IEEE 1588 Master module can lock the clock signal output from the standard clock source, The alternate clock can indirectly lock the standard clock source.
  • the output clock detection selection module 3043 is composed of a phase detector, a state detection module, and a selection output module.
  • the phase difference data of the clock signal of the clock and the reference signal is used and reported to the standard clock source synchronization module 3042.
  • the available clock signal is output to other modules of the base station during operation.
  • the clock source detection selection module 3044 is configured to include a state detection and selection output module, configured to detect whether the second standard clock source receiving module 3045 is available, and if not available, switch to the standby clock, that is, the clock output by the IEEE 1588 Slave module 3041. The signal is used as a reference signal.
  • the operation of the TDD base station clock backup system provided by the present invention is divided into the following steps:
  • the base station or the network receiving the IEEE 1588 Master module 3022 is located with the standard clock source as the reference signal, and the clock signal output by the IEEE 1588Master module 3022 is locked with the standard clock source; simultaneously running on the TDD base station 304
  • the second standard clock source receiving module 3045, the standard clock source synchronization module 3042, and the IEEE 1588 Slave module 3041, the IEEE 1588 Slave module 3041 establishes a connection with the IEEE 1588 Master module 3022, and indirectly locks the standard clock source through the 1588 4 ⁇ text interaction
  • the selection module 3044 selects the standard clock source as the reference signal by default;
  • the standard clock source synchronization module 3042 can output the output signal through the output clock detection selection module 3043 after the reference signal is locked, and the standby clock is not output.
  • FIG. 4 is another flowchart of a clock backup method of a TDD base station according to an embodiment of the present invention, which includes the following steps:
  • S406 Select an alternate clock output by using an output clock detection selection module.
  • the output clock detection selection module detects that the status reported by the standard clock source synchronization module is abnormal, it will continue to output the next mega-edge of the main clock and then turn off the main clock, and at the same time the next mega-edge of the clock frequency of the standby clock. Start counting, the clock frequency of the standby clock is calculated until the next standby clock clock signal transition edge replaces the main clock, and the switching to the standby clock is realized;
  • the output clock detection selection module reports phase difference data between the main clock and the standard clock source. S414, calculating the phase difference data of the upper 4 ⁇ ;
  • S420 directly select a clock signal of the standby clock as a reference signal in the clock source detection selection module, and the standard clock source synchronization module is locked with the new reference signal, that is, the primary clock and the standby clock are locked;
  • S424. Calculate the phase difference data obtained after the switching time, and obtain the result for controlling the synchronization between the primary clock and the standby clock.
  • the standard clock source receiving module returns to normal; when the synchronization algorithm is run, the initial phase difference data of the 4 ⁇ main clock and the standard clock source on the switching time detector is discarded, and the obtained phase difference data is calculated, and the obtained result is used. Synchronize the control master clock with the standard clock source.
  • the clock signal of the standard clock source receiving module is used as a reference signal, and is locked with the standard clock source synchronization module, that is, the standard clock source is locked with the main clock;
  • S430 ignoring the main clock of the switching time read by the standard clock source synchronization module Phase difference data with a standard clock source;
  • the phase detector inside the output clock detection selection module replaces the phase detector inside the standard clock source synchronization module, so from the structural point of view, the original standard clock source synchronization module and the output clock detection
  • the selection modules together form a new standard clock source synchronization module.
  • the IEEE 1588 Slave module is used as the backup clock of the TDD base station.
  • the primary and backup clocks are in two modules on the same board.
  • the standard clock source synchronization module locks the standard clock source.
  • the IEEE 1588 Slave module indirectly locks the standard clock source by locking the IEEE 1588Master clock module, and then selects the clock through the clock source detection selection module.
  • FIG. 5 is a block diagram showing still another structure of a clock backup system of a TDD base station according to an embodiment of the present invention.
  • the TDD base station clock backup system includes the following modules or interfaces: 1)
  • the GPS module 502 includes a GPS receiver and its peripheral antenna feed state detection circuit, and is configured to receive a GPS satellite signal output 1PPS and The current status can be 4 ⁇ in real time.
  • the clock source detection selection module 504 includes a GPS module status detection module, an IEEE 1588 Slave module status detection module, and a 1PPS (pulse/second) selection output module, which is set to state detection and output 1PPS according to the detection result.
  • the clock synchronization module 506 includes a voltage controlled crystal oscillator, a phase detector, a synchronization algorithm module, and a control output module, and is configured to output a 1PPS synchronized with the input signal and a 10 MHz clock frequency for counting and generating the 1PPS.
  • an output clock detection selection module 508 including a phase detector, a clock synchronization module state detection module, an IEEE 1588 Slave module state detection module, and a 1PPS selection output module, configured to state detection and output 1PPS according to the detection result, as an available clock signal, Output to other modules of the base station.
  • the IEEE 1588 Slave module 510 outputs a 1PPS that is indirectly synchronized with the GPS receiver output 1PPS by interacting with the message of the IEEE 1588 Master module on the network timing server or other base station.
  • the above clock synchronization module and the IEEE 1588 Slave module are set to count and generate 1PPS clock frequencies of 10MHz.
  • the specific process of starting the clock switch is as follows:
  • the output clock detection selection module 508 will continue to output the next transition edge and then turn off its 1PPS output, and simultaneously start with the next mega-edge of the standby clock of 10 MHz. Counting, outputting a 1 PPS of IEEE 1588 Slave at a nearby time of 10 M. 2) When the clock synchronization module 506 returns to normal, in the output clock detection selection module 508,
  • the standby clock is turned off, and at the same time, the next edge of the 10MHz of the main clock is started to count, and each time 10M is output, the 1PPS is output, and the signal is detected by the phase detector.
  • the phase difference data of the reference signal transparently transmitted by the clock synchronization module 506 is supplied to the clock synchronization module 506, and then normal control is implemented.
  • GPS module 502 is abnormal, and the main clock is normal.
  • the 1PPS outputted by the IEEE 1588 Slave module 510 is directly selected as the reference signal in the clock source detection selection module 504, and is locked by the clock synchronization module 506 with the new reference signal.
  • the synchronization algorithm is run, the initial phase difference data is discarded, and the subsequent phase difference data is used for calculation, and the obtained result is used to control the main clock.
  • the standard clock source may also be other satellite positioning systems: including GLONASS (global navigation satellite system), BD (Beidou), GALILEO (Galileo), and the like.
  • GLONASS global navigation satellite system
  • BD Beidou
  • GALILEO Galileo
  • the implementation of each module, especially the clock synchronization module and the IEEE 1588 Slave module can be understood by those skilled in the art and will not be described herein.
  • the base station simultaneously runs the GPS clock synchronization scheme and the IEEE 1588 scheme, and the default output is 1PPS in phase with the 1PPS output by the GPS module. In practical applications, the reliability and synchronization of the GPS clock scheme are higher, so the GPS clock scheme is preferred, and the IEEE 1588 scheme is used as the backup clock. From the above description, it can be seen that the present invention achieves the following technical effects:
  • the standard clock source signal receiving module is installed on the board where the IEEE 1588 master is located and the TDD base station. Therefore, the clock backup is performed on the same board but the standard clock source is the same. The ability of the module to be abnormal;
  • the backup solution can be seamlessly switched; 4)
  • the standard clock source receiving module and the standard clock source synchronization module are backed up at the same time, and visible based on seamless switching, the clock backup method can greatly improve the reliability of the system.
  • the various modules or steps of the present invention described above can be implemented by a general-purpose computing device, which can be centralized on a single computing device, or distributed in multiple Optionally, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into respective integrated circuits. Modules, or a plurality of modules or steps in them, are implemented as a single integrated circuit module.

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Abstract

本发明公开了一种时分双工基站的时钟备份方法及系统,其中,该方法包括如下步骤:将第一时分双工基站采用的主用时钟与第一时分双工基站接收的第一标准时钟源进行同步,将第一时分双工基站采用的备用时钟与第二时分双工基站接收的第二标准时钟源进行同步;检测主用时钟或第一标准时钟源是否出现异常;若出现异常,则将出现异常的主用时钟或第一标准时钟源切换到备用时钟。本发明解决了备份成本增加以及备份方案不具完备性而导致的系统可靠性不高的问题。

Description

一种时分双工基站的时钟备份方法及系统 技术领域 本发明涉及通信领 i或, 具体而言, 涉及一种 TDD ( Time Division Duplex, 时分双工)基站的时钟备份方法及系统。 背景技术
TDD基站与终端之间的上行和下行通信使用同一频率信道的不同时隙,用 时间来分离接收和发送信道。 要求在某一时段基站发送信号给终端, 另外的时 段终端发信号给基站。 为保证切换, TDD基站对基站间的时偏要求较高, 但前提是要保证时钟的 可靠性, 故此需要增加时钟备份的功能, 传统的做法是另外加入一个时钟源作 为备份或在同一台基站上釆用两套时钟系统互为备份。 但在实际应用中, 上述方案会存在以下不足:
1 ) 前者在时钟备份成本上明显增加。
2 ) 后者在备份方案上不具完备性。 因为当两套时钟的参考源异常时, 备 份时钟将无法发挥作用。 发明内容 本发明的主要目的在于提供一种 TDD基站的时钟备份方法及系统, 以解 决备份成本增加以及备份方案不具完备性而导致的系统可靠性不高的问题。 根据本发明的一个方面, 提供了一种时分双工基站的时钟备份方法, 包括 如下步骤: 将第一时分双工基站釆用的主用时钟与第一时分双工基站接收的第 一标准时钟源进行同步, 将第一时分双工基站釆用的备用时钟与第二时分双工 基站接收的第二标准时钟源进行同步; 检测主用时钟或第一标准时钟源是否出 现异常; 若出现异常, 则将出现异常的主用时钟或第一标准时钟源切换到备用 时钟。 将出现异常的主用时钟切换到备用时钟的步骤包括: 在主用时钟出现异常 的时刻之后输出主用时钟的第一个跳变沿, 关闭主用时钟, 并在关闭主用时钟 的时刻后的备用时钟的第一个正确的时钟信号兆变沿时, 将备用时钟替代主用 时钟。 在将出现异常的主用时钟切换到备用时钟之后, 还包括: 在主用时钟恢复 正常的时刻之后输出备用时钟的第一个跳变沿, 关闭备用时钟, 并在关闭备用 时钟的时刻后的主用时钟的第一个正确的时钟信号兆变沿时, 切换回主用时 钟。 切换回主用时钟的步骤还包括: 使用切换时刻后的主用时钟和第一标准时 钟源的相位差数据来控制主用时钟与第一标准时钟源同步。 将出现异常的第一标准时钟源切换到备用时钟的步骤包括: 在第一标准时 钟源出现异常的时刻时, 将出现异常的第一标准时钟源切换到备用时钟, 并将 主用时钟与备用时钟进行同步。 将主用时钟与备用时钟进行同步的步骤还包括: 使用切换时刻后的主用时 钟和备用时钟的相位差数据来控制主用时钟与备用时钟同步。 将出现异常的第一标准时钟源切换到备用时钟之后, 还包括: 在第一标准 时钟源恢复正常的时刻时, 将备用时钟切换到恢复正常的第一标准时钟源, 并 将主用时钟与第一标准时钟源进行同步。 将主用时钟与第一标准时钟源进行同步的步骤还包括: 使用切换时刻后的 主用时钟和第一标准时钟源的相位差数据来控制主用时钟与第一标准时钟源 同步。 第二时分双工基站接收的第二标准时钟源与多个第一时分双工基站上的 备用时钟同步。 根据本发明的另一个方面, 提供了一种时分双工基站的时钟备份系统, 包 括: 主用时钟模块, 设置为产生第一时分双工基站使用的主用时钟; 备用时钟 模块, 设置为产生第一时分双工基站使用的备用时钟; 第一标准时钟源模块, 位于第一时分双工基站上, 设置为产生与主用时钟同步的标准时钟源, 并与主 用时钟同步; 第二标准时钟源模块, 位于第二时分双工基站上, 设置为产生与 备用时钟同步的标准时钟源, 并与备用时钟同步; 检测模块, 设置为检测主用 时钟模块或第一标准时钟源模块是否出现异常, 若出现异常, 则将出现异常的 主用时钟模块或第一标准时钟源模块切换到备用时钟模块。 检测模块包括: 第一检测子模块, 设置为检测主用时钟是否出现异常; 第 一切换子模块, 设置为在主用时钟出现异常的时刻之后输出主用时钟的第一个 兆变沿, 关闭主用时钟, 并在关闭主用时钟的时刻后的备用时钟的第一个正确 的时钟信号跳变沿时, 将备用时钟替代主用时钟。 检测模块还包括: 第二检测子模块, 设置为检测第一标准时钟源是否出现 异常; 第二切换子模块, 设置为在第一标准时钟源出现异常的时刻时, 将出现 异常的第一标准时钟源切换到备用时钟, 并将主用时钟与备用时钟进行同步。 第二标准时钟源模块釆用以下至少之一: 全球定位系统、 全球导航卫星系 统、 北斗或伽利略。 在本发明中, 第一基站上的备份时钟与第二基站上的标准时钟源同步, 并 将此备份时钟作为第一基站上的标准时钟源和主用时钟的备份, 从而在保证正 确时钟输出信号的同时, 降低了第一基站上的硬件开销, 降低了系统成本。 此 夕卜, 本发明还同时对标准时钟源和主用时钟同时进行备份, 从而进一步提升了 系统的可靠性的效果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解, 构成本申请的一部 分, 本发明的示意性实施例及其说明用于解释本发明, 并不构成对本发明的不 当限定。 在附图中: 图 1是根据本发明实施例提供的 TDD基站的时钟备份方法的一种优选的 流程图; 图 2是根据本发明实施例提供的 TDD基站的时钟备份系统的一种优选的 结构框图; 图 3是根据本发明实施例提供的 TDD基站的时钟备份系统的另一种结构 框图; 图 4是根据本发明实施例提供的 TDD基站的时钟备份方法的另一种流程 图; 图 5是根据本发明实施例提供的 TDD基站的时钟备份系统的又一种结构 框图。 具体实施方式 下文中将参考附图并结合实施例来详细说明本发明。 需要说明的是, 在不 冲突的情况下, 本申请中的实施例及实施例中的特征可以相互组合。 实施例 1 图 1是根据本发明实施例提供的 TDD基站的时钟备份方法的一种优选的 流程图, 其包括如下步骤:
S 102, 将第一时分双工基站釆用的主用时钟与第一时分双工基站接收的第 一标准时钟源进行同步, 将第一时分双工基站釆用的备用时钟与第二时分双工 基站接收的第二标准时钟源进行同步;
S 104 , 检测主用时钟或第一标准时钟源是否出现异常;
S 106, 若出现异常, 则将出现异常的主用时钟或第一标准时钟源切换到备 用时钟。 在本优选的实施例中, 第一基站上的备份时钟与第二基站上的标准时钟源 同步, 并将此备份时钟作为第一基站上的标准时钟源和主用时钟的备份, 从而 在保证正确时钟输出信号的同时, 降低了第一基站上的硬件开销, 降低了系统 成本。 jtb夕卜, 在本优选的实施例中, 还同时对标准时钟源和主用时钟同时进行 备份, 从而进一步提升了系统的可靠性的效果。 优选的, 将出现异常的主用时钟切换到备用时钟的步骤包括: 在主用时钟 出现异常的时刻之后输出主用时钟的第一个跳变沿, 关闭主用时钟, 并在关闭 主用时钟的时刻后的备用时钟的第一个正确的时钟信号兆变沿时, 将备用时钟 替代主用时钟。 在本优选的实施例中, 通过上述的切换方式, 实现了无缝切换, 保证了数据传输的稳定性。 优选的, 在将出现异常的主用时钟切换到备用时钟之后, 根据本发明实施 例提供的 TDD基站的时钟备份方法还包括: 在主用时钟恢复正常的时刻之后 输出备用时钟的第一个跳变沿, 关闭备用时钟, 并在关闭备用时钟的时刻后的 主用时钟的第一个正确的时钟信号兆变沿时, 切换回主用时钟。 在本优选的实 施例中, 通过上述的切换方式, 实现了无缝切换, 保证了数据传输的稳定性。 优选的, 切换回主用时钟的步骤还包括: 使用切换时刻后的主用时钟和第 一标准时钟源的相位差数据来控制主用时钟与第一标准时钟源同步。 进一步保 证了主用时钟的准确性。 优选的, 将出现异常的第一标准时钟源切换到备用时钟的步骤包括: 在第 一标准时钟源出现异常的时刻时, 将出现异常的第一标准时钟源切换到备用时 钟, 并将主用时钟与备用时钟进行同步。 在本优选的实施例中, 通过上述的切 换方式, 实现了无缝切换, 保证了数据传输的稳定性。 同时, 通过将主用时钟 与备用时钟(其中,备用时钟代替了出现异常的标准时钟源作为新的参考时钟) 同步, 保证了主用时钟的准确性。 优选的, 将主用时钟与备用时钟进行同步的步骤还包括: 使用切换时刻后 的主用时钟和备用时钟的相位差数据来控制主用时钟与备用时钟同步。 在本优 选的实施例中, 通过相位差数据来控制主用时钟与备用时钟(其中, 备用时钟 代替了出现异常的标准时钟源作为新的参考时钟) 的同步, 进一步保证了主用 时钟的准确 >!"生。 优选的, 将出现异常的第一标准时钟源切换到备用时钟之后, 根据本发明 实施例提供的 TDD基站的时钟备份方法还包括: 在第一标准时钟源恢复正常 的时刻时, 将备用时钟切换到恢复正常的第一标准时钟源, 并将主用时钟与第 一标准时钟源进行同步。 在本优选的实施例中, 通过上述的切换方式, 实现了 无缝切换, 保证了数据传输的稳定性。 同时, 通过将主用时钟与恢复正常的第 一标准时钟源同步, 保证了主用时钟的准确性。 优选的, 将主用时钟与第一标准时钟源进行同步的步骤还包括: 使用切换 时刻后的主用时钟和第一标准时钟源的相位差数据来控制主用时钟与第一标 准时钟源同步。 进一步保证了主用时钟的准确性。 优选的, 第二时分双工基站接收的第二标准时钟源与多个第一时分双工基 站上的备用时钟同步, 进一步保证了成本的降低。 实施例 2 图 2是根据本发明实施例提供的 TDD基站的时钟备份方法的一种优选系 统框图, 一种时分双工基站的时钟备份系统, 包括: 主用时钟模块 202 , 设置 为产生第一时分双工基站使用的主用时钟; 备用时钟模块 204 , 设置为产生第 一时分双工基站使用的备用时钟; 第一标准时钟源模块 206 , 位于第一时分双 工基站上, 设置为产生与主用时钟同步的标准时钟源, 并与主用时钟同步; 第 二标准时钟源模块 208 , 位于第二时分双工基站上, 设置为产生与备用时钟同 步的标准时钟源, 并与备用时钟同步; 检测模块 210 , 设置为检测主用时钟模 块 202或第一标准时钟源模块 206是否出现异常, 若出现异常, 则将出现异常 的主用时钟模块 202或第一标准时钟源模块 206切换到备用时钟模块 204。 在本优选的实施例中, 第一基站上的备份时钟与第二基站上的标准时钟源 同步, 并将此备份时钟作为第一基站上的标准时钟源和主用时钟的备份, 从而 在保证正确时钟输出信号的同时, 降低了第一基站上的硬件开销, 降低了系统 成本。 jtb夕卜, 在本优选的实施例中, 还同时对标准时钟源和主用时钟同时进行 备份, 从而进一步提升了系统的可靠性的效果。 优选的, 检测模块 210包括: 第一检测子模块 2101 , 设置为检测主用时钟 是否出现异常; 第一切换子模块 2102 , 设置为在主用时钟出现异常的时刻之后 输出主用时钟的第一个兆变沿, 关闭主用时钟, 并在关闭主用时钟的时刻后的 备用时钟的第一个正确的时钟信号兆变沿时, 将备用时钟替代主用时钟。 在本 优选的实施例中, 通过上述的切换方式, 实现了无缝切换, 保证了数据传输的 稳定性。 优选的, 检测模块 210还设置为在将出现异常的主用时钟切换到备用时钟 之后, 在主用时钟恢复正常的时刻之后输出备用时钟的第一个跳变沿, 关闭备 用时钟, 并在关闭备用时钟的时刻后的主用时钟的第一个正确的时钟信号兆变 沿时, 切换回主用时钟。 在本优选的实施例中, 通过上述的切换方式, 实现了 无缝切换, 保证了数据传输的稳定性。 优选的, 检测模块 210还设置为使用切换时刻后的主用时钟和第一标准时 钟源的相位差数据来控制主用时钟与第一标准时钟源同步。 进一步保证了主用 时钟的准确 >!"生。 优选的, 检测模块 210还包括: 第二检测子模块 2103 , 设置为检测第一标 准时钟源是否出现异常; 第二切换子模块 2104 , 设置为在第一标准时钟源出现 异常的时刻时, 将出现异常的第一标准时钟源切换到备用时钟, 并将主用时钟 与备用时钟进行同步。 在本优选的实施例中, 通过上述的切换方式, 实现了无 缝切换, 保证了数据传输的稳定性。 同时, 通过将主用时钟与备用时钟(其中, 备用时钟代替了出现异常的第一标准时钟源作为新的参考时钟) 同步, 保证了 主用时钟的准确性。 优选的, 检测模块 210还设置为使用切换时刻后的主用时钟和备用时钟的 相位差数据来控制主用时钟与备用时钟同步。 在本优选的实施例中, 通过相位 差数据来控制主用时钟与备用时钟(其中, 备用时钟代替了出现异常的标准时 钟源作为新的参考时钟) 的同步, 进一步保证了主用时钟的准确性。 优选的, 检测模块 210还设置为将出现异常的第一标准时钟源切换到备用 时钟之后, 在第一标准时钟源恢复正常的时刻时, 将备用时钟切换到恢复正常 的第一标准时钟源, 并将主用时钟与第一标准时钟源进行同步。 在本优选的实 施例中, 通过上述的切换方式, 实现了无缝切换, 保证了数据传输的稳定性。 同时, 通过将主用时钟与恢复正常的第一标准时钟源同步, 保证了主用时钟的 准确性。 优选的, 检测模块 210还设置为使用切换时刻后的主用时钟和第一标准时 钟源的相位差数据来控制主用时钟与第一标准时钟源同步。 进一步保证了主用 时钟的准确 >!"生。 优选的, 第二时分双工基站接收的第二标准时钟源与多个第一时分双工基 站上的备用时钟同步, 进一步保证了成本的降低。 优选的, 所述标准时钟源模块釆用 GPS ( Global Position System, 全球定 位系统)、 GLONASS (全球导航卫星系统)、 BD (北斗) 或 GALILEO (伽利 略)。 优选的, 主用时钟模块 202釆用压控晶振输出频率计数产生的时钟信号, 例如实施例 3中标准时钟源同步模块 3042。 优选的,备用时钟模块 204釆用如实施例 3中的 IEEE( Institute for Electrical and Electronic Engineers, 电气和电子工程师协会 ) 1588 的从( Slave )模块 3041 输出的时钟信号。 优选的, 第一标准时钟源模块 206可釆用如实施例 3中的第二标准时钟源 接收模块 3045 , 用以接收标准时钟源, 主用时钟模块 202通过实施例 3中的时 钟源检测选择模块 3044与第二标准时钟源接收模块 3045接收到的标准时钟源 进行锁定。 优选的, 第二标准时钟源模块 208釆用实施例 3中的 IEEE 1588的主模块 3022 , 与实施例 3 中的第一标准时钟源接收模块 3021接收到的标准时钟源锁 定, 从而将与 IEEE 1588的主模块 3022连接的 IEEE 1588的从模块 3041与标 准时钟源锁定, 即备用时钟模块 204与第二标准时钟源模块 208同步。 优选的, 检测模块 210釆用实施例 3中的输出时钟检测选择模块 3043、 时 钟源检测选择模块 3044。 优选的, 主用时钟和备用时钟的时钟信号通常为秒脉冲, 并且将计数产生 主用时钟或备用时钟的基准时钟统称为时钟频率。
其中, 所述主用时钟和备用时钟在同一块单板上, 进一步地, 可以釆用处 理器加逻辑器件的架构或 ASIC实现, 外加压控晶振组成整个主备时钟系统。 实施例 3 图 3是根据本发明实施例提供的 TDD基站的时钟备份系统的另一种结构 框图, 本发明的 TDD基站的时钟备份系统, 包括基站或网络授时服务器 302 以及 TDD基站 304 , 其中,基站或网络授时服务器 302包括第一标准时钟源接 收模块 3021和 IEEE 1588的主模块 3022; TDD基站 304包括 IEEE 1588的从 模块 3041、 标准时钟源同步模块 3042、 输出时钟检测选择模块 3043、 时钟源 检测选择模块 3044和第二标准时钟源接收模块 3045。 基站或网络授时服务器 302的第一标准时钟源接收模块 3021和 TDD基站
304的第二标准时钟源接收模块 3045用于接收同一个标准时钟源;
IEEE 1588的主模块 3022设置为与标准时钟源锁定;
IEEE 1588的从模块 3041 包含备用时钟, 设置为与 IEEE 1588的主模块 3022锁定; 标准时钟源同步模块 3042 包含主用时钟, 设置为锁定主用时钟与参考信 号, 并透传参考信号; 输出时钟检测选择模块 3043 设置为检测主用时钟是否可用, 不可用切换 到备用时钟, 以及检测主用时钟的时钟信号与参考信号的相位差数据, 上报给 所述标准时钟源同步模块 3042 , 并输出可用时钟信号给所述 TDD基站的其他 模块; 时钟源检测选择模块 3044设置为检测标准时钟源接收模块是否可用, 不 可用则切换到备用时钟。 其中: 标准时钟源同步模块 3042 包含主用时钟, 其组成包括鉴相器、 同步算法 模块、 控制输出模块和压控晶振, 由鉴相器检测压控晶振输出频率计数产生的 时钟信号与参考信号的相位差数据并上报给同步算法模块进行处理, 计算得到 的频偏调整值经控制输出模块以电压形式作用于压控晶振, 通过调整压控晶振 的输出频率间接调整其计数产生的时钟信号的相位, 从而将主用时钟与参考信 号锁定, 该参考信号可以是标准时钟源或 IEEE 1588 Slave模块 3041输出的时 钟信号即备用时钟。 同时标准时钟源同步模块 3042可透传参考信号。
IEEE 1588 Slave模块 3041包含备用时钟, 其组成包括字段解析模块、 时 间戳模块、 同步算法模块和时钟输出模块, 由字段解析模块和时间戳模块共同 完成时间戳的提取并送到同步算法模块, 计算得到的结果用于调整时钟输出模 块的时钟信号, 从而将备用时钟与 IEEE 1588 Master (主)模块输出的时钟信 号锁定,由于 IEEE 1588 Master模块可将其输出的时钟信号与标准时钟源锁定, 所以备用时钟可间接锁定标准时钟源。 输出时钟检测选择模块 3043 , 其组成包括鉴相器、 状态检测模块、 选择输 出模块,一方面设置为检测主用时钟是否可用,如果不可用则切换到备用时钟, 另一方面可设置为检测主用时钟的时钟信号与参考信号的相位差数据, 并上报 给标准时钟源同步模块 3042。 运行过程中输出可用时钟信号给基站的其它模 块。 时钟源检测选择模块 3044 , 其组成包括状态检测和选择输出模块, 设置为 检测第二标准时钟源接收模块 3045是否可用, 如果不可用则切换到备用时钟, 即以 IEEE 1588 Slave模块 3041输出的时钟信号作为参考信号。 本发明提供的 TDD基站时钟备份系统的运行分为以下几个步骤: 运行 IEEE 1588Master模块 3022所在的基站或网络 ·ί受时月艮务器 302 , 以标 准时钟源为参考信号,则 IEEE 1588Master模块 3022输出的时钟信号与标准时 钟源锁定; 在 TDD基站 304上同时运行第二标准时钟源接收模块 3045、 标准时钟源 同步模块 3042和 IEEE 1588 Slave模块 3041 , IEEE 1588 Slave模块 3041与 IEEE 1588Master模块 3022建立连接后通过 1588 4艮文交互间接锁定标准时钟源; 时钟源检测选择模块 3044默认选择标准时钟源作为参考信号; 标准时钟源同步模块 3042 锁定参考信号后即可通过输出时钟检测选择模 块 3043输出, 备用时钟暂不输出。 从而可以看出本发明提供的 TDD基站时钟备份系统的备份方法, 可同时 为第二标准时钟源接收模块 3045和标准时钟源同步模块 3042提供备份, 基于 不同的情况可釆用不同的备份方案。 实施例 4 图 4是根据本发明实施例提供的 TDD基站的时钟备份方法的另一种流程 图, 其包括如下步^^
S402, 检测时钟链路是否异常, 是则执行 S404, 否则执行 S402;
S404, 判断主用时钟是否异常, 是则执行 S406, 否则执行 S418;
S406, 通过输出时钟检测选择模块选择备用时钟输出。 当输出时钟检测选 择模块检测到标准时钟源同步模块上报的状态异常时, 将继续输出主用时钟下 一个兆变沿后关闭主用时钟, 并同时以备用时钟的时钟频率的下一个兆变沿开 始计数, 备用时钟的时钟频率计满到下一个备用时钟时钟信号跳变沿代替主用 时钟, 实现到备用时钟的切换;
S408, 主用时钟恢复正常;
S410, 输出备用时钟下一个兆变沿后关闭备用时钟, 并同时以主用时钟的 时钟频率的下一个兆变沿开始计数, 主用时钟频率计满到下一个主用时钟时钟 信号跳变沿代替备用时钟, 切换回主用时钟;
S412, 输出时钟检测选择模块上报主用时钟与标准时钟源的相位差数据; S414, 将上 4艮的相位差数据进行计算;
S416, 计算结果用于控制主用时钟与标准时钟源同步, 并执行 S402; S418, 标准时钟源接收模块异常;
S420, 在时钟源检测选择模块中直接选择备用时钟的时钟信号作为参考信 号, 由标准时钟源同步模块与新的参考信号锁定, 即主用时钟与备用时钟锁定;
S422, 运行同步算法时, 忽略切换时刻鉴相器上报主用时钟和备用时钟的 初始相位差数据;
S424, 计算切换时刻后得到的相位差数据, 得到的结果用于控制主用时钟 和备用时钟同步。 S426, 标准时钟源接收模块恢复正常; 运行同步算法时, 丢掉切换时刻鉴 相器上 4艮的主用时钟和标准时钟源的初始相位差数据, 计算后续得到的相位差 数据, 得到的结果用于控制主用时钟和标准时钟源同步。
S428, 以标准时钟源接收模块的时钟信号作为参考信号, 与标准时钟源同 步模块锁定, 即标准时钟源与主用时钟锁定; S430, 忽略标准时钟源同步模块读取的切换时刻的主用时钟和标准时钟源 的相位差数据;
S432, 计算切换时刻后的主用时钟和标准时钟源的相位差数据, 用于控制 主用时钟与标准时钟源同步, 并执行 S402。
由此可以看出, 上述方法中, 用输出时钟检测选择模块内部的鉴相器代替 了标准时钟源同步模块内部的鉴相器, 所以从结构上看, 原标准时钟源同步模 块与输出时钟检测选择模块共同组成了新的标准时钟源同步模块。 通过比较可以发现, 本发明的技术方案与现有技术的主要区别在于, 以 IEEE 1588 Slave模块作为 TDD基站的备用时钟。 主、 备用时钟在同一单板的两个模块中, 标准时钟源同步模块锁定标准时 钟源, IEEE 1588 Slave模块通过锁定 IEEE 1588Master的时钟模块间接锁定标 准时钟源, 然后通过时钟源检测选择模块选择时钟源主备切换或通过输出时钟 检测选择模块进行输出时钟主备切换。 实施例 5 图 5是根据本发明实施例提供的 TDD基站的时钟备份系统的又一种结构 框图。 提供了本发明的一个具体实现, 该 TDD基站时钟备份系统包括下述模 块或接口: 1 ) GPS模块 502 , 包括 GPS接收机及其外围天馈状态检测电路, 设置为 接收 GPS卫星信号输出 1PPS并可实时上 4艮当前状态。
2 )时钟源检测选择模块 504 ,包括 GPS模块状态检测模块, IEEE 1588 Slave 模块状态检测模块和 1PPS (脉冲 /秒) 选择输出模块, 设置为状态检测并根据 检测结果输出 1PPS。 3 ) 时钟同步模块 506 , 包括压控晶振、 鉴相器、 同步算法模块和控制输出 模块, 设置为输出与输入信号同步的 1PPS及用于计数产生该 1PPS的 10MHz 时钟频率。
4 )输出时钟检测选择模块 508 , 包括鉴相器、时钟同步模块状态检测模块, IEEE 1588 Slave模块状态检测模块、 1PPS选择输出模块, 设置为状态检测并 根据检测结果输出 1PPS , 作为可用时钟信号, 输出给基站的其它模块。
5 )IEEE 1588 Slave模块 510,通过与网络授时服务器或其它基站上的 IEEE 1588 Master模块的报文交互,输出间接与 GPS接收机输出 1PPS同步的 1PPS。 上述时钟同步模块与 IEEE 1588 Slave模块设置为计数产生 1PPS的时钟频 率均为 10MHz。 启动时钟切换的具体流程如下:
1 ) 主用时钟异常即时钟同步模块 506 的状态异常时, 输出时钟检测选择 模块 508将继续输出下一个跳变沿后关闭其 1PPS输出, 并同时以备用时钟的 10MHz的下一个兆变沿开始计数,输出计数值为 10M的附近时刻的 IEEE 1588 Slave的 1PPS。 2 ) 当时钟同步模块 506恢复正常时, 在输出时钟检测选择模块 508 中,
^!夺继续输出下一个兆变沿后关闭备用时钟, 并同时以主用时钟的 10MHz 的下 一个跳变沿开始计数, 每次计满 10M后输出 1PPS , 过程中由鉴相器检测该信 号与时钟同步模块 506透传的参考信号的相位差数据给时钟同步模块 506 , 随 后实现正常控制。
3 ) GPS模块 502异常, 而主用时钟正常。 此时在时钟源检测选择模块 504 中直接选择 IEEE 1588 Slave模块 510输出的 1PPS作为参考信号, 由时钟同步 模块 506与新的参考信号锁定。 运行同步算法时, 丢掉初始相位差数据, 后续 得到的相位差数据用于计算, 得到的结果用于控制主用时钟。
4 ) 当主用时钟恢复正常时, 则仍以 GPS模块 502的时钟信号作为参考信 号, 运行同步算法时, 处理方法与上述流程相同。 本发明中, 标准时钟源还可以是其它卫星定位系统: 包括 GLONASS (全 球导航卫星系统)、 BD (北斗)、 GALILEO (伽利略) 等。 本实施例中, 各个模块, 尤其是时钟同步模块和 IEEE 1588 Slave模块的 实现, 本领域的普通技术人员都可以理解, 在此不做赞述。 基站同时运行 GPS时钟同步方案和 IEEE 1588方案, 默认输出与 GPS模 块输出的 1PPS 同相的 1PPS。 实际应用中 GPS 时钟方案可靠性和同步^"度更 高, 所以优先选择 GPS时钟方案, 而 IEEE 1588方案作为备用时钟。 从以上的描述中, 可以看出, 本发明实现了如下技术效果:
1 ) 由于一个 IEEE 1588 Master可以同时带多个 IEEE 1588 Slave, 因此, 通过同一个标准时钟源, 可以锁定多个 TDD基站中的备用时钟, 即 IEEE 1588 Slave 模块, 所以相对于背景技术中说明的加入一个时钟源作为备份釆用的两 块单板进行时钟备份的方案, 其成本可以极大地降低;
2 ) 标准时钟源信号接收模块分别安装在 IEEE 1588 Master 所在单板和 TDD基站上,所以相对于同一块单板进行时钟备份但标准时钟源也为同一个的 情况, 可提升应对标准时钟源接收模块异常的能力;
3 ) 备份方案的实现可做到无缝切换; 4 ) 同时对标准时钟源接收模块和标准时钟源同步模块进行备份, 并基于 无缝切换可见, 该时钟备份方法可极大地提升系统的可靠性。 显然, 本领域的技术人员应该明白, 上述的本发明的各模块或各步骤可以 用通用的计算装置来实现, 它们可以集中在单个的计算装置上, 或者分布在多 个计算装置所组成的网络上, 可选地, 它们可以用计算装置可执行的程序代码 来实现, 从而可以将它们存储在存储装置中由计算装置来执行, 或者将它们分 别制作成各个集成电路模块, 或者将它们中的多个模块或步骤制作成单个集成 电路模块来实现。 这样, 本发明不限制于任何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已, 并不用于限制本发明, 对于本领 域的技术人员来说, 本发明可以有各种更改和变化。 凡在本发明的 ^"神和原则 之内, 所作的任何修改、 等同替换、 改进等, 均应包含在本发明的保护范围之 内。

Claims

权 利 要 求 书
1. 一种时分双工基站的时钟备份方法, 包括如下步 4聚: 将第一时分双工基站釆用的主用时钟与所述第一时分双工基站接收 的第一标准时钟源进行同步, 将所述第一时分双工基站釆用的备用时钟 与第二时分双工基站接收的第二标准时钟源进行同步;
检测所述主用时钟或所述第一标准时钟源是否出现异常; 若出现异常, 则将出现异常的所述主用时钟或所述第一标准时钟源 切换到所述备用时钟。
2. 根据权利要求 1所述的方法, 其中, 所述将出现异常的所述主用时钟切 换到所述备用时钟的步骤包括:
在所述主用时钟出现异常的时刻之后输出所述主用时钟的第一个跳 变沿, 关闭所述主用时钟, 并在关闭所述主用时钟的时刻后的所述备用 时钟的第一个正确的时钟信号兆变沿时, 将所述备用时钟替代所述主用 时钟。
3. 根据权利要求 2所述的方法, 其中, 所述在将出现异常的所述主用时钟 切换到所述备用时钟之后, 还包括:
在所述主用时钟恢复正常的时刻之后输出所述备用时钟的第一个跳 变沿, 关闭所述备用时钟, 并在关闭所述备用时钟的时刻后的所述主用 时钟的第一个正确的时钟信号兆变沿时, 切换回所述主用时钟。
4. 根据权利要求 3所述的方法, 其中, 所述切换回所述主用时钟的步骤还 包括:
使用切换时刻后的所述主用时钟和所述第一标准时钟源的相位差数 据来控制所述主用时钟与所述第一标准时钟源同步。
5. 根据权利要求 1所述的方法, 其中, 所述将出现异常的所述第一标准时 钟源切换到所述备用时钟的步骤包括:
在所述第一标准时钟源出现异常的时刻时, 将出现异常的所述第一 标准时钟源切换到所述备用时钟, 并将所述主用时钟与所述备用时钟进 行同步。
6. 根据权利要求 5所述的方法, 其中, 所述将所述主用时钟与所述备用时 钟进行同步的步骤还包括:
使用切换时刻后的所述主用时钟和所述备用时钟的相位差数据来控 制所述主用时钟与所述备用时钟同步。
7. 根据权利要求 5所述的方法, 其中, 所述将出现异常的所述第一标准时 钟源切换到所述备用时钟之后, 还包括:
在所述第一标准时钟源恢复正常的时刻时, 将所述备用时钟切换到 所述恢复正常的第一标准时钟源, 并将所述主用时钟与所述第一标准时 钟源进行同步。
8. 根据权利要求 7所述的方法, 其中, 所述将所述主用时钟与所述第一标 准时钟源进行同步的步 4聚还包括:
使用切换时刻后的所述主用时钟和所述第一标准时钟源的相位差数 据来控制所述主用时钟与所述第一标准时钟源同步。
9. 根据权利要求 1所述的方法, 其中, 所述第二时分双工基站接收的第二 标准时钟源与多个所述第一时分双工基站上的备用时钟同步。
10. —种时分双工基站的时钟备份系统, 包括
主用时钟模块, 设置为产生第一时分双工基站使用的主用时钟; 备用时钟模块,设置为产生所述第一时分双工基站使用的备用时钟; 第一标准时钟源模块, 位于所述第一时分双工基站上, 设置为产生 与所述主用时钟同步的标准时钟源, 并与所述主用时钟同步;
第二标准时钟源模块, 位于第二时分双工基站上, 设置为产生与所 述备用时钟同步的标准时钟源, 并与所述备用时钟同步;
检测模块, 设置为检测所述主用时钟模块或所述第一标准时钟源模 块是否出现异常, 若出现异常, 则将出现异常的所述主用时钟模块或所 述第一标准时钟源模块切换到所述备用时钟模块。
11. 根据权利要求 10所述的系统, 其中, 所述检测模块包括:
第一检测子模块, 设置为检测所述主用时钟是否出现异常; 第一切换子模块, 设置为在所述主用时钟出现异常的时刻之后输出 所述主用时钟的第一个跳变沿, 关闭所述主用时钟, 并在关闭所述主用 时钟的时刻后的所述备用时钟的第一个正确的时钟信号兆变沿时, ^!夺所 述备用时钟替代所述主用时钟。
12. 根据权利要求 10所述的系统, 其中, 所述检测模块还包括:
第二检测子模块, 设置为检测所述第一标准时钟源是否出现异常; 第二切换子模块,设置为在所述第一标准时钟源出现异常的时刻时, 将出现异常的所述第一标准时钟源切换到所述备用时钟, 并将所述主用 时钟与所述备用时钟进行同步。
13. 根据权利要求 10所述的系统, 其中, 所述第二标准时钟源模块釆用以下 至少之一: 全球定位系统、 全球导航卫星系统、 北斗或伽利略。
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