WO2012070416A1 - データ処理装置、及び、データ処理方法 - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
- H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0064—Concatenated codes
- H04L1/0065—Serial concatenated codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0072—Error control for data other than payload data, e.g. control data
Definitions
- the present invention relates to a data processing apparatus and a data processing method, and in particular, easily performs control data processing necessary for demodulation, for example, with improved PAPR (Peak-to-Average Power Ratio).
- PAPR Peak-to-Average Power Ratio
- the present invention relates to a data processing apparatus and a data processing method.
- DVB Digital Video Broadcasting
- OFDM Orthogonal Frequency Division Multiplexing
- the new standard which is a new standard of digital broadcasting
- a new frame which is a frame which becomes a unit for transmitting data
- an existing standard for example, a T2 frame defined in DVB-T.2
- a receiving device compliant with the new standard can easily process the new frame (of the OFDM signal).
- a receiving device that conforms to a new standard that employs a T2 frame as a new frame can process a new frame in the same manner as a receiving device that conforms to DVB-T.2.
- a preamble called a P2 symbol containing control data necessary for performing demodulation called L1 is arranged, but the PAPR of the OFDM signal of the P2 symbol of the T2 frame is relatively large May be a value.
- the PAPR of the OFDM signal of the P2 symbol of the T2 frame is a large value
- the power of the OFDM signal of the P2 symbol is large
- the OFDM signal having the large power is clipped in the receiving apparatus that receives the OFDM signal. It can happen.
- the signal quality of the OFDM signal is deteriorated, which may adversely affect the demodulation of the OFDM signal.
- control data when control data is scrambled to improve PAPR, the receiving apparatus performs processing different from that in the case where control data is not scrambled, in addition to descrambling for returning the control data to the original state.
- the control data OFDM signal
- the present invention has been made in view of such a situation, and makes it possible to easily perform control data processing with improved PAPR.
- the data processing apparatus scrambles the control data necessary for performing demodulation with padding means for padding dummy data and post-padding control data as the control data after the padding.
- Scramble means for performing replacement replacement means for generating replacement data by replacing the scrambled dummy data of the scrambled post-padding control data with the dummy data, and an error correction code for the replacement data
- dummy data is padded with control data necessary for demodulation, and the padded control data, which is the control data after padding, is scrambled
- a data processing method comprising the steps of: replacing the scrambled dummy data of the scrambled post-padding control data with the dummy data, generating replacement data, and performing error correction coding of the replacement data It is.
- dummy data is padded with control data necessary for demodulation, and scrambling is performed on post-padding control data that is the control data after padding. Further, the scrambled dummy data in the post-scrambled padding control data is replaced with the dummy data to generate replacement data, and error correction coding of the replacement data is performed.
- the data processing apparatus is directed to control data necessary for demodulation, scrambling means for scrambling, padding means for padding dummy data to the control data after scramble,
- a data processing apparatus comprising: error correction encoding means for performing error correction encoding of post-padding scrambled data obtained by padding dummy data to the scrambled control data.
- the control data necessary for demodulation is scrambled, the scrambled control data is padded with dummy data, and the scrambled control data
- the data processing method includes a step of performing error correction coding of post-padding scrambled data obtained by padding dummy data.
- control data necessary for demodulation is scrambled, and dummy data is padded into the scrambled control data. Then, error correction coding of post-padding scrambled data is performed by padding dummy data to the scrambled control data.
- the data processing apparatus pads dummy data on control data necessary for demodulation, performs scrambling on post-padding control data that is the control data after padding, Of the scrambled post-padding control data, the scrambled dummy data is replaced with the dummy data, the replacement data is generated, and the error obtained by the transmission apparatus that performs error correction coding of the replacement data
- the data processing apparatus includes an error correction unit that performs error correction for decoding a correction code into the replacement data, and a descrambling unit that performs descrambling on the replacement data.
- dummy data is padded with control data necessary for demodulation, and the padded control data, which is the control data after padding, is scrambled, Of the scrambled post-padding control data, the scrambled dummy data is replaced with the dummy data, the replacement data is generated, and the error obtained by the transmission apparatus that performs error correction coding of the replacement data
- the data processing method includes steps of performing error correction for decoding a correction code into the replacement data and descrambling the replacement data.
- error correction for decoding the error correction code obtained by the transmission device into the replacement data is performed, and descrambling is performed on the replacement data.
- a data processing device scrambles control data necessary for demodulation, pads dummy data on the scrambled control data, and controls the scrambled control data
- error correction means for performing error correction for decoding an error correction code obtained by a transmission device that performs error correction coding of post-padding scrambled data obtained by padding dummy data into the scrambled data after padding, and the scrambled data after padding
- the data processing apparatus comprises: deletion means for deleting the dummy data and outputting the scrambled control data; and descrambling means for descrambling the scrambled control data.
- the control data necessary for demodulation is scrambled, dummy data is padded in the scrambled control data, and the scrambled control data
- error correction code obtained by a transmission device that performs error correction coding of post-padding scrambled data obtained by padding dummy data is decoded into the post-padding scrambled data, and among the post-padding scrambled data.
- the data processing method includes the steps of deleting the dummy data, outputting the scrambled control data, and descrambling the scrambled control data.
- error correction for decoding the error correction code obtained by the transmission device into the post-padding scrambled data is performed, and the dummy data in the post-padding scrambled data is deleted.
- the scrambled control data is output.
- descrambling is performed on the control data after the scramble.
- the data processing apparatus may be an independent apparatus or an internal block constituting one apparatus.
- FIG. It is a block diagram which shows the structural example of the transmitter which transmits data, without performing the scramble of control data. It is a figure which shows the format of the bit stream of the OFDM signal which a transmitter transmits. It is a figure explaining the process of the padder 21, the BCH encoder 22, the LDPC encoder 23, and the shortening part 24.
- FIG. It is a block diagram which shows the structural example of the receiver which receives the data from the transmitter which transmits data, without performing the scramble of control data. It is a block diagram which shows the 1st structural example of the transmitter which performs the scrambling of control data and transmits data.
- FIG. It is a figure explaining the process of the padder 21, the scrambler 101, the BCH encoder 22, the LDPC encoder 23, and the shortening part 24.
- FIG. It is a block diagram which shows the 1st structural example of the receiver which performs the scrambling of control data and receives the data from the transmitter which transmits data. It is a block diagram which shows the 2nd structural example of the transmitter which scrambles control data and transmits data. It is a figure explaining the process of the scrambler 101, the padder 21, the BCH encoder 22, the LDPC encoder 23, and the shortening part 24.
- FIG. 1 is a block diagram illustrating a configuration example of a transmission apparatus that transmits data without scrambling control data, for example, a transmission apparatus compliant with DVB-T.2.
- the transmitting device transmits actual data such as image data and audio data as a digital broadcast program as target data to be transmitted, for example, by OFDM.
- one or more streams as target data are supplied to a mode adaptation / multiplexer (Mode Adaptation / Multiplexer) 11.
- the mode adaptation / multiplexer 11 selects a mode such as a transmission mode, multiplexes one or more streams supplied thereto, and supplies data obtained as a result to a padder 12.
- the padder 12 pads the data from the mode adaptation / multiplexer 11 as dummy data, for example, by padding the necessary number of zeros (inserting Null), and the resulting data is converted into a BB scrambler (BB Scrambler) 13.
- BB Scrambler BB Scrambler
- the BB scrambler 13 scrambles (energy spreads) data from the padder 12 and supplies data obtained as a result to a BCH encoder 14.
- the BCH encoder 14 performs BCH encoding, which is error correction encoding of data from the BB scrambler 13, and uses the resulting BCH code as LDPC target data to be LDPC encoded as an LDPC encoder (LDPC encoder ) 15. *
- the LDPC encoder 15 performs LDPC encoding, which is error correction encoding of the LDPC target data from the BCH encoder 14, and supplies the resulting LDPC code to the bit interleaver 16.
- the bit interleaver 16 performs bit interleaving for interleaving the LDPC code from the LDPC encoder 15 in bit units, and supplies the LDPC code after the bit interleaving to a QAM encoder (QAM encoder) 17.
- QAM encoder QAM encoder
- the QAM encoder 17 maps the LDPC code from the bit interleaver 16 to a signal point representing one symbol of orthogonal modulation in units of one or more bits (symbol unit) of the LDPC code, and performs orthogonal modulation (multilevel modulation). )I do.
- the QAM encoder 17 defines the LDPC code from the bit interleaver 16 by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier in symbol units of 1 bit or more.
- the quadrature modulation is performed by mapping to a signal point determined by a modulation scheme for performing quadrature modulation of the LDPC code on the IQ plane (IQ constellation).
- a modulation method of quadrature modulation performed by the QAM encoder 17 for example, a modulation method including a modulation method defined in the DVB-T standard, that is, for example, QPSK (Quadrature Phase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc.
- QPSK Quadratture Phase Shift Keying
- 16QAM Quadratture Amplitude Modulation
- 64QAM 256QAM
- 1024QAM 1024QAM
- 4096QAM etc.
- the QAM encoder 17 can perform other quadrature modulation such as 4PAM (Pulse Amplitude Modulation), for example.
- 4PAM Pulse Amplitude Modulation
- Time Interleaver Time Interleaver
- the time interleaver 18 performs time interleaving (interleaving in the time direction) in units of symbols on the data (symbols) from the QAM encoder 17, and obtains the resulting data as a SISO / MISO encoder (SISO / MISO coder) 19. To supply.
- the SISO / MISO encoder 19 performs space-time coding on the data (symbol) from the time interleaver 18 and supplies the data to a frequency interleaver 20.
- the frequency interleaver 20 performs frequency interleaving (interleaving in the frequency direction) for each data (symbol) from the SISO / MISO encoder 19 and supplies it to a frame builder / resource allocation unit (Frame Builder & Resource Allocation) 27. To do.
- the padder 21 is supplied with control data (signalling) for transmission control, which is necessary for demodulating data transmitted from the transmission device, for example, called L1.
- the padder 21 pads the control data supplied thereto with dummy data, for example, zero as many as necessary (inserts null), and supplies the resulting data to the BCH encoder 22. .
- the BCH encoder 22 performs BCH encoding on the data from the padder 21 in the same manner as the BCH encoder 14, and supplies the resulting BCH code to the LDPC encoder 23.
- the LDPC encoder 23 performs LDPC encoding on the data from the BCH encoder 22 as LDPC target data in the same manner as the LDPC encoder 15, and supplies the resulting LDPC code to the shortening unit 24.
- the shortening unit 24 performs shortening that is deletion of dummy data included in the LDPC code from the LDPC encoder 23 and puncturing of parity bits of the LDPC code, and the shortened LDPC The code is supplied to the QAM encoder 25.
- the QAM encoder 25 maps the LDPC code from the shortening unit 24 to signal points representing one symbol of orthogonal modulation in units of 1 bit or more (symbol unit) of the LDPC code. Then, quadrature modulation is performed, and data (symbol) obtained as a result is supplied to the frequency interleaver 26.
- the frequency interleaver 26 performs frequency interleaving on the data (symbol) from the QAM encoder 25 in units of symbols and supplies the data to the frame builder / resource allocation unit 27.
- the frame builder / resource allocation unit 27 inserts pilot symbols at necessary positions of data (symbols) from the frequency interleavers 20 and 26, and from the resulting data (symbols), a predetermined number For example, a frame conforming to DVB-T.2 called a T2 frame is formed and is supplied to an OFDM generation unit (OFDM generation) 28.
- OFDM generation OFDM generation
- the OFDM generation unit 28 performs necessary signal processing such as IFFT (Inverse Fast Fourier Transform) on the frame from the frame builder / resource allocation unit 27, generates an OFDM signal corresponding to the frame, and transmits it by radio .
- IFFT Inverse Fast Fourier Transform
- FIG. 2 is a diagram showing the format of the bit stream of the OFDM signal transmitted by the transmission apparatus of FIG.
- the bit stream of the OFDM signal transmitted by the transmission apparatus in FIG. 1 is composed of T2 frames.
- a P1 symbol that is a preamble As shown in FIG. 2, in the T2 frame, a P1 symbol that is a preamble, a P2 symbol, a symbol called Normal, and a symbol called FC (Flame Closing) (both data symbols) are arranged in that order. .
- GI represents a guard interval
- a symbol (P2 symbol and data symbol) between a certain guard interval and the next guard interval is an OFDM symbol subject to one IFFT (and FFT) in OFDM.
- the P1 symbol is a symbol for transmitting P1 signaling (P1 signalling).
- the P1 symbol includes transmission parameters called S1 and S2.
- S1 and S2 are either SISO (Single Input Single output (meaning one transmitting and one receiving antenna)) or MISO (Multiple Input, Single Output (meaning multiple transmitting antennas but one receiving antenna)) Or the FFT size (number of samples (symbols) to be subjected to one FFT), etc. when performing the FFT of the P2 symbol.
- S1 and S2 included in the P1 symbol include information (frame identification information) indicating that the frame is a T2 frame.
- the receiving apparatus can identify whether or not the frame is a T2 frame by referring to S1 and S2 included in the P1 symbol.
- the P2 symbol is a symbol for transmitting control data called L1 necessary for demodulating the OFDM signal, and the first and second data, that is, the first data is stored in L1.
- L1 post-signaling L1 post-signalling
- L1 pre-signalling L1 pre-signalling
- L1 pre-signaling includes information necessary for performing demodulation of L1 post-signaling
- L1 post-signaling is information necessary for a receiving apparatus that receives an OFDM signal to access a physical layer (layer pipes), That is, information necessary for demodulating data symbols is included.
- the L1 pre-signaling includes, for example, a guard interval length, a pilot pattern (PP) indicating an arrangement of a pilot signal indicating which pilot signal which is a known signal is included in which symbol (subcarrier), and an OFDM signal.
- PP pilot pattern
- Whether or not the transmission band to be transmitted is extended (BWT_EXT), the number of OFDM symbols included in one T2 frame (NDSYM), and the like are included as information necessary for demodulating the data symbols.
- FIG. 3 is a diagram for explaining processing of the padder 21, the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24 of FIG.
- the L1 pre-signaling, the L1 post-signaling, or both the L1 pre-signaling and the L1 post-signaling, which are control data K sig of a predetermined length, are supplied to the padder 21.
- the padder 21 pads the control data K sig supplied thereto with, for example, a required number of zeros as dummy data.
- the data length (number of bits) of the control data K sig is shorter than the data length (information bit length) to be subjected to BCH encoding as error correction encoding performed by the BCH encoder 22 at the subsequent stage.
- the control data after the padding has a data length (number of bits) corresponding to the data length to be subjected to BCH encoding as error correction encoding performed by the BCH encoder 22 in the subsequent stage.
- the zero as dummy data is padded.
- Post-padding control data K bch that is control data after padding is supplied from the padder 21 to the BCH encoder 22.
- the BCH encoder 22 performs BCH encoding as error correction encoding of the post-padding control data K bch from the padder 21, and supplies the BCH code K ldpc obtained as a result to the LDPC encoder 23.
- the BCH encoder 22 obtains a parity (BCH Parity) bit of the BCH code for the post-padding control data K bch and adds the parity bit to the post-padding control data K bch , thereby performing post-padding control data K bch.
- Processing for obtaining the BCH code K ldpc of the data K bch is performed as BCH encoding.
- the LDPC encoder 23 performs LDPC encoding as error correction encoding of the BCH code K ldpc of the post-padding control data K bch from the BCH encoder 22, and the resulting LDPC code N ldpc is sent to the shortening unit 24. Supply.
- the LDPC encoder 23 obtains a parity (LDPC Parity) bit of the LDPC code for the BCH code K ldpc of the post-padding control data K bch , and adds the parity bit to the BCH code K ldpc , process of obtaining the LDPC code N [iota] dpc BCH code K [iota] dpc is performed as LDPC coding.
- LDPC Parity LDPC Parity
- the shortening unit 24 shortens zero as dummy data included in the LDPC code N ldpc from the LDPC encoder 23 and performs (partial) puncturing of the parity bits of the LDPC code N ldpc. A certain shortening is performed, and the shortened LDPC code N post is supplied to the QAM encoder 25.
- FIG. 4 shows a configuration example of a receiving apparatus that receives data from the transmitting apparatus of FIG. 1 that transmits data without scrambling control data, for example, a receiving apparatus that complies with DVB-T.2. It is a block diagram.
- the receiving apparatus receives the OFDM signal from the transmitting apparatus in FIG. 1 and supplies it to an OFDM processing unit (OFDM operation) 31.
- OFDM processing unit OFDM operation
- the OFDM processing unit (OFDM operation) 31 performs signal processing such as FFT of the OFDM signal supplied thereto, and supplies data (symbols) obtained as a result to the frame management unit (Frame management) 32.
- the frame management unit 32 performs processing (frame interpretation) of a frame configured by the symbols supplied from the OFDM processing unit 31, and converts the symbol of the target data included in the data symbol in the frame (T2 frame) to the frequency deinterpolator.
- the signal is supplied to a frequency deinterleaver 33 and a control data symbol included in the P2 symbol in the frame is supplied to a frequency deinterleaver 43.
- the frequency deinterleaver 33 performs frequency deinterleaving for each symbol from the frame management unit 32 and supplies the symbol to the SISO / MISO decoder 34.
- the SISO / MISO decoder 34 performs space-time decoding of data (symbols) from the frequency deinterleaver 33 and supplies it to a time deinterleaver (Time Deinterleaver) 35.
- the time deinterleaver 35 performs time deinterleaving on the data (symbol) from the SISO / MISO decoder 34 in units of symbols and supplies the data to a QAM decoder (QAM decoder) 36.
- QAM decoder QAM decoder
- the QAM decoder 36 performs demapping (signal point constellation decoding) on the symbols (symbols arranged at signal points) from the time deinterleaver 35 and performs orthogonal demodulation, and the resulting data (symbols) is subjected to bit deinterlacing. It is supplied to a Lieber (Bit Deinterleaver) 37.
- the bit deinterleaver 37 performs bit deinterleaving on the data (symbols) from the QAM decoder 36 to restore the original arrangement of the bits rearranged by the bit interleaver 16 performed in the bit interleaver 16 of FIG.
- the resulting LDPC code is supplied to the LDPC decoder 38.
- the LDPC decoder 38 performs LDPC decoding of the LDPC code from the bit deinterleaver 37, and supplies the BCH code obtained as a result to the BCH decoder 39.
- the BCH decoder 39 performs BCH decoding of the BCH code from the LDPC decoder 38 and supplies data obtained as a result to a BB descrambler 40.
- the BB descrambler 40 descrambles the data from the BCH decoder 39 (energy despreading), and supplies data obtained as a result to a null deletion unit (Null Deletion) 41.
- the null deletion unit 41 deletes the null inserted by the padder 12 of FIG. 1 from the data from the BB descrambler 40 and supplies it to the demultiplexer 42.
- the demultiplexer 42 separates and outputs each of one or more streams (target data) multiplexed in the data from the null deletion unit 41.
- the frequency deinterleaver 43 performs frequency deinterleaving for each symbol (control data symbol) from the frame management unit 32 and supplies it to a QAM decoder 44.
- the QAM decoder 44 de-maps (symbols arranged at signal points) the symbols from the frequency deinterleaver 43 and performs orthogonal demodulation and obtains a shortened LDPC code N post as a result. (FIG. 3) is supplied to the restoration unit 45.
- the restoration unit 45 pads the shortened LDPC code N post from the QAM decoder 44 with zeros as dummy data, and performs a restoration process for depuncturing the parity bits of the LDPC code, thereby performing the LDPC before shortening.
- the code N ldpc (FIG. 3) is restored and supplied to an LDPC decoder 46.
- the LDPC decoder 46 performs LDPC decoding of the LDPC code N ldpc from the restoration unit 45, and supplies the BCH code K ldpc (FIG. 3) obtained as a result to the BCH decoder 47.
- the BCH decoder 47 performs BCH decoding of the BCH code K ldpc from the LDPC decoder 46, and supplies post-padding control data K bch (FIG. 3) obtained as a result to the deletion unit 48.
- the deletion unit 48 deletes zero as dummy data padded in the post-padding control data K bch and supplies the control data K sig (FIG. 3) obtained as a result to the control unit 49.
- the control unit 49 controls each block configuring the receiving device based on the control data K sig from the deletion unit 48.
- the new standard which is a new standard for digital broadcasting
- an existing standard for example, a T2 frame defined in DVB-T.2
- the receiving apparatus compliant with the new standard can easily process the new frame (of the OFDM signal).
- a receiving device that conforms to a new standard that employs a T2 frame as a new frame can process a new frame in the same manner as a receiving device that conforms to DVB-T.2.
- the PAPR of the OFDM signal of the P2 symbol including L1 as the control data of the T2 frame may have a relatively large value.
- the OFDM signal having a large power may be clipped in the receiving device compliant with the new standard.
- the signal quality of the OFDM signal is deteriorated, which may adversely affect the demodulation of the OFDM signal.
- FIG. 5 is a block diagram illustrating a first configuration example of a transmission apparatus that scrambles control data and transmits data.
- the transmission apparatus in FIG. 5 is common to the transmission apparatus in FIG. 1 in that it includes a mode adaptation / multiplexer 11 or an OFDM generation unit 28.
- the transmission apparatus in FIG. 5 is different from the transmission apparatus in FIG. 1 in that a scrambler 101 is newly provided between the padder 21 and the BCH encoder 22.
- the padding control data K bch (FIG. 3) is supplied from the padder 21 to the scrambler 101.
- the scrambler 101 performs scrambling (energy diffusion) on the post-padding control data K bch from the padder 21 and outputs post-padding control data after the scramble.
- the scrambled post-padding control data output from the scrambler 101 is supplied to the BCH encoder 22, and the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24 perform processing similar to that of the transmission apparatus in FIG. Done.
- FIG. 6 is a diagram for explaining processing of the padder 21, the scrambler 101, the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24 of FIG.
- the padder 21 is supplied with control data K sig having a predetermined length.
- the padder 21 pads the control data K sig supplied thereto with the required number of zeros as dummy data, and the padded control data K bch that is the control data after the padding is sent to the scrambler 101. Supply.
- the scrambler 101 scrambles the post-padding control data K bch from the padder 21, and supplies the post-padding control data K bch (s) after the scramble to the BCH encoder 22.
- the BCH encoder 22 performs BCH encoding as error correction encoding of the post-padding control data K bch (s) after the scramble from the padder 21, and supplies the resulting BCH code K ldpc to the LDPC encoder 23. .
- the BCH encoder 22 obtains the parity bit of the BCH code for the post-padding control data K bch (s) after the scramble, as in the case described with reference to FIG. by being added to the padding after control data K bch (s), BCH code K [iota] dpc scrambling after padding after control data K bch (s) is obtained.
- the LDPC encoder 23 performs LDPC coding as error correction coding of the BCH code K ldpc of the post-padding control data K bch (s) after scrambled from the BCH encoder 22, and obtains the resulting LDPC code N ldpc To the shortening unit 24.
- the parity bit of the LDPC code is obtained for the BCH code K ldpc of the post-padding control data K bch (s) after the scramble, as in the case described with reference to FIG. but by being added to the BCH code K [iota] dpc, LDPC codes N [iota] dpc BCH code K [iota] dpc is obtained.
- the shortening unit 24 deletes the scrambled dummy data included in the LDPC code N ldpc from the LDPC encoder 23 and shortens (partial) the puncture of the parity bits of the LDPC code N ldpc.
- the shortened LDPC code N post is supplied to the QAM encoder 25.
- FIG. 7 is a block diagram illustrating a configuration example of a receiving apparatus that scrambles control data and receives data from the transmitting apparatus in FIG. 5 that transmits data.
- FIG. 7 is the same as the receiving apparatus in FIG. 4 in that it includes an OFDM processing unit 31 through a QAM decoder 44, and an LDPC decoder 46 through a control unit 49.
- the receiving apparatus in FIG. 7 is provided with a restoration unit 111 instead of the restoration unit 45 and a descrambler 112 is newly provided between the BCH decoder 47 and the deletion unit 48. 4 is different from the receiving apparatus of FIG.
- the QAM decoder 44 outputs the shortened LDPC code N post (FIG. 6) as in the receiving apparatus of FIG. 4, and the shortened LDPC code N post is the restoration unit. 111.
- the restoration unit 111 restores the LDPC code N ldpc (FIG. 6) before the shortening from the shortened LDPC code N post from the QAM decoder 44 and supplies the LDPC code N ldpc (FIG. 6) to the LDPC decoder 46.
- the post-padding control data K bch is scrambled in the scrambler 101 (FIG. 5), and the scrambled part in the shortening unit 24 (FIG. 5).
- the scrambled dummy data included in the LDPC code N ldpc of the BCH code K ldpc of the control data K bch (s) after the padding and shortening which is a puncture of the parity bit of the LDPC code N ldpc
- the LDPC code N ldpc is shortened to the LDPC code N post .
- LDPC code N post to restore the original (pre-reduction) LDPC code N [iota] dpc is the LDPC code N post after reduction, rather than the dummy data itself It is necessary to pad the scrambled dummy data.
- the reception apparatus (FIG. 4) that receives data from such a transmission apparatus has the shortened LDPC code N post In restoring (FIG. 3) to the LDPC code N ldpc (FIG. 3) before shortening, zero as dummy data may be padded.
- the receiving apparatus receives data from such a transmitting apparatus. 7), when restoring the shortened LDPC code N post (FIG. 6) to the LDPC code N ldpc before shortening (FIG. 6), the dummy data is included in the LDPC code N ldpc before shortening. It is necessary to generate scrambled dummy data, and then pad the scrambled dummy data.
- the restoration unit 111 restores the shortened LDPC code N post (FIG. 6) to the pre-shortened LDPC code N ldpc (FIG. 6). It is necessary to newly perform a process of generating scrambled dummy data that is not performed by the restoration unit 45.
- the restoration unit 111 generates scrambled dummy data, and then pads the scrambled dummy data on the shortened LDPC code N post from the QAM decoder 44 and depunctures the parity bits of the LDPC code. By doing this, the LDPC code N ldpc (FIG. 6) before shortening is restored and supplied to the LDPC decoder 46.
- the LDPC decoder 46 performs LDPC decoding of the LDPC code N ldpc from the restoration unit 111, and supplies the BCH code K ldpc (FIG. 6) obtained as a result to the BCH decoder 47.
- the BCH decoder 47 performs BCH decoding of the BCH code K ldpc from the LDPC decoder 46, and supplies the scrambled post-padding control data K bch (s) (FIG. 6) obtained as a result to the descrambler 112.
- the descrambler 112 performs descrambling (energy despreading) of post-scrambled padding control data K bch (s) from the BCH decoder 47, and zero-padded control data (post-padding control) Data) K bch is obtained and supplied to the deletion unit 48.
- the deletion unit 48 deletes zero as dummy data padded in the post-padding control data K bch and supplies the control data K sig (FIG. 6) obtained as a result to the control unit 49.
- the receiving apparatus (FIG. 7) that receives data from such a transmitting apparatus performs scrambling.
- shortened LDPC code N post (FIG. 6) is restored to LDPC code N ldpc (FIG. 6) before shortening from dummy data to LDPC code N before shortening. It is necessary to generate scrambled dummy data included in ldpc .
- FIG. 8 is a block diagram illustrating a second configuration example of a transmission apparatus that scrambles control data and transmits data.
- the transmission apparatus in FIG. 8 is common to the transmission apparatus in FIG. 1 in that it has a mode adaptation / multiplexer 11 or an OFDM generation unit 28.
- the transmission apparatus of FIG. 8 is different from the transmission apparatus of FIG. 1 in that the scrambler 101 described in FIG.
- a predetermined length of control data is supplied to the scrambler 101.
- the scrambler 101 scrambles the control data supplied thereto, and outputs the scrambled control data.
- the scrambled control data output from the scrambler 101 is supplied to the padder 21.
- the padder 21 the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24, processing similar to that of the transmission apparatus in FIG. Done.
- FIG. 9 is a diagram for explaining processing of the scrambler 101, the padder 21, the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24 of FIG.
- the scrambler 101 is supplied with control data K sig having a predetermined length.
- the scrambler 101 scrambles the control data K bch supplied thereto, and supplies the control data K sig (s) after the scramble to the padder 21.
- the padder 21 pads the scrambled control data K sig (s) from the scrambler 101 with a required number of zeros as dummy data.
- data obtained by padding zero as dummy data to control data K sig (s) after scramble is also referred to as post-padding scramble data.
- the scrambled control data K sig (s) is padded with padding scrambled data K bch obtained by padding zero as dummy data to the BCH encoder 22.
- the BCH encoder 22 performs BCH encoding as error correction encoding of the scrambled data K bch after padding from the padder 21, and supplies the BCH code K ldpc obtained as a result to the LDPC encoder 23.
- the BCH encoder 22 As with the case described in FIG. 3, with respect to the padding scrambled data K bch, parity bit BCH code is determined, the parity bits are added to the padding scrambled data K bch Thus, the BCH code K ldpc of the post-padding scrambled data K bch is obtained.
- the LDPC encoder 23 performs LDPC coding as error correction coding of the BCH code K ldpc of the scrambled data K bch after padding from the BCH encoder 22, and supplies the resulting LDPC code N ldpc to the shortening unit 24 To do.
- the parity bit of the LDPC code is obtained for the BCH code K ldpc of the post-padding scrambled data K bch , and the parity bit is converted into the BCH code K ldpc.
- the LDPC code N ldpc of the BCH code K ldpc is obtained for the BCH code K ldpc .
- the shortening unit 24 deletes the dummy data included in the LDPC code N ldpc from the LDPC encoder 23 and shortens the puncture of the parity bit of the LDPC code N ldpc .
- the shortened LDPC code N post is supplied to the QAM encoder 25.
- FIG. 10 is a block diagram illustrating a configuration example of a receiving apparatus that receives data from the transmitting apparatus in FIG. 8 that scrambles control data and transmits data.
- 10 is common to the receiving apparatus of FIG. 4 in that it includes an OFDM processing unit 31 or a control unit 49.
- the receiving apparatus in FIG. 10 is different from the receiving apparatus in FIG. 4 in that the descrambler 112 described in FIG. 7 is newly provided between the deleting unit 48 and the control unit 49.
- the QAM decoder 44 outputs the shortened LDPC code N post (FIG. 9) similarly to the receiving apparatus of FIG. 4, and the shortened LDPC code N post is the restoration unit. 45.
- the restoration unit 45 restores the LDPC code N ldpc (FIG. 9) before the shortening from the shortened LDPC code N post from the QAM decoder 44 and supplies the LDPC code N ldpc (FIG. 9) to the LDPC decoder 46.
- the scrambler 101 (FIG. 8), controlled data K sig is scrambled
- the padder 21 (FIG. 8)
- the control of the scrambled data K sig The padding scrambled data K bch is obtained by padding zero as dummy data with respect to (s) .
- the shortening unit 24 (FIG. 8), the dummy data itself included in the LDPC code N ldpc of the BCH code K ldpc of the post-padding scrambled data K bch is deleted, and the parity bit of the LDPC code N ldpc is punctured Due to the shortening, the LDPC code N ldpc is shortened to the LDPC code N post .
- the restoration of the original (before shortening) LDPC code N ldpc from the LDPC code N post subjected to such shortening is the same processing as that of the receiving apparatus in FIG. 4, that is, after shortening. This can be done by padding the LDPC code N post with the dummy data itself (and depuncturing the parity bits of the LDPC code).
- the LDPC decoder 46 performs LDPC decoding of the LDPC code N ldpc from the restoration unit 45, and supplies the BCH code K ldpc (FIG. 9) obtained as a result to the BCH decoder 47.
- the BCH decoder 47 performs BCH decoding of the BCH code K ldpc from the LDPC decoder 46 and supplies post-padding scrambled data K bch (FIG. 9) obtained as a result to the deletion unit 48.
- the deletion unit 48 deletes zero as dummy data padded in the post-padding scrambled data K bch and supplies the control data K sig (s) (FIG. 9) obtained as a result to the descrambler 112. To do.
- the descrambler 112 descrambles the scrambled control data K sig (s) from the deletion unit 48, obtains the original control data K sig , and supplies it to the control unit 49.
- the transmitter of FIG. 8 in order to improve the PAPR, as a target control data K sig, it performs scrambling, the control data K sig of scrambled (s), padding dummy data, scrambling BCH encoding and LDPC encoding as error correction encoding of post-padding scrambled data K bch padded with dummy data is performed on the subsequent control data K sig (s) , and obtained by the BCH encoding and LDPC encoding.
- the receiving apparatus FIG. 10 that receives data from such a transmitting apparatus performs control.
- FIG. 11 is a block diagram illustrating a third configuration example of a transmission apparatus that scrambles control data and transmits data.
- the transmission apparatus in FIG. 11 is common to the transmission apparatus in FIG. 1 in that it includes a mode adaptation / multiplexer 11 or an OFDM generation unit 28.
- the transmission apparatus of FIG. 11 is that the scrambler 101 and the replacement unit 121 described in FIGS. 5 and 8 are newly provided between the padder 21 and the BCH encoder 22. Different from the transmitting device.
- dummy data is padded into the control data in the padder 21, and the post-padding control data obtained as a result is supplied to the scrambler 101.
- the scrambler 101 scrambles the post-padding control data from the padder 21 and supplies the post-padding control data after the scramble to the replacement unit 121.
- the replacement unit 121 replaces the scrambled dummy data in the post-scrambled padding control data from the scrambler 101 with the dummy data itself, and supplies the replacement data obtained by the replacement to the BCH encoder 22. To do.
- FIG. 12 is a diagram for explaining processing of the padder 21, the scrambler 101, the replacement unit 121, the BCH encoder 22, the LDPC encoder 23, and the shortening unit 24 of FIG.
- the padder 21 is supplied with control data K sig having a predetermined length.
- the padder 21 pads the control data K sig supplied thereto with the required number of zeros as dummy data, and the padded control data K bch that is the control data after the padding is sent to the scrambler 101. Supply.
- the scrambler 101 scrambles the post-padding control data K bch from the padder 21, and supplies the post-padding control data K bch (s) after the scramble to the replacement unit 121.
- the replacement unit 121 replaces the scrambled dummy data in the post-scrambled padding control data K bch (s) from the scrambler 101 with zero that is the dummy data itself, and the replacement obtained by the replacement Data K bch (r) is supplied to the BCH encoder 22.
- the BCH encoder 22 performs BCH encoding as error correction encoding of the replacement data K bch (r) from the replacement unit 121, and supplies the resulting BCH code K ldpc to the LDPC encoder 23.
- the parity bits of a BCH code is determined, the parity bit, the replacement data K bch (r)
- the BCH code K ldpc of the replacement data K bch (r) is obtained.
- the LDPC encoder 23 performs LDPC coding as error correction coding of the BCH code K ldpc of the replacement data K bch (r) from the BCH encoder 22, and the resulting LDPC code N ldpc is sent to the shortening unit 24. Supply.
- the parity bit of the LDPC code is obtained for the BCH code K ldpc of the replacement data K bch (r) as in the case described with reference to FIG.
- LDPC code N ldpc of BCH code K ldpc is obtained.
- the shortening unit 24 deletes the dummy data included in the LDPC code N ldpc from the LDPC encoder 23 and shortens the puncture of the parity bit of the LDPC code N ldpc .
- the shortened LDPC code N post is supplied to the QAM encoder 25.
- FIG. 13 is a block diagram illustrating a configuration example of a receiving apparatus that scrambles control data and receives data from the transmitting apparatus in FIG. 11 that transmits data.
- the receiving apparatus in FIG. 13 is common to the receiving apparatus in FIG. 4 in that it includes an OFDM processing unit 31 or a control unit 49.
- the receiving apparatus of FIG. 13 is different from the receiving apparatus of FIG. 4 in that the descrambler 112 described in FIG. 7 and FIG. 10 is newly provided between the BCH decoder 47 and the deletion unit 48. .
- QAM decoder 44 As in the receiver of FIG. 4, and outputs an LDPC code N post after reduction (FIG. 12), the LDPC code N post after the shortening has restoring unit 45.
- the restoration unit 45 restores the LDPC code N ldpc (FIG. 12) before the shortening from the shortened LDPC code N post from the QAM decoder 44 and supplies it to the LDPC decoder 46.
- dummy data is padded to the control data K sig in the padder 21 (FIG. 11), and the padding is obtained in the scrambler 101 (FIG. 11).
- padding after control data K bch for it is scrambled after padding the scrambled control data K bch (s) is obtained.
- the replacement unit 121 replaces the scrambled dummy data included in the post-padding padding control data K bch (s) with the dummy data itself, and the replacement data K bch (r) obtained by the replacement.
- the LDPC code N ldpc is shortened to the LDPC code N post by deleting the dummy data itself contained in the LDPC code N ldpc of the BCH code K ldpc and shortening the parity bit puncture of the LDPC code N ldpc . Is done.
- the restoration of the original (before shortening) LDPC code N ldpc from the LDPC code N post subjected to such shortening is the same processing as that of the receiving apparatus in FIG. 4, that is, after shortening. This can be done by padding the LDPC code N post with dummy data itself.
- the LDPC decoder 46 performs LDPC decoding of the LDPC code N ldpc from the restoration unit 45, and supplies the BCH code K ldpc (FIG. 12) obtained as a result to the BCH decoder 47.
- the BCH decoder 47 performs BCH decoding of the BCH code K ldpc from the LDPC decoder 46 and supplies the replacement data K bch (r) (FIG. 12) obtained as a result to the descrambler 112.
- the descrambler 112 descrambles the replacement data K bch (r) from the BCH decoder 47, and the data obtained as a result, that is, control data in a state where the descrambled dummy data is padded (hereinafter, referred to as “control data”). (Also referred to as post-padding control data) is supplied to the deletion unit 48.
- the deletion unit 48 deletes the descrambled dummy data included in the post-padding control data from the descrambler 112, and supplies the control data K sig (FIG. 12) obtained as a result to the control unit 49.
- the replacement data K bch (r) (FIG. 12) supplied from the BCH decoder 47 to the descrambler 112 includes the dummy data itself padded by the restoration unit 45.
- the dummy data included in the replacement data K bch (r) becomes the descrambled dummy data.
- the descrambled dummy data is included in the post-padding control data obtained by descrambling the replacement data K bch (r) in the descrambler 112. That is, the post-padding control data obtained by descrambling the replacement data K bch (r) is data in a state in which the descrambled dummy data is padded to the control data.
- the position of the descrambled dummy data included in the post-padding control data obtained by descrambling the replacement data K bch (r) is included in the post-padding control data K bch in FIG. 13 is the same as the position of the dummy data itself. Therefore, the deletion unit 48 of the reception device in FIG. 13 performs the same processing as the deletion unit 48 of the reception device in FIG. The descrambled dummy data included in the control data can be deleted.
- the padding control data K bch that is the control data after padding is scrambled.
- the scrambled dummy data in the post-padding control data K bch (s) after scramble is replaced with dummy data, and the error correction coding of the replacement data K bch (r) obtained by the replacement is performed.
- the transmitting apparatus transmits data without scrambling the control data.
- the LDPC code N post after reduction, to restore the shortened before LDPC code N [iota] dpc ( Figure 9) Therefore, for example, using the receiving apparatus of FIG. 4 compliant with DVB-T.2, control data processing (demodulation) with improved PAPR can be easily performed.
- control unit 49 does not control data itself, but control data (padded control data) in which dummy data (descrambled) is padded. ), It is not necessary to provide the deletion unit 48, and the receiving apparatus can be made compact.
- FIG. 14 is a block diagram showing a configuration example of the scrambler 101 (FIGS. 5, 8, and 11).
- the scrambler 101 includes a register group 201 and EXOR circuits 202 and 203.
- the register group 201 includes, for example, 15 registers # 1 to # 15, and each register #i is latched in the preceding register # i-1 in synchronization with the data to be scrambled (each bit). Latch a bit.
- the output of the EXOR circuit 202 is supplied to the first (first) register # 1 of the register group 201, and the register # 1 latches the output of the EXOR circuit 202.
- the EXOR circuit 202 (first EXOR circuit) is, for example, the bit latched in the 14th register # 14 and the 15th register # 15 in the registers # 1 to # 15 of the register group 201.
- the exclusive OR with the other bits is calculated, and the calculation result is supplied to the first register # 1 of the register group 201 and the EXOR circuit 203.
- the EXOR circuit 203 In addition to the output of the EXOR circuit 202 (exclusive OR operation result of the bit latched in the 14th register # 14 and the bit latched in the 15th register # 15), the EXOR circuit 203 also scrambles The target data (control data (FIG. 8) or post-padding control data (FIG. 11)) is supplied.
- the target data control data (FIG. 8) or post-padding control data (FIG. 11)
- the EXOR circuit 203 calculates an exclusive OR of the output of the EXOR circuit 202 and the data to be scrambled, and outputs the calculation result as scrambled data.
- bits 1,0,0,1,0,1,0 are assigned to the first to fifteenth registers # 1 to # 15 of the register group 201. 1,0,0,0,0,0,0,0 are set respectively.
- each register #i except for the first register # 1 in the register group 201 latches the bit latched in the preceding register # i-1 in synchronization with the data to be scrambled.
- the first register # 1 of the register group 201 latches the output of the EXOR circuit 202.
- an exclusive OR of the bit latched in the 14th register # 14 and the bit latched in the 15th register # 15 is calculated, and an M sequence (which is obtained as a result of the calculation) is configured.
- an M sequence (which is obtained as a result of the calculation) is configured.
- the EXOR circuit 203 calculates the exclusive OR of the M series from the EXOR circuit 202 and the data to be scrambled to scramble the data to be scrambled and output the scrambled data.
- the descrambler 112 of the receiving device (FIGS. 7, 10, and 13) is configured in the same manner as the scrambler 101.
- FIG. 15 is a diagram showing a first example of a bit stream format of an OFDM signal transmitted by a transmission device compliant with the new standard for scrambling control data, that is, the transmission devices of FIG. 5, FIG. 8, and FIG. It is.
- bit stream of the OFDM signal transmitted by the transmission device compliant with the new standard is composed of new frames.
- a new frame is a frame that is a unit for transmitting data.
- a T2 frame defined in DVB-T.2, which is an existing standard, is adopted as the new frame. Has been.
- the new frame is configured by arranging a P1 symbol, a P2 symbol, and a data symbol (a symbol called Normal and a symbol called FC) in that order.
- the receiver that conforms to the new standard that processes the new frame uses a receiver conforming to DVB-T.2 (a fraction of the receiver that conforms to DVB-T.2). It can be configured by simply changing the specifications.
- S1 and S2 included in the P1 symbol which is a preamble arranged at the head of the T2 frame include frame identification information indicating that the frame is a T2 frame.
- S1 and S2 included in the P1 symbol of the frame include frame identification information indicating that the frame is a new frame.
- the receiving apparatus that receives the OFDM signal identifies whether the frame is a T2 frame or a new frame based on the frame identification information included in S1 and S2 included in the P1 symbol of the frame. be able to.
- FIG. 16 is a diagram showing a second example of the bit stream format of the OFDM signal transmitted by the transmission device compliant with the new standard for scrambling control data, that is, the transmission devices of FIG. 5, FIG. 8, and FIG. It is.
- the bit stream of the OFDM signal transmitted by the transmission device compliant with the new standard is composed of a T2 frame and a new frame.
- the new frame is multiplexed with the T2 frame specified in DVB-T.2 and transmitted.
- the transmission apparatus compliant with the new standard that is, the transmission apparatus in FIG. 5, FIG. 8, or FIG. 11, has the mode adaptation / multiplexer 11 or the OFDM generation unit 28 that constitutes the transmission apparatus in FIG. Therefore, a T2 frame defined in DVB-T.2 can be configured.
- a new frame and a T2 frame can be configured, and the new frame and the T2 frame can be multiplexed (time division) and transmitted.
- the T2 frame defined in DVB-T.2 can be adopted as the new frame.
- the P1 symbol (included in S1 and S2) of the T2 frame includes frame identification information indicating that the frame is the T2 frame
- the P1 symbol of the new frame includes the frame
- the receiving apparatus that receives the OFDM signal determines whether the frame is a T2 frame or not based on the frame identification information included in the P1 symbol of the frame. Can be identified.
- FIG. 17 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.
- the program can be recorded in advance in a hard disk 305 or ROM 303 as a recording medium built in the computer.
- the program can be stored (recorded) in a removable recording medium 311.
- a removable recording medium 311 can be provided as so-called package software.
- examples of the removable recording medium 311 include a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, and a semiconductor memory.
- the program can be installed in the computer from the removable recording medium 311 as described above, or can be downloaded to the computer via the communication network or the broadcast network and installed in the built-in hard disk 305. That is, the program is transferred from a download site to a computer wirelessly via a digital satellite broadcasting artificial satellite, or wired to a computer via a network such as a LAN (Local Area Network) or the Internet. be able to.
- a network such as a LAN (Local Area Network) or the Internet.
- the computer includes a CPU (Central Processing Unit) 302, and an input / output interface 310 is connected to the CPU 302 via the bus 301.
- a CPU Central Processing Unit
- an input / output interface 310 is connected to the CPU 302 via the bus 301.
- the CPU 302 executes a program stored in a ROM (Read Only Memory) 303 accordingly. .
- the CPU 302 loads a program stored in the hard disk 305 to a RAM (Random Access Memory) 304 and executes it.
- the CPU 302 performs processing according to the flowchart described above or processing performed by the configuration of the block diagram described above. Then, the CPU 302 causes the processing result to be output from the output unit 306 or transmitted from the communication unit 308 via the input / output interface 310, or recorded on the hard disk 305, for example, as necessary.
- the input unit 307 includes a keyboard, a mouse, a microphone, and the like.
- the output unit 306 includes an LCD (Liquid Crystal Display), a speaker, and the like.
- the processing performed by the computer according to the program does not necessarily have to be performed in chronological order in the order described as the flowchart. That is, the processing performed by the computer according to the program includes processing executed in parallel or individually (for example, parallel processing or object processing).
- the program may be processed by one computer (processor), or may be distributedly processed by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.
- the T2 frame format is adopted as the new frame format, but a format other than the T2 frame format can be adopted as the new frame.
- 11 mode adaptation / multiplexer 12 padder, 13 BB scrambler, 14 BCH encoder, 15 LDPC encoder, 16 bit interleaver, 17 QAM encoder, 18 hour interleaver, 19 SISO / MISO encoder, 20 frequency interleaver, 21 padder, 22 BCH encoder, 23 LDPC encoder, 24 shortening section, 25 QAM encoder, 26 frequency interleaver, 27 frame builder / resource allocation section, 28 OFDM generation section, 31 OFDM processing section, 32 frame management section, 33 frequency deinterleaver , 34 SISO / MISO decoder, 35 hour deinterleaver, 36 QAM decoder, 37 bit deinterleaver, 38 LDPC decoder , 39 BCH decoder, 40 BB descrambler, 41 null deletion unit, 42 demultiplexer, 43 frequency deinterleaver, 44 QAM decoder, 45 restoration unit, 46 LDPC decoder, 47 BCH decoder, 48 deletion unit, 49 control unit
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Abstract
Description
Claims (21)
- 復調を行うために必要な制御データに、ダミーデータをパディングするパディング手段と、
前記パディング後の制御データであるパディング後制御データを対象として、スクランブルを行うスクランブル手段と、
前記スクランブル後のパディング後制御データのうちの、スクランブルされているダミーデータを、前記ダミーデータに置換して、置換データを生成する置換手段と、
前記置換データの誤り訂正符号化を行う誤り訂正符号化手段と
を備えるデータ処理装置。 - 復調を行うために必要な制御データを対象として、スクランブルを行うスクランブル手段と、
前記スクランブル後の制御データに、ダミーデータをパディングするパディング手段と、
前記スクランブル後の制御データに、ダミーデータをパディングしたパディング後スクランブルデータの誤り訂正符号化を行う誤り訂正符号化手段と
を備えるデータ処理装置。 - 前記誤り訂正符号化手段は、前記誤り訂正符号化の対象のデータのパリティビットを求め、前記誤り訂正符号化の対象のデータに、前記パリティビットを付加したデータを、誤り訂正符号として求め、
前記誤り訂正符号に含まれる前記ダミーデータの削除、及び、前記誤り訂正符号のパリティビットのパンクチャである短縮化を行う短縮化手段をさらに備える
請求項1又は2に記載のデータ処理装置。 - 前記パディング手段は、パディング後のデータのデータ長が、前記誤り訂正符号化の対象となるデータ長になるように、前記ダミーデータをパディングする
請求項1又は2に記載のデータ処理装置。 - 前記スクランブル手段は、
シリーズに接続された15個のレジスタを有し、後段のレジスタが前段のレジスタにラッチされたビットをラッチするレジスタ群と、
14番目のレジスタにラッチされたビットと、15番目のレジスタにラッチされたビットとの排他的論理和を演算する第1のEXOR回路と、
前記第1のEXOR回路の出力と、スクランブル対象のデータとの排他的論理和を演算し、その演算結果を、スクランブル後のデータとして出力する第2のEXOR回路と
を有し、
前記レジスタ群の1番目のレジスタは、前記第1のEXOR回路の出力をラッチし、
前記レジスタ群の1ないし15番目のレジスタには、初期値として、ビット1,0,0,1,0,1,0,1,0,0,0,0,0,0,0が、それぞれセットされる
請求項1又は2に記載のデータ処理装置。 - 前記制御データは、
実データの復調を行うために必要な第1のデータ、
前記第1のデータの復調を行うために必要な第2のデータ、
又は、前記第1及び第2のデータの両方
である
請求項1又は2に記載のデータ処理装置。 - 前記誤り訂正符号化によって得られた誤り訂正符号を含むフレームである新フレームは、DVB-T.2に規定されたT2フレームと多重化されて送信される
請求項1又は2に記載のデータ処理装置。 - 前記T2フレーム、及び、新フレームの先頭には、プリアンブルが配置され、
前記T2フレームのプリアンブルは、前記T2フレームであることを表す情報を含み、
前記新フレームのプリアンブルは、前記新フレームであることを表す情報を含む
請求項1又は2に記載のデータ処理装置。 - 復調を行うために必要な制御データに、ダミーデータをパディングし、
前記パディング後の制御データであるパディング後制御データを対象として、スクランブルを行い、
前記スクランブル後のパディング後制御データのうちの、スクランブルされているダミーデータを、前記ダミーデータに置換して、置換データを生成し、
前記置換データの誤り訂正符号化を行う
ステップを含むデータ処理方法。 - 復調を行うために必要な制御データを対象として、スクランブルを行い、
前記スクランブル後の制御データに、ダミーデータをパディングし、
前記スクランブル後の制御データに、ダミーデータをパディングしたパディング後スクランブルデータの誤り訂正符号化を行う
ステップを含むデータ処理方法。 - 復調を行うために必要な制御データに、ダミーデータをパディングし、
前記パディング後の制御データであるパディング後制御データを対象として、スクランブルを行い、
前記スクランブル後のパディング後制御データのうちの、スクランブルされているダミーデータを、前記ダミーデータに置換して、置換データを生成し、
前記置換データの誤り訂正符号化を行う
送信装置で得られる誤り訂正符号を、前記置換データに復号する誤り訂正を行う誤り訂正手段と、
前記置換データを対象として、デスクランブルを行うデスクランブル手段と
を備えるデータ処理装置。 - 復調を行うために必要な制御データを対象として、スクランブルを行い、
前記スクランブル後の制御データに、ダミーデータをパディングし、
前記スクランブル後の制御データに、ダミーデータをパディングしたパディング後スクランブルデータの誤り訂正符号化を行う
送信装置で得られる誤り訂正符号を、前記パディング後スクランブルデータに復号する誤り訂正を行う誤り訂正手段と、
前記パディング後スクランブルデータのうちの、前記ダミーデータを削除し、前記スクランブル後の制御データを出力する削除手段と、
前記スクランブル後の制御データを対象として、デスクランブルを行うデスクランブル手段と
を備えるデータ処理装置。 - 前記送信装置は、前記誤り訂正符号化によって得られた誤り訂正符号に含まれる前記ダミーデータの削除、及び、前記誤り訂正符号のパリティビットのパンクチャである短縮化を行い、
前記送信装置で得られる短縮化後の誤り訂正符号に、前記ダミーデータをパディングし、パリティビットのデパンクチャを行うことにより、短縮化前の誤り訂正符号を復元する復元手段をさらに備える
請求項11又は12に記載のデータ処理装置。 - 前記デスクランブル後の置換データのうちの、デスクランブルされているダミーデータを削除する削除手段をさらに備える
請求項11に記載のデータ処理装置。 - 前記ダミーデータのパディングは、パディング後のデータのデータ長が、前記誤り訂正符号化の対象となるデータ長になるように行われる
請求項13に記載のデータ処理装置。 - 前記スクランブルは、
15個のレジスタを有し、後段のレジスタが前段のレジスタにラッチされたビットをラッチするレジスタ群と、
14番目のレジスタにラッチされたビットと、15番目のレジスタにラッチされたビットとの排他的論理和を演算する第1のEXOR回路と、
前記第1のEXOR回路の出力と、スクランブル対象のデータとの排他的論理和を演算し、その演算結果を、スクランブル後のデータとして出力する第2のEXOR回路と
を有し、
前記レジスタ群の1番目のレジスタは、前記第1のEXOR回路の出力をラッチし、
前記レジスタ群の1ないし15番目のレジスタには、初期値として、ビット1,0,0,1,0,1,0,1,0,0,0,0,0,0,0が、それぞれセットされる
スクランブル手段によって行われる
請求項13に記載のデータ処理装置。 - 前記制御データは、
実データの復調を行うために必要な第1のデータ、
前記第1のデータの復調を行うために必要な第2のデータ、
又は、前記第1及び第2のデータの両方
である
請求項13に記載のデータ処理装置。 - 前記誤り訂正符号化によって得られた誤り訂正符号を含むフレームである新フレームは、DVB-T.2に規定されたT2フレームと多重化されて送信される
請求項13に記載のデータ処理装置。 - 前記T2フレーム、及び、新フレームの先頭には、プリアンブルが配置され、
前記T2フレームのプリアンブルは、前記T2フレームであることを表す情報を含み、
前記新フレームのプリアンブルは、前記新フレームであることを表す情報を含む
請求項13に記載のデータ処理装置。 - 復調を行うために必要な制御データに、ダミーデータをパディングし、
前記パディング後の制御データであるパディング後制御データを対象として、スクランブルを行い、
前記スクランブル後のパディング後制御データのうちの、スクランブルされているダミーデータを、前記ダミーデータに置換して、置換データを生成し、
前記置換データの誤り訂正符号化を行う
送信装置で得られる誤り訂正符号を、前記置換データに復号する誤り訂正を行い、
前記置換データを対象として、デスクランブルを行う
ステップを含むデータ処理方法。 - 復調を行うために必要な制御データを対象として、スクランブルを行い、
前記スクランブル後の制御データに、ダミーデータをパディングし、
前記スクランブル後の制御データに、ダミーデータをパディングしたパディング後スクランブルデータの誤り訂正符号化を行う
送信装置で得られる誤り訂正符号を、前記パディング後スクランブルデータに復号する誤り訂正を行い、
前記パディング後スクランブルデータのうちの、前記ダミーデータを削除し、前記スクランブル後の制御データを出力し、
前記スクランブル後の制御データを対象として、デスクランブルを行う
ステップを含むデータ処理方法。
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US13/885,557 US9172497B2 (en) | 2010-11-22 | 2011-11-14 | Data processing device and data processing method |
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EP21189633.7A EP4002700A1 (en) | 2010-11-22 | 2011-11-14 | Device and method for removing dummy data and parity bits of concatenated bch/ldpc code |
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CN104518847A (zh) * | 2013-09-29 | 2015-04-15 | 中国科学院上海高等研究院 | 基于bch码与短ldpc码级联的信令编码方法及系统 |
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RU2790440C2 (ru) * | 2015-06-19 | 2023-02-21 | Панасоник Интеллекчуал Проперти Корпорэйшн оф Америка | Способ передачи, способ приема, устройство передачи и устройство приема |
Also Published As
Publication number | Publication date |
---|---|
EP2645579B1 (en) | 2018-09-05 |
HUE055929T2 (hu) | 2022-01-28 |
JP5648440B2 (ja) | 2015-01-07 |
RU2586857C2 (ru) | 2016-06-10 |
PL3429084T3 (pl) | 2021-12-20 |
EP2645579A4 (en) | 2014-09-17 |
RU2013122265A (ru) | 2014-11-20 |
US9172497B2 (en) | 2015-10-27 |
RU2016118156A3 (ja) | 2019-09-10 |
US20130246883A1 (en) | 2013-09-19 |
EP2645579A1 (en) | 2013-10-02 |
EP3429084B1 (en) | 2021-08-25 |
CN103339864A (zh) | 2013-10-02 |
RU2016118156A (ru) | 2018-10-26 |
ES2893450T3 (es) | 2022-02-09 |
EP3429084A1 (en) | 2019-01-16 |
JP2012114527A (ja) | 2012-06-14 |
CN107342772B (zh) | 2020-10-27 |
CN107342772A (zh) | 2017-11-10 |
EP4002700A1 (en) | 2022-05-25 |
CN103339864B (zh) | 2017-08-22 |
RU2715020C2 (ru) | 2020-02-21 |
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