WO2007068554A1

WO2007068554A1 - Serial concatenation scheme and its iterative decoding using an inner ldpc and an outer bch code

Info

Publication number: WO2007068554A1
Application number: PCT/EP2006/068661
Authority: WO
Inventors: Stefan Müller; Alexander Kravtchenko; Marten Kabutz
Original assignee: Thomson Holding Germany Gmbh & Co. Ohg
Priority date: 2005-12-12
Filing date: 2006-11-20
Publication date: 2007-06-21

Abstract

Disclosed is a method and apparatus for decoding (2) error correction coded data (12, 201), having a BCH decoder (211) and an LDPC decoder (205) connected in series (207). For improving the error correction performance, the BCH decoder (211) inputs reliability information, uses maximum-likelihood sequence estimation for decoding, and outputs modified reliability information, and the input (204, 209) of at least one of the BCH decoder (211) and the LDPC decoder (205) is connected to the output (207, 213) of the respective other decoder (205, 211), to receive the reliability information originating therefrom.

Description

SERIAL CONCATENATION SCHEME AND ITS ITERATIVE DECODING USING AN INNER LDPC AND AN OUTER BCH CODE

The present invention relates to soft decision decoding of error correction codes, Low Density Parity Check codes, to Chase Decoding, and to Bose-Chaudhuri-Hocquenghem codes.

Low Density Parity Check codes, also known as LDPC, are the most powerful codes today; they achieve a very good error correction performance at high code rates but they often suffer under so- called error floor at high signal to noise ratios. To eliminate the error floor it is common to use an algebraic code, like BCH code as an outer code, see for instance the specification of DVB-S2 as described in [ETSI TR 102 376] .

When designing a communication system, the use of soft decision decoding provides additional degrees of freedom. The additional information provided by soft decision in most instances can provide additional coding gain or error correction performance. Turbo Decoding as known from US 5,406,570 means to pass soft decisions or reliability information from one decoder to the input of the next decoder and to iterate through this process. As mentioned above, it is common to use LDPC code as inner code and BCH code as outer code.

Figure 1 shows a common encoding and decoding channel of the prior art. At the encoding side 1, data from a source 3 are outer coded 4 with a BCH code, the first resulting bitstream 11 is inner coded 5 with an LDPC code. The second resulting bitstream 12 is sent through the channel 6 and into the inner decoder 7, which performs LDPC decoding, e.g. using soft decoding. A hard decision 8 then converts the soft information 13 from LDPC decoding 7 into the hard bitstream 14, because the subsequent outer decoder 9 needs hard bits. The recovered data 15 is finally provided to the data sink 10. With other words, the BCH decoder 9 is fed with hard decided bits 14 derived from the LDPC decoder output 13, hence much of the soft information 13 available after LDPC decoding 7 gets lost. This is a disadvantage in the overall system.

The invention has recognised that turbo decoding principles could be applied if the outer BCH decoding 9 could be made to accept and produce soft information as well, and also that additional decoding gain is provided by performing the iterations according to the turbo decoding principle over the entire decoder configuration consisting of the inner and outer decoders connected in series. Accordingly, the problem to be solved is to improve an inner-outer error correcting scheme to that respect. An idea of the invention is, in a system where BCH decoding is to be performed in series with LDPC decoding, to implement the BCH decoder as a maximum-likelihood sequence estimator and to apply turbo decoding over the two concatenated codes. The result will be an additional coding gain. The problem is solved by the method according to independent claim 1 and the apparatus according to independent claim 4.

Using the so-called Chase or Weldon algorithms as known from CLARK et al . : "Error-Correction Coding for Digital Communications", New York, Plenum Press, 1981, it is possible to implement a BCH decoder as a soft-in soft-out or SISO decoder which receives and provides soft information, i.e. an information encompassing reliability information about data elements. A SISO BCH decoder enables to pass soft information from the BCH decoder to the LDPC decoder and vice versa. More specifically, in a decoder according to the invention, soft information from the output of a SISO LDPC decoder is passed to the input of a SISO BCH decoder, and/or soft information from the output of the SISO BCH decoder is passed to the input of the SISO LDPC decoder.

According to the invention, a method for decoding error correction coded data has a BCH decoding step and an LDPC decoding step, which two steps are being performed sequentially. For improving the decoding gain or error correction performance, specifically, the BCH decoding step is performed using maximum- likelihood sequence estimation, and in at least one of the BCH decoding step and the LDPC decoding step, soft information or reliability information originating from the respective other one of the BCH decoding step and the LDPC decoding step is used. The corresponding apparatus has a BCH decoder and an LDPC decoder connected in series, and specifically the BCH decoder is equipped and configured to input reliability information, to use maximum-likelihood sequence estimation for decoding, and to output reliability information. Additionally, the input of at least one of the BCH decoder and the LDPC decoder is connected to the output of the respective other decoder, to receive soft information originating therefrom. This has the advantage that reliability information is not being discarded and error correction performance is increased.

Advantageously, both of the BCH decoding step and the LDPC decoding step use soft information from the respective other step, and both steps together are being repeatedly performed in turbo decoding iterations. In the corresponding apparatus, the inputs of both the BCH decoder and the LDPC decoder are connected to the output of the respective other decoder, and the BCH decoder and the LDPC decoder are equipped and configured to pass the soft information to the respective other decoder more than once in turbo decoding iterations. This has the advantage of increasing the performance further.

Advantageously, the BCH decoding step employs one of the Chase algorithm and the Weldon algorithm. In the corresponding apparatus, the BCH decoder is equipped and configured to employ one of the Chase algorithm and the Weldon algorithm. This has the advantage of being a well-understood method to enable BCH decoding based on soft-input and soft-output. The invention is explained and illustrated by the following description of example embodiments, and in the Figures, where

- Figure 1 shows a general encoding and decoding channel of the state of the art; - Figure 2 shows the decoder architecture according to the invention;

- Figure 3 shows a comparison of error correction performance curves of LDPC + BCH decoding schemes; and

- Figure 4 shows simulations of error correction performance curves for different LDPC + BCH decoding schemes.

Figure 2 shows the decoder architecture according to the invention. Therein, a first decoder 215, which is an LDPC decoder plus some arithmetic stages 204, 206, is connected to a second decoder 216, which has corresponding arithmetic stages

209, 212. The signals 201, 207, 208, 210, 213, 214 at the input and output of blocks all are log-likelihood-ratios LLR. An LLR is commonly denoted as L (CC) , where CC is the conditional probability that a bit x=0 was sent when a symbol y is being received. L(OC) is then defined as the natural logarithm of the quotient of that conditional probability with the complementary probability that a bit x=l was sent:

With P between 0 and 1, L (CC) is between ±∞. Whenever P (x=0/y) is greater than P (x=l/y) , the quotient is greater than 1, hence the

In is positive; when P (x=l/y) is greater, the In is negative.

Therefore the binary representation or the result of a binary decision from the continuous-valued quantity L can directly be derived from the sign of the LLR value L, and the magnitude or absolute value of the LLR value L represents the reliability of the decision, because it can be interpreted as the distance to the decision threshold. In Fig. 2, a so-called extrinsic information Le, which is provided by the decoder based on the received sequence and the a-priori information excluding the received systematic bit, is nominally input or initalised 202 as Le=O. In this case, the log-likelihood value Li, also called intrinsic information, at the input of the SISO LDPC decoder 205 results as the unchanged LLR value of the channel Lc 201. In later iteration stages, by means of a switch 203, a third extrinsic information value 213 derived from the output of the SISO BCH Decoder 211 is provided as a feedback value and used at the input of the first decoder 215, instead. The second input of the first decoder 215 is the log-likelihood-ratio Lc, which comes from the channel decoder and is the a-priori information about a bit known before decoding starts. From the extrinsic information Le and the a-priori information 201, the input proper of the LDPC decoder 205 is derived by addition 204. With other words: In the later iteration stages, the intrinsic information Li at the input of the SISO LDPC decoder 205 results as the sum of the feedback value 213 and the a-priori information Lc 201. At the output of the first decoder 215, two quantities are provided: a second extrinsic information 207, here also designated as Le, and an a- posteriori information L 208, which constitutes the information that the decoder gives, taking into account all available sources of information about the received bit.

The second extrinsic information 207 as well as the a-priori information Lc 201 from the overall input are input to the second decoder 216 containing a Soft-in Soft-out BCH decoder 211. At the output of the second decoder 216, two quantities are provided: a third extrinsic information 213, here also designated as Le, and a second a-posteriori information L 214, which serves as the final LLR for a subsequent hard decision not shown in Fig. 2. For both decoders 215, 216, the quantity Li at their respective input is subtracted from the quantity L at the output of the respective decoder 205, 211, to obtain the respective second or third extrinsic information Le 207, 213. A decoder architecture as shown in Fig. 2 additionally enables for a flexible error correction system. Figure 3 qualitatively shows the error correction performance of such architectures. The performance for a conventional error correcting system, as shown in Fig 1 and based on hard decisions after LDPC decoding, is shown in curve 1. Curve 2 shows the performance of a decoder according to the invention which uses the soft-output from the inner LDPC decoder 205 in the outer BCH decoder 211 implemented as a maximum likelihood detector. The fact that, for all SNR values except very small ones, curve 2 is underneath curve 1 symbolises the improvement in bit error rate BER achieved by not discarding the soft information from the inner decoder. Curve 3, finally, shows one example of the performance of the configuration of the two SISO decoders being used iteratively. The arrow 301 symbolises that with increasing number of iterations, the performance is increased further, equivalent to a further decrease of BER over SNR.

Fig. 4 shows quantitative simulations of error correction performance for the case of no error correction being performed, shown in curve 401, as well as for two types of BCH codes being for the outer protection, namely a BCH (63, 57, 3) code as shown in curves 402 and 404; and a BCH (127, 120, 3) code as shown in curves 403 and 405. For both these codes, error correction performance with hard BCH decoding, corresponding to the approach of Fig. 1, is shown in curves 402 and 403, respectively; and error correction performance for a scheme using Chase type BCH decoding is shown in curves 404 and 405, respectively. These simulation results show that the coding gain achieved by using and not discarding the soft information in the BCH decoder is approximately 1 dB at a constant bit error rate BER. This corresponds to the transition from curve 1 to curve 2 in Fig. 3. An advantage of the invention is an increased coding gain. The invention is also applicable to every communication system where LDPC and BCH codes are used.

Claims

1. A method for decoding (2) error correction coded data (12, 201), having a BCH decoding step (9, 211) and an LDPC decoding step (7, 205) being performed sequentially (207), characterized by

- the BCH decoding step (211) being performed using maximum- likelihood sequence estimation, and by having a step of

- using, in at least one of the BCH decoding step and the LDPC decoding step, soft information originating from the respective other one of the BCH decoding step and the LDPC decoding step.

2. The method of claim 1, where both of the BCH decoding step (211) and the LDPC decoding step (205) use soft information from the respective other step, and where the BCH decoding step (211) and the LDPC decoding step (205) are, both together, being repeatedly performed in turbo decoding iterations (207, 213, 301) .

3. The method of claim 1 or claim 2, where the BCH decoding step (211) employs one of the Chase algorithm and the Weldon algorithm.

4. An apparatus for decoding (2) error correction coded data

(12, 201), having a BCH decoder (9, 211) and an LDPC decoder (7, 205) connected in series (207), characterized in that

- the BCH decoder (211) is equipped and configured to input reliability information, to use maximum-likelihood sequence estimation for decoding, and to output reliability information; and in that

- the input (204, 209) of at least one of the BCH decoder (211) and the LDPC decoder (205) is connected to the output (207, 213) of the respective other one of the BCH decoder (211) and the LDPC decoder (205), to receive soft information originating therefrom.

5. The apparatus of claim 4, where the inputs of both the BCH decoder (211) and the LDPC decoder (205) are connected to the output of the respective other one of the BCH decoder and the LDPC decoder, and where the BCH decoder (211) and the LDPC decoder (205) are equipped and configured to pass the soft information to the respective other decoder more than once in turbo decoding iterations (207, 213, 301) .

6. The apparatus of claim 4 or claim 5, where the BCH decoder (211) is equipped and configured to employ one of the Chase algorithm and the Weldon algorithm.