WO2012066892A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a semiconductor device used for high-power switching and a manufacturing method thereof, and more particularly to a semiconductor device using a GaN-based semiconductor among nitride semiconductors and a manufacturing method thereof.
- a high current switching element is required to have a high reverse breakdown voltage and a low on-resistance.
- a field effect transistor (FET: Field Effect Transistor) using a group III nitride semiconductor is excellent in terms of high breakdown voltage, high temperature operation and the like because of its large band gap. For this reason, vertical transistors using GaN-based semiconductors are attracting attention as high-power control transistors.
- FET Field Effect Transistor
- 2DEG 2 Dimensional Electron Gas
- the breakdown voltage performance may be improved by the depletion layer formed at the pn junction between the p-type GaN barrier layer and the n ⁇ -type GaN drift layer.
- the opening penetrates through the p-type GaN barrier layer and reaches the n ⁇ -type GaN drift layer. Therefore, the gate electrode G faces the drain electrode without interposing the p-type GaN barrier layer.
- a voltage of several hundred volts to several hundred hundred volts is applied between the source electrode (ground) and the drain electrode in the off operation. During the off operation, a voltage of about minus several volts is applied to the gate electrode.
- An object of the present invention is to provide a semiconductor device with improved breakdown voltage performance during off operation and a method of manufacturing the same in a vertical semiconductor device provided with an opening and having a channel and a gate electrode in the opening. .
- the semiconductor device of the present invention is a vertical semiconductor device including a GaN-based stacked body provided with an opening.
- the GaN-based stacked body has an n-type GaN-based drift layer / p-type GaN-based barrier layer / n-type GaN-based contact layer sequentially toward the surface layer side, and the opening portion extends from the surface layer to the n-type GaN. It reaches even within the system drift layer.
- a regrowth layer including an electron transit layer and an electron supply layer, and a source electrode in contact with the regrowth layer, the n-type GaN-based contact layer, and the p-type GaN-based barrier layer, so as to cover the wall surface and bottom of the opening; And a gate electrode positioned on the regrowth layer in the opening, and a bottom insulating film positioned below the gate electrode and limited to the bottom of the opening.
- a source electrode on one main surface (the surface of a GaN-based semiconductor layer) and a drain electrode facing the source electrode with the GaN-based semiconductor layer sandwiched between several hundred volts to A high voltage of thousands of volts is applied.
- the source electrode is fixed at the ground potential, and a high voltage is applied to the drain electrode.
- the gate electrode is held at minus several volts, for example, ⁇ 5 V when it is turned off to open and close the channel. That is, the gate electrode holds the lowest potential during the off operation.
- the distance between the gate electrode and the drain electrode is smaller than the distance between the source electrode and the drain electrode, and during the off operation, the distance between the drain electrode and the gate electrode is higher by ⁇ 5V. Voltage is applied.
- the gate electrode is in contact with the semiconductor layer and constitutes a metal part having a Schottky structure.
- the bottom insulating film is disposed at the bottom of the opening, and the bottom insulating film includes the gate electrode of the lowest potential holding portion and the n-type GaN-based drift layer in a portion in contact with the bottom of the opening. Intervene in between. For this reason, the distance between the gate electrode and the n-type GaN-based drift layer is surely increased by the thickness of the insulating film.
- the convex portion of the gate electrode that is fitted inside the corner portion of the opening portion is separated from the corner portion.
- the Schottky structure formed by the gate electrode in the conventional device as described above is changed to a MIS (Metal Insulator Semiconductor) structure in the present invention.
- MIS Metal Insulator Semiconductor
- the electric field concentration generated in the n-type GaN-based drift layer that is in contact with the outside of the corner is alleviated.
- the n-type GaN-based drift layer at that location is less likely to break.
- the concentration of the impurity conductivity type n-type or p-type is not limited, but includes the entire range from low concentration to high concentration.
- the bottom insulating film can be located on the regrowth layer covering the bottom of the opening.
- the bottom and the wall of the opening are continuously covered with the regrowth layer, so that there are no irregular irregularities that occur accidentally at the corners and the like, eliminating the form factor that locally promotes electric field concentration. be able to.
- the manufacturing process can be simplified by disposing the bottom insulating film on the regrowth layer that continuously covers the bottom and the wall surface of the opening.
- the regrowth layer terminates with an n-type GaN-based drift layer that covers the wall surface of the opening and forms the bottom of the opening, and the bottom insulating film covers the n-type GaN-based drift layer located at the bottom of the opening Can be located.
- the bottom of the opening has a simple structure of metal (gate electrode) / bottom insulating film / n-type GaN-based drift layer, and a preferable structure can be obtained in terms of pressure resistance.
- An insulating layer located below the gate electrode and on the regrowth layer may be provided at least on the wall surface of the opening.
- an insulating layer By disposing an insulating layer on the channel under the gate electrode, a gate leakage current when a positive voltage is applied to the gate can be suppressed, so that a large current operation is facilitated. Further, since the threshold voltage can be shifted in the positive direction, it is easy to obtain normally-off.
- the insulating layer can extend continuously above or below the bottom insulating film located at the bottom of the opening. In this case, the thickness of the insulating layer and the bottom insulating film can be increased at the bottom, and the distance between the gate electrode of the lowest potential holding portion and the n ⁇ -type GaN drift layer can be further increased when turned off. As a result, the electric field concentration in the portion of the n ⁇ -type GaN drift layer in contact with the corner can be further relaxed.
- the insulating film also serves as the bottom insulating film continuously from the wall surface of the opening.
- the semiconductor device manufacturing method of the present invention is a vertical GaN-based semiconductor device manufacturing method.
- This manufacturing method includes a step of forming a p-type GaN-based barrier layer on the n-type GaN-based drift layer, a step of forming an n-type GaN-based contact layer on the p-type GaN-based barrier layer, and etching from the surface layer.
- a step of forming an opening reaching the n-type GaN-based drift layer a step of epitaxially growing a regrowth layer including an electron transit layer and an electron supply layer so as to cover a wall surface and a bottom of the opening, and a bottom of the opening
- a step of forming a bottom insulating film a step of forming a gate electrode on the bottom insulating film.
- the bottom insulating film is formed so that the n-type GaN drift layer near the corner of the opening is easily formed. Electric field concentration can be reduced.
- the regrowth layer is formed up to the n-type GaN-based drift layer forming the bottom of the opening on the wall surface of the opening, or the regrowth located at the bottom of the opening
- the layer can be removed by etching, and then the bottom insulating film can be formed so as to cover the n-type GaN-based drift layer exposed at the bottom of the opening in the manufacturing process of the bottom insulating film.
- the regrowth layer can be formed so as to cover the wall surface and the bottom of the opening, and in the bottom insulating film forming step, the bottom insulating film can be formed on the regrowth layer. .
- a step of forming an insulating layer may be provided before the gate electrode forming step and after or before the bottom insulating film forming step so as to be positioned below the gate electrode at least on the wall surface of the opening.
- the withstand voltage performance at the time of off operation can be improved.
- FIG. 1 is a cross-sectional view showing a vertical GaN-based FET (semiconductor device) in Embodiment 1 of the present invention (cross-sectional view taken along the line II in FIG. 2).
- FIG. 2 is a plan view of the vertical GaN-based FET of FIG. 1. It is a figure which shows the manufacturing method of the vertical GaN-type FET of FIG. 1, and shows the state which formed the epitaxial laminated body to a contact layer in the board
- FIG. 6 is a cross-sectional view of a semiconductor device belonging to the first embodiment of the present invention, showing a modification of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the vertical GaN-type FET (semiconductor device) in Embodiment 2 of this invention.
- GaN substrate 4 n ⁇ type GaN drift layer, 6 p type GaN barrier layer, 7 n + type GaN contact layer, 9 insulating layer, 10 semiconductor device (vertical GaN-based FET), 12 gate wiring, 13 gate pad, 15 GaN-based laminated body, 22 GaN electron transit layer, 26 AlGaN electron supply layer, 27 regrowth layer, 28 opening, 28a wall surface of opening, 28b bottom of opening, 37 bottom insulating film, D drain electrode, G gate Electrode, K edge line or corner of opening, M1 resist pattern, S source electrode.
- semiconductor device vertical GaN-based FET
- 12 gate wiring 13 gate pad
- 15 GaN-based laminated body 22 GaN electron transit layer, 26 AlGaN electron supply layer, 27 regrowth layer, 28 opening, 28a wall surface of opening, 28b bottom of opening, 37 bottom insulating film, D drain electrode, G gate Electrode, K edge line or corner of opening, M1 resist pattern, S source electrode.
- FIG. 1 is a cross-sectional view of a vertical GaN-based FET (semiconductor device) 10 according to the first embodiment of the present invention.
- the vertical GaN-based FET 10 includes a conductive GaN substrate 1 and an n ⁇ -type GaN drift layer 4 / p-type GaN barrier layer 6 / n + -type GaN contact layer 7 grown epitaxially thereon.
- This n ⁇ -type GaN drift layer 4 / p-type GaN barrier layer 6 / n + -type GaN contact layer 7 forms a continuously formed GaN-based laminate 15.
- a buffer layer made of an AlGaN layer or a GaN layer may be inserted between the GaN substrate 1 and the n ⁇ -type GaN drift layer 4.
- the GaN substrate 1 may be a so-called thick GaN substrate, or a substrate having a GaN layer in ohmic contact with a support base. Furthermore, it is formed on a GaN substrate or the like during the growth of the GaN-based laminate, and in the subsequent process, except for a predetermined thickness portion such as the GaN substrate, only a thin GaN layer base remains in the product state. There may be.
- GaN substrates substrates having a GaN layer in ohmic contact with the support base, and underlying GaN layers left thin on the product may be simply referred to as GaN substrates.
- the thin underlying GaN layer may be conductive or non-conductive, and the drain electrode can be provided on the front or back surface of the thin GaN layer depending on the manufacturing process and the structure of the product.
- the supporting base or the substrate may be conductive or non-conductive.
- the drain electrode can be directly provided on the back surface (lower) or front surface (upper) of the supporting base or substrate.
- a drain electrode can be provided on the non-conductive substrate and on the conductive layer located on the lower layer side in the semiconductor layer.
- the p-type GaN barrier layer is the p-type GaN barrier layer 6 in the present embodiment, but a p-type AlGaN layer may be used.
- the GaN layer described above may be used as another GaN-based semiconductor layer depending on the case.
- the GaN-based layered body 15, through the n + -type GaN contact layer 7 to the p-type GaN barrier layer 6 n - opening 28 leading to the -type GaN drift layer 4 is provided.
- the opening portion 28 has a wall surface (side surface) 28a and a bottom portion 28b exposed.
- An epitaxially grown regrowth layer 27 is formed so as to cover the wall surface 28a and bottom 28b of the opening 28 and the surface layer (n + -type GaN contact layer 7) of the GaN-based stacked body 15.
- the regrowth layer 27 includes an i (intrinsic) type GaN electron transit layer 22 and an AlGaN electron supply layer 26.
- An intermediate layer such as AlN may be inserted between the i-type GaN electron transit layer 22 and the AlGaN electron supply layer 26.
- the source electrode S is electrically connected to the regrowth layer 27, the n + -type contact layer 7, and the p-type GaN barrier layer. In FIG. 1, the source electrode S extends downward, contacts the regrowth layer 27 and the n + -type contact layer 7 on its side surface, and contacts the p-type GaN contact layer 7 on its tip to electrically Connected.
- the drain electrode D is located on the back surface of the GaN substrate 1.
- the insulating layer 9 is located under the gate electrode G so as to cover the regrowth layer 27.
- the insulating layer 9 is arranged to suppress a gate leakage current when a positive voltage is applied to the gate electrode, and facilitates a large current operation. Further, since the threshold voltage can be shifted in the positive direction, it is easy to obtain normally-off. However, the insulating layer 9 may be omitted and is not essential.
- a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is generated at the inner interface of the regrowth layer 27 between the AlGaN electron supply layer 26 and the i-type GaN electron transit layer 22.
- a two-dimensional electron gas is generated at the interface on the AlGaN layer side in the i-type GaN electron transit layer 22 due to natural polarization, piezo polarization, or the like due to the difference in lattice constant.
- the electrons to be switched take a path from the source electrode S through the two-dimensional electron gas to the n ⁇ -type GaN drift layer 4 to the drain electrode D.
- the impurity level and the like at the interface between them are kept low. For this reason, it is possible to flow a large current (per area) with a low on-resistance while providing the opening 28 and flowing a large current in the thickness direction.
- a feature of the present embodiment is the bottom insulating film 37 located at the bottom 28 b of the opening 28.
- the n ⁇ -type GaN drift layer 4 near the bottom of the opening and the gate electrode G are spaced apart.
- the gate electrode G is reliably separated from the n ⁇ -type GaN drift layer 4 in contact with the ridgeline or corner K where the bottom 28b of the opening intersects with the wall 28a from the outside, and the gate electrode G.
- the MIS structure in which the bottom insulating film 37 is interposed therebetween It has become.
- the gate electrode G As described above, during the off operation, a high voltage of several hundred volts to thousands of volts is applied between the source electrode S and the drain electrode D held at the ground potential. Further, the gate electrode is held at minus several volts, for example, ⁇ 5 V when it is turned off to open and close the channel. During the off operation, the gate electrode holds the lowest potential. In a structure in which the gate electrode G continuously covers the bottom 28b and the wall surface 28a of the opening 28 without a gap as in the conventional semiconductor device, the n ⁇ -type GaN in the portion in contact with the corner K under the boundary condition of the potential described above. A large electric field concentration occurs in the drift layer 4.
- the gate electrode has a convex portion that fits into the corner portion K from the inside.
- the lines of electric force flow at a high density with the cross-section narrowed from the outside to the inside of the corner K.
- the convex portion fitted from the inside of the corner portion should be fitted from the inside to the regrowth layer covering the corner portion K, but the thickness of the regrowth layer is small and the difference is small, so that If there is no significant influence, it will be explained without making a strict distinction.
- a large electric field concentration occurs in the n-type GaN-based drift layer 4 in contact with the convex portion that holds the lowest potential of the gate electrode G.
- the p-type GaN barrier layer 6 in this part may be destroyed by this electric field concentration.
- the gate electrode G of the semiconductor device 10 of the present embodiment is separated from the n ⁇ -type GaN drift layer 4 in contact with the bottom portion 28 b of the opening 28 by a bottom insulating film 37 by a predetermined distance.
- the gate electrode G does not have a portion that fits into the corner K of the opening 28 from the inside.
- the thickness of the bottom insulating film 37 is desirably three times or more the thickness of the regrowth layer 27 (22, 26), more preferably five times or more. Since the thickness of the regrowth layer 27 is at most about 0.3 ⁇ m, the thickness of the bottom insulating film 37 is preferably 0.9 ⁇ m (3 times) or more, and more preferably 1.5 ⁇ m (5 times) or more. .
- Al 2 O 3 , SiO 2 , SiN, NiO, Sc 2 O 3 or the like can be used.
- the p-type impurity concentration of the p-type GaN barrier layer 6 is preferably about 1 ⁇ 10 17 (1E17) cm ⁇ 3 to 1 ⁇ 10 19 (1E19) cm ⁇ 3 .
- an impurity that forms an acceptor in a GaN-based semiconductor such as Mg is used as the p-type impurity.
- the thickness of the p-type GaN barrier layer 6 varies depending on the thickness of the n ⁇ -type GaN drift layer and the like. For this reason, the thickness range cannot be determined unconditionally. However, a typical thickness can be about 0.3 ⁇ m to 1 ⁇ m in view of the thickness used in many specifications.
- the p-type GaN barrier layer 6 has a thickness of about 0.3 ⁇ m to 1 ⁇ m, if the Mg concentration is too high, the p-type GaN barrier layer 6 moves linearly toward the end face of the p-type GaN barrier layer 6. Adversely affect the channel. In addition, the reverse characteristics (breakdown voltage performance) at the pn junction with the n ⁇ -type GaN drift layer when the channel is OFF are deteriorated.
- the thickness of the n + -type GaN contact layer 7 is preferably set to about 0.1 [mu] m ⁇ 0.6 .mu.m.
- the length of the n + -type GaN contact layer 7 is preferably 5 ⁇ m or less.
- FIG. 2 is a plan view of the vertical GaN-based semiconductor device 10 shown in FIG. 1, and FIG. 1 is a cross-sectional view taken along the line II in FIG.
- the opening 28 and the gate electrode G are hexagonal, and the periphery thereof is covered with the source electrode S while avoiding the gate wiring 12, so as to form the closest packing (honeycomb structure).
- the perimeter of the gate electrode per unit area can be increased.
- the on-resistance can also be lowered from the surface of such a shape.
- the source structure including the source electrode S can have a low electric resistance and a high mobility suitable for a high-power element.
- the above hexagonal honeycomb structure can be formed in a bowl shape, and even by arranging the bowl-shaped openings densely, the opening perimeter per area can be increased, and as a result, the current density can be improved. it can.
- a method for manufacturing the semiconductor device 10 in the present embodiment will be described.
- a stacked body 15 of n ⁇ -type GaN drift layer 4 / p-type GaN barrier layer 6 / n + -type GaN contact layer 7 is grown on the GaN substrate 1 having the above meaning.
- a GaN buffer layer (not shown) may be inserted between the GaN substrate 1 and the n ⁇ -type GaN drift layer 4.
- MOCVD metal organic chemical vapor deposition
- the GaN substrate 1 when a gallium nitride film is grown on the conductive substrate by the MOCVD method, trimethylgallium is used as a gallium source.
- High purity ammonia is used as the nitrogen raw material.
- Purified hydrogen is used as the carrier gas.
- the purity of high purity ammonia is 99.999% or more, and the purity of purified hydrogen is 99.999995% or more.
- a conductive GaN substrate having a diameter of 2 inches is used as the conductive substrate.
- the formation of the GaN layer on the conductive substrate is a common method not only for the formation of the GaN substrate 1 but also for the growth of the stacked body 15 on the GaN substrate 1.
- the n ⁇ -type GaN layer drift layer 4 / p-type GaN barrier layer 6 / n + -type GaN contact layer 7 are grown on the GaN substrate 1 in this order.
- the opening 28 is formed by RIE (reactive ion etching).
- RIE reactive ion etching
- FIGS. 5A and 5B after a resist pattern M1 is formed on the surfaces of the epitaxial layers 4, 6, and 7, the opening is widened while the resist pattern M1 is etched back by RIE to widen the opening. .
- the slope of the opening 28, that is, the end face of the laminate 15 is damaged by being irradiated with ions. In the damaged portion, a dangling bond, a high density region of lattice defects, and the like are generated, and conductive impurities from the RIE apparatus or from a portion that cannot be specified reach the damaged portion to cause enrichment.
- the occurrence of the damaged portion causes an increase in drain leakage current and needs to be repaired.
- hydrogen and ammonia at a predetermined level, it is possible to obtain dangling bond repair, removal of impurities, and inactivation when the regrowth layer 27 described later is grown.
- the wafer is introduced into an MOCVD apparatus, and as shown in FIG. 6, an electron transit layer 22 made of undoped GaN and an electron supply layer 26 made of undoped AlGaN.
- a regrowth layer 27 containing GaN is grown.
- thermal cleaning is performed in an (NH 3 + H 2 ) atmosphere, and then an organometallic raw material is supplied while introducing (NH 3 + H 2 ).
- restoration of the damaged portion, removal of conductive impurities, and passivation are performed.
- the wafer is taken out of the MOCVD apparatus, and a bottom insulating film 37 is grown using a resist pattern (not shown) having an opening at the bottom of the opening, as shown in FIG.
- a resist pattern not shown
- the source electrode S is formed on the surface of the epitaxial layer and the drain electrode D is formed on the back surface of the GaN-based substrate 1 as shown in FIG.
- FIG. 8 shows a semiconductor device 10 according to the embodiment of the present invention, which is a modification of the first embodiment.
- the insulating layer 9 is disposed under the gate electrode G.
- the distance between the gate electrode G and the n ⁇ -type GaN drift layer 4 is increased, and the n ⁇ -type GaN drift in the portion in contact with the corner K is further increased. Electric field concentration in the layer 4 can be reduced.
- the thickness of the insulating layer 9 is preferably about 0.05 ⁇ m to 0.3 ⁇ m.
- Al 2 O 3 , SiO 2 , SiN, NiO, Sc 2 O 3 or the like can be used. Note that the insulating layer 9 may be positioned on the regrowth layer 27 under the bottom insulating film 37.
- FIG. 9 is a sectional view of a vertical GaN-based FET (semiconductor device) 10 according to the second embodiment of the present invention.
- the GaN-based stacked body 15 is formed of the n ⁇ -type GaN drift layer 4 / p-type GaN barrier layer 6 / n + -type GaN contact layer 7, and the opening 28 reaches the n ⁇ -type GaN drift layer 4 from the surface layer.
- the provided points are the same as those in the first embodiment.
- the characteristics of the semiconductor device 10 of the present embodiment are as follows. (1) A bottom insulating film 37 is provided on the bottom 28 b of the opening 28. This is the same as the semiconductor device of FIG.
- No regrowth layer is disposed at the bottom 28 b of the opening 28, and the regrowth layer 27 terminates at a location that hits the bottom along the wall surface of the opening 28.
- the feature (2) above does not cause an essential difference from the semiconductor device of the first embodiment.
- the bottom insulating film 37 cooperates with the insulating film 9 to determine the distance between the n ⁇ -type GaN drift layer 4 in contact with the corner K of the opening 28 and the gate electrode G that is the lowest potential holding portion. Enlarge. As a result, similarly to the first embodiment, the electric field concentration at the corner K in the n ⁇ -type GaN drift layer 4 can be reduced.
- the effect of the insulating layer 9 positioned below the gate electrode is the same as that of the first embodiment. That is, by disposing an insulating layer on the channel under the gate electrode, a gate leakage current when a positive voltage is applied to the gate can be suppressed, so that a large current operation is facilitated. Further, since the threshold voltage can be shifted in the positive direction, it is easy to obtain normally-off.
- the insulating layer 9 in FIG. 9 passes over the bottom insulating film 37, it can also pass under the bottom insulating film 37.
- the action of the insulating films 37 and 9 at the bottom 28b of the opening 28 does not depend on the stacking order at the bottom. Furthermore, the insulating layer 9 is not essential, and the above-described action can be obtained as long as it is present.
- the semiconductor device or the like of the present invention in a vertical semiconductor device having an opening, by disposing an insulating film only at the bottom of the opening, the withstand voltage performance at the time of off can be improved. Since the low on-resistance obtained by forming the two-dimensional electron gas in the thickness direction along the wall surface of the opening and the high body pressure performance are combined, it can be used for a large current switching element.
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Abstract
Description
本発明は、開口部が設けられ、当該開口部にチャネルおよびゲート電極を備える縦型半導体装置において、オフ動作時の耐圧性能を向上させた半導体装置およびその製造方法を提供することを目的とする。
上記の構成によれば、開口部の底部に底部絶縁膜が配置され、その底部絶縁膜が、最低電位保持部のゲート電極と、開口部の底部に接する部分のn型GaN系ドリフト層との間に介在する。このため、ゲート電極とn型GaN系ドリフト層との間の距離は、確実に、絶縁膜の厚み分だけ大きくなる。従来の形態では、とくに開口部の角部の内側に嵌合していたゲート電極の凸部は、その角部から離れる。このとき、上記のように従来の装置におけるゲート電極が形成するショットキー構造は、本発明ではMIS(Metal Insulator Semiconductor)構造へと変えられている。この結果、角部の外側に接していたn型GaN系ドリフト層に生じる電界集中は緩和される。この結果、当該箇所のn型GaN系ドリフト層に破壊が生じにくくなる。
なお、不純物の導電型n型またはp型について、濃度は限定していないが、低濃度から高濃度の全範囲を含むものである。
これによって、開口部の底部および壁面が連続して再成長層で覆われるので、角部等に偶発的に生成する不規則な凹凸などがなく、電界集中を局所的に助長する形状要因をなくすことができる。また、開口部の底部および壁面を連続して覆う再成長層上に底部絶縁膜を配置することで、製造工程の簡単化をはかることができる。
これによって開口部の底部は、金属(ゲート電極)/底部絶縁膜/n型GaN系ドリフト層という、簡単な構造になり、耐圧性能上、好ましい構造を得ることができる。
ゲート電極下でチャネル上に絶縁層を配置することで、ゲートに正電圧を印加したときのゲートリーク電流を抑制できるため、大電流動作がしやすくなる。また、しきい値電圧をより正方向にシフトできるため、ノーマリーオフを得やすくなる。
なお、上記の絶縁層は、開口部の底部へと連続して、当該底部に位置する底部絶縁膜の上または下に延在することができる。この場合、この絶縁層と底部絶縁膜とは、底部において厚みを増して、オフ時に最低電位保持部のゲート電極とn-型GaNドリフト層との間の距離をより大きくすることができる。この結果、角部に接するn-型GaNドリフト層の部分における電界集中を一層緩和することができる。
これによって、上述のノーマリーオフなどの性能を得ながら、耐圧性能を向上させる簡単な一つの構造を得ることができる。
または、再成長層の形成工程では、該再成長層を開口部の壁面および底部を覆うように形成し、底部絶縁膜の形成工程において再成長層上に当該底部絶縁膜を形成することができる。
上記のどちらの製造方法によっても、簡単に、底部絶縁膜を配置して電界集中の生じにくい半導体装置を製造することができる。
これによって、ゲートに正電圧を印加したときのゲートリーク電流を抑制でき、大電流動作がしやすい半導体装置を簡単に製造することができる。また、上記の絶縁層を設けることで、ノーマリーオフを得やすい半導体装置を製造することができる。
図1は、本発明の実施の形態1における縦型GaN系FET(半導体装置)10の断面図である。縦型GaN系FET10は、導電性のGaN基板1と、その上にエピタキシャル成長した、n-型GaNドリフト層4/p型GaNバリア層6/n+型GaNコンタクト層7、を備える。このn-型GaNドリフト層4/p型GaNバリア層6/n+型GaNコンタクト層7は、連続して形成されたGaN系積層体15を形成する。GaN基板1の種類によっては、GaN基板1とn-型GaNドリフト層4との間にAlGaN層またはGaN層からなるバッファ層を挿入してもよい。
なお、GaN基板1は、いわゆる一体物の厚手のGaN基板でも、または支持基体上にオーミック接触するGaN層を有する基板であってもよい。さらに、GaN系積層体の成長時にGaN基板等の上に形成して、その後の工程で、GaN基板等の所定厚み部分を除いて、製品の状態では薄いGaN層下地のみが残っているものであってもよい。これら、GaN基板、支持基体上にオーミック接触するGaN層を有する基板、製品に薄く残された下地のGaN層などを、単にGaN基板と略称する場合もある。
上記の薄い下地のGaN層は、導電性でも非導電性でもよく、ドレイン電極は、製造工程および製品の構造によるが、薄いGaN層の表面または裏面に設けることができる。GaN基板または支持基体等が製品に残る場合、当該支持基体または基板は、導電性でも、非導電性でもよい。導電性の場合は、ドレイン電極は、その支持基体または基板の裏面(下)またはおもて面(上)に直接設けることができる。また、非導電性の場合は、非導電性基板の上であって、上記半導体層中の下層側に位置する導電層の上に、ドレイン電極を設けることができる。
また、p型GaNバリア層は、本実施の形態ではp型GaNバリア層6としているが、p型AlGaN層を用いてもよい。積層体15を構成するその他の層についても、場合に応じて、上記に示したGaN層を他のGaN系半導体層としてよい。
i型GaN電子走行層22とAlGaN電子供給層26との間にAlN等の中間層を挿入してもよい。ソース電極Sは、再成長層27、n+型コンタクト層7、およびp型GaNバリア層に電気的に接続する。図1では、ソース電極Sは、下方に延在して、その側面で再成長層27およびn+型コンタクト層7に接触し、その先端部でp型GaNコンタクト層7に接触して電気的接続をしている。ドレイン電極DはGaN基板1の裏面に位置する。
上記したように、オフ動作時には、グランド電位に保持されるソース電極Sとドレイン電極Dとの間に、数百ボルト~千数百ボルトの高電圧が印加される。またゲート電極は、チャネルの開閉のためにオフ時にマイナス数ボルト、たとえば-5Vに保持される。オフ動作時、ゲート電極が最低電位を保持する。
従来の半導体装置のように、ゲート電極Gが開口部28の底部28bおよび壁面28aを連続して隙間なく覆う構造では、上記電位の境界条件下で、角部Kに接する部分のn-型GaNドリフト層4に大きな電界集中が生じる。従来の半導体装置では、ゲート電極は、上記角部Kに内側から嵌合する凸部を有する。角部Kに接する部分のn-型GaNドリフト層4では、電気力線は角部Kの外側から内側に向かって断面を絞られて高密度になって流れる。角部の内側から嵌合する凸部とは、厳密には、角部Kを覆う再成長層に内側から嵌合するというべきであるが、再成長層の厚みは小さく差異は小さいので、それほど大きな影響がない場合は、厳密に区別しないで説明する。
上記の内側から嵌合する凸部のために、ゲート電極Gの最低電位を保持する凸部に接する部分のn型GaN系ドリフト層4に大きな電界集中が生じる。この電界集中によってこの部分のp型GaNバリア層6が破壊される場合がある。
底部絶縁膜37には、Al2O3、SiO2、SiN、NiO、Sc2O3などを用いることができる。
n+型GaNコンタクト層7の厚みは、0.1μm~0.6μm程度とするのがよい。
n+型GaNコンタクト層7の長さは、5μm以下とするのがよい。
上記の六角形のハニカム構造は、畝状にして、畝状の開口部を密に配置することでも、上記の面積当たりの開口部周囲長を大きくでき、この結果、電流密度を向上させることができる。
上記の層の形成は、MOCVD(有機金属化学気相成長)法などを用いるのがよい。たとえばMOCVD法で成長することで、結晶性の良好な積層体15を形成できる。GaN基板1の形成において、導電性基板上に窒化ガリウム膜をMOCVD法によって成長させる場合、ガリウム原料として、トリメチルガリウムを用いる。窒素原料としては高純度アンモニアを用いる。キャリアガスとしては純化水素を用いる。高純度アンモニアの純度は99.999%以上、純化水素の純度は99.999995%以上である。n型ドーパント(ドナー)のSi原料には水素ベースのシランを用い、p型ドーパント(アクセプタ)のMg原料にはシクロペンタジエニルマグネシウムを用いるのがよい。
導電性基板としては、直径2インチの導電性GaN基板を用いる。温度1030℃、圧力100Torrで、アンモニアおよび水素の雰囲気中で、基板クリーニングを実施する。その後、基板を1050℃に昇温して、圧力200Torr、窒素原料とガリウム原料の比率であるV/III比=1500で窒化ガリウム層を成長させる。上記の導電性基板上のGaN層の形成は、GaN基板1の形成だけでなく、GaN基板1上の積層体15の成長においても共通する方法である。
上記の方法で、GaN基板1上に、n-型GaN層ドリフト層4/p型GaNバリア層6/n+型GaNコンタクト層7、の順に成長する。
次いで、上記ウエハをMOCVD装置から取り出し、開口部の底部に開口部をもつレジストパターン(図示せず)を用いて、図7に示すように、底部絶縁膜37を成長させる。
その後、再びフォトリソグラフィと電子ビーム蒸着法を用いて、図1に示すように、ソース電極Sをエピタキシャル層表面に、ドレイン電極DをGaN系基板1の裏面に形成する。
図8は、本発明の実施の形態の半導体装置10であり、実施の形態1の変形例である。
この変形例では、図1の半導体装置と異なり、ゲート電極Gの下に、絶縁層9を配置する。
ゲート電極下に絶縁層を配置することで、ゲートに正電圧を印加したときのゲートリーク電流を抑制できるため、大電流動作がしやすくなる。また、しきい値電圧をより正方向にシフトできるため、ノーマリーオフを得やすくなる。さらに、底部絶縁膜37と絶縁層9とが積層されるので、ゲート電極Gとn-型GaNドリフト層4との間の距離が大きくなり、さらに角部Kに接する部分のn-型GaNドリフト層4における電界集中を緩和することができる。
絶縁層9の厚みは、0.05μm以上0.3μm以下程度とするのがよい。絶縁層9についても、底部絶縁膜37と同様に、Al2O3、SiO2、SiN、NiO、Sc2O3などを用いることができる。
なお、絶縁層9は、底部絶縁膜37の下で、再成長層27の上に位置してもよい。
図9は、本発明の実施の形態2における縦型GaN系FET(半導体装置)10の断面図である。GaN系積層体15が、n-型GaNドリフト層4/p型GaNバリア層6/n+型GaNコンタクト層7で形成され、開口部28が表層からn-型GaNドリフト層4に届くように設けられる点などは、実施の形態1と共通する。
本実施の形態の半導体装置10の特徴は、次の点にある。
(1)開口部28の底部28bに底部絶縁膜37が設けられている。この点は、実施の形態1における図1の半導体装置または、その変形例である図8の半導体装置と同じである。
(2)開口部28の底部28bにおいて再成長層が配置されず、再成長層27は、開口部28の壁面を伝って底部に当たった箇所で終端している。
上記の(2)の特徴は、実施の形態1の半導体装置との間に本質的な相違を生じるものではない。底部絶縁膜37は、絶縁膜9と協働して、開口部28の角部Kに接する部分のn-型GaNドリフト層4と、最低電位保持部であるゲート電極Gとの間の距離を大きくする。この結果、実施の形態1と、同様に、n-型GaNドリフト層4における角部Kの電界集中を緩和することができる。
絶縁層9がゲート電極下に位置することによる作用は、実施の形態1と同じである。すなわちゲート電極下でチャネル上に絶縁層を配置することで、ゲートに正電圧を印加したときのゲートリーク電流を抑制できるため、大電流動作がしやすくなる。また、しきい値電圧をより正方向にシフトできるため、ノーマリーオフを得やすくなる。
さらに、絶縁層9は必須ではなく、あれば上記の作用を得ることができるが、耐圧性能の向上等に限定すれば、なくてもよい。
Claims (9)
- 開口部が設けられたGaN系積層体を備える縦型の半導体装置であって、
前記GaN系積層体は、表層側へと順次、n型GaN系ドリフト層/p型GaN系バリア層/n型GaN系コンタクト層、を有し、前記開口部は表層から前記n型GaN系ドリフト層内にまで届いており、
前記開口部の壁面および底部を覆うように位置する、電子走行層および電子供給層を含む再成長層と、
前記再成長層、前記n型GaN系コンタクト層および前記p型GaN系バリア層に接するソース電極と、
前記開口部において前記再成長層上に位置するゲート電極と、
前記開口部の底部に限定されて前記ゲート電極の下に位置する底部絶縁膜とを備えることを特徴とする、半導体装置。 - 前記底部絶縁膜は、前記開口部の底部を覆う前記再成長層の上に位置することを特徴とする、請求項1に記載の半導体装置。
- 前記再成長層は、前記開口部の壁面を覆って該開口部の底部を形成する前記n型GaN系ドリフト層で終端し、前記底部絶縁膜は、前記開口部の底部に位置する前記n型GaN系ドリフト層を覆うように位置することを特徴とする、請求項1に記載の半導体装置。
- 開口部の、少なくとも壁面において、前記ゲート電極の下であって前記再成長層上に位置する絶縁層を備えることを特徴とする、請求項1~3のいずれか1項に記載の半導体装置。
- 前記再成長層が、前記開口部の壁面を覆って、該壁面と該開口部の底部とが交差する箇所で終端する構造において、前記絶縁膜が前記開口部の壁面から連続して前記底部絶縁膜を兼ねて、前記開口部の底部に位置する前記n型GaN系ドリフト層を覆うように位置することを特徴とする、請求項4に記載の半導体装置。
- 縦型のGaN系半導体装置の製造方法であって、
n型GaN系ドリフト層上にp型GaN系バリア層を形成する工程と、
前記p型GaN系バリア層上にn型GaN系コンタクト層を形成する工程と、
エッチングにより、表層から前記n型GaN系ドリフト層内に届く開口部を形成する工程と、
前記開口部の壁面および底部を覆うように、電子走行層および電子供給層を含む再成長層をエピタキシャル成長させる工程と、
前記開口部の底部に限定して底部絶縁膜を形成する工程と、
前記底部絶縁膜上にゲート電極を形成する工程とを備えることを特徴とする、半導体装置の製造方法。 - 前記再成長層の成長工程において、前記開口部の壁面に該開口部の底部を形成している前記n型GaN系ドリフト層にまで当該再成長層を形成するか、または開口部の底部に位置する前記再成長層をエッチングによって除き、次いで、前記底部絶縁膜の製造工程において前記開口部の底部に露出する前記n型GaN系ドリフト層を覆うように前記底部絶縁膜を形成することを特徴とする、請求項6に記載の半導体装置の製造方法。
- 前記再成長層の形成工程では、該再成長層を前記開口部の壁面および底部を覆うように形成し、前記底部絶縁膜の形成工程において前記再成長層上に当該底部絶縁膜を形成することを特徴とする、請求項6に記載の半導体装置の製造方法。
- 前記ゲート電極形成工程よりも前、前記底部絶縁膜の形成工程の後または前に、少なくとも前記開口部の壁面において前記ゲート電極の下に位置するように、絶縁層を形成する工程を備えることを特徴とする、請求項6~8のいずれか1項に記載の半導体装置の製造方法。
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CN106653610A (zh) * | 2016-12-26 | 2017-05-10 | 东莞市联洲知识产权运营管理有限公司 | 一种改良的沟槽超势垒整流器件及其制造方法 |
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US10756207B2 (en) * | 2018-10-12 | 2020-08-25 | Transphorm Technology, Inc. | Lateral III-nitride devices including a vertical gate module |
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