WO2012066791A1 - Boîtier pour semi-conducteur - Google Patents

Boîtier pour semi-conducteur Download PDF

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Publication number
WO2012066791A1
WO2012066791A1 PCT/JP2011/052088 JP2011052088W WO2012066791A1 WO 2012066791 A1 WO2012066791 A1 WO 2012066791A1 JP 2011052088 W JP2011052088 W JP 2011052088W WO 2012066791 A1 WO2012066791 A1 WO 2012066791A1
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WO
WIPO (PCT)
Prior art keywords
terminal
input
semiconductor package
input matching
lead
Prior art date
Application number
PCT/JP2011/052088
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English (en)
Japanese (ja)
Inventor
幸谷　真人
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to DE112011103767.8T priority Critical patent/DE112011103767B4/de
Priority to CN201180054709.4A priority patent/CN103210487B/zh
Publication of WO2012066791A1 publication Critical patent/WO2012066791A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to input matching by a semiconductor package.
  • FIG. 4 shows a block diagram of a MOP-IC (Mixer, Oscillator, PLL-IC) used as an LNB (Low Noise Block down converter) for satellite broadcast reception.
  • the MOP-IC 10 shown in FIG. 4 includes an RF input terminal RFIN, a bandpass filter 1, an RF amplifier 2, a mixing circuit 3, a VCO (Voltage Controlled Oscillator) 4, an IF amplifier 5, and an IF amplifier. And an output terminal IFOUT.
  • MOP-IC Mater, Oscillator, PLL-IC
  • LNB Low Noise Block down converter
  • the high frequency signal received by the satellite broadcast receiving antenna is input to the RF input terminal RFIN.
  • the band pass filter 1 attenuates components other than the predetermined frequency band among the frequency components of the high frequency signal.
  • the high frequency signal that has passed through the band pass filter 1 is amplified by the RF amplifier 2 and input to the mixing circuit 3.
  • the VCO 4 is a part of a PLL loop (not shown) and outputs a local oscillation signal to the mixing circuit 3.
  • the high frequency signal of 10.7 to 12.7 GHz is mixed with the local oscillation signal of 9.75 GHz or 10.6 GHz by the mixing circuit 3 and down-converted to an intermediate frequency signal of 950 MHz to 2.15 GHz.
  • the intermediate frequency signal is amplified by the IF amplifier 5 and output from the IF output terminal IFOUT.
  • FIG. 5A shows a top view
  • FIG. 5B shows a bottom view of a bond wire design example of a conventional typical QFN (Quad Flatpack Non-leaded package) package.
  • a QFN package Q1 shown in FIGS. 5A and 5B includes a MOP-IC 10, a die bond / lead frame 11, and lead terminals.
  • the die bond lead frame 11 includes a die bond region and a lead frame integrated therewith.
  • the MOP-IC 10 which is a semiconductor integrated circuit chip, is attached to the die bond area of the die bond / lead frame 11 with a paste agent. Twenty-four lead terminals are arranged around the die bond region. Pins 2 to 5, 8 to 11, 14 to 17, and 20 to 23 are lead terminals that are separate from the die bond lead frame 11. Also, the 1st pin, 6th pin, 7th pin, 12th pin, 13th pin, 18th pin, 19th pin and 24th pin for the ground are formed as a lead frame of the die bond lead frame 11. Lead terminal. Each terminal included in the MOP-IC 10 is bonded to each lead terminal.
  • a part of the ground terminal of the MOP-IC 10 is down-bonded to the die bond region of the die bond lead frame 11.
  • the 20th pin which is a lead terminal for high frequency signal input, is bonded to the RF input terminal RFIN of the MOP-IC 10, and the 11th pin, which is the lead terminal for intermediate frequency signal output, is an IF of the MOP-IC 10. Bonded to the output terminal IFOUT.
  • the microstrip line wiring connected to the 20th pin which is the lead terminal for high frequency signal input on the module substrate, is laid out adjacent to the ground region in order to maximize the high frequency characteristics, it is adjacent to the 20th pin. It is preferable to use the 19th pin and the 21st pin for the ground. Furthermore, in parallel with the high-frequency signal input bonding wire (20th pin), the ground bonding wires (19th pin and 21st pin) are directly connected to the lead terminals and are often not down-bonded.
  • the lead terminals at the four corners of the package (1st pin, 24th pin, 6th pin, 7th pin, 12th pin, 13th pin, 18th pin, 19th pin) It is formed as a lead frame integrated with the die bond region of the die bond lead frame 11.
  • Patent Document 1 proposes a high-frequency matching circuit that takes into account the inductance of a bonding wire that connects a spiral inductor of an IC and a transmission line.
  • Non-Patent Document 1 proposes an LNA (Low-Noise Amplifier) having a 3-section Chebyshev LC type bandpass filter.
  • the LNA corresponds to a portion composed of the bandpass filter 1 and the RF amplifier 2 in the MOP-IC 10 shown in FIG.
  • the configuration of the LNA proposed in Non-Patent Document 1 is shown in FIG. 6A.
  • the LNA shown in FIG. 6A includes inductors L1, L2, Lg, Ls, and L1, capacitors C1, C2, and Cp, a resistor R1, and MOS transistors M1 and M2.
  • the three-section Chebyshev LC type bandpass filter B1 includes inductors L1, L2, Lg, and Ls, capacitors C1, C2, and Cp, and a MOS transistor M1.
  • a high-frequency signal is input to a 3-section Chebyshev LC type bandpass filter B1 from a 50 ⁇ signal source composed of a high-frequency signal source Vs and a resistor Rs.
  • One end of the inductor L1 is connected to one end of the resistor Rs, and the other end of the inductor L1 is connected to one end of the capacitor C1.
  • the other end of the capacitor C1 is connected to one end of the inductor Lg, and the other end of the inductor Lg is connected to the gate of the MOS transistor M1.
  • a capacitor C2 and an inductor L2 are connected in parallel to a connection point between the capacitor C1 and the inductor Lg, and a bias voltage Vbias is applied to the capacitor C2 and the inductor L2.
  • One end of the capacitor Cp is connected to the connection point between the inductor Lg and the gate of the MOS transistor M1, and the other end of the capacitor Cp is connected to the connection point between the source of the MOS transistor M1 and one end of the inductor Ls.
  • the other end of the inductor Ls is connected to the ground.
  • the drain of the MOS transistor M1 and the source of the MOS transistor M2 are connected.
  • a resistor Rl and an inductor Ll are connected in series to the drain of the MOS transistor M2, and a power supply voltage Vdd is applied to the inductor Ll.
  • the power supply voltage Vdd is also applied to the gate of the MOS transistor M2.
  • the output voltage Vout is output from the connection point between the drain of the MOS transistor M2 and the resistor Rl.
  • FIG. 6B shows an equivalent circuit of the 3-section Chebyshev LC type bandpass filter B1.
  • the inductor Lg and the inductor Ls are connected, and one end of the gate-drain parasitic capacitance Cgd of the MOS transistor M1 is connected to the connection point, and the other end of the gate-drain parasitic capacitance Cgd is connected to the ground. Further, one end of a capacitor which is the sum of the capacitance Cp and the gate-source capacitance of the MOS transistor M1 is connected to one end of the inductor Ls.
  • One end of a resistor having a resistance value that is the product of the cutoff frequency ⁇ t of the MOS transistor M1 and the inductance of the inductor Ls is provided at the other end of the capacitor, which is the sum of the capacitance of the capacitor Cp and the capacitance between the gate and source of the MOS transistor M1. And the other end of the resistor is connected to the ground.
  • FIG. 7 shows a circuit design example of a three-section Chebyshev LC type bandpass filter that realizes 10 GHz band wideband input matching.
  • a three-section Chebyshev LC type bandpass filter B10 shown in FIG. 7 includes inductors L1, L2, and L3, capacitors C1, C2, and C3, and a resistor R1.
  • a high-frequency signal is input from the high-frequency signal source Vs to the three-section Chebyshev LC type bandpass filter B10 through the resistor Rs.
  • One end of the inductor L1 is connected to one end of the resistor Rs, and the other end of the inductor L1 is connected to one end of the capacitor C1.
  • the other end of the capacitor C1 and one end of the inductor L3 are connected, and the capacitor C2 and the inductor L2 are connected in parallel at the connection point.
  • a ground is connected to the capacitor C2 and the inductor L2.
  • One end of a capacitor C3 is connected to the other end of the inductor L3, and one end of a resistor R1 is connected to the other end of the capacitor C3.
  • the other end of the resistor R1 is connected to the ground.
  • FIG. 8 shows simulation results of the power reflection coefficient characteristic and gain characteristic of the three-section Chebyshev LC type bandpass filter B10 having such a configuration.
  • Andrea Bevilacqua An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6 GHz Wireless Receivers, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004.
  • FIG. 9 shows bonding to the LNA in the conventional QFN package.
  • An RF input terminal RFIN included in the MOP-IC 10 is connected to an input of an input matching circuit included in the LNA 6 provided in the MOP-IC 10.
  • the RF input terminal RFIN is bonded to the lead terminal LT20 which is the 20th pin (FIG. 5A) by the bond wire Wr.
  • a high frequency signal is input to the LNA 6 from the high frequency signal source Vs via the resistor Rs, the lead terminal LT20, the bond wire Wr, and the RF input terminal RFIN.
  • the ground terminals GD1, GD2, and GD3 included in the MOP-IC 10 are terminals for ground connection of the input matching circuit included in the LNA 6.
  • the ground terminals GD1, GD2, and GD3 are bonded to the lead terminals LT19, LT21, and LT22, which are the 19th, 21st, and 22nd pins (FIG. 5A), respectively, by bond wires Wg1, Wg2, and Wg3.
  • the lead terminals LT19, LT21, LT22 are connected to the ground.
  • an object of the present invention is to provide a semiconductor package capable of reducing the parasitic inductance of a bond wire and improving the high frequency characteristics.
  • the present invention includes a semiconductor integrated circuit chip having an input matching circuit to which a high-frequency signal is input and disposed in a die bond region, and a lead terminal disposed in the periphery of the die bond region.
  • a semiconductor integrated circuit chip having an input matching circuit to which a high-frequency signal is input and disposed in a die bond region, and a lead terminal disposed in the periphery of the die bond region.
  • each terminal of the semiconductor integrated circuit chip and each lead terminal are connected by a bond wire, Shift from the center of the die bond region to the high-frequency input terminal side that is the lead terminal for inputting a high-frequency signal to the input matching circuit and / or the ground terminal side that is the lead terminal for ground connection of the input matching circuit
  • the semiconductor integrated circuit chip is arranged at the position.
  • the bond wire length of the high frequency input terminal and / or the ground terminal can be shortened, the parasitic inductance of the bond wire can be reduced, and the high frequency characteristics can be improved.
  • the ground terminal formed integrally with the die bond region may be provided in a direction in which the semiconductor integrated circuit chip is shifted.
  • the shift amount of the semiconductor integrated circuit chip can be increased by allowing the bond wire to be down-bonded to escape to the ground terminal.
  • the package has two lead terminals formed integrally with the die bond region in at least one of the four corners of the package, and is formed integrally with the die bond region in the remaining corners. It is good also as a structure which has one lead terminal and one lead terminal which is a different body from the said die-bonding area
  • the number of effective terminals of the package can be increased while ensuring the strength of the lead terminals.
  • the semiconductor integrated circuit chip for ground connection of the input matching circuit may have two or more bond wires for connecting the terminal and the ground terminal.
  • the ground impedance caused by the bond wire can be reduced, and the high frequency gain characteristic and NF (Noise Figure) can be improved.
  • the package may have ground connection lead terminals at the four corners
  • the semiconductor integrated circuit chip may have ground connection terminals at the four corners
  • ground connection lead terminals at the four corners of the package is preferable in terms of mounting and board layout, and since there are ground connection terminals at the four corners of the semiconductor integrated circuit chip. , Bond wire layout becomes easy.
  • each circuit element of the input matching circuit has the best high frequency characteristics by the input matching of the input matching unit including the bond wire of the high frequency input terminal as an inductor in the input matching circuit.
  • a circuit constant may be set.
  • the inductor included in the input matching circuit connected in series to the bond wire of the high-frequency input terminal can be reduced or eliminated, and the semiconductor integrated circuit chip can be reduced in size and cost. Therefore, high-frequency characteristics can be improved with an inexpensive package.
  • the input matching circuit may be a band pass filter. According to such a configuration, by forming a band pass filter including a bond wire of a high frequency input terminal, input matching in a high frequency wide band can be realized.
  • the high frequency input terminal has an intermediate frequency output terminal which is the lead terminal from which an intermediate frequency signal obtained by frequency conversion of the high frequency signal input through the high frequency input terminal is output.
  • the intermediate frequency output terminal may be arranged on the sides of the package facing each other.
  • the semiconductor integrated circuit chip may include an LNA (Low-Noise Amplifier) and / or a mixing circuit having the input matching circuit, and the semiconductor package may be a broadcast receiving device. Good.
  • LNA Low-Noise Amplifier
  • the high frequency characteristics of the broadcast receiving apparatus can be improved.
  • the parasitic inductance of the bond wire can be reduced and the high frequency characteristics can be improved.
  • FIG. 1A A top view of a bond wire design example of the QFN package according to the first embodiment of the present invention is shown in FIG. 1A, and a bottom view is shown in FIG. 1B.
  • a QFN package Q100 shown in FIGS. 1A and 1B includes a MOP-IC 12, a die bond lead frame 13, and lead terminals.
  • the die bond lead frame 13 includes a die bond region and a lead frame integrated therewith.
  • the MOP-IC 12 which is a semiconductor integrated circuit chip, is attached to the die bond region of the die bond / lead frame 13 with a paste agent. Twenty-four lead terminals are arranged around the die bond region. Pins 2 to 6, 8 to 11, 13 to 17, 20, and 22 to 24 are lead terminals that are separate from the die bond lead frame 13. In addition, the first pin, the seventh pin, the 12th pin, the 18th pin, the 19th pin, and the 21st pin for ground are lead terminals formed as lead frames of the die bond lead frame 13. Each terminal of the MOP-IC 12 is bonded to each lead terminal. A part of the ground terminal of the MOP-IC 12 is down-bonded to the die bond region of the die bond / lead frame 13.
  • the MOP-IC 12 is arranged at a position shifted in the X-axis direction (left and right direction in FIG. 1A) from the center of the die bond area of the die bond / lead frame 13 toward the direction in which the 18th to 22nd pins are densely packed. .
  • An RF input terminal of the MOP-IC 12 for inputting a high frequency signal to an input matching circuit of an LNA (not shown) provided in the MOP-IC 12 is bonded to the 20th pin for inputting the high frequency signal.
  • the ground terminals of the MOP-IC 12 for ground connection of the input matching circuit are bonded to the 18th, 19th, 21st and 22nd pins for ground connection, respectively.
  • the bond wire length of the 20th pin for high-frequency signal input and the bond wire lengths of the 18th, 19th, 21st and 22nd pins for ground connection can be shortened.
  • Inductance can be reduced to about 0.5 nH.
  • the input matching state is improved, and the high-frequency gain characteristic can be improved.
  • the lead terminal of the 21st pin is formed as a lead frame integrated with the die bond region of the die bond lead frame 13, and the bond wire to be down bonded is released to the lead terminal.
  • the shift amount of the MOP-IC 12 can be further increased.
  • two lead terminals, pin 18 and pin 19 are formed as a lead frame integrated with the down bond region, and pin 1 is formed in each of the remaining three corners.
  • Only one lead terminal for each of the 7th and 12th pins is formed as a lead frame integrated with the down bond region.
  • the 24th pin, the 6th pin, and the 13th pin can be made effective as compared with the conventional FIG. 5A while securing the strength of the lead terminal. That is, the number of package effective terminals can be increased.
  • the bond wire The ground impedance due to the parasitic inductance can be made smaller, and the high frequency gain characteristic and NF (Noise Figure) can be improved.
  • the first, seventh, twelfth, twentieth, eighteenth, and nineteenth pins which are lead terminals for ground connection, are arranged at the four corners of the package in terms of mounting and board layout. This is because it is preferable. That is, the thermal stress is most strongly applied to the four corners of the package, and even if the solder joint interface of one pin at the four corners of the package breaks due to the thermal stress, at least function failure can be prevented. . Since two ground terminals are provided at each of the four corners of the MOP-IC 12, layout of bond wires is facilitated.
  • the 20th pin which is the lead terminal for high-frequency signal input
  • the 11th pin which is the lead terminal for outputting the intermediate frequency signal
  • the 22nd pin and 15th pin which are lead terminals for ground connection, are given independently for the LNA and VCO, and are intentionally integrated with the die bond area so that they can be used for purposes other than ground connection when the pins are changed.
  • the lead terminals are separate from the die bond lead frame 13.
  • FIG. 2 shows a top view of a bond wire design example of the QFN package according to the second embodiment of the present invention.
  • the MOP-IC 12 is only in the X-axis direction (the left-right direction in FIG. 2) from the center of the die bond area of the die bond lead frame 13 toward the direction where the 18th to 22nd pins are densely packed. Instead, it is arranged at a position shifted in the Y-axis direction (up and down direction in FIG. 2).
  • the length of the bond wire for bonding the 20th pin for high-frequency signal input and the RF input terminal of the MOP-IC 12 can be made shorter, and the parasitic inductance can be made smaller.
  • FIG. 6B The configuration of an LC type bandpass filter according to the third embodiment of the present invention is shown in FIG.
  • the MOPI-IC 12 having the LC type bandpass filter B100 is disposed at a position shifted from the center of the die bond region as in the first or second embodiment described above.
  • the configuration of the LC type bandpass filter B100 is the same as that of the conventional three-section Chebyshev LC type bandpass filter B1 (FIG. 6B).
  • an LC type bandpass including the inductor L1b in the LC type bandpass filter B100 The circuit constants of the respective circuit elements of the LC type bandpass filter B100 are set so that the high frequency characteristics are optimized by the input matching of the filter (input matching unit).
  • the inductor L1a included in the MOP-IC 12 connected in series to the inductor L1b can be reduced or eliminated. Therefore, the MOP-IC 12 can be reduced in size and cost, and wide-band input matching can be realized with an inexpensive package.
  • the LNA is not limited to those using MOS transistors.
  • the IC chip has the LNA as an example.
  • the input matching circuit of the mixing circuit may be provided in the IC chip.
  • the present invention is applicable to all semiconductor packages for electronic devices.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un boîtier pour semi-conducteur, doté d'une puce de circuit intégré semi-conducteur qui possède un circuit d'adaptation d'entrée qui a une entrée de signal à haute fréquence et qui est disposé dans une région de fixation de la puce, et des bornes de raccordement qui sont disposées à la périphérie de la région de fixation de la puce. Dans le boîtier pour semi-conducteur, les bornes du circuit intégré semi-conducteur et les bornes de raccordement sont chacune reliées par des fils de connexion. La puce de circuit intégré semi-conducteur est placée dans une position qui est décalée par rapport au centre de la région de fixation de la puce vers le côté de la borne d'entrée à haute fréquence qui possède les bornes de raccordement pour l'injection d'un signal à haute fréquence dans le circuit d'adaptation d'entrée et/ou un côté de la borne de masse qui possède les bornes de raccordement pour les connexions de masse du circuit d'adaptation d'entrée.
PCT/JP2011/052088 2010-11-15 2011-02-02 Boîtier pour semi-conducteur WO2012066791A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112011103767.8T DE112011103767B4 (de) 2010-11-15 2011-02-02 Halbleitereinheit
CN201180054709.4A CN103210487B (zh) 2010-11-15 2011-02-02 半导体封装

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010254520A JP4851618B1 (ja) 2010-11-15 2010-11-15 半導体パッケージ
JP2010-254520 2010-11-15

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JP (1) JP4851618B1 (fr)
CN (1) CN103210487B (fr)
DE (1) DE112011103767B4 (fr)
TW (1) TW201142992A (fr)
WO (1) WO2012066791A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014064237A (ja) * 2012-09-24 2014-04-10 Sharp Corp 衛星通信または衛星放送受信装置、およびそれに用いられる低雑音コンバータ

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104679929A (zh) * 2013-12-03 2015-06-03 上海北京大学微电子研究院 适合高速ic-qfn封装设计应用的寄生参数提取方法
CN104392974A (zh) * 2014-11-26 2015-03-04 厦门科塔电子有限公司 Qfn封装高频集成电路的端子和内芯片配置结构
CN108292291A (zh) * 2015-11-30 2018-07-17 Pezy计算股份有限公司 管芯和封装件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088378A (ja) * 2005-09-26 2007-04-05 Mitsubishi Electric Corp 半導体モールドパッケージ
JP2007324499A (ja) * 2006-06-05 2007-12-13 Sharp Corp 高周波用半導体装置
JP2009278117A (ja) * 2002-04-30 2009-11-26 Renesas Technology Corp 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685593A (ja) * 1992-08-28 1994-03-25 Mitsubishi Electric Corp 高周波整合用回路装置
JPH085593A (ja) 1994-06-22 1996-01-12 Riken Corp ＮＯｘセンサ
US7341887B2 (en) * 2004-10-29 2008-03-11 Intel Corporation Integrated circuit die configuration for packaging
US7769355B2 (en) * 2005-01-19 2010-08-03 Micro Mobio Corporation System-in-package wireless communication device comprising prepackaged power amplifier
CN101211794A (zh) * 2006-12-27 2008-07-02 联发科技股份有限公司 封装半导体元件方法、制作引线框架方法及半导体封装产品

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009278117A (ja) * 2002-04-30 2009-11-26 Renesas Technology Corp 半導体装置
JP2007088378A (ja) * 2005-09-26 2007-04-05 Mitsubishi Electric Corp 半導体モールドパッケージ
JP2007324499A (ja) * 2006-06-05 2007-12-13 Sharp Corp 高周波用半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014064237A (ja) * 2012-09-24 2014-04-10 Sharp Corp 衛星通信または衛星放送受信装置、およびそれに用いられる低雑音コンバータ

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DE112011103767B4 (de) 2020-12-31
TW201142992A (en) 2011-12-01
JP4851618B1 (ja) 2012-01-11
TWI375304B (fr) 2012-10-21
DE112011103767T5 (de) 2013-10-24
CN103210487B (zh) 2016-02-10
CN103210487A (zh) 2013-07-17
JP2012104776A (ja) 2012-05-31

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