WO2012061436A2 - Procédé de gravure à sec pour former une texture de surface sur tranche de silicium - Google Patents

Procédé de gravure à sec pour former une texture de surface sur tranche de silicium Download PDF

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Publication number
WO2012061436A2
WO2012061436A2 PCT/US2011/058846 US2011058846W WO2012061436A2 WO 2012061436 A2 WO2012061436 A2 WO 2012061436A2 US 2011058846 W US2011058846 W US 2011058846W WO 2012061436 A2 WO2012061436 A2 WO 2012061436A2
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
wafer
oxide layer
chamber
etching
Prior art date
Application number
PCT/US2011/058846
Other languages
English (en)
Other versions
WO2012061436A3 (fr
WO2012061436A4 (fr
Inventor
Young Kyu Cho
Original Assignee
Intevac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intevac, Inc. filed Critical Intevac, Inc.
Priority to EP11838708.3A priority Critical patent/EP2635513A4/fr
Priority to SG2013033428A priority patent/SG190085A1/en
Priority to CN201180057975.2A priority patent/CN103237745B/zh
Priority to JP2013536933A priority patent/JP2013544028A/ja
Publication of WO2012061436A2 publication Critical patent/WO2012061436A2/fr
Publication of WO2012061436A3 publication Critical patent/WO2012061436A3/fr
Publication of WO2012061436A4 publication Critical patent/WO2012061436A4/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • This invention relates to the art of silicon wafers for solar cells and, more particularly, to surface texture formation using a dry etch process.
  • Solar cells also known as photovoltaic (PV) cells, convert solar radiation into electrical energy.
  • Solar cells are fabricated using semiconductor processing techniques, which typically, include, for example, deposition, doping and etching of various materials and layers.
  • Typical solar cells are made on semiconductor wafers or substrates, which are doped to form p-n junctions in the wafers or substrates.
  • Solar radiation e.g., photons
  • Solar radiation directed at the surface of the substrate cause electron-hole pairs in the substrate to be broken, resulting in migration of electrons from the n-doped region to the p-doped region (i.e., an electrical current is generated). This creates a voltage differential between two opposing surfaces of the substrate.
  • Metal contacts coupled to electrical circuitry, collect the electrical energy generated in the substrate.
  • Semiconductor materials used to make solar cells are very reflective. To reduce the reflectivity of the solar cell, the surface of the solar cell that receives the solar radiation is textured. Decreasing the reflection at the surface increases the efficiency of the solar cell.
  • Solar cells manufactured using conventional techniques e.g., wet texture
  • Solar cells manufactured using conventional techniques typically have a reflectance of about 27%, and an efficiency that is only on the order of about 12-18%. Solar cell efficiency improvement is critical to those who manufacture solar cell device in order for maximize the commercial value of solar cell.
  • wet chemicals need to be selected depending on the types of silicon wafers (e.g., mono crystal silicon wafer, multi crystal silicon) due to the chemical etching property dependency on crystal types.
  • silicon wafers e.g., mono crystal silicon wafer, multi crystal silicon
  • Mono crystal wafers usually requires Alkaline based chemicals
  • multi crystal wafers requires Acid chemicals, while dry etching texturing result does not depend on wafer types, mono or multi crystal.
  • a system includes a silicon etch chamber to perform a first etch process to remove a portion of a silicon oxide layer on a silicon wafer and a second etch process that is highly selective of silicon to oxide.
  • the system may also include an oxidation chamber to form the silicon oxide layer on a surface of a silicon wafer.
  • the oxidation chamber may be a plasma oxidation chamber.
  • the oxidation chamber may be coupled to the silicon etch chamber so the silicon oxide layer is formed on the surface of the silicon wafer before the wafer enters the silicon etch chamber.
  • the system may also include a wafer loading chamber and a wafer unloading chamber.
  • the system may also include a loadlock between the wafer loading chamber and the plasma oxidation chamber, and a loadlock between the silicon etch chamber and the wafer unloading chamber.
  • a method of making a silicon wafer having a textured surface includes performing a first silicon etch process on a silicon wafer having an oxide layer; and performing a second silicon etch process on the silicon wafer, wherein the second silicon etch process is more selective etching of silicon to oxide.
  • a solar cell made by this process is also provided.
  • the method may also include performing a surface oxidation process on a silicon wafer to grow the oxide layer before performing the first silicon etch process.
  • the surface oxidation process may be a plasma oxidation.
  • the first and second silicon etch processes my be dry etching.
  • the dry etching may be one of reactive ion etching, plasma etching and physical sputtering.
  • the second silicon etch process may be an anisotropic etch process.
  • a method includes etching a silicon oxide layer on a silicon wafer having defect sites and non- defect sites to remove at least the portion of the silicon oxide layer over the non-defect sites; and selectively etching the wafer.
  • a solar cell made by this process is also provided.
  • the method may also include growing the silicon oxide layer before etching the silicon oxide layer.
  • Growing the silicon oxide layer may include oxidizing the silicon wafer.
  • the silicon oxide layer may be thicker over the defect sites than over the non- defect sites.
  • Etching the silicon oxide layer may include dry etching the silicon oxide layer.
  • Selectively etching the wafer may include dry etching the wafer.
  • FIG. 1 is perspective view illustrating a solar cell having an ideal texture surface according to one embodiment of the invention.
  • This drawing shows typical Passivated Emitter Rear Contact (PERC) solar cell structure which was developed by University of New South Wales (UNSW) with wet textured front surface on mono crystal silicon wafer.
  • PERC Passivated Emitter Rear Contact
  • Figure 2 is a perspective view of a solar cell having a typical solar cell texture surface on multi crystal silicon wafer according to one embodiment of the invention.
  • Figure 3 is a conceptual and schematic view illustrating a Dry etch system for making a solar cell surface texture according to one embodiment of the invention.
  • Figure 4 is a flow diagram illustrating a process sequence for making a solar cell surface texture according to one embodiment of the invention.
  • Figures 5A-5B are photographs illustrating results of dry texturing with pre oxidation
  • Figures 5C-5D are photographs illustrating results of dry texturing with no pre oxidation.
  • Figures 6A-6B illustrate the wafer surface as cut
  • Figures 6C-6D illustrate the wafer surface after saw damage layer removal and wet chemical texturing
  • Figures 6E-6H illustrating the wafer surface after dry etch texturing.
  • Figure 7 is a graph illustrating the improvement in reflectance achieved with wet texturing and dry texturing processes according to embodiments of the invention.
  • Figure 8A illustrates the wafer surface after wet texture
  • Figures 8B-8C illustrate the wafer surface after dry texturing etch
  • Figure 8D illustrates the wafer surface after residual removal.
  • Embodiments of the invention are directed to systems and methods for improving surface reflectance of silicon wafers.
  • the systems and methods improve surface reflectance by forming a textured surface on the silicon wafer by performing surface oxidation and dry etching processes.
  • the surface oxidation is performed using oxygen plasma. Selective oxidation occurs between defect sites and non-defect sites.
  • the etching chemistry is then switched to highly selective etching of silicon to silicon oxide. Dry etching enables nano-scale textured surface formation, which minimizes or eliminates light reflection or scattering.
  • Fig. 1 illustrates a typical PERC solar cell 100
  • Fig. 2 illustrates a typical multi crystal solar cell 150
  • the solar cell 100 includes a substrate 104 which is typically formed of silicon.
  • a n-doped layer 108 is formed at a surface of the substrate 104, and a dielectric layer 112 (e.g., an oxide) is formed over the n-doped layer 108, which together form a substrate surface 116.
  • Metal contacts 120 are formed on the surface 116.
  • P-doped regions 124 are formed in the substrate 104, and a dielectric layer 128 and metal contacts 132 are formed over the p-doped regions 124.
  • the ideal solar cell 100 has a surface 116 that has a periodic inverted pyramid structure.
  • the textured surface 116 of the typical solar cell 150 often includes micro-cavities or micro-grooves.
  • Fig. 3 illustrates a system 300 for forming the improved texture according to embodiments of the invention.
  • the system 300 includes a wafer loading chamber 304 for loading wafers 308, a buffer stage/loadlock 308, an oxidation chamber 316, an interface 320, a silicon etch chamber 324, a buffer stage/loadlock 328, and a wafer unloading chamber 332.
  • the wafer 308 enters the system 300 at loading chamber 304, and passes through the buffer stage/loadlock 308 before entering the plasma oxidation chamber 316.
  • the wafer 308 undergoes an oxidation process in the plasma oxidation chamber 316.
  • the wafer 308 then passes through interface 320 before entering the silicon etch chamber 324.
  • the wafer 308 undergoes a dry etch process in the silicon etch chamber 324. After the dry etch process, the wafer 308 passes through the buffer stage/loadlock 328 before exiting the system 300 through the wafer unloading chamber 332.
  • Fig. 4 illustrates a flow diagram of a process for forming the textured surface 400 according to one embodiment of the invention.
  • the process 400 begins by performing a silicon surface oxidation process 404 to form a silicon oxide layer at the surface of the silicon wafer.
  • the silicon surface oxidation process 404 is a dry oxygen plasma process. It will be appreciated that other oxidation processes be used, such as for example, a wet oxidant chemistry oxidation, a thermal process oxidation, such as thermal oxidation and RTP oxidation, and the like.
  • a wet oxidant chemistry oxidation such as thermal oxidation and RTP oxidation, and the like.
  • thermal process oxidation such as thermal oxidation and RTP oxidation
  • the silicon wafer surface has a micro lattice boundary and lattice defect sites all over the surface, and it is usually easier to get a chemical reaction at the defect site.
  • a thicker oxidation layer is formed at the defect site.
  • the average thickness of the oxide layer formed with the oxidation process is about 25 A thick. It will be appreciated that the thickness may be any value or range of values between about 20 and about 50 A.
  • the oxidation process results in a surface having a reflectance of about 8.5%.
  • the reflectance of the silicon wafer is about 10%, as shown in Figs. 5C-5D.
  • about 10 to about 15A of the silicon oxide layer exists due to native oxidation and wet oxidation during the wet texturing process.
  • the process 400 continues by etching the silicon wafer 408 to remove a substantial portion of the silicon oxide layer formed by the oxidation process 404.
  • the entire oxidation layer over the non-defect sites is removed during the etch process 408, but the portion of the oxidation layer that is thicker over the defect sites remains.
  • etch 408 a major part of oxide layer (thin layer) is removed and only the thicker oxide area is left. It will be appreciated that a substantial portion of the oxidation layer over the non-defect sites may be removed.
  • the etch process 408 is a dry etch process.
  • Dry etching refers to the removal of material by exposing the material to a bombardment of ions that dislodge portions of the material from the exposed surface.
  • Exemplary dry etch techniques include reactive ion etching (RIE), plasma etching, physical sputtering, and the like.
  • the dry etch step is fluorine -based.
  • the dry etch step may use a mixture of SF 6 and 0 2 .
  • An exemplary process occurs for about 60 seconds or less at lOOmT at room temperature.
  • the process 400 continues by selectively etching the wafer 412 with high silicon etch selectivity to oxide.
  • the etch process condition has high silicon etch selectivity to oxide (i.e., a high silicon etch rate and a low oxide etch rate).
  • the remaining oxide layer i.e., the oxide layer over the defect sites that is not removed in the etch step 408) works as a mask during the silicon etching step 412.
  • etching of silicon begins while silicon under the remaining oxide area remains intact during etch 412.
  • Process step 412 uses the non-uniform oxide thickness characteristic for masking pattern generation.
  • Etch 412 may also be a dry etching process. This dry etching process typically etches
  • the selective etching continues as long as the oxide layer exists.
  • the silicon etch step is fluourine-based as well.
  • the process 400 may optionally continue by cleaning the silicon wafer to remove residuals 416.
  • a diluted HF solution is used to clean the wafer by dissolving any remaining silicon oxide material.
  • Figs. 6A-6B illustrate the wafer as cut
  • Figures 6C-6D illustrate the wafer after saw damage removal (SDR)
  • Figs. 6E-6F illustrate the wafer after post dry etch.
  • the texture size shown in Figs. 6E-6F is about lOOnm.
  • SDR removes the mechanically damaged silicon layer (damaged during the cutting process).
  • SDR is typically done using a diamond saw-type sawing machine, and is typically followed by a wet texturing process.
  • FIG. 7A illustrates reflectance of the surface after saw damage removal (23.6% reflectance), after saw damage removal and dry etch (11.4% reflectance) and after saw damage removal, dry etch and cleaning (11.8% reflectance).
  • Figs. 8A-8D show the wafer surface after saw damage removal (Fig. 8A), after dry etching (Figs. 8B-8C) and after residual removal (Fig. 8D).
  • the substrate or wafer may be made of other materials commonly used in the semiconductor or solar industry.
  • the above processes may be adapted to such different materials.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention porte sur des systèmes et des procédés qui permettent d'améliorer le facteur de réflexion de surface de tranches de silicium. Les systèmes et les procédés améliorent le facteur de réflexion de surface par la formation d'une surface texturée sur la tranche de silicium en exécutant des procédés d'oxydation de surface et de gravure à sec. L'oxydation de surface peut être effectuée à l'aide d'un procédé à plasma d'oxygène à sec. Le procédé de gravure à sec est effectué pour éliminer la couche d'oxyde formée par l'étape d'oxydation de surface et pour graver la couche de silicium en utilisant un masquage d'oxyde. La gravure à sec permet de former du silicium noir, ce qui réduit à un minimum ou élimine la réflexion ou la diffusion de lumière, conduisant finalement à un rendement énergétique de conversion plus élevé.
PCT/US2011/058846 2010-11-01 2011-11-01 Procédé de gravure à sec pour former une texture de surface sur tranche de silicium WO2012061436A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP11838708.3A EP2635513A4 (fr) 2010-11-01 2011-11-01 Procédé de gravure à sec pour former une texture de surface sur tranche de silicium
SG2013033428A SG190085A1 (en) 2010-11-01 2011-11-01 Dry etching method of surface texture formation on silicon wafer
CN201180057975.2A CN103237745B (zh) 2010-11-01 2011-11-01 在硅晶片上形成表面纹理的干法蚀刻方法
JP2013536933A JP2013544028A (ja) 2010-11-01 2011-11-01 シリコンウェハの表面テクスチャリング加工のドライエッチング方法優先権本出願は、”ｄｒｙｅｔｃｈｉｎｇｍｅｔｈｏｄｏｆｓｕｒｆａｃｅｔｅｘｔｕｒｅｆｏｒｍａｔｉｏｎｏｎｓｉｌｉｃｏｎｗａｆｅｒ”なるタイトルの２０１０年１１月１日出願の米国仮特許出願第６１／４０９，０６４号明細書の利益を請求し、そのすべての内容がここに参考文献として援用される。

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40906410P 2010-11-01 2010-11-01
US61/409,064 2010-11-01

Publications (3)

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WO2012061436A2 true WO2012061436A2 (fr) 2012-05-10
WO2012061436A3 WO2012061436A3 (fr) 2013-04-11
WO2012061436A4 WO2012061436A4 (fr) 2013-05-30

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US (1) US20120138139A1 (fr)
EP (1) EP2635513A4 (fr)
JP (1) JP2013544028A (fr)
CN (1) CN103237745B (fr)
SG (1) SG190085A1 (fr)
WO (1) WO2012061436A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2579321A2 (fr) 2011-10-06 2013-04-10 Altis Semiconductor Procédé de fabrication d'un substrat semi-conducteur structuré
WO2015186064A1 (fr) * 2014-06-04 2015-12-10 Université D'aix-Marseille Procede de texturation aleatoire d'un substrat semi-conducteur
CN110491971A (zh) * 2019-08-22 2019-11-22 东方环晟光伏（江苏）有限公司 一种大尺寸叠瓦电池制绒工艺

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9867269B2 (en) 2013-03-15 2018-01-09 Starfire Industries, Llc Scalable multi-role surface-wave plasma generator
WO2019102073A1 (fr) * 2017-11-24 2019-05-31 Aalto-Korkeakoulusäätiö Sr Structure semi-conductrice photovoltaïque
CN109037396A (zh) * 2018-06-25 2018-12-18 浙江师范大学 一种高少子寿命黑硅的制备方法
CN110783417B (zh) * 2019-11-08 2021-06-29 国家纳米科学中心 一种硅表面制作密度可调的锥状陷光结构的方法及制得的黑硅

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01297822A (ja) * 1988-05-25 1989-11-30 Matsushita Electron Corp 半導体装置の製造方法
JPH1050674A (ja) * 1996-08-02 1998-02-20 Nissan Motor Co Ltd 光吸収膜の形成方法
JPH11214356A (ja) * 1998-01-29 1999-08-06 Sony Corp シリコン基板のドライエッチング方法
JPH11312665A (ja) * 1998-04-27 1999-11-09 Kyocera Corp 半導体基板の粗面化法
JP3208384B2 (ja) * 1999-06-25 2001-09-10 三洋電機株式会社 半導体素子の製造方法
KR100684657B1 (ko) * 2005-05-04 2007-02-22 (주)울텍 태양전지 디바이스 제조 방법
US8168465B2 (en) * 2008-11-13 2012-05-01 Solexel, Inc. Three-dimensional semiconductor template for making high efficiency thin-film solar cells
JP2008198629A (ja) * 2007-02-08 2008-08-28 Mitsubishi Electric Corp 表面処理方法および太陽電池セル
JP2009267111A (ja) * 2008-04-25 2009-11-12 Tokyo Electron Ltd 半導体デバイスの製造方法、製造装置、コンピュータプログラム、及びコンピュータ可読記憶媒体
US8309446B2 (en) * 2008-07-16 2012-11-13 Applied Materials, Inc. Hybrid heterojunction solar cell fabrication using a doping layer mask
TW201027784A (en) * 2008-10-07 2010-07-16 Applied Materials Inc Advanced platform for processing crystalline silicon solar cells
US8288195B2 (en) * 2008-11-13 2012-10-16 Solexel, Inc. Method for fabricating a three-dimensional thin-film semiconductor substrate from a template
JP4968861B2 (ja) * 2009-03-19 2012-07-04 東京エレクトロン株式会社 基板のエッチング方法及びシステム
CN101800264B (zh) * 2010-02-20 2012-01-18 山东力诺太阳能电力股份有限公司 一种晶体硅太阳能电池干法刻蚀制绒工艺

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
None
See also references of EP2635513A4

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2579321A2 (fr) 2011-10-06 2013-04-10 Altis Semiconductor Procédé de fabrication d'un substrat semi-conducteur structuré
EP2579321B1 (fr) 2011-10-06 2016-02-24 Altis Semiconductor Procédé de fabrication d'un substrat semi-conducteur structuré
WO2015186064A1 (fr) * 2014-06-04 2015-12-10 Université D'aix-Marseille Procede de texturation aleatoire d'un substrat semi-conducteur
FR3022070A1 (fr) * 2014-06-04 2015-12-11 Univ Aix Marseille Procede de texturation aleatoire d'un substrat semiconducteur
CN110491971A (zh) * 2019-08-22 2019-11-22 东方环晟光伏（江苏）有限公司 一种大尺寸叠瓦电池制绒工艺
CN110491971B (zh) * 2019-08-22 2024-05-31 环晟光伏(江苏)有限公司 一种大尺寸叠瓦电池制绒工艺

Also Published As

Publication number Publication date
WO2012061436A3 (fr) 2013-04-11
WO2012061436A4 (fr) 2013-05-30
US20120138139A1 (en) 2012-06-07
SG190085A1 (en) 2013-06-28
CN103237745B (zh) 2016-05-04
EP2635513A4 (fr) 2014-04-16
JP2013544028A (ja) 2013-12-09
EP2635513A2 (fr) 2013-09-11
CN103237745A (zh) 2013-08-07

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