WO2012054642A1 - Procédé et appareil à utiliser dans l'amélioration de la linéarité de mosfet à l'aide de dissipateur de charge accumulée - réduction d'ondulation harmonique - Google Patents

Procédé et appareil à utiliser dans l'amélioration de la linéarité de mosfet à l'aide de dissipateur de charge accumulée - réduction d'ondulation harmonique Download PDF

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Publication number
WO2012054642A1
WO2012054642A1 PCT/US2011/056942 US2011056942W WO2012054642A1 WO 2012054642 A1 WO2012054642 A1 WO 2012054642A1 US 2011056942 W US2011056942 W US 2011056942W WO 2012054642 A1 WO2012054642 A1 WO 2012054642A1
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Prior art keywords
acs
accumulated charge
acc
gate
mosfet
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PCT/US2011/056942
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English (en)
Inventor
Christopher N. Brindle
Jie Deng
Chieh-Kai Yang
Alper Genc
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Peregrine Semiconductor Corporation
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Priority to JP2013535054A priority Critical patent/JP6006219B2/ja
Priority to DE112011103554T priority patent/DE112011103554T5/de
Publication of WO2012054642A1 publication Critical patent/WO2012054642A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Definitions

  • the present invention relates to metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Semiconductor-On-Sapphire (“SOS”) substrates.
  • MOS metal-oxide-semiconductor
  • SOI Semiconductor-On-Insulator
  • SOS Semiconductor-On-Sapphire
  • an SOI (or SOS) MOSFET is adapted to control accumulated charge and thereby improve linearity of circuit elements.
  • MOSFETs are described herein as applicable for use in SOI MOSFETs, it will be appreciated by those skilled in the electronic device design arts that the present teachings are equally applicable for use in SOS MOSFETs.
  • the present teachings can be used in the implementation of MOSFETs using any convenient semiconductor-on-insulator technology, including silicon-on- insulator technology.
  • the inventive MOSFETs described herein can be implemented using compound semiconductors on insulating substrates.
  • Such compound semiconductors include, but are not limited to, the following: Silicon Germanium (SiGe), Gallium Arsenide (GaAs), Indium Phosphide (InP), Gallium Nitride (GaN), Silicon Carbide (SiC), and II- VI compound semiconductors, including Zinc Selenide (ZnSe) and Zinc Sulfide (ZnS).
  • the present teachings also may be used in implementing MOSFETs fabricated from thin- film polymers.
  • Organic thin-film transistors (OTFTs) utilize a polymer, conjugated polymers, oligomers, or other molecules to form the insulting gate dielectric layer.
  • the present inventive methods and apparatus may be used in implementing such OTFTs.
  • FIGURE 1 shows a cross-sectional view of an exemplary prior art SOI NMOSFET 100.
  • the prior art SOI NMOSFET 100 includes an insulating substrate 118 that may comprise a buried oxide layer, sapphire, or other insulating material.
  • a source 112 and drain 116 of the NMOSFET 100 comprise N+ regions (i.e.
  • the NMOSFET 100 also includes a gate oxide 110 positioned over the body 114.
  • the gate oxide 110 typically comprises a thin layer of an insulating dielectric material such as Si0 2 .
  • the gate oxide 110 electrically insulates the body 114 from a gate 108 positioned over the gate oxide 110.
  • the gate 108 comprises a layer of metal or, more typically, polysilicon
  • a source terminal 102 is operatively coupled to the source 112 so that a source bias voltage "Vs" may be applied to the source 112.
  • a drain terminal 106 is operatively coupled to the drain 116 so that a drain bias voltage "Vd” may be applied to the drain 116.
  • a gate terminal 104 is operatively coupled to the gate 108 so that a gate bias voltage "Vg" may be applied to the gate 108.
  • an inversion channel is formed in the channel region of the body 114.
  • the polarity of carriers in the inversion channel is identical to the polarity of carriers in the source and drain.
  • the carriers in the channel comprise N polarity carriers.
  • the carriers in the channel of turned on (i.e. , conducting) PMOSFETs comprise P polarity carriers.
  • accumulated charge is used herein to refer to gate-bias induced carriers that may accumulate in the body of an off-state MOSFET, even if the majority carriers in the body do not have the same polarity as the accumulated charge. This situation may occur, for example, in an off-state depletion mode NMOSFET, wherein the accumulated charge may comprise holes (i.e. , having P polarity) even though the body doping is N- rather than P-.
  • the accumulated charge is opposite in polarity to the polarity of carriers in the channel. Because, as described above, the polarity of carriers in the channel is identical to the polarity of carriers in the source and drain, the polarity of the accumulated charge 120 is also opposite to the polarity of carriers in the source and drain. For example, under the operating conditions described above, holes (having "P" polarity) accumulate in off-state NMOSFETs, and electrons (having "N” polarity) accumulate in off-state PMOSFETs. Therefore, a MOSFET device is defined herein as operating within the "accumulated charge regime" when the MOSFET is biased to operate in an off-state, and when carriers having opposite polarity to the channel carriers are present in the channel region.
  • a MOSFET is defined as operating within the accumulated charge regime when the MOSFET is biased to operate in an off-state, and when carriers are present in the channel region having a polarity that is opposite the polarity of the source and drain carriers.
  • Vs and Vd may comprise nonzero bias voltages.
  • Vg must be sufficiently negative to both Vs and Vd (in order for Vg to be sufficiently negative to V ⁇ , for example) in order to bias the NMOSFET in the off-state.
  • bias voltages may be used to practice the present teachings. As described below in more detail, the present disclosed method and apparatus contemplates use in any SOI MOSFET device biased to operate in the accumulated charge regime.
  • a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime.
  • An accumulated charge sink (ACS) operatively coupled to the body of the SOI MOSFET, receives accumulated charge generated in the body, thereby reducing the nonlinearity of the net source-drain capacitance of the SOI MOSFET.
  • an accumulated charge control (ACC) floating body metal-oxide- semiconductor field effect transistor comprises: a gate; a drain; a source; a body, where the body has a gate modulated conductive channel between the source and the drain; a gate oxide layer positioned between the gate and the body; and an accumulated charge sink (ACS) operatively coupled to the body, wherein the ACS comprises material selected to shift a capacitance versus voltage inflection inside the ACS away from a desired region of operation; where accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in an accumulated charge regime, and where the gate modulated conductive channel, source, and drain have carriers of identical polarity when the MOSFET is biased to operate in an on-state and wherein the MOSFET operates in the accumulated charge regime when the MOSFET is biased to operate in a off-state and when the accumulated charge has a polarity that is opposite to the polarity of the source, drain
  • an ACC MOSFET adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprises: a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, where the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region proximate and underneath the gate oxide layer; b) a first accumulated charge sink positioned proximate a first distal end of the floating body, where the first ACS is in electrical communication with the floating body, and wherein, when the MOSFET is operated in the accumulated charge regime, a first ACS bias voltage is applied to the first ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the first ACS; c) a second accumulated charge sink positioned
  • an ACC MOSFET adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprises: a) a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, where the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is operated in a non-conducting or near non-conducting state and charge accumulates within the body in a region proximate and underneath the gate oxide layer; b) a plurality of accumulated charge sinks positioned proximate portions of the floating body, wherein each accumulated charge sink of the plurality of accumulated charge sinks is electrically coupled to the floating body, and where, when the MOSFET is operated in the accumulated charge regime, ACS bias voltages are applied to each accumulated charge sink to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the plurality of accumulated charge sinks
  • FIGURE 2B is a schematic of an exemplary simplified RF switching circuit implemented using prior art SOI MOSFETs such as the prior art SOI NMOSFET of FIGURE 1.
  • FIGURES 3A and 3B are simplified schematic diagrams of a top view of an improved SOI NMOSFET adapted to control accumulated charge in accordance with the present teachings.
  • FIGURE 3C is a cross-sectional perspective schematic of an improved SOI NMOSFET adapted to control accumulated charge showing gate, source, drain and accumulated charge sink (ACS) terminals.
  • ACS accumulated charge sink
  • FIGURE 3D is a simplified top view schematic of an improved SOI NMOSFET adapted to control accumulated charge having an accumulated charge sink (ACS) electrically coupled to a P+ region.
  • ACS accumulated charge sink
  • FIGURE 3E is a simplified top view schematic of an improved SOI NMOSFET adapted to control accumulated charge and showing a cross-sectional view line A-A' taken along approximately a center of the SOI NMOSFET.
  • FIGURE 3F is a cross-sectional view of the improved SOI NMOSET of FIGURE 3E taken along the A-A' view line of FIGURE 3E.
  • FIGURE 3G is a cross-sectional view of the improved SOI NMOSET of FIGURES 3A-3B.
  • FIGURE 3H is a simplified top view schematic of an SOI NMOSFET illustrating a region of increased threshold voltage that can occur in prior art MOSFETs and in some embodiments of the improved SOI MOSFET due to manufacturing processes.
  • FIGURE 31 is a plot of inversion channel charge as a function of applied gate voltage when a region of increased threshold voltage is present in an SOI MOSFET.
  • FIGURE 3J is a simplified top view schematic of an improved SOI NMOSFET adapted to control accumulated charge and configured in a "T-gate" configuration.
  • FIGURE 3K is a simplified top view schematic of an improved SOI NMOSFET adapted to control accumulated charge and configured in an "H-gate" configuration.
  • FIGURE 4A is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge embodied as a four terminal device.
  • FIGURE 4B is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a gate terminal.
  • ACS accumulated charge sink
  • FIGURE 4D is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a control circuit.
  • ACS accumulated charge sink
  • FIGURE 4E is a simplified schematic of an exemplary RF switch circuit implemented using the four terminal ACC NMOSFET of FIGURE 4D, wherein the ACS terminal is driven by an external bias source.
  • FIGURE 4F is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a clamping circuit.
  • ACS accumulated charge sink
  • FIGURE 4G is a simplified schematic of an improved SOI NMOSFET adapted to control accumulated charge, embodied as a four terminal device, wherein an accumulated charge sink (ACS) terminal is coupled to a gate terminal via a diode in parallel with a capacitor.
  • ACS accumulated charge sink
  • FIGURE 5A is a schematic of an exemplary prior art single pole, single throw (SPST) radio frequency (RF) switch circuit.
  • FIGURE 5B is a schematic of an RF switch circuit adapted for improved performance using accumulated charge control, wherein the gate of a shunting SOI NMOSFET is coupled to an accumulated charge sink (ACS) terminal.
  • SPST single pole, single throw
  • ACS accumulated charge sink
  • FIGURE 5C is a schematic of an RF switch circuit adapted for improved performance using accumulated charge control, wherein the gate of a shunting SOI NMOSFET is coupled to an accumulated charge sink (ACS) terminal via a diode.
  • ACS accumulated charge sink
  • FIGURE 5D is a schematic of an RF switch circuit adapted for improved performance using accumulated charge control, wherein the accumulated charge sink (ACS) terminal is coupled to a control circuit.
  • ACS accumulated charge sink
  • FIGURE 6 is a schematic of an RF switch circuit including stacked MOSFETs, adapted for improved performance using accumulated charge control, wherein the accumulated charge sink (ACS) terminals of the shunting stacked MOSFETs are coupled to a control signal.
  • ACS accumulated charge sink
  • FIGURE 7 shows a flowchart of an exemplary method of improving the linearity of an SOI MOSFET device using an accumulated charge sink in accordance with the present disclosure.
  • FIGURE 8 shows a simplified circuit schematic of an exemplary embodiment of an RF switch circuit made in accordance with the present disclosure, wherein the RF switch circuit includes drain-to-source resistors between the drain and source of the ACC MOSFETs.
  • FIGURE 9 shows a simplified schematic of an exemplary single-pole double-throw (SPDT) RF switch circuit made in accordance with the present disclosure, wherein drain-to- source resistors are shown across the switching ACC SOI MOSFETs.
  • SPDT single-pole double-throw
  • FIGURE 10A shows the second order harmonic response on an ACC MOSFET with various dopants and dopant levels in the ACS region.
  • FIGURE 10B shows the third order harmonic response on an ACC MOSFET with various dopants and dopant levels in the ACS region.
  • FIGURE 12 shows a schematic of an exemplary H-gate dual body contact (ACS) FET device without an AC short present at the bottom of the FET device.
  • ACS H-gate dual body contact
  • FIGURE 13 shows a schematic of an exemplary H-gate dual body contact (ACS) FET device with the AC short shown at the bottom of the FET device.
  • ACS H-gate dual body contact
  • FIGURE 14A shows an exemplary dual ACS contact test structure layout in accordance with the present methods and apparatus.
  • FIGURE 14B shows a magnified version of the AC short shown at the bottom of the FET stack shown in FIGURE 14A.
  • FIGURE 15 shows an exemplary simplified layout of a dual body ACS ACC MOSFET with an AC short made in accordance with the present methods and apparatus.
  • the MOSFET As described above in the background, no matter what mode of operation the MOSFET employs ⁇ i.e., enhancement mode or depletion mode), under some circumstances, when a MOSFET is operated in an off-state with a nonzero gate bias voltage applied with respect to the source and drain, an accumulated charge may occur under the gate. According to the present teachings, as described above when the MOSFET is in an off-state, and when carriers are present in the channel region having a polarity that is opposite the polarity of the source and drain carriers, the MOSFET is defined herein as operating in the accumulated charge regime.
  • FIGURE 2A is a simplified schematic of an electrical model 200 showing the off-state impedance (or conversely, conductance) characteristics of the exemplary prior art SOI NMOSFET 100 of FIGURE 1. More specifically, the model 200 shows the impedance characteristics from the source 112 to the drain 1 16 when the NMOSFET 100 is operated in the off-state. Because the drain-to-source off-state impedance characteristic of the NMOSFET 100 is primarily capacitive in nature, it is referred to herein as the drain-to-source off-state capacitance (C 0ff ).
  • C 0ff drain-to-source off-state capacitance
  • the junction between the drain 116 and the body 114 (i.e., the drain-body junction 220) of the off-state NMOSFET 100 can be represented by a junction diode 210 and a junction capacitor 216, configured as shown.
  • the body 114 is represented simply as an impedance 212 that is present between the source-body junction 218 and the drain-body junction 220.
  • a capacitor 206 represents the capacitance between the gate 108 and the body 114.
  • a capacitor 202 represents the capacitance between the source 112 and the gate 108, and another capacitor 204 represents the capacitance between the drain 116 and the gate 108.
  • a substrate capacitance due to the electrical coupling between the source 112 and the drain 116 (through the insulating substrate 118 shown in FIGURE 1) is taken to be negligibly small in the exemplary description set forth below, and therefore is not shown in the electrical model 200 of FIGURE 2A.
  • the body 114 is depleted of charge carriers.
  • the body impedance 212 is analogous to the impedance of an insulator, and the electrical conductance through the body 114 is very small (i.e., the NMOSFET 100 is in the off- state). Consequently, the principal contributions to the drain-to-source off-state capacitance C 0ff are provided by the capacitors 202 and 204.
  • the capacitors 202 and 204 are only slightly voltage dependent, and therefore do not significantly contribute to a nonlinear response that adversely affects harmonic generation and intermodulation distortion characteristics.
  • DC and low-frequency current flow through the SOI NMOSFET 100 is prevented by the diode properties of the source- body junction 218 and the drain-body junction 220, as represented by the junction diodes 208 and 210, respectively. That is, because the junction diodes 208 and 210 are anti-series (i.e., "back- to-back") in this case, no DC or low-frequency currents flow through the SOI NMOSFET 100. However, high-frequency currents may flow through the SOI NMOSFET 100 via the capacitances of the source-body junction 218 and the drain-body junction 220, as represented by the junction capacitors 214 and 216, respectively.
  • the junction capacitors 214 and 216 are voltage dependent because they are associated with junctions between n-type and p-type regions. This voltage dependence results from the voltage dependence of the width of the depletion region of the junction between the n-type and p-type regions. As a bias voltage is applied to the NMOSFET, the width of the depletion region of the junction between the n-type and p-type regions is varied. Because the capacitance of the junction depends on the width of the junction depletion region, the capacitance also varies as a function of the bias applied across the junction (i.e. , the capacitance is also voltage dependent).
  • the capacitors 202 and 204 may also have a voltage dependence caused by the presence of the accumulated charge 120. Although the complex reasons for this voltage dependence are not described in detail herein, persons skilled in the arts of electronic devices shall understand that electric field regions (e.g. , electric field regions 122 and 124 described above with reference to FIGURE 1) may be affected by the response of the accumulated charge and its response to an applied Vds, thereby causing a voltage dependence of capacitors 202 and 204. An additional nonlinear effect may occur due to a direct capacitance (not shown) between the source 112 and the drain 116.
  • electric field regions e.g. , electric field regions 122 and 124 described above with reference to FIGURE 1
  • An additional nonlinear effect may occur due to a direct capacitance (not shown) between the source 112 and the drain 116.
  • RF switch linearity is an important design parameter in many applications. Improved switch linearity leads to improved suppression of harmonic and intermodulation (IM) distortion of signals processed by the switch. These improved switch characteristics can be critically important in some applications such as use in cellular communication devices.
  • IM harmonic and intermodulation
  • the well known GSM cellular communication system standard imposes stringent linearity, harmonic and intermodulation suppression, and power consumption requirements on front-end components used to implement GSM cell phones.
  • One exemplary GSM standard requires that all harmonics of a fundamental signal be suppressed to below -30 dBm at frequencies up to 12.75 GHz. If harmonics are not suppressed below these levels, reliable cell phone operation can be significantly adversely impacted (e.g. , increased dropped calls or other communication problems may result due to harmonic and intermodulation distortion of the transmit and receive signals).
  • the RF switching function is generally implemented in the cell phone front-end components, improvements in the RF switch linearity, harmonic and intermodulation suppression, and power consumption performance characteristics is highly desirable. A description of how the non-linear behavior of the off-state capacitance C 0ff of the prior art MOSFETs adversely affects these RF switch characteristics is now described with reference to FIGURE 2B.
  • the switching MOSFET 254 is thereby enabled when the shunting MOSFETs 260a-260e are disabled, and vice versa. As shown in the exemplary embodiment of the RF switch 250 of FIGURE 2B, the switching MOSFET 254 is enabled by applying a gate bias voltage of +2.5V (via the first switch control signal). The shunting MOSFETs 260a-260e are disabled by applying a gate bias voltage of -2.5V (via the second switch control signal).
  • the RF signal 252 propagates through the switching MOSFET 254, through the transmission path 256, and to the antenna 258.
  • the shunting MOSFETS 260a-260e comprise prior art SOI (or SOS) MOSFETs, such as the SOI NMOSFET 100 (FIGURE 1)
  • SOI MOSFET bodies i.e., when the SOI MOSFETs operate in the accumulated charge regime as described above.
  • the accumulated charge can produce nonlinear behavior in the off-state capacitance C 0ff of the SOI MOSFETs when AC voltages are applied to the MOSFETs.
  • harmonic distortion and EVID of the RF signal is a major disadvantage of the prior art RF switch circuits implemented using the prior art SOI MOSFET devices.
  • harmonics and IMD of the RF signal must be suppressed to levels that heretofore have been difficult or impossible to achieve using prior art SOI MOSFET devices.
  • prior art switches typically have only a 6 dB margin to the GSM third order harmonics suppression requirement of less than -30 dBm.
  • Very low even order harmonic distortion is also desirable in GSM systems as the second order harmonic of the GSM transmit band also resides in the DCS receive band. Suppression of odd order (e.g. , third order) harmonics of the RF signal, however, is desirable and improvements in that regard are needed.
  • BVDSS drain-to-source breakdown voltage
  • the present disclosure describes methods and apparatuses for improving semiconductor device linearity (e.g., reducing adverse harmonic distortion and IMD effects) in SOI MOSFETs.
  • the method and apparatus improves the linearity and controls the harmonic distortion and IMD effects of the MOSFET devices by reducing the accumulated charge in the bodies of the MOSFET devices.
  • the present method and apparatus reduces or otherwise controls the accumulated charge in the MOSFET bodies using an accumulated charge sink (ACS) that is operatively coupled to the MOSFET body.
  • ACS accumulated charge sink
  • the present method and apparatus entirely removes all of the accumulated charge from the bodies of the MOSFET devices.
  • the present disclosure is particularly applicable to FETs and associated applications benefiting from a fully depleted channel when the FET is operated in the off-state, wherein an accumulated charge may result.
  • the disclosed method and apparatus for use in improving the linearity of MOSFETs also finds applicability for use with partially depleted channels.
  • the doping and dimensions of the body vary widely.
  • the body comprises silicon having a thickness of approximately 100 angstroms to approximately 2,000 angstroms.
  • dopant concentration within the FET bodies ranges from no more than that associated with intrinsic silicon to approximately 1 X 10 18 active dopant atoms per cm 3 , resulting in fully-depleted transistor operation.
  • dopant concentration within the FET bodies ranges from 1 x 10 18 to 1 x 1019 active dopant atoms per cm 3 and/or the silicon comprising the body ranges from a thickness of 2000 angstroms to many micrometers, resulting in partially-depleted transistor operation.
  • the present disclosed method and apparatus for use in improving linearity of MOSFETs can be used in MOSFETs implemented in a wide variety of dopant concentrations and body dimensions. The present disclosed method and apparatus therefore is not limited for use in MOSFETs implemented using the exemplary dopant concentrations and body dimensions as set forth above.
  • accumulated charge within a FET body is reduced using control methodologies and associated circuitry. In one embodiment all of the accumulated charge is removed from the FET body. In other embodiments, the accumulated charge is reduced or otherwise controlled. In one embodiment, holes are removed from the FET body, whereas in another embodiment, electrons are removed from the FET body, as described below in more detail. By removing holes (or electrons) from the FET body using the novel and nonobvious teachings of the present disclosure, voltage induced variations in the parasitic capacitances of the off- state FETs are reduced or eliminated, thereby reducing or eliminating nonlinear behavior of the off- state FETs.
  • Accumulated charge control not only facilitates a beneficial overall reduction in the FET off-state capacitance C Q ff (as described above with reference to FIGURE 2A and below with reference to FIGURE 4H), it also facilitates a reduction in C Q ff variations that can occur over time in the presence of a time varying V ds bias voltage.
  • a reduction of undesirable harmonics generation and intermodulation distortion in RF switch circuits is obtained using SOI MOSFETs made in accordance with the present disclosure.
  • Improved SOI MOSFET power handling, linearity, and performance are achieved by devices made in accordance with the present teachings. While the methods and apparatuses of the present disclosure are capable of fully removing accumulated charge from the FET bodies, those skilled in the electronic device design arts shall appreciate that any reduction of accumulated charge is beneficial.
  • SOI systems include any semiconductor architecture employing semiconductor-containing regions positioned above an underlying insulating substrate. While any suitable insulating substrate can be used in a SOI system, exemplary insulating substrates include silicon dioxide (e.g. , a buried oxide layer supported by a silicon substrate, such as that known as Separation by Implantation of Oxygen (SEVIOX)), bonded wafer (thick oxide), glass, and sapphire. As noted above, in addition to the commonly used silicon-based systems, some embodiments of the present disclosure may be implemented using silicon-germanium (SiGe), wherein the SiGe is used equivalently in place of Si.
  • SiGe silicon-germanium
  • an ACS is used to remove or otherwise control accumulated charge (referenced as 120 in FIGURE 1 described above) from the MOSFETs when the MOSFETs are configured to operate in the accumulated charge regime.
  • SOI or SOS
  • ACC Accumulated Charge Control
  • the ACC MOSFETs are useful in improving performance of many circuits, including RF switching circuits.
  • FIGURES 3A-3K Various characteristics and possible configurations of the exemplary ACC MOSFETs are described in detail below with reference to FIGURES 3A-3K. This section also describes how the exemplary ACS implementations of the present disclosure differ from the body contacts of the prior art.
  • FIGURE 4A The ACC MOSFET is shown schematically embodied as a four-terminal device in FIGURE 4A.
  • FIGURES 4B-4G show various exemplary simple circuit configurations that can be used in removing the accumulated charge from the ACC MOSFET when it operates in an accumulated charge regime. The operation of the simplified circuit configurations is described in more detail below with reference to FIGURES 4A-4G.
  • the improvement in off-state capacitance C 0ff of the ACC MOSFETs, as compared with the off-state capacitance of the prior art SOI MOSFETs, is described below with reference to FIGURE 4H.
  • FIGURES 5B-5D The operation of various exemplary RF switch circuits implemented using the ACC MOSFETs of the present disclosure is described below with reference to the circuit schematics of FIGURES 5B-5D. Further, an exemplary RF switch circuit using stacked ACC MOSFETs (for increased power handling) of the present disclosure is described below with reference to FIGURE 6. An exemplary method of improving the linearity of an SOI MOSFET using an accumulated charge sink (ACS) is described with reference to FIGURE 7. Finally, exemplary fabrication methods that may be used to manufacture the ACC MOSFET are described. The various exemplary ACS implementations and structures that can be used to practice the disclosed method and apparatus are now described with reference to FIGURES 3A-3K.
  • FIGURES 3A and 3B are simplified schematic diagrams of a top view of an Accumulated Charge Control (ACC) SOI NMOSFET 300 adapted to control accumulated charge 120 (FIGURE 1) in accordance with the present disclosure.
  • a gate contact 301 is coupled to a first end of a gate 302.
  • a gate oxide (not shown in FIGURE 3 A but shown in FIGURE 1) and a body 312 (shown in FIGURE 3B) are positioned under the gate 302.
  • a source 304 and a drain 306 comprise N+ regions.
  • the ACC NMOSFET 300 includes an accumulated charge sink (ACS) 308 comprising a P- region.
  • ACS accumulated charge sink
  • the ACS 308 is coupled to and is in electrical communication with the body 312 which also comprises a P- region.
  • An electrical contact region 310 provides electrical connection to the ACS 308.
  • the electrical contact region 310 comprises a P+ region. As shown in FIGURE 3A, the electrical contact region 310 is coupled to and is in electrical communication with the ACS 308.
  • the electrical contact region 310 may be used to facilitate electrical coupling to the ACS 308 because in some embodiments it may be difficult to make a direct contact to a lightly doped region.
  • the ACS 308 and the electrical contact region 310 may be coextensive.
  • the electrical contact region 310 comprises an N+ region.
  • the electrical contact region 310 functions as a diode connection to the ACS 308, which prevents positive current flow into the ACS 308 (and also prevents positive current flow into the body 312) under particular bias conditions, as described below in more detail.
  • FIGURE 3B is an alternative top view of the ACC SOI NMOSFET 300 of FIGURE 3 A, illustrating the ACC NMOSFET 300 without its gate contact 301, gate 302, and gate oxide being visible. This view allows the body 312 to be visible.
  • FIGURE 3B shows the coupling of the ACS 308 to one end of the body 312.
  • the body 312 and the ACS 308 comprise a combined P- region that may be produced by a single ion-implantation step.
  • the body 312 and ACS 308 comprise separate P- regions that are coupled together.
  • the ACC NMOSFET 300 of FIGURES 3A and 3B can be implemented as an ACC PMOSFET simply by reversing the dopant materials used to implement the various FET component regions (i.e., replace p-type dopant material with n-type dopant material, and vice versa). More specifically, in an ACC PMOSFET, the source and drain comprise P+ regions, and the body comprises an N- region. In this embodiment, the ACS 308 also comprises an N- region. In some embodiments of the ACC PMOSFET, the electrical contact region 310 may comprise an N+ region. In other embodiments of the ACC PMOSFETs, the region 310 comprises a P+ region, which functions as a diode connection to the ACS 308 and thereby prevents current flow into the ACS 308 under particular bias conditions.
  • the ACS 308 used to implement ACC SOI MOSFETs includes novel features in structure, function, operation and design that distinguish it from the so-called “body contacts” (also sometimes referred to as “body ties”, usually when the "body contact” is directly connected to the source) that are well known in the prior art.
  • Exemplary references relating to body contacts used in prior art SOI MOSFETs include the following: (1) F. Hameau and O. Rozeau, Radio-Frequency Circuits Integration Using CMOS SOI 0.25 ⁇ Technology," 2002 RF IC Design Workshop Europe, 19 - 22 March 2002, Grenoble, France; (2) J. R. Cricci et al., "Silicon on Sapphire MOS Transistor," U. S. Patent No. 4,053,916, October 11, 1977; (3) O. Rozeau et al., "SOI Technologies Overview for Low-Power Low- Voltage Radio-Frequency Applications,” Analog Integrated Circuits and Signal Processing, 25, pp. 93-114, Boston, MA, Kluwer Academic Publishers, Nov.
  • applications such as RF switch circuits, may use SOI MOSFETs operated with off-state bias voltages, for which accumulated charge may result.
  • the SOI MOSFETs are defined herein as operating within the accumulated charge regime when the MOSFETs are biased in the off-state, and when carriers having opposite polarity to the channel carriers are present in the channel regions of the MOSFETs.
  • the SOI MOSFETs may operate within the accumulated charge regime when the MOSFETs are partially depleted yet still biased to operate in the off-state.
  • Significant benefits in improving nonlinear effects on source-drain capacitance can be realized by removing or otherwise controlling the accumulated charge according to the present teachings.
  • the ACS 308 operates effectively to remove or otherwise control the accumulated charge from the SOI NMOSFET 300 using a high impedance connection to and throughout the body 312.
  • High impedance ACSs may be used because the accumulated charge 120 is primarily generated by phenomena (e.g. , thermal generation) that take a relatively long period of time to produce significant accumulated charge.
  • a typical time period for producing non-negligible accumulated charge when the NMOSFET operates in the accumulated charge regime is approximately a few milliseconds or greater.
  • Such relatively slow generation of accumulated charge corresponds to very low currents, typically less than 100 nA/mm of transistor width. Such low currents can be effectively conveyed even using very high impedance connections to the body.
  • the ACS 308 is implemented with a connection having a resistance of greater than 10 6 ohms. Consequently, the ACS 308 is capable of effectively removing or otherwise controlling the accumulated charge 120 even when implemented with a relatively high impedance connection, relative to the low impedance prior art body contacts.
  • the relative rates for electron-hole pair generation by impact ionization versus the pair generation processes causing accumulated charge can be estimated from the roll-off frequencies for the two phenomena.
  • reference (3) cited above indicates roll-off frequencies for impact ionization effects in the range of 10 5 Hz.
  • a roll-off frequency for the accumulated charge effects has been observed to be in the range of 10 Hz or less, as indicated by recovery times for odd harmonics.
  • impact ionization primarily occurs when the SOI MOSFET operates in an on- state
  • the effects of impact ionization can be amplified by on-state transistor operation.
  • Low impedance body contacts to and throughout a body region is even more critical in these environments in order to control the effects of impact ionization under the on-state conditions.
  • the ACS 308 of the present teachings removes or otherwise controls the accumulated charge only when the ACC SOI MOSFET operates in the accumulated charge regime.
  • the FET is in the off-state in this regime, so there is no requirement to remove impact ionization as amplified by an on- state FET. Therefore, a high impedance ACS 308 is perfectly adequate for removing the accumulated charge under these operating conditions.
  • the prior art requirements for low impedance body connections results in numerous problems of implementation that are overcome by the present teachings, as described below in more detail.
  • the ACS 308 may be implemented with much lower source-to-drain parasitic capacitance as compared to the body contacts of the prior art.
  • the above-described low impedance connection to the SOI MOSFET body required of the prior art body contacts necessitates proximity of the contacts to the entire body. This may require a plurality body contact "fingers" that contact the body at different locations along the body.
  • the low impedance connection to the body also necessitates proximity of the prior art body contacts to the source and drain. Because of parasitic capacitances produced by such body contacts, the cited prior art references teach away from the use of such structures for many high frequency applications such as RF.
  • the ACS 308 of the present disclosure may be positioned a selected distance away from the source 304 and the drain 306, and the ACS 308 may also be coupled to the body 312 at a first distal end of the body 312 (shown in FIGURES 3A and 3B). Arranged in this manner, the ACS 308 makes minimal contact (as compared to the prior art body contacts that may contact the body at many locations along the body) with the body 312.
  • This configuration of the ACS 308 with the MOSFET eliminates or greatly reduces the parasitic capacitances caused by a more proximate positioning of the ACS 308 relative to the source, drain, and body.
  • the ACS 308 may be implemented in SOI MOSFETs operated with a depleted channel. In general, the cited prior art references teach away from the use of body contacts for this environment (see, e.g. , reference (3), cited above).
  • the prior art does not teach how to effectively implement very large body widths (i.e. , much greater than approximately 10 ⁇ ).
  • the ACS 308 of the present disclosed device may be implemented in SOI MOSFETs having relatively large body widths. This provides improvements in on-state conductance and transconductance, insertion loss and fabrication costs, particularly for RF switch devices. According to the prior art teachings cited above, larger body widths adversely affect the efficient operation of body contacts because their impedances are necessarily thereby increased.
  • a plurality of fingers may be used to contact the body at different locations, the plurality of fingers adversely affects parasitic source-to-drain capacitances, as described above.
  • the present disclosure provides novel MOSFET devices, circuits and methods that overcome the limitations according to the prior art teachings as cited above.
  • FIGURE 3C is a cross- sectional perspective schematic of an ACC SOI NMOSFET 300' adapted to control accumulated charge in accordance with the disclosed method and apparatus.
  • the ACC NMOSFET 300' includes four terminals that provide electrical connection to the various FET component regions.
  • the terminals provide means for connecting external integrated circuit (IC) elements (such as metal leads, not shown) to the various FET component regions.
  • IC integrated circuit
  • Three of the terminals shown in FIGURE 3C are typically available in prior art FET devices.
  • the ACC NMOSFET 300' includes a gate terminal 302' that provides electrical connection to the gate 302.
  • the ACC NMOSFET 300' includes source and drain terminals 304', 306' that provide electrical connection to the source 304 and drain 306, respectively.
  • the terminals are coupled to their respective FET component regions (i.e., gate, drain and source) via so-called "ohmic" (i.e., low resistance) contact regions.
  • “ohmic” i.e., low resistance
  • the ACC NMOSFET 300' is adapted to control accumulated charge when the NMOSFET operates in the accumulated charge regime.
  • the ACC NMOSFET 300' includes a fourth terminal that provides electrical connection to the body 312, and thereby facilitates reduction (or other control) of the accumulated charge when the FET 300' operates in the accumulated charge regime. More specifically, and referring again to FIGURE 3C, the ACC NMOSFET includes a "body" terminal, or Accumulated Charge Sink (ACS) terminal 308'.
  • ACS Accumulated Charge Sink
  • the ACS terminal 308' provides an electrical connection to the ACS 308 (not shown in FIGURE 3C, but shown in FIGURES 3A and 3B) and to the body 312.
  • the ACS terminal 308' is shown in FIGURE 3C as being physically coupled to the body 312, those skilled in the electronic design arts shall understand that this depiction is for illustrative purposes only.
  • the direct coupling of the ACS terminal 308' to the body 312 shown in FIGURE 3C illustrates the electrical connectivity (i.e., not the physical coupling) of the terminal 308' with the body 312.
  • the other terminals i.e., terminals 302', 304' and 306'
  • FIGURE 3C are also shown in FIGURE 3C as being physically coupled to their respective FET component regions.
  • the ACS terminal 308' provides the electrical connection to the body 312 via coupling to the ACS 308 via the electrical contact region 310.
  • the present disclosure also contemplates embodiments where the coupling of the ACS terminal 308' is made directly to the body 312 (i.e., no intermediate regions exist between the ACS terminal 308' and the body 312).
  • the ACC NMOSFET 300' when the ACC NMOSFET 300' is biased to operate in the accumulated charge regime (i.e., when the ACC NMOSFET 300' is in the off-state, and there is an accumulated charge 120 of P polarity (i.e., holes) present in the channel region of the body 312), the accumulated charge is removed or otherwise controlled via the ACS terminal 308'.
  • the charge 312 can be removed or otherwise controlled by applying a bias voltage (V b (for "body”) or V ACS (ACS bias voltage)) to the ACS terminal 308'.
  • the ACS bias voltage V ACS applied to the ACS terminal 308' may be selected to be equal to or more negative than the lesser of the source bias voltage Vs and drain bias voltage Vd. More specifically, in some embodiments, the ACS terminal 308' can be coupled to various accumulated charge sinking mechanisms that remove (or "sink") the accumulated charge when the FET operates in the accumulated charge regime. Several exemplary accumulated charge sinking mechanisms and circuit configurations are described below with reference to FIGURES 4A-5D.
  • the ACC SOI NMOSFET 300' of FIGURE 3C can be biased to operate in the accumulated charge regime by applying specific bias voltages to the various terminals 302', 304', and 306'.
  • the source and drain bias voltages (Vs and Vd, respectively) are zero (i.e., the terminals 304' and 306' are connected to ground).
  • the ACC NMOSFET 300' operates in the off- state. If the ACC NMOSFET 300' continues to be biased in the off-state, the accumulated charge (holes) will accumulate in the body 312.
  • the accumulated charge can be removed from the body 312 via the ACS terminal 308'.
  • the ACS terminal 308' is coupled to the gate terminal 302' (thereby ensuring that the same bias voltages are applied to both the gate (Vg) and the body (shown in FIGURE 3C as "Vb" or "V A cs")-
  • bias voltages can be applied to the four device terminals while still employing the techniques of the present disclosed method and apparatus.
  • the ACC SOI NMOSFET 300' is biased to operate in the accumulated charge regime, the accumulated charge can be removed or otherwise controlled by applying a bias voltage V ACS to the ACS terminal 308', and thereby remove the accumulated charge from the body 312.
  • V th is negative by definition.
  • both the Vs and Vd bias voltages comprise zero volts (i.e., both terminals tied to circuit ground node)
  • a gate bias Vg applied to the gate terminal 302' is sufficiently negative to V th (for example, Vg is more negative than approximately -I V relative to V th )
  • holes may accumulate under the gate oxide 110 thereby becoming the accumulated charge 120.
  • the voltage V ACS applied to the ACS 308 may be selected to be equal to or more negative than the lesser of Vs and Vd.
  • the source and drain bias voltages, Vs and Vd, respectively may comprise voltage other than zero volts.
  • the gate bias voltage Vg must be sufficiently negative to both Vs and Vd (in order for Vg to be sufficiently negative to V th , for example) in order to bias the NMOSFET in the off-state.
  • the ACS bias voltage V ACS applied to the ACS terminal 308' may be selected to be equal to or more negative than the lesser of Vs and Vd.
  • V ACS should, in the exemplary embodiments, be equal to or more negative than the lesser of Vs and Vd.
  • Vs, Vd, Vg and V ACS bias voltages may be used when the ACC MOSFET comprises a PMOSFET device. Because the prior art body contacts are typically tied to the source, this implementation cannot be effected using the prior art body contact approach.
  • FIGURE 3D is a simplified schematic diagram of a top view of an ACC SOI NMOSFET 300" adapted to control accumulated charge 120 (FIGURE 1) in accordance with the present disclosure.
  • FIGURE 3D shows the ACC NMOSFET 300" without its gate contact 301, gate 302, and gate oxide being visible.
  • the ACC NMOSFET 300" of FIGURE 3D is very similar in design to the ACC NMOSFET 300 described above with reference to FIGURES 3A and 3B.
  • the ACC NMOSFET 300" includes a source 304 and drain 306 comprising N+ regions.
  • the ACC NMOSFET 300" also includes an accumulated charge sink (ACS) 308 comprising a P- region.
  • ACS accumulated charge sink
  • the P- region that comprises the ACS 308 abuts (i.e., is directly adjacent) the body 312, which also comprises a P- region.
  • the ACC NMOSFET 300" includes an electrical contact region 310 that provides electrical connection to the ACS 308.
  • the electrical contact region 310 comprises a P+ region.
  • the electrical contact region 310 may comprise an N+ region (which thereby prevents positive current flow into the body 312 as noted above).
  • the electrical contact region 310 is formed in the ACC NMOSFET 300" directly adjacent the ACS 308.
  • the ACC SOI NMOSFET 300" functions to control accumulated charge similarly to the operation of the ACC NMOSFETs described above with reference to FIGURES 3A-3C.
  • FIGURE 3E is a simplified schematic diagram of a top view of an ACC SOI NMOSFET 300"' adapted to control accumulated charge in accordance with the present disclosure.
  • the ACC NMOSFET 300"' is very similar in design and function to the ACC NMOSFETs described above with reference to FIGURES 3A-3D.
  • FIGURE 3E shows a dashed cross-sectional view line A-A' taken along the approximate center of the NMOSFET 300"'.
  • This cross-sectional view is used herein to describe structural and performance characteristics of some exemplary prior art MOSFETS and some embodiments of the ACC NMOSFET that may occur as a result of the fabrication processes. Details of this cross-sectional view A-A' are now described with reference to FIGURE 3F.
  • View line A-A' slices through the following component regions of the ACC NMOSFET 300"': the P+ electrical contact region 310, the ACS 308 (shown in FIGURE 3E, but not shown in FIGURE 3F), a P+ overlap region 310', a gate oxide 110, and a poly-silicon gate 302.
  • the region 310 is doped with p- type dopant material, proximate the P- body region, some additional P+ doping may be implanted (i.e., the p-type dopant material may overlap) into the P+ overlap region 310' of the poly-silicon gate 302.
  • such overlapping is performed intentionally to ensure that all of the gate oxide 110 is completely covered by the P+ region (i.e., to ensure that no gap exists on the edge of the oxide 110 between the gate 302 and the P+ region 310). This, in turn, aids in providing a minimum impedance connection between the P+ region 310 and the body 312.
  • the present teachings encompass such embodiments described above, those skilled in the electronic device design and manufacturing arts shall recognize that such low- resistance connections are not required. Therefore, disadvantages associated with the embodiment shown in FIGURE 3H, as described below in more detail, can be overcome by using other embodiments described herein (for example, the embodiments 300 and 300"" described below with reference to FIGURES 3G and 3J, respectively), in which gaps are intentionally implemented between the P+ region 310 and the body 312.
  • the P+ overlap region 310' overlaps the oxide 110 by approximately 0.2 - 0.7 microns.
  • the remaining area over the gate oxide 110 and over the P- body is doped with n-type dopant material (i.e., it comprises an N+ region).
  • an increased threshold voltage region is created in the NMOSFET 300"'. More specifically, due to the P+ doping (in the P+ overlap region 310') proximate the edge 340 of the gate 302 over the channel region of the body 312, a region of increased threshold voltage is formed in that region of the MOSFET 300"'. The effects of the region of increased threshold voltage are now described in more detail with reference to FIGURES 3H and 31.
  • FIGURE 31 shows a plot 380 of inversion channel charge versus applied gate voltage for an ACC NMOSFET.
  • the plot 380 shown in FIGURE 31 illustrates one effect of the above- described increased threshold voltage that can occur in prior art MOSFETs, and in some embodiments of the present ACC NMOSFETs due to certain manufacturing processes.
  • the increased threshold voltage region shown in FIGURE 3H and described in more detail below, also occurs in prior art MOSFET designs due to the proximity of body ties to the FET body.
  • the present disclosed method and apparatus can be used to reduce or eliminate the region of increased threshold voltage found in some prior art SOI MOSFET designs.
  • FIGURE 3H shows one embodiment of an ACC NMOSFET without its gate contact, gate, and gate oxide being visible.
  • the MOSFET region of increased threshold voltage described above with reference to FIGURES 3E and 3F is shown in FIGURE 3H as occurring in the region encompassed by the ellipse 307.
  • the region 307 of the ACC MOSFET shown in FIGURE 3H effectively "turns on” after the rest of the ACC MOSFET channel region.
  • the increased threshold voltage can be reduced by reducing the size of the region 307. Eliminating the region 307 altogether eliminates the threshold voltage increase. Because the threshold voltage increase can increase harmonic and intermodulation distortion of the "on" state MOSFET, eliminating this effect improves MOSFET performance. The increased threshold voltage also has the detrimental effect of increasing the MOSFET on-resistance (i.e., the resistance presented by the MOSFET when it is in the on-state (conducting state), which detrimentally impacts the MOSFET insertion loss.
  • the detrimental effects associated with threshold voltage increase are mitigated or overcome by positioning the P+ region 310 a selected distance away from an edge of the poly-silicon gate 302. This approach is shown both in the top view of the ACC MOSFET 300 of FIGURE 3A, and in the cross-sectional view of the ACC MOSFET 300 shown in FIGURE 3G.
  • the P+ region 310 does not extend all the way to the edge 340 of the poly-silicon gate 302. This is in stark contrast to the embodiment 300"' shown in FIGURE 3F, where the P+ region 310' extends all the way to the gate edge 340.
  • the P+ region 310 By positioning the P+ region 310 a distance away from the gate edge 340 as shown in the embodiment 300 of FIGURE 3G, no P+ region is positioned proximate the poly- silicon gate 302 (i.e., there is no P+ region present in the poly-silicon gate 302).
  • This configuration of the P+ region 310 eliminates or greatly reduces the problems associated with threshold voltage increase as described above.
  • the relatively high impedance of the ACS 308 P- region (shown in FIGURE 3 A) between the P+ region 310 and the gate 302 does not adversely affect the performance of the ACC NMOSFET 300.
  • the accumulated charge can be effectively removed even using a relatively high impedance ACS connection.
  • the threshold voltage increase is removed by positioning the P+ region 310 (and the ACS 308) a distance away from the body 312. Because the electrical connectivity between the ACS 308 and the body 312 has relatively high impedance when the small region of P+ 310 is positioned a distance away from the body 312, this approach is never taught or suggested by the body contact prior art references (which require low impedance contacts as described above). This improved embodiment is described next with reference to FIGURE 3 J.
  • FIGURE 3 J is a simplified top view schematic of another embodiment of an ACC SOI NMOSFET 300"" adapted to control accumulated charge and configured in a "T-gate” configuration.
  • FIGURE 3 J shows the ACC NMOSFET 300"" without its gate contact 301, gate 302, and gate oxide being visible.
  • the gate (not shown in FIGURE 3J) and the body 312 are configured as "supporting" members of the "T-gate” configured ACC MOSFET 300"" (i.e., they comprise the "bottom” portion of the "T-shaped” FET).
  • the ACC NMOSFET 300" includes a small P+ region 310 conjoined to an ACS 308.
  • the P+ region 310 (and thus the ACS external electrical connection) is disposed a selected distance away from the body 312. The total impedance of the electrical connection from the body 312, through the ACS 308, and to the P+ region 310 is increased by positioning the P+ region 310 a selected distance away from the body 312.
  • the present ACC NMOSFET 300"" works perfectly well to remove accumulated charge even using relatively high impedance ACS connections.
  • the ACC NMOSFET 300"" does not require low impedance ACS electrical connections in order to remove accumulated charge from the body 312.
  • an ACS connection of relatively large impedance may be used in practicing the present teachings, with corresponding improvements in NMOSFET performance as described above (e.g. , reductions in parasitic capacitance as compared with prior art low impedance body contacts).
  • a low impedance ACS connection may be used to practice the disclosed method and apparatus for use in improving linearity characteristics of SOI MOSFETs.
  • FIGURE 3 J improves device performance owing to the fact that the small P+ region 310 is positioned a distance away from the body 312. Because the small P+ region 310 is positioned a distance away from the body 312, the threshold voltage increase is reduced or entirely eliminated, together with the consequent adverse performance effects described above.
  • FIGURE 3K is a simplified top view schematic of another embodiment of an ACC SOI NMOSFET 300""' adapted to control accumulated charge and configured in an "H-gate” configuration.
  • FIGURE 3K shows the ACC NMOSFET 300 without its gate contact 301, gate 302, and gate oxide being visible.
  • the ACC NMOSFET 300 is very similar in design and function to the ACC NMOSFETs described above with reference to FIGURES 3A-3D and 3J.
  • the ACC NMOSFET 300 includes two ACSs, 308 and 308", disposed at opposite ends of the H-gate ACC NMOSFET 300 P+ regions 310 and 310" are formed to abut their respective
  • ACSs, 308 and 308 and provide electrical contact thereto.
  • the ACC NMOSFET 300""' is biased to operate in the accumulated charge regime, the accumulated charge is removed or otherwise controlled via the two ACSs 308 and 308".
  • the ACSs 308 and 308" may also comprise much narrower (or wider) regions, and still function perfectly well to remove or otherwise control the accumulated charge. Also, in some embodiments, it is not necessary that the impedance of the ACS 308 matches the impedance of the ACS 308". It will further be understood by the skilled person that the ACSs 308 and 308" may comprise different sizes and configurations (i.e. , rectangular, square, or any other convenient shape), and may also be positioned at various distances away from the body 312 (i.e. , not necessarily the same distance away from the body 312). As described above with reference to FIGURE 3J, when the ACS 308 is positioned a selected distance away from the body 312, the problems associated with threshold voltage increase are reduced or eliminated.
  • the SOI NMOSFET 300 of FIGURES 3A and 3B may be implemented as a four terminal device, as illustrated schematically in FIGURE 4A.
  • a gate terminal 402 is electrically coupled to the gate contact 301 (e.g. , FIGURE 3 A) and is analogous to the gate terminal 302' shown in FIGURE 3C.
  • the gate contact 301 is electrically coupled to the gate 302 (e.g. , FIGURES 3A and 3C).
  • a source terminal 404 is electrically coupled to the source 304 (e.g. , FIGURES 3A-3C) and is analogous to the source terminal 304' of FIGURE 3C.
  • a drain terminal 406 is electrically coupled to the drain 306 (e.g. , FIGURES 3A-3C) and is analogous to the drain terminal 306' of FIGURE 3C.
  • the ACC NMOSFET 300 includes an ACS terminal 408 that is electrically coupled to the ACS 308 (e.g. , see FIGURES 3A-3B, and FIGURES 3D, 3J- 3K) via the region 310.
  • the region 310 may be used in some embodiments to facilitate electrical coupling to the ACS 308 because, in some embodiments, it may be difficult to make a direct contact to a lightly doped region (i.e. , the ACS 308).
  • the ACS terminal 408 is analogous to the ACS terminal 308' shown in FIGURE 3C.
  • the ACC SOI NMOSFET 300 of FIGURE 4A may be operated using various techniques and implemented in various circuits in order to control accumulated charge present in the FET when it is operating in an accumulated charge regime.
  • the gate and ACS terminals, 402 and 408, respectively are electrically coupled together.
  • the source and drain bias voltages applied to the terminals 404 and 406, respectively may be zero.
  • the ACC NMOSFET 300 operates in the accumulated charge regime. As described above with reference to FIGURE 3C, for example, when the MOSFET operates in this regime, accumulated charge (holes) may accumulate in the body of the NMOSFET 300.
  • the accumulated charge can be removed via the ACS terminal 408 by connecting the ACS terminal 408 to the gate terminal 402 as shown.
  • This configuration ensures that when the FET 300 is in the off-state, it is held in the correct bias region to effectively remove or otherwise control the accumulated charge.
  • connecting the ACS terminal 408 to the gate ensures that the same bias voltages are applied to both the gate (Vg) and the body (shown in FIGURE 3C as "Vb" or "V AC s")- Because the bias voltage V AC s is the same as the gate voltage Vg in this embodiment, the accumulated charge is no longer trapped below the gate oxide (by attraction to the gate bias Vg) because it is conveyed to the gate terminal 402 via the ACS terminal 408. The accumulated charge is thereby removed from the body via the ACS terminal 408.
  • Vs and Vd may comprise nonzero bias voltages.
  • Vg must be sufficiently negative to both Vs and Vd in order for Vg to be sufficiently negative to V th to turn the NMOSFET 300 off (i.e., operate the NMOSFET 300 in the off-state).
  • the NMOSFET 300 may enter the accumulated charge regime and thereby have accumulated charge present in the body.
  • the voltage V ACS may also be selected to be equal to Vg by connecting the ACS terminal 408 to the gate terminal 402, thereby conveying the accumulated charge from the body of the ACC NMOSFET, as described above.
  • the ACC NMOSFET 300 comprises a depletion mode device.
  • the threshold voltage, V th is, by definition, less than zero.
  • Vs and Vd both at zero volts, when a gate bias Vg sufficiently negative to V th is applied to the gate terminal 402 (for example, Vg more negative than approximately -I V relative to V th ), holes may accumulate under the gate oxide and thereby comprise an accumulated charge.
  • the voltage V ACS may also be selected to be equal to Vg by connecting the ACS terminal 408 to the gate terminal 402, thereby conveying the accumulated charge from the ACC NMOSFET as described above.
  • diodes formed at the edge of the device may become forward biased thereby allowing current to flow into the source and drain regions.
  • this may introduce nonlinearity into the NMOSFET.
  • the nonlinearity results because the current that flows as a result of the forward biased interface diodes comprises nonlinear current.
  • Vgs and Vgd are reduced in that region of the device, the on resistance Ron at the edge of the device is increased.
  • FIGURE 4C Another exemplary simplified circuit using the improved ACC SOI NMOSFET 300 is shown in FIGURE 4C.
  • the ACS terminal 408 may be electrically coupled to a diode 410, and the diode 410 may, in turn, be coupled to the gate terminal 402.
  • FIGURE 4H is a plot 460 of the off- state capacitance (C Qff ) versus an applied drain- to-source voltage of an SOI MOSFET when an AC signal is applied to the MOSFET (the plot 460 is relevant to an exemplary 1 mm wide MOSFET, though similar plots result using wider and narrower devices).
  • a gate voltage equals -2.5 Volts + Vd/2, and Vs equals 0.
  • a first plot 462 shows the off-state capacitance C Qff of a typical prior art NMOSFET operating within the accumulated charge regime and thereby having an accumulated charge as described above with reference to FIGURE 1.
  • a second plot 464 illustrates the off- state capacitance C Q ff of an improved ACC SOI MOSFET made in accordance with the present teachings, wherein the accumulated charge is conveyed from the ACC MOSFET, thereby reducing, controlling and/or eliminating the accumulated charge from the ACC MOSFET body.
  • the off-state capacitance C Q ff shown in plot 464 of the ACC SOI MOSFET is not voltage- dependent (i.e., it is linear).
  • the impedance 212 of the NMOSFET body 312 (FIGURE 3C, and shown as the MOSFET body 114 in the electrical model of FIGURE 2A) is increased to a very large value.
  • This increase in the impedance 212 of the MOSFET body reduces the contribution to C 0 ff caused by the impedance of the junctions 218 and 220 (FIGURE 2A), thereby reducing the overall magnitude of C 0 ff and the nonlinear effects associated with the impedances of the junctions 218 and 220.
  • FIGURE 5A shows a schematic diagram of a single pole, single throw (SPST) RF switch circuit 500 in accordance with prior art.
  • the RF switch circuit 500 is one example of a general class of well-known RF switch circuits. Similar RF switch circuits are described in the following co-pending and commonly assigned U. S. Applications and Patent: Provisional Application No. 60/651,736, filed February 9, 2005, entitled “UNPOWERED SWrfCH AND BLEEDER CIRCUIT;" Application No. 10/922,135, filed August 18, 2004, pending, which is a continuation application of Application No.
  • a shunting SOI NMOSFET 508 is adapted to receive the RF input signal RFin at its drain terminal, and to selectively shunt the input signal RFin to ground via an optional load resistor 518.
  • the shunting SOI NMOSFET 508 is controlled by a second control signal Clx which is conveyed by a control line 516 through a gate resistor 514 (optionally included for suppression of parasitic RF coupling and for purposes of voltage division).
  • the control line 516 is electrically coupled to the control circuit 520, which generates the second control signal Clx.
  • switching and shunting are used interchangeably herein with the terms “switch” and “shunt”, respectively.
  • the switching transistor 506 (and all of its analogous switching transistors described below in FIGURES 5B-5D, 6, 8, and 9) is also referred to herein as the "switch” transistor.
  • the shunting transistor 508 (and all of its analogous shunting transistors described below in FIGURES 5B-5D, 6, 8, and 9) is also referred to herein as the "shunt” transistor.
  • switch and “switching” (and similarly the terms “shunt” and “shunting”), when used to describe the RF switch circuit transistors, are used interchangeably herein. Further, as described below in more detail with reference to FIGURE 6, those skilled in the RF switching design and fabrication arts shall recognize that although the switch and shunt transistors are shown in FIGURES 5A-5D and FIGURE 9 as comprising a single MOSFET, it shall be understood that they may comprise transistor groupings comprising one or more MOSFET transistors.
  • the RF switch circuits described with reference to FIGURES 2B, 4E, 5A-5D, 6, 8 and 9 are described herein as having "input” and “output” ports (or “nodes") that input and output RF signals, respectively.
  • RF input node 905 and RF input node 907 are described below as inputting RF signals RF1 and RF2 respectively.
  • RFC common port 903 is described below as providing an RF common output signal.
  • the RF switch is bidirectional, and that the previously described input ports function perfectly well as output ports, and vice versa.
  • the RFC common port can be used to input an RF signal which is selectively output by the RF nodes 905 and 907.
  • the maximum power of the RF input signal RFin is thereby limited by the maximum magnitude of the gate bias voltage Vg (or, more generally, the gate-to- source operating voltage, Vgs) that the SOI NMOSFETs 506 and 508 can reliably sustain.
  • Vgs the gate bias voltage
  • Vgs the gate bias voltage
  • Vds Vd - Vs
  • Vds(max) comprises the maximum Vds due to the high- power input signal voltage levels associated with the RF input signal RFin.
  • Exemplary bias voltages for the switching and shunting SOI NMOSFETs 506 and 508, respectively, may include the following: with V th approximately zero volts, Vg, for the on- state, of +2.5 V, and Vg, for the off-state, of - 2.5 V.
  • Vg approximately zero volts
  • Vg for the on- state
  • Vg for the off-state
  • the SOI NMOSFETs may eventually operate in an accumulated charge regime when placed into their off-states.
  • the output signal RFout may become distorted by the nonlinear behavior of the off capacitance C 0ff of the shunting NMOSFET 508 caused by the accumulated charge.
  • the improved ACC MOSFETs made in accordance with the present teachings can be used to improve circuit performance, especially as it is adversely affected by the accumulated charge.
  • FIGURE 5B is a schematic of an improved RF circuit 501 adapted for higher performance using the present accumulated charge reduction and control techniques.
  • the switch circuit 501 differs from the prior art circuit 500 (FIGURE 5 A) in that the shunting NMOSFET 508 is replaced by a shunting ACC NMOSFET 528 made in accordance with the present teachings.
  • the shunting ACC NMOSFET 528 is analogous to the ACC NMOSFET described above with reference to FIGURES 4A and 4B.
  • the gate, source, drain and ACC terminals of the shunting ACC NMOSFET 528 are analogous to the respective terminals of the ACC NMOSFET 300.
  • the operation of the RF switch circuit 501 is very similar to the operation of the RF switch circuit 500 described above with reference to FIGURE 5A.
  • Exemplary bias voltages for the switching NMOSFET 526 and the shunting ACC NMOSFET 528 may include: with V th approximately zero, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of - 2.5 V.
  • the SOI NMOSFETs may operate in an accumulated charge regime when placed into the off-state.
  • the output signal RFout at the output terminal 505 will not be distorted by nonlinear behavior of the off-state capacitance C Qff of the improved shunting ACC NMOSFET 528 due to the accumulated charge.
  • the shunting ACC NMOSFET 528 operates in the accumulated charge regime, the accumulated charge is removed via the ACS terminal 508'. More specifically, because the gate terminal 502' of the shunting ACC NMOSFET 528 is connected to the ACS terminal 508', the accumulated charge is removed or otherwise controlled as described above in reference to the simplified circuit of FIGURE 4B.
  • the control of the accumulated charge improves performance of the switch 501 by improving the linearity of the off transistor, shunting ACC NMOSFET 528, and thereby reducing the harmonic and intermodulation distortion of the RF output signal Rfout generated at the output terminal 505.
  • FIGURE 5C is a schematic of another embodiment of an improved RF switch circuit 502 adapted for higher performance using the accumulated charge control techniques of the present disclosure.
  • the switch circuit 502 differs from the prior art circuit 500 (FIGURE 5A) in that the NMOSFET 508 is replaced by an ACC NMOSFET 528 made in accordance with the present teachings.
  • the ACC NMOSFET 528 is analogous to the ACC NMOSFET 300 described above with reference to FIGURES 4A and 4C.
  • the gate, source, drain and ACC terminals of the ACC NMOSFET 528 are analogous to the respective terminals of the ACC NMOSFETs 300 described above with reference to FIGURE 4A and 4C.
  • the operation of the switch circuit 502 is very similar to the operations of the switch circuits 500 and 501 described above with reference to FIGURES 5 A and 5B, respectively.
  • Exemplary bias voltages for the NMOSFET 526 and the ACC NMOSFET 528 may include the following: with V th approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of - 2.5 V.
  • Vg approximately zero volts
  • Vg for the on-state
  • Vg for the off-state
  • the output signal RFout will not be distorted by nonlinear behavior of the off- state capacitance C Qff of the ACC NMOSFET 528 due to the accumulated charge.
  • the gate terminal 502' of the ACC NMOSFET 528 is connected to the ACS terminal 508' via a diode 509, the accumulated charge is entirely removed, reduced or otherwise controlled, as described above with reference to FIGURE 4C. Similar to the improved switch 501 described above with reference to FIGURE 5B, control of the accumulated charge improves performance of the switch 502 by improving the linearity of the off transistor, 528, and thereby reducing the harmonic and intermodulation distortion of the RF output signal Rfout output of the RF output terminal 505. Connection of the diode 509 as shown may be desired in some embodiments for suppression of positive current flow into the ACC NMOSFET 528 when it is biased into an on-state, as described above with reference to FIGURE 4C.
  • FIGURE 5D is a schematic of another embodiment of an improved RF switch circuit 503 adapted for higher performance using the present accumulated charge control techniques.
  • the switch circuit 503 differs from the prior art circuit 500 (FIGURE 5A) in that the NMOSFET 508 of FIGURE 5A is replaced by an ACC NMOSFET 528 made in accordance with the present teachings.
  • the ACC NMOSFET 528 is analogous to the ACC NMOSFET described above with reference to FIGURES 4A and 4D.
  • the operation of the switch circuit 503 is very similar to the operations of the switch circuits 500, 501 and 502 described above with reference to FIGURES 5A-5C, respectively.
  • Exemplary bias voltages for the NMOSFET 526 and the ACC NMOSFET 528 may include the following: with V th approximately zero volts, Vg, for the on-state, of +2.5 V, and Vg, for the off-state, of - 2.5 V.
  • Vg approximately zero volts
  • Vg for the on-state
  • Vg for the off-state
  • Vg for the off-state
  • the SOI NMOSFETs 526, 528 may operate in an accumulated charge regime when placed into the off-state.
  • the ACS terminal 508' of the ACC NMOSFET 528 is electrically coupled to the control circuit 520 via the control line 517 (i.e., controlled by the control signal "C2" as shown), the accumulated charge can be eliminated, reduced or otherwise controlled by applying selected bias voltages to the ACS terminal 508' as described above with reference to FIGURE 4D.
  • bias voltage signals can be applied to the ACS terminal for the purpose of reducing or otherwise controlling the accumulated charge.
  • the specific bias voltages may be adapted for use in a particular application.
  • the control of the accumulated charge improves performance of the switch 503 by improving the linearity of the off-state transistor, 528, and thereby reducing the harmonic and intermodulation distortion of the RF output signal Rfout generated at the output terminal 505.
  • the switching SOI MOSFETs 526 are shown and described as implemented using SOI MOSFETs of the prior art (i.e. , they do not comprise ACC MOSFETs and therefore do not have an ACS terminal).
  • the prior art switching SOI MOSFETs 526 may be replaced, as desired or required, by ACC SOI MOSFETs made in accordance with the present disclosure.
  • the RF switch comprises a single-pole double-throw RF switch.
  • the exemplary RF switches have been described as being implemented using ACC SOI NMOSFET devices, they can also be implemented using ACC SOI PMOSFET devices.
  • single-pole single-throw, and single-pole double-throw RF switches have been described above as examples of RF switches implemented in accordance with the present teachings, the present application encompasses any variation of single-pole multi-throw, multi-pole single-throw, and multi-pole multi-throw RF switch configurations.
  • Those skilled in the RF switch design and fabrication arts shall recognize and appreciate that the present teachings can be used in implementing any convenient RF switch configuration design.
  • a single SOI NMOSFET (e.g., the single SOI NMOSFET 508 of FIGURE 5A, and ACC SOI NMOSFET 528 of FIGURES 5B-5D) is used to shunt (FET in the on-state) or block (FET in the off-state) the RF input signal to ground.
  • FIGURE 6 One example of how stacked NMOSFETs may be implemented in accordance with the teachings of the present disclosure is illustrated in FIGURE 6.
  • An RF switch circuit 600 is analogous to the RF switch circuit 503 of FIGURE 5D, wherein the single SOI NMOSFET 526 is replaced by a stack of SOI NMOSFETs 602, 604 and 606.
  • the single ACC SOI NMOSFET 528 is replaced by a stack of ACC SOI NMOSFETs 620, 622 and 624.
  • the control signal C2 is provided to the ACS terminals of the ACC SOI NMOSFETs 620, 622 and 624 via optional resistors 626, 628, and 630, respectively.
  • the present teachings can be applied in implementing both symmetrically and asymmetrically stacked (having an unequal number of shunting and switching transistors) RF switches.
  • the designer will readily understand how to use the ACC MOSFETs of the present disclosure in implementing asymmetrical, as well as symmetrical, RF switch circuits.
  • FIGURE 7 illustrates an exemplary method 700 of improving the linearity of an SOI MOSFET having an accumulated charge sink (ACS) in accordance with the present disclosure.
  • the method 700 begins at a STEP 702, whereat an ACC SOI MOSFET having an ACS terminal is configured to operate in a circuit.
  • the ACS terminal may be operatively coupled to the gate of the SOI MOSFET (as described above with reference to FIGURES 4B, 4C, 5B and 5C), or to a control circuit (as described above with reference to FIGURES 4D and 5D).
  • the ACS terminal may be operatively coupled to any convenient accumulated charge sinking mechanism, circuit, or device as is convenient to the circuit or system designer.
  • removing or otherwise controlling the accumulated charge in the ACC MOSFET body improves the linearity of the off-state ACC MOSFET, which reduces the harmonic distortion and IMD of signals affected by the ACC MOSFET, and which, in turn, improves circuit and system performance.
  • improvements in both linearity and magnitude
  • the off capacitance of shunting ACC MOSFET devices improves the performance of the RF switch circuits.
  • the harmonic and intermodulation distortions of the RF switch are reduced using the ACC method and apparatus of the present teachings.
  • FIGURE 8 shows one exemplary embodiment of an RF switch circuit 800 made in accordance with the present disclosure.
  • some embodiments of RF switches made in accordance with the present disclosure may include drain-to- source (Ra s ) resistors electrically connected to the respective sources and drains of the ACC MOSFETs.
  • the exemplary switch 800 of FIGURE 8 includes drain-to-source R ds resistors 802, 804, and 806 electrically connected to the respective sources and drains of the shunting ACC SOI NMOSFETs 620, 622, and 624, respectively.
  • Drain-to- source R ds resistors is now described.
  • removal of the accumulated charge via the ACS terminal causes current to flow from the body of the ACC SOI MOSFET.
  • a hole current flows from the body of an ACC SOI MOSFET via the ACS
  • an equal electron current flows to the FET source and/or drain.
  • the sources and/or drains of the ACC SOI NMOSFETs are connected to other SOI NMOSFETs.
  • off-state SOI NMOSFETs have a very high impedance (e.g., in the range of 1 Gohm for a 1 mm wide SOI NMOSFET), even a very small drain-to-source current (e.g., in the range of 1 nA) can result in an unacceptably large drain-to- source voltage Vds across the ACC SOI NMOSFET in satisfaction of Kirchhoff s well known current and voltage laws.
  • Vds undesirably impacts reliability and linearity of the ACC SOI NMOSFET.
  • Exemplary values for the R ds resistors 802 to 806 may be selected in some embodiments by selecting a value approximately equal to the resistance of the gate resistors 632- 636 divided by the number of ACC SOI NMOSFETs in the stack (in the exemplary embodiment, there are three ACC FETs in the stack). More generally, the value of the R ds resistors may be equal to the gate resistor value divided by the number of ACC SOI NMOSFETs in the stack. In one example, a stack of eight ACC SOI NMOSFETs may have gate resistors of 80 kohm and R ds resistors of 10 kohm.
  • the R ds resistors may be selected so that they do not adversely affect switch performance characteristics, such as, for example, the insertion loss of the switch 800 due to the off-state ACC SOI NMOSFETs. For example, for a net shunt resistance greater than 10 kohm, the insertion loss is increased by less than 0.02 dB.
  • a DC blocking capacitor 902 is electrically connected to an RF common output node 903 that provides an RF common output signal (RFC) selectively conveyed to the node RFC 903 by the switch circuit 900 from either the first RF input node 905 or the second RF input node 907 (i.e., RFC either outputs RF1 or RF2, depending upon the operation of the switch as controlled by the control signals CI and Clx described below in more detail).
  • RFC RF common output signal
  • a first control signal CI is provided to control the operating states of the ACC SOI NMOSFETs 526 and 528' (i.e., CI selectively operates the FETs in the on-state or the off-state).
  • a second control signal Clx is provided to control the operating states of the ACC SOI NMOSFETs 528 and 526'.
  • the control signals CI and Clx are generated so that the ACC SOI NMOSFETs 526 and 528' are in an on-state when the ACC SOI NMOSFETs 528 and 526' are in an off-state, and vice versa.
  • This configuration allows the RF switch circuit 900 to selectively convey either the signal RF1 or RF2 to the RF common output node 903.
  • a first ACS control signal C2 is configured to control the operation of the ACS terminals of the SOI NMOSFETs 526 and 528'.
  • a second ACS control signal C2x is configured to control the ACS terminals of the ACC SOI NMOSFETs 528 and 526'.
  • the first and second ACS control signals, C2 and C2x, respectively, are selected so that the ACSs of the associated and respective NMOSFETs are appropriately biased in order to eliminate, reduce, or otherwise control their accumulated charge when the ACC SOI NMOSFETs operate in an accumulated charge regime.
  • the circuit 900 is operated so that either the shunting ACC NMOSFET 528 or the shunting ACC NMOSFET 528' operate in an on-state at any time (i.e., at least one of the input signals RF1 at the node 905 or RF2 at the node 907 is always conveyed to the RFC node 903), thereby providing a low-impedance path to ground for the node 905 or 907, respectively.
  • either the R ds resistor 908 or the R ds resistor 910 provides a low-impedance path to ground from the RF common node 903, thereby preventing voltage bias problems caused as a result of ACC current flow into the nodes 903, 905 and 907 that might otherwise be caused when using the DC blocking capacitors 902, 904 and 906.
  • the prior art off-state shunting NMOSFET 528 may introduce harmonic distortion and/or intermodulation distortion in the presence of multiple RF signals This will also introduce a noticeable loss of signal power.
  • the switch By reducing the magnitude of Coff using the present disclosed method and apparatus, the switch (implemented with ACC MOSFETs) has reduced insertion loss due to lowered parasitic capacitance, reduced insertion phase (or delay), again due to lowered parasitic capacitance, and increased isolation due to less capacitive feedthrough.
  • the exemplary RF switches described above may be implemented using a fully insulating substrate semiconductor-on-insulator (SOI) technology. Also, as noted above, in addition to the commonly used silicon-based systems, some embodiments of the present disclosure may be implemented using silicon-germanium (SiGe), wherein the SiGe is used equivalently in place of silicon.
  • SOI semiconductor-on-insulator
  • SiGe silicon-germanium
  • switch isolation is improved using the fully insulating substrates provided by UTSi technology.
  • fully insulating nature of silicon-on-sapphire technology the parasitic capacitance between the nodes of the RF switches is greatly reduced as compared with bulk CMOS and other traditional integrated circuit manufacturing technologies.
  • silicon-on-bonded wafer techniques include the so-called NanoCleaveTM bonding process which can be performed at room temperature.
  • SOI wafers can be formed with materials having substantially different thermal expansion coefficients, such as in the manufacture of Germanium-on-Insulator wafers (GeOI).
  • Exemplary patents describing silicon-on-bonded wafer implementations are as follows: US Pat. No. 7,056,808, issued June 6, 2006 to Henley, et al.; US Pat. No. 6,969,668, issued November 29, 2005 to Kang, et al.; US Pat. No.
  • the present CIP describes methods and apparatuses for improving linearity characteristics of ACC FETs.
  • Persons skilled in the art of electronics devices will appreciate that the teachings herein apply equally to NMOSFETs and PMOSFETs and other similar devices.
  • the embodiments and examples presented herein for illustrative purposes may include only NMOSFETs, unless otherwise noted.
  • dopants, charge carriers, polarity of bias voltages, etc. persons skilled in the art of electronic devices will easily understand how these embodiments and examples may be adapted for use with PMOSFETs and other similar devices.
  • the worst-case peak deviating from linearity can be moved away from standard operating conditions. More specifically, modifications of the implants can move the worst-case harmonic peak either to more negative bias voltages, or closer to zero bias condition. Because each direction has its advantages and disadvantages, there is room for tunability to the application specifications. Characterization of a variety of implants would provide for the desired tunability in future applications.
  • TIN thin oxide intrinsic NMOSFET
  • the testing results presented in FIGURES 10A and 10B demonstrate how adjusting the implant in the ACS region shifts the curves of the harmonic responses from the results of an NMOSFET without any engineering in the ACS implant which correspond to Curve 1023 in FIGURE 10A and Curve 1033 in FIGURE 10B .
  • FIGURES 10A and 10B a significant nonlinear response (i.e., a "harmonic wrinkle") occurs around the operational voltage of the device due to the formation of a parasitic MOS capacitor in the ACS region which is turned on when the bias voltage difference between gate and body terminals is approximately zero.
  • Curve 1021 in FIGURE 10A and Curve 1031 in FIGURE 10B show the results from heavily doped P-type implant in the ACS region.
  • Curve 1022 in FIGURE 10A and Curve 1032 in FIGURE 10B show the results from lightly doped P-type implant.
  • Curve 1023 in FIGURE 10A and Curve 1033 in FIGURE 10B show the results from lightly-doped N-type implant.
  • P-type implants push the worst case harmonic peak toward more negative operational voltage region, while N-type implants push the peak closer to zero bias condition.
  • the non-linear harmonic response is believed to arise from the parasitic MOS capacitance in the ACS region. Adjusting the implant in the ACS region allows for the voltage threshold in which the parasitic MOS capacitor is turned on to be moved out of the desired operational voltage range to achieve a linear or near-linear response within the specified operating range.
  • the new H-gate type device is defined by an AC short between the dual-sided ACS regions at the bottom of the FET stack. Because each of the ACS regions on each side of the stack is independently radio-frequency coupled by parasitic capacitance to the gate polysilicon, second-order intermodulation distortion harmonics improve dramatically with symmetry. Because the body contacts on either side of the stack are shorted together, and thus jointly coupling to the gate polysilicon, there is a cancellation of voltage across C BG - This cancellation of voltage sets the voltage across nonlinear capacitances to 0V, voiding the generation of nonlinearity altogether.
  • FIGURE 15 shows an exemplary simplified layout of a dual body ACS ACC MOSFET with an AC short.
  • FIGURE 15 is similar to the structure of the MOSFET shown in FIGURE 3K, except that FIGURE 15 shows the addition of an AC short structure.
  • FIGURE 15K is a simplified top view schematic of an embodiment of an ACC SOI NMOSFET adapted to control accumulated charge and configured in an "H-gate" configuration.
  • FIGURE 3K shows the ACC NMOSFET 1500 without its gate contact 301, gate 302, and gate oxide being visible. With the exception of some structural differences described herein, the ACC NMOSFET 1500 is very similar in design and function to the ACC NMOSFETs described above with reference to FIGURES 3A-3D and 3J.
  • the ACC NMOSFET 1500 includes two ACSs, 308 and 308", disposed at opposite ends of the H-gate ACC NMOSFET 1500.
  • P+ electrical contact regions 310 and 310" are formed to abut their respective ACSs, 308 and 308", and provide electrical contact thereto.
  • FIGURE 15 shows an AC short structure 1501 electrically connecting the two ACSs, 308 and 308", through their respective electrical contact regions 310 and 310".
  • the AC short structure 1501 may be provided by a metal layer or a conductive semiconductor layer or other methods or techniques.
  • the AC short can be made by any of the interconnect methods, direct or inductive.
  • An example of a direct connection is by use of a metal layer.
  • An example of an inductive connection is use of P+ routing
  • FIGURES 11A and 11B show respectively the second- and third-order harmonic responses of an AC shorted dual ACS ACC MOSFET and a single ACS ACC MOSFET versus body bias voltage without any engineering in the ACS implant of both devices.
  • curve 1121 represents the second-order harmonic response of a single ACS ACC MOSFET with a spike (i.e., a "harmonic wrinkle") around the operating voltage of the device (indicated by line 1120).
  • Curve 1123 represents the harmonic response of an AC shorted dual ACS ACC MOSFET where the spike is almost completely removed. Similar trend can also be observed in terms of third-order harmonic response as shown in FIGURE 11B.
  • FIGURES 11A and 11B demonstrate that, the AC shorted dual ACS ACC MOSFET provides an effective way to almost completely remove the harmonic spike (and the accumulation of degrading harmonics) observed in an ACC MOSFET with ACS other than shifting the position of the harmonic spike with the adjustment of the implant in the ACS region. .
  • FIGURE 12 shows a schematic of an exemplary H-gate dual body contact (ACS) FET device without an AC short present at the bottom of the FET device
  • FIGURE 13 shows a schematic of an exemplary H-gate dual body contact (ACS) FET device with the AC short shown at the bottom of the FET device.
  • ACS H-gate dual body contact
  • the gray area in between the source region contact vias and the drain regions contact vias 1430 is the gate region.
  • Electrical contact to the ACS regions (not shown in FIGURE14B) is provided by ACS electrical contacts 1440 at each end of the gate regions 1430.
  • the ACS electrical contacts 1440 are connected together by body bus bars 1450.
  • a shorting electrical connection to the ACS electrical contacts is provided by a metalized AC short 1460.
  • the effectiveness of the AC short in reducing the linearity sensitivity of the dual ACS contact MOSFET may be improved by controlling certain layout dependent characteristics. These layout dependent characteristics include controlling layout dependent critical capacitances.
  • These critical capacitances include the following: (1) Cos should be the same as C GD ; and (2) C BS should be the same as C BD ; and (3) C GG and C BB should be negligible. Also, for FETs with many fingers, if symmetric, parasitics should be almost identical. Such capacitances may be achieved through a layout where the source and drain are symmetric with respect to a horizontal line passing through a center of the gate. Layout connections may also improve the effectiveness of the AC short. Preferably, contacts to the ACS regions on both sides of the MOSFET should be connected together through a low impedance path. In the layout shown in FIGURE 14B, a second metal layer connects the body bus bars 1450 on either side of the structure.
  • embodiments according to the present invention are not limited to a single ACS region contacting the MOSFET body at one end of the body or dual ACS regions contacting the MOSFET body at both ends of the body.
  • Alternative MOSFET architectures according to embodiments of the present invention may allow for multiple ACS regions to contact the MOSFET body in a variety of orientations.
  • the ACS regions are disposed in a symmetric manner so as to maximize the cancellation of voltage across C BG when shorting the ACS regions, which provides for reduction of the second order harmonic.
  • the multiple ACS regions are also preferably disposed close to the Gate oxide, where the accumulated charges are located.
  • MOSFET architectures may also comprise three dimensional structures. Again, embodiments of the present invention having three dimensional structures may have multiple ACS regions contacting the MOSFET body. ACS regions in such a three dimensional structure are preferably disposed in a symmetric manner.
  • Still other embodiments of the present invention may use both the method described above of controlling the doping type and doping level of the ACS region and the method described above of shorting the ACS regions to achieve a linearity improvement in a MOSFET.
  • an electrical contact region or regions to the ACS region may comprise the same material as the ACS region, that is, the two regions may be coextensive.
  • the two regions may be different materials, such as shown in FIGURE 14B, where electrical contacts to the ACS regions are made via a metal layer.
  • electrical contact regions and ACS regions may comprise regions doped at different levels and/or doped with different materials.
  • MOSFETs incorporating either or both of the described method of controlling the ACS region implant and the AC short may be made in the manner described above in regard to FIGURES 4A through 4G and FIGURES 5 A through 5D.
  • an electrical connection may be made from each ACS region to the MOSFET gate, such as shown in FIGURE 4B and described above.
  • Embodiments of MOSFETs incorporating the described methods may also be utilized in electrical circuits as described above in regard to FIGURES 6, 8 and 9 and other circuits where such MOSFETS provide desired performance.

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Abstract

L'invention porte sur un procédé et sur un appareil devant être utilisés dans l'amélioration de la sensibilité de linéarité de dispositifs à transistors à effet de champ métal-oxyde-semi-conducteur ayant un dissipateur de charge accumulée (ACS). Le procédé et l'appareil sont conçus pour traiter une dégradation de la distorsion harmonique d'intermodulation du second et du troisième ordres à une plage désirée de tension de fonctionnement dans des dispositifs employant un dissipateur de charge accumulée.
PCT/US2011/056942 2010-10-20 2011-10-19 Procédé et appareil à utiliser dans l'amélioration de la linéarité de mosfet à l'aide de dissipateur de charge accumulée - réduction d'ondulation harmonique WO2012054642A1 (fr)

Priority Applications (2)

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JP2013535054A JP6006219B2 (ja) 2010-10-20 2011-10-19 蓄積電荷シンクを用いてｍｏｓｆｅｔの線形性を改善することに使用される方法及び装置−高調波リンクルの抑制
DE112011103554T DE112011103554T5 (de) 2010-10-20 2011-10-19 Verfahren und Vorrichtung zur Verwendung bei der Verbesserung einer Linearität von Mosfets unter Verwendung einer Ladungsakkumulationssenke - Reduktion harmonischer Falten

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US61/405,165 2010-10-20

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WO2012054642A1 true WO2012054642A1 (fr) 2012-04-26

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