Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
  • H05K1/0231—Capacitors or dielectric substances
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
  • H05K1/0234—Resistors or by disposing resistive or lossy substances in or near power planes
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
  • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Definitions

• the invention relates to multilevel printed circuit board according to the preamble of claim 1.
• printed circuits use discrete capacitors for blocking and filtering voltages. These discrete components have connecting lines with an inductive pad, which can lead to a critical resonance behavior in the field of high-frequency applications. In addition, these frequencies result in a high space requirement of these components on the surface of the expensive carrier substrate of high-frequency suitable material. The discrete components must be additionally equipped and the circuit must be protected against EMC interference of these components.
• multi-level circuit board for high-frequency applications are already known.
• a multilevel printed circuit board consists of at least one first carrier substrate of high-frequency suitable first material, on which at least parts of the high-frequency circuit are realized.
• the use of at least a second carrier substrate of a second, cheaper material is known, which, however, is associated with the first material with higher dielectric losses.
• Such multilevel circuit boards of different carrier substrate are already available on the market.
• the object of the present invention is therefore to provide a suitable multi-layer printed circuit board for high-frequency applications.
• This object is solved by the features of the independent claims.
• Advantageous developments of the invention will become apparent from the dependent claims, wherein combinations and developments of individual features are conceivable with each other.
• An essential idea of the invention is that the per se for the high frequency applications usually disturbing dielectric losses in the second material can be specifically exploited to form a capacity for absorbing high-frequency power.
• At least one signal line structure on the first carrier substrate and at least one mass ground connected to ground potential on one side of at least one second carrier substrate and electrical vias are provided by the carrier substrates and the capacitance is formed by at least a second carrier substrate towards the ground layer by on the mass position formed on the opposite side of the second carrier substrate a Metalltechnischesflache having a size corresponding to the desired capacity and the metallization is connected via a via with the signal line structure.
• the multilevel printed circuit board consists of at least 3 carrier substrates, wherein a first Masseniage between the first carrier substrate and the second carrier substrate is provided and to the second carrier substrate, a third carrier substrate is also disposed of the second material and the metallization of the capacitance between the second and formed third carrier substrate and on the opposite side of the third carrier substrate, a second ground layer is arranged.
• the metallization surface of the capacitance is thus surrounded on both sides by carrier substrates with desired dielectric losses and can thus optimally utilize the size of the metallization surface and better prevent radiation into the first carrier substrate.
• the multi-level printed circuit board has a plurality of distributed plated-through holes around the metallization area at a predetermined distance from the metallization area, in each case from the first to the second ground layer. These vias also allow prevention of lateral radiation of electromagnetic waves from the region of the capacitance into other parts of the substrates of the second material and thus can be readily used for other parts of the circuit.
• FIG. 1 shows the multilevel printed circuit board with 3 carrier substrates and thus 4 metallization planes, the first carrier substrate consisting of a first, high-frequency suitable material and the second and third carrier substrate made of a comparatively cheaper material with higher dielectric Losses exists. Since there are quite a large number of such suitable substrates on the market, a material selection can be given here only as a suggestion and embodiment, without limiting the scope of protection of the application.
• the loss angle tani2 of the material of the second or third carrier substrate is at least a factor of 3 of the loss angle of the material of the first carrier substrate PCB1, then:
• the resulting dielectric and ohmic losses are significantly dependent on the respective signal frequency and the respective loss angle and the design of the conductivity, Therefore, it is not possible to give the loss angle meaningful as an absolute value.
• the person skilled in the art can select the appropriate materials at any time for the selected application, that is, for example, 77 GHz for a distance measuring radar.
• the multilevel conductor plate has a signal line structure S1.C1 on the first carrier substrate PCB1 and at least one ground plane M2.M4, preferably connected to ground potential, on each side of the two second carrier substrates PCB2, PCB3.
• a metallization C3 is formed with a desired capacity at the application frequency of appropriate size and shape and the metallization (C3) is over a Via (V (C1-C3)) connected to the signal line structure (C1).
• the capacitance for absorbing high-frequency power to reference potential is formed, as sketched in the figure.
• the poorer higher dielectric losses of the cheaper carrier substrate are specifically exploited.
• the third carrier substrate could be dispensed with and the metallization area in the second metallization level L2 could be arranged directly between the 1st and 2nd carrier substrate and the reference ground position already be arranged in the 3rd metallization level.
• the EMC radiation in the 1st and 2nd carrier substrate would be higher and the size of the metallization surface larger than in the preferred embodiment shown in the figure.
• the multilevel printed circuit board has at least one through-connection (V (M2-M4)) from the first ground layer (M2) to the second ground layer (M4) at a predetermined distance from the metallization surface (C3).
• V (M2-M4) a through-connection
• V1 (M2-M4), V2 (M2-M4) a plurality of vias
• V1 (M2-M4), V2 (M2-M4) arranged spatially preferably distributed approximately uniformly around the metallization surface at a predetermined distance from the metallization surface (C3) from the first to the second ground position M2-M4 intended.
• the size and shape of the metallization of the capacitor determines the capacity and this together with the Indukt foundedsbelag the connection to the metallization C3 a resonant frequency which can be tuned specifically to the frequency required for the application.
• the distance between the outer edge of the metallization surface and the center of the via also influences the damping characteristic of the system. Namely, if one reaches a distance of at least approximately one through a ratio expressable with a rational number of the wavelength of the interference frequency to be eliminated, so there is a quasi standing wave and amplifies the attenuation and thus elimination crucial. Of course, this effect is greatest for exact match, but still a sufficiently good effect can be achieved in the virtually unavoidable deviations. In addition to the size of the Metaiitechniksthesis and thus their capacity determines so the distance of the outer edge of the metallization to the center of the via again the effect. Looking first at FIG.
• the metallization surface is here designed as a full circle with the radius R.
• the radius R also determines the size of the area.
• this shaping offers the possibility, on the one hand on the radius of the distance of the outer edge of the metallization to make the center of the via an optimization to the wavelength of the interference frequency or interference wave, on the other hand, but over the angle of the segment or the area and thus capacitance independently influence and thus both sizes independently to the respective fürsfal! to optimize.
• Rectangular segments are used in which of course in the mathematical sense, the distance of the outer edge of the metallization to the center of the via just does not constantly equal to the length of the side surface of the rectangle, at least if sufficient narrow width B of these rectangular surfaces, ie a width whose length is negligible.
• such rectangular surfaces can possibly be structured much more accurately than circular segments and likewise offer the possibility of optimizing the distance between the outer edge of the metalizing surface and the center of the via, on the one hand, to the wavelength of the interfering wave, and, on the other hand, independently thereof to determine the capacity by adjusting the width of the rectangle.
• trapezoidal segments with a narrow side at the via and a widening of the surface out toward the outer edge of the metallization surface were also used.
• the metallization surface (C3) consists in each case of two segments S1 and S2 with different distances R1> R2 or L1 ⁇ L2.
• Each of these distances is optimized for a different interference frequency to be eliminated, ie with two such segments, two different interference frequencies can be eliminated with a metallization structure by the respective distance R1, R2, L1, L2 of the outer edge of this segment to the center of the via is directed to at least approximately by an expressible with a rational number ratio of the wavelength to these interference frequencies f1, f2.
• a butterfly shape as shown in Figure 2b may be provided, i. a shape with four or more segments arise.
• the choice of the specific material and the properties of the metallization surface, the capacity and, in particular, their ohmic losses for the purpose of dissipating or better vaporizing interference energy, ie the conversion of this energy into heat can be achieved.
• the ohmic loss can certainly also be increased below 15 .mu.m.
• the surface of the metallization just designed specifically targeted rough and so the loss rate can be further increased for the targeted generation of these losses.
• Such a multilevel circuit board is suitable for high-frequency applications, for example a DC voltage supply filter of an amplifier in high frequency, preferably greater than 1 GHz range, in particular for distance measuring radars in motor vehicles.
• such an exemplary embodiment finds application at frequencies above 1 GHz.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Structure Of Printed Boards (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

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ID=45420519

Family Applications (1)

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Cited By (1)

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Citations (5)

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• 2010
  • 2010-08-26 DE DE102010035453A patent/DE102010035453A1/de not_active Withdrawn
• 2011
  • 2011-08-17 WO PCT/DE2011/001625 patent/WO2012025100A1/de not_active Ceased
  • 2011-08-17 JP JP2013527470A patent/JP5863801B2/ja active Active
  • 2011-08-17 DE DE112011102175T patent/DE112011102175A5/de not_active Withdrawn
  • 2011-08-17 EP EP11802260.7A patent/EP2609796B1/de active Active
  • 2011-08-17 US US13/819,052 patent/US8878074B2/en active Active

Patent Citations (5)

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