WO2012017633A1 - プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 - Google Patents
プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 Download PDFInfo
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- WO2012017633A1 WO2012017633A1 PCT/JP2011/004311 JP2011004311W WO2012017633A1 WO 2012017633 A1 WO2012017633 A1 WO 2012017633A1 JP 2011004311 W JP2011004311 W JP 2011004311W WO 2012017633 A1 WO2012017633 A1 WO 2012017633A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/292—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for reset discharge, priming discharge or erase discharge occurring in a phase other than addressing
- G09G3/2927—Details of initialising
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0238—Improving the black level
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
Definitions
- the present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.
- a typical plasma display panel (hereinafter abbreviated as “panel”) as a display device has a large number of discharge cells formed between a front substrate and a rear substrate arranged to face each other.
- a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other.
- a dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
- the back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
- the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed.
- a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.
- ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
- the subfield method is generally used as a method for driving the panel.
- one field is divided into a plurality of subfields, and light emission and non-light emission of each discharge cell are controlled in each subfield.
- gradation display is performed by controlling the number of times of light emission generated in one field.
- Each subfield has an initialization period, an address period, and a sustain period.
- an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell.
- wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.
- a scan pulse is sequentially applied to the scan electrode, and an address pulse is selectively applied to the data electrode based on the image signal to be displayed.
- an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and wall charges are formed in the discharge cell (hereinafter, this operation is also referred to as “address”).
- the number of sustain pulses determined for each subfield is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode.
- a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.)
- each discharge cell emits light at a luminance corresponding to the luminance weight determined for each subfield.
- each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.
- One of the important factors for improving the quality of images displayed on the panel is the improvement of contrast.
- a driving method is disclosed in which light emission not related to gradation display is reduced as much as possible to improve the contrast of an image displayed on the panel.
- an initializing operation for generating an initializing discharge in all the discharge cells in the image display area of the panel is performed in the initializing period of one subfield among a plurality of subfields constituting one field.
- an initializing operation for selectively generating initializing discharge is performed in the discharge cells that have generated sustain discharge in the sustaining period of the immediately preceding subfield.
- all cell initialization operation the initialization operation for generating the initialization discharge in all the discharge cells in the image display area regardless of the operation of the immediately preceding subfield.
- all cell initialization operation an initialization operation that selectively generates an initialization discharge in a discharge cell that has generated a sustain discharge in the sustain period of the immediately preceding subfield.
- the luminance of the black display area where no sustain discharge occurs (hereinafter abbreviated as “black luminance”) varies depending on the light emission that occurs regardless of the magnitude of the gradation value.
- This light emission includes, for example, light emission caused by initialization discharge.
- light emission in the black display region is only weak light emission when performing an initialization operation in which initialization discharge is generated in all the discharge cells. As a result, the black luminance of the image displayed on the panel can be reduced, and an image with high contrast can be displayed on the panel (see, for example, Patent Document 1).
- an initializing waveform having a rising portion having a gradual slope portion where the voltage gradually increases and a falling portion having a gradual slope portion where the voltage gradually decreases is applied to the scan electrode, and the immediately preceding subfield is applied.
- An initializing period for generating an initializing discharge is provided in a discharge cell that has generated a sustaining discharge in the sustaining period, and the sustaining electrodes and scan electrodes for all the discharging cells are provided immediately before any initializing period in one field.
- a driving method is disclosed in which a period during which a weak discharge is generated is provided (see, for example, Patent Document 2). With this driving method, the black luminance of the image displayed on the panel can be reduced and the black visibility can be improved.
- the wall charge of the discharge cell that does not generate a sustain discharge changes due to the influence of the sustain discharge generated in the adjacent discharge cell. It's easy to do. It has also been confirmed that the influence is increased in the subfield where the number of sustain pulses generated in the sustain period is large.
- an erroneous address discharge may occur in a discharge cell that should not generate an address discharge.
- erroneously generated discharge is also referred to as “erroneous discharge”.
- the erroneous discharge causes deterioration of image display quality in the plasma display device.
- the panel has a larger screen and higher definition.
- the plasma display apparatus provides a driving voltage based on a subfield method in which a plurality of subfields having a plurality of scan electrodes and a subfield having an initialization period, an address period, and a sustain period are provided in one field to display gradation.
- a scan electrode driving circuit that generates and applies the scan electrode to the scan electrode.
- the scan electrode drive circuit applies a first ramp waveform voltage that rises from the base potential to the first potential to the scan electrode, and then sets the scan electrode potential to a second potential that is equal to or lower than the first potential. Then, a second ramp waveform voltage rising from the second potential to a third potential higher than the first potential is applied to the scan electrode.
- the second erasing discharge is generated.
- the discharge generation amounts when the second erase discharge is applied to the first erase discharge can be made substantially equal to each other. Therefore, even in a panel having discharge cells miniaturized by high definition, the discharge generation amount of the erasure discharge can be made almost equal to each other in each discharge cell, and the initialization operation and the write operation after the erase operation Can be performed stably.
- the scan electrode driving circuit may use the scan electrode potential once as the base potential after the first ramp waveform voltage reaches the first potential, and then the scan electrode potential as the base potential.
- a second ramp waveform voltage that changes from the potential to the second potential and then increases from the second potential to the third potential may be applied to the scan electrode.
- a panel having a plurality of scan electrodes is driven by a subfield method in which a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field to display gray scales. . Then, at the end of the sustain period, a first ramp waveform voltage that rises from the base potential to the first potential is applied to the scan electrode, and then the potential of the scan electrode is set to a second potential that is equal to or lower than the first potential. Subsequently, a second ramp waveform voltage that rises from the second potential to a third potential that is higher than the first potential is applied to the scan electrode.
- the second erasing discharge is generated.
- the discharge generation amounts when the second erase discharge is applied to the first erase discharge can be made substantially equal to each other. Therefore, even in a panel having discharge cells miniaturized by high definition, the discharge generation amount of the erasure discharge can be made almost equal to each other in each discharge cell, and the initialization operation and the write operation after the erase operation Can be performed stably.
- the potential of the scan electrode is once set as the base potential, and then the potential of the scan electrode is changed from the base potential to the second potential.
- a second ramp waveform voltage that rises from the second potential to the third potential may be applied to the scan electrode.
- FIG. 1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention.
- FIG. 2 is an electrode array diagram of a panel used in the plasma display device according to one embodiment of the present invention.
- FIG. 3 is a waveform diagram showing an example of a drive voltage waveform applied to each electrode of the panel used in the plasma display device according to one embodiment of the present invention.
- FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention.
- FIG. 5 is a circuit diagram showing a configuration example of the scan electrode driving circuit in one embodiment of the present invention.
- FIG. 6 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the last period of the sustain period and the selective initialization period in the embodiment of the present invention.
- FIG. 7 is a characteristic diagram showing the relationship between the voltage Vr2 and the write pulse (amplitude) in one embodiment of the present invention.
- FIG. 8 is a characteristic diagram showing the relationship between voltage Vr2 and black luminance in one embodiment of the present invention.
- FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device according to one embodiment of the present invention.
- a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21.
- a dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.
- This protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient when encapsulating neon (Ne) and xenon (Xe) gas, and It is made of a material mainly composed of magnesium oxide (MgO) having excellent durability.
- a plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon.
- a phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
- the front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween.
- the outer peripheral part is sealed with sealing materials, such as glass frit.
- a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.
- a discharge gas with a xenon partial pressure of about 10% is used in order to improve the light emission efficiency in the discharge cell.
- the discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. Thus, a plurality of discharge cells are formed on the panel 10.
- discharge is generated in these discharge cells, and the phosphor layer 35 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.
- One pixel is composed of three discharge cells that emit blue (B) light.
- the structure of the panel 10 is not limited to the above-described structure, and for example, the panel may be provided with stripe-shaped partition walls in which the partition walls are arranged only in the vertical direction (column direction).
- the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.
- FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to one embodiment of the present invention.
- the panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) extended in the horizontal direction (row direction) and n sustain electrodes SU1 to SUn (sustain electrodes in FIG. 1). 23), and m data electrodes D1 to Dm (data electrode 32 in FIG. 1) extending in the vertical direction (column direction) are arranged.
- the plasma display device in the present embodiment displays gradation on the panel 10 by the subfield method.
- the subfield method one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield.
- Each subfield has an initialization period, an address period, and a sustain period.
- an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.
- one of two initialization operations of “all cell initialization operation” and “selective initialization operation” is performed in the initialization period.
- the all-cell initializing operation is an initializing operation for generating an initializing discharge in all the discharge cells in the image display area regardless of the operation of the immediately preceding subfield.
- the selective initializing operation is an initializing operation that generates an initializing discharge only in a discharge cell that has generated a sustaining discharge in the sustaining period of the immediately preceding subfield.
- the selective initialization operation is performed.
- the all-cell initializing waveform for performing the all-cell initializing operation is applied to the discharge cells, and the initializing periods of the other subfields
- a selective initialization waveform for performing a selective initialization operation is applied to the discharge cells.
- the initialization period for performing the all-cell initialization operation is referred to as “all-cell initialization period”, and the subfield having the all-cell initialization period is referred to as “all-cell initialization subfield”.
- An initialization period for performing the selective initialization operation is referred to as a “selective initialization period”, and a subfield having the selective initialization period is referred to as a “selective initialization subfield”.
- the address period by generating address discharge in the discharge cells to emit light, the light emission / non-light emission of each discharge cell is controlled for each subfield.
- the number of sustain pulses obtained by multiplying the brightness weight of each subfield by a predetermined brightness magnification is applied to each display electrode pair 24.
- An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.
- the luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, various gradations can be displayed on the panel 10 and images can be displayed on the panel 10 by selectively emitting each subfield in a combination according to the image signal.
- one field is composed of eight subfields from subfield SF1 to subfield SF8, and each subfield from subfield SF1 to subfield SF8 has (1, 2, 4, An example of setting luminance weights of 8, 16, 32, 64, and 128) will be described.
- subfield SF1 is an all-cell initialization subfield
- subfields SF2 to SF8 are selective initialization subfields.
- the number of subfields and the luminance weight of each subfield are not limited to the above values.
- the structure which switches the structure of a subfield based on an image signal etc. may be sufficient.
- two rising ramp waveform voltages are continuously generated at the end of the sustain period.
- the initialization operation in the initialization period of the subsequent subfield and the write operation in the write period are stabilized.
- the outline of the drive voltage waveform will be described first, and then the configuration of the drive circuit will be described.
- FIG. 3 is a waveform diagram showing an example of a drive voltage waveform applied to each electrode of the panel 10 used in the plasma display device in one embodiment of the present invention.
- FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080), sustain electrode SU1 to sustain electrode SUn, and data electrode D1.
- FIG. 4 shows driving voltage waveforms applied to each of the data electrodes Dm.
- subfield SF1 for performing all-cell initialization operation in the initialization period
- subfield SF2 for performing selective initialization operation in the initialization period
- each subfield except subfield SF1 is a selective initialization subfield in the present embodiment, and each period except for the number of sustain pulses generated. Generates substantially the same drive voltage waveform. Therefore, the waveform shape of the drive voltage applied to scan electrode 22 in the initialization period differs between subfield SF1 and subfield SF2 to subfield SF8.
- scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from each electrode based on subfield data (data indicating light emission / non-light emission for each subfield).
- subfield SF1 which is an all-cell initialization subfield
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn.
- voltage Vi1 is applied and then gradually from voltage Vi1 to voltage Vi2 (for example, at a gradient of about 1.3 V / ⁇ sec).
- a rising ramp waveform voltage (hereinafter referred to as “up-ramp voltage L1”) is applied.
- voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn
- voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
- weak initializing discharges are continuously generated.
- Negative wall voltage is accumulated on scan electrode SC1 through scan electrode SCn, and is positive on sustain electrode SU1 through sustain electrode SUn and on data electrode D1 through data electrode Dm intersecting scan electrode SC1 through scan electrode SCn.
- Sex wall voltage is accumulated.
- the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 25 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.
- voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn
- voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
- the above voltage waveform is the all-cell initialization waveform that generates the initialization discharge in the discharge cells regardless of the operation of the immediately preceding subfield.
- the operation for applying the all-cell initialization waveform to the scan electrode 22 is the all-cell initialization operation.
- a scan pulse is sequentially applied to scan electrode SC1 through scan electrode SCn, and an address pulse is applied to data electrode Dk corresponding to a discharge cell to emit light to data electrode D1 through data electrode Dm.
- address discharge is selectively generated only in the discharge cells to emit light, and wall charges necessary for generating the sustain discharge in the subsequent sustain period are formed in the discharge cells.
- write operations are also referred to as “write operations”.
- voltage Ve2 is applied to sustain electrode SU1 through sustain electrode SUn
- voltage Vcc Va + Vsc
- a scan pulse of a negative voltage Va is applied to the first scan electrode SC1 from the top (first row) in terms of arrangement, and light is emitted from the first row of the data electrodes D1 to Dm.
- An address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell to be performed.
- the voltage difference at the intersection between the data electrode Dk of the discharge cell to which the address pulse of the voltage Vd is applied and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd ⁇ voltage Va) and the wall voltage on the data electrode Dk and the scan electrode.
- the difference from the wall voltage on SC1 is added.
- the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.
- the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve2 ⁇ voltage Va) and sustain electrode SU1.
- the difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added.
- the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.
- a discharge generated between the data electrode Dk and the scan electrode SC1 can be triggered to generate a discharge between the sustain electrode SU1 and the scan electrode SC1 in the region intersecting the data electrode Dk.
- an address discharge is generated in the discharge cell to emit light, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative polarity is also formed on data electrode Dk.
- the wall voltage is accumulated.
- the above address operation is sequentially performed in the order of scan electrode SC2, scan electrode SC3,..., Scan electrode SCn until reaching the discharge cell in the n-th row, and the address period of subfield SF1 is completed.
- address discharge is selectively generated in the discharge cells to emit light, and wall charges are formed in the discharge cells.
- the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is alternately applied to the scan electrode 22 and the sustain electrode 23, and the discharge that generated the address discharge in the immediately preceding address period
- a sustain operation is performed in which a sustain discharge is generated in the cell and the discharge cell emits light.
- This proportional constant is the luminance magnification.
- the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.
- the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi.
- the fluorescent substance layer 35 light-emits with the ultraviolet-ray which generate
- negative wall voltage is accumulated on scan electrode SCi
- positive wall voltage is accumulated on sustain electrode SUi.
- a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
- sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.
- scan electrode SC1 to scan are performed while voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm.
- the electrode SCn has a first ramp waveform voltage (hereinafter referred to as “erase”) that gradually increases (for example, with a gradient of about 10 V / ⁇ sec) from the voltage 0 (V) that is the base potential to the voltage Vers that is the first potential.
- Erase first ramp waveform voltage
- the erase lamp voltage L3 applied to scan electrode SC1 through scan electrode SCn rises above the discharge start voltage, and the discharge cells that have generated the sustain discharge A weak discharge is continuously generated between the sustain electrode SUi and the scan electrode SCi.
- the charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi.
- the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are the difference between the voltage applied to the scan electrode SCi and the discharge start voltage, for example, while leaving the positive wall voltage on the data electrode Dk. It is weakened to the level of (Voltage Vers ⁇ discharge start voltage).
- this discharge is referred to as “erase discharge”.
- the erasing discharge is a discharge for erasing a part of unnecessary wall charges in the discharge cell.
- voltage Vsc which is the second potential
- the voltage Vsc is set to a voltage value equal to or lower than the voltage Vers.
- sustain voltage SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm are applied with voltage 0 (V) to scan electrode SC1 to scan electrode SCn from voltage Vsc, which is the second potential, to third voltage.
- a second ramp waveform voltage (hereinafter referred to as “erase ramp voltage L5”) that rises at the same slope as the erase ramp voltage L3 (for example, at a slope of about 10 V / ⁇ sec) is applied to the voltage Vr2 that is the potential of To do.
- the voltage Vr2 is set to a voltage value higher than the voltage Vers. Therefore, while the erase lamp voltage L5 applied to scan electrode SC1 through scan electrode SCn rises above voltage Vers, a weak erase discharge continues again in the discharge cell in which an erase discharge is generated by erase lamp voltage L3. Occur.
- two erasing discharges that is, an erasing discharge by the erasing ramp voltage L3 and an erasing discharge by the erasing ramp voltage L5 are generated in the discharge cell that has generated the sustain discharge. Therefore, the wall charges in the discharge cell can be erased more stably compared to the configuration in which the erase discharge is generated only by the erase lamp voltage L3. Thereby, also in the panel 10 having the discharge cells miniaturized by high definition, the initialization operation and the write operation after the erase operation can be stably performed.
- the selective initializing waveform is applied to all the scan electrodes 22.
- This selective initialization waveform is a drive voltage waveform in which the first half of the all-cell initialization waveform is omitted.
- voltage Ve1 is applied to sustain electrode SU1 through sustain electrode SUn
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm.
- the voltage falls below the discharge start voltage (for example, voltage 0 (V)) toward negative voltage Vi4 exceeding the discharge start voltage with the same gradient as the down-ramp voltage L2.
- a down-ramp voltage L4 is applied.
- the above waveform is a selective initializing waveform in which initializing discharge is generated only in the discharge cells that have generated sustain discharge in the sustain period of the immediately preceding subfield.
- the operation of applying the selective initialization waveform to the scan electrode 22 is the selective initialization operation.
- a drive voltage waveform similar to that in the address period of the subfield SF1 is applied to each electrode, and an address operation for accumulating wall voltage on each electrode of the discharge cell to emit light is performed.
- the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.
- a sustain discharge is generated in a discharge cell that has generated an address discharge in the address period.
- each subfield after subfield SF3 In the initialization period and address period of each subfield after subfield SF3, the same drive voltage waveform as that in the initialization period and address period of subfield SF2 is applied to each electrode. In the sustain period of each subfield after subfield SF3, the same drive voltage waveform as in subfield SF2 is applied to each electrode except for the number of sustain pulses generated.
- Voltage Ve1 125 (V)
- voltage Ve2 130 (V)
- voltage Vers 190 (V)
- voltage Vsc 145 (V)
- voltage Vs 190 (V)
- voltage Va ⁇ 180 (V)
- each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
- FIG. 4 is a circuit block diagram of the plasma display device 1 according to the embodiment of the present invention.
- the plasma display device 1 includes a panel 10 and a drive circuit.
- the drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a control signal generation circuit 45, and a power supply circuit (not shown) that supplies power necessary for each circuit block. )).
- the image signal processing circuit 41 assigns a gradation value to each discharge cell based on the number of pixels of the panel 10 and the input image signal sig. Then, the gradation value is converted into subfield data indicating light emission / non-light emission for each subfield (data corresponding to light emission / non-light emission corresponding to digital signals “1” and “0”). That is, the image signal processing circuit 41 converts the image signal for each field into subfield data indicating light emission / non-light emission for each subfield.
- each gradation value of R, G, and B is assigned to each discharge cell based on the R signal, the G signal, and the B signal.
- the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal, etc.)
- the luminance signal and saturation signal Based on the degree signal, R signal, G signal, and B signal are calculated, and thereafter, R, G, and B gradation values (gradation values expressed in one field) are assigned to each discharge cell. Then, the R, G, and B gradation values assigned to each discharge cell are converted into subfield data indicating light emission / non-light emission for each subfield.
- the control signal generation circuit 45 generates various control signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V. Then, the generated control signal is supplied to each circuit block (image signal processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, etc.).
- the data electrode drive circuit 42 converts the subfield data for each subfield into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the control signal supplied from the control signal generating circuit 45, the data electrodes D1 to Dm are driven. In the address period, an address pulse is generated and applied to each of the data electrodes D1 to Dm.
- Scan electrode drive circuit 43 includes an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 4). Then, a drive voltage waveform is created based on the control signal supplied from the control signal generation circuit 45 and applied to each of scan electrode SC1 to scan electrode SCn.
- the initialization waveform generation circuit generates an initialization waveform to be applied to scan electrode SC1 to scan electrode SCn based on the control signal during the initialization period.
- the sustain pulse generating circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn based on the control signal during the sustain period.
- the scan pulse generating circuit includes a plurality of scan electrode driving ICs (hereinafter abbreviated as “scan ICs”), and generates scan pulses to be applied to scan electrode SC1 to scan electrode SCn based on a control signal during an address period. .
- scan ICs scan electrode driving ICs
- Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve1 and voltage Ve2 (not shown in FIG. 4), and generates a drive voltage waveform based on a control signal supplied from control signal generation circuit 45. It is prepared and applied to each of sustain electrode SU1 through sustain electrode SUn. In the sustain period, a sustain pulse is generated based on the control signal and applied to sustain electrode SU1 through sustain electrode SUn.
- FIG. 5 is a circuit diagram showing an example of the configuration of scan electrode drive circuit 43 in one embodiment of the present invention.
- the scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 51 that generates an initialization waveform, and a scan pulse generation circuit 52 that generates a scan pulse.
- Each output terminal of scan pulse generating circuit 52 is connected to each of scan electrode SC1 through scan electrode SCn of panel 10.
- the voltage input to the scan pulse generation circuit 52 is referred to as “reference potential A”.
- the operation for conducting the switching element is expressed as “on”
- the operation for shutting off is expressed as “off”
- the signal for turning on the switching element is expressed as “Hi”
- the signal for turning off is expressed as “Lo”. To do.
- FIG. 5 details of the signal path of the control signal (control signal supplied from the control signal generation circuit 45) input to each circuit are omitted.
- FIG. 5 shows a circuit using the negative voltage Va (for example, the Miller integrating circuit 54), the circuit, the sustain pulse generating circuit 50, and a circuit using the voltage Vr (for example, , Miller integrating circuit 53) and a circuit using voltage Vers (for example, Miller integrating circuit 55), a separation circuit using switching element Q4 for electrically separating.
- the circuit and a circuit using a voltage Vers having a voltage lower than the voltage Vr (for example, the Miller integrating circuit 55) 2 shows a separation circuit using a switching element Q6 for electrically separating the two.
- Sustain pulse generation circuit 50 includes a generally used power recovery circuit (not shown) and a clamp circuit (not shown).
- the power recovery circuit has a capacitor for power recovery and an inductor for resonance. Then, by causing the interelectrode capacitance Cp of the panel 10 and the resonance inductor to resonate, the power stored in the power recovery capacitors is supplied to the scan electrodes SC1 to SCn, or the interelectrode capacitance Cp is supplied to the interelectrode capacitance Cp. The stored power is recovered in a power recovery capacitor.
- the clamp circuit clamps scan electrode SC1 to scan electrode SCn to voltage Vs, or clamps scan electrode SC1 to scan electrode SCn to voltage 0 (V).
- the sustain pulse generation circuit 50 operates while switching between the power recovery circuit and the clamp circuit by switching each switching element provided inside based on the control signal output from the control signal generation circuit 45, and generates a sustain pulse. appear.
- the scan pulse generation circuit 52 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse to each of the n scan electrodes SC1 to SCn.
- the other terminal of the switching element QHj is the input terminal INb, and the other terminal of the switching element QLj is the input terminal INa.
- switching elements QH1 to QHn and the switching elements QL1 to QLn are integrated into a plurality of outputs and integrated into an IC.
- This IC is a scanning IC.
- the scan pulse generation circuit 52 includes a switching element Q5 for connecting the reference potential A to the negative voltage Va in the writing period, a power supply VSC that generates the voltage Vsc and superimposes the voltage Vsc on the reference potential A, a reference A diode Di31 and a capacitor C31 for applying a voltage Vc generated by superimposing the voltage Vsc on the potential A to the input terminal INb are provided.
- the voltage Vc is input to the input terminals INb of the switching elements QH1 to QHn
- the reference potential A is input to the input terminals INa of the switching elements QL1 to QLn.
- the switching element Q5 in the address period, the switching element Q5 is turned on to make the reference potential A equal to the negative voltage Va, and the negative voltage Va is applied to the input terminal INa.
- the voltage Vcc which is the voltage Va + voltage Vsc, is applied to the input terminal INb.
- the switching element QHi is turned off and the switching element QLi is turned on so that the scan electrode SCi is negatively connected to the scan electrode SCi via the switching element QLi.
- a scan pulse of voltage Va is applied.
- the switching element QLh is turned off and the switching element QHh is turned on, thereby passing through the switching element QHh.
- Scan pulse generation circuit 52 is controlled by control signal generation circuit 45 to output the voltage waveform of initialization waveform generation circuit 51 in the initialization period and to output the voltage waveform of sustain pulse generation circuit 50 in the sustain period. Is done.
- the initialization waveform generation circuit 51 includes a Miller integration circuit 53, a Miller integration circuit 54, and a Miller integration circuit 55.
- the input terminal of Miller integrating circuit 53 is shown as input terminal IN1
- the input terminal of Miller integrating circuit 54 is shown as input terminal IN2
- the input terminal of Miller integrating circuit 55 is shown as input terminal IN3.
- Miller integrating circuit 53 and Miller integrating circuit 55 are ramp voltage generating circuits that generate rising ramp waveform voltages
- Miller integrating circuit 54 is a ramp voltage generating circuit that generates falling ramp waveform voltages.
- Miller integrating circuit 53 has switching element Q1, capacitor C1, and resistor R1, and during the all-cell initialization operation, reference potential A of scan electrode driving circuit 43 is gradually ramped up to voltage Vr (eg, 1.. It rises (at 3V / ⁇ sec).
- Vr voltage
- switching elements QH1 to QHn are turned on, and switching elements QL1 to QLn are turned off. Therefore, the reference potential A rises from the voltage 0 (V) to the voltage Vr, and a voltage obtained by superimposing the voltage Vsc on the reference potential A is applied to scan electrode SC1 through scan electrode SCn.
- L1 is generated and applied to scan electrode SC1 through scan electrode SCn.
- Miller integrating circuit 55 has switching element Q3, capacitor C3, and resistor R3. At the end of the sustain period, Miller integrating circuit 55 sets reference potential A to a voltage 0 (with a steeper slope (eg, 10 V / ⁇ sec) than rising ramp voltage L1. V) rises to voltage Vers to generate erase ramp voltage L3, which is applied to scan electrode SC1 through scan electrode SCn. Miller integrating circuit 55 generates erasing ramp voltage L5. In the present embodiment, switching element QH1 to switching element QHn are turned on and switching element QL1 to switching element QLn are turned off during the period of generation of erase ramp voltage L5.
- scan electrode drive circuit 43 generates erase ramp voltage L5 and applies it to scan electrode SC1 through scan electrode SCn.
- Miller integrating circuit 54 includes switching element Q2, capacitor C2, and resistor R2, and during initialization operation, reference potential A is gradually ramped from voltage 0 (V) to voltage Vi4 (for example, ⁇ 2.5 V).
- V voltage
- Vi4 voltage
- the ramp down voltage L2 and the down ramp voltage L4 are generated and applied to scan electrode SC1 through scan electrode SCn.
- FIG. 6 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 in the last period of the sustain period and the selective initialization period in the embodiment of the present invention.
- the last period of the sustain period is divided into six periods indicated by periods T1 to T6, the selective initialization period is indicated as period T7, and each period will be described.
- the voltage Vers is equal to the voltage Vs
- the voltage Vsc is lower than the voltage Vers
- the voltage Vr2 is higher than the voltage Vers
- the voltage Vi4 is equal to the negative voltage Va.
- a signal for turning on the switching element is represented as “Hi”
- a signal for turning off is represented as “Lo”.
- FIG. 6 shows an example in which the voltage Vsc is set to a voltage value lower than the voltage Vers and the voltage Vr2 is set to a voltage value higher than the voltage Vers.
- the voltage Vsc is set.
- Each voltage value is set so that ⁇ voltage Vers ⁇ voltage Vr2. That is, the second potential is set to a potential equal to or lower than the first potential, and the third potential is set to a potential higher than the first potential.
- the erasing ramp voltage L3, the erasing ramp voltage L5 in the last period of the sustain period, and then the down ramp voltage L4 in the selective initialization period will be described in this order. Note that the generation of the sustain pulse is finished before the period T1 is entered.
- the reference potential A is set to the voltage 0 (V) by the clamp circuit of the sustain pulse generating circuit 50. Then, switching element QH1 to switching element QHn are turned off, switching element QL1 to switching element QLn are turned on, and reference potential A, that is, voltage 0 (V) is applied to scan electrode SC1 to scan electrode SCn.
- Period T1 In the period T1, the switching elements QH1 to QHn are turned off, and the switching elements QL1 to QLn are kept on.
- the switching element Q6 is turned on and the Miller integrating circuit 55 is electrically connected to the reference potential A. Further, each switching element of sustain pulse generating circuit 50 is turned off, and sustain pulse generating circuit 50 is electrically separated from Miller integrating circuit 55.
- the input terminal IN3 of the Miller integrating circuit 55 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN3. Thereby, a constant current flows toward the capacitor C3, and the source voltage of the switching element Q3 starts to rise in a ramp shape. Thereby, the reference potential A rises from the voltage 0 (V) in a ramp shape, and the output voltage of the scan electrode driving circuit 43 rises in a ramp shape. This voltage increase continues until the input terminal IN3 is set to “Hi” or until the reference potential A reaches the voltage Vers.
- a constant current to be input to the input terminal IN3 is generated so that the gradient of the ramp waveform voltage becomes a desired value (for example, 10 V / ⁇ sec).
- the erase ramp voltage L3 rising from the voltage 0 (V) toward the voltage Vers is generated and applied to scan electrode SC1 through scan electrode SCn.
- the discharge generated by the erase lamp voltage L3 is the first erase discharge.
- the data electrode D1 to the data electrode Dm are held at 0 (V) at this time, so that the positive electrode is placed on the data electrode Dk corresponding to the discharge cell that has generated the erase discharge. A wall voltage is formed.
- the gradient of the period T1, the voltage Vers, the erasing ramp voltage L3, and the like are set to values at which erasing discharge occurs even in a discharge cell having a relatively high discharge starting voltage in consideration of such a variation in the discharge starting voltage.
- the voltage Vers may be a voltage equal to or higher than the voltage Vs, or may be a voltage equal to or lower than the voltage Vs.
- the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T1.
- the reference potential A is set to voltage 0 (V) by the clamp circuit of the sustain pulse generation circuit 50.
- the voltage of scan electrode SC1 through scan electrode SCn drops to the voltage 0 (V) which is the base potential.
- Period T3 In period T3, switching element QH1 to switching element QHn are turned on and switching element QL1 to switching element QLn are turned off while maintaining reference potential A at voltage 0 (V) by the clamp circuit of sustain pulse generating circuit 50. Thereby, a voltage obtained by superimposing voltage Vsc on reference potential A is applied to scan electrode SC1 through scan electrode SCn. At this time, since the reference potential A is 0 (V), voltage Vsc is applied to scan electrode SC1 through scan electrode SCn.
- the voltage Vsc is set to a voltage value equal to or lower than the voltage Vers. Therefore, no discharge is generated in the period T3 even in the discharge cells in which the erasing discharge is generated by the erasing ramp voltage L3.
- Period T4 In the period T4, the switching elements QH1 to QHn are turned on and the switching elements QL1 to QLn are kept off.
- the switching element Q6 is turned on and the Miller integrating circuit 55 is electrically connected to the reference potential A. Further, each switching element of sustain pulse generating circuit 50 is turned off, and sustain pulse generating circuit 50 is electrically separated from Miller integrating circuit 55.
- the input terminal IN3 of the Miller integrating circuit 55 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN3. As a result, a constant current flows toward the capacitor C3, the source voltage of the switching element Q3 increases in a ramp shape, and the reference potential A starts to increase in a ramp shape from the voltage 0 (V). At this time, a constant current to be input to the input terminal IN3 is generated so that the gradient of the ramp waveform voltage becomes a desired value (for example, 10 V / ⁇ sec). This voltage increase continues as long as the input terminal IN3 is set to “Hi”, or until the reference potential A reaches the voltage Vers, as described in the period T1.
- the output voltage of the scan electrode driving circuit 43 is a voltage obtained by superimposing the voltage Vsc on the reference potential A. Therefore, the scan electrode driving circuit 43 outputs a ramp waveform voltage that rises from the voltage Vsc with the same gradient as the erase ramp voltage L3, for example.
- scan electrode drive circuit 43 generates erase ramp voltage L5 that rises from voltage Vsc toward voltage Vr2 during period T4, and applies it to scan electrode SC1 through scan electrode SCn.
- the discharge generated by the erase lamp voltage L5 is the second erase discharge.
- the inventor of the present application generates a second erasing discharge in a discharge cell having a relatively large discharge generation amount (discharge duration) of the erasing discharge (first erasing discharge) generated by the erasing ramp voltage L3.
- discharge duration discharge generation amount of the erasing discharge (first erasing discharge) generated by the erasing ramp voltage L3.
- discharge start voltage when the second erase discharge is generated is relatively low in the discharge cell in which the discharge generation voltage of the first erase discharge is relatively small. This was confirmed by experiments.
- the discharge generation amount of the second erase discharge varies depending on the discharge generation amount of the first erase discharge.
- the timing at which the second erase discharge is started is delayed as compared with a discharge cell having a relatively small amount of discharge.
- the amount of discharge generated in the first erasing discharge is relatively small.
- the amount of discharge generated is relatively large.
- the discharge generation amount of the first erase discharge is relatively large.
- the amount of discharge generated is relatively small.
- the discharge generation amount which is the sum of the discharge generation amount of the first erase discharge and the discharge generation amount of the second erase discharge, is a discharge cell having a relatively high discharge start voltage when generating the first erase discharge. And a discharge cell having a relatively low discharge starting voltage when the first erasing discharge is generated.
- the second time By generating the erasing discharge, the discharge generation amounts when the second erasing discharge is added to the first erasing discharge can be made substantially equal to each other.
- the discharge start voltage in the discharge cell varies depending on the design of the image displayed so far and the presence or absence of discharge in the surrounding discharge cells. And in the panel 10 which has the discharge cell refined
- the discharge generation amount of the erasing discharge can be made almost equal to each other in each discharge cell, and the erasing operation can be appropriately performed to achieve the wall. Since the charge can be adjusted appropriately, the initialization operation and the write operation after the erase operation can be performed stably.
- the voltage Vr2 when the voltage Vr2 is set to 255 (V), if the voltage Vsc is 145 (V), the input terminal IN3 is set to “Lo” when the reference potential A reaches the voltage 110 (V).
- the voltage applied to scan electrode SC1 through scan electrode SCn becomes the voltage up to 255 (V) when voltage 110 (V) of reference potential A is superimposed on 145 (V) of voltage Vsc.
- the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T4.
- the reference potential A is set to voltage 0 (V) by the clamp circuit of the sustain pulse generation circuit 50. Since the voltage applied to scan electrode SC1 through scan electrode SCn is a voltage obtained by superimposing voltage Vsc on reference potential A, the voltage applied to scan electrode SC1 through scan electrode SCn drops to voltage Vsc.
- Period T6 Although not shown in the period T6, the reference potential A is maintained at the voltage 0 (V) by the clamp circuit of the sustain pulse generation circuit 50. Then, switching elements QH1 to QHn are turned off, and switching elements QL1 to QLn are turned on. As a result, the voltage of scan electrode SC1 through scan electrode SCn drops to the voltage 0 (V) which is the base potential.
- Period T7 In the period T7 which is the selective initialization period, the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T6.
- switching element Q4 is turned off to electrically isolate Miller integrating circuit 53, Miller integrating circuit 55, and sustain pulse generating circuit 50 from reference potential A.
- the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp voltage L4 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN2. As a result, a constant current flows toward the capacitor C2, the drain voltage of the switching element Q2 starts to decrease in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also decreases in a ramp shape toward the negative voltage Vi4. Begin to. This voltage drop continues until the input terminal IN2 is set to “Hi” or until the reference potential A reaches the voltage Va.
- the ramp-down voltage L4 that decreases from the voltage 0 (V) that is the base potential toward the negative voltage Vi4 is generated and applied to scan electrode SC1 through scan electrode SCn.
- the input terminal IN2 is set to “Lo”. Specifically, the constant current input to the input terminal IN2 is stopped. Thus, the operation of Miller integrating circuit 54 is stopped. Although not shown, the switching element Q4 is turned on, and the reference potential A is connected to 0 (V) by the clamp circuit of the sustain pulse generating circuit. As a result, the voltage of scan electrode SC1 through scan electrode SCn rises to voltage 0 (V), which is the base potential.
- each voltage value is set such that voltage Vsc ⁇ voltage Vers ⁇ voltage Vr2. This is because the second erase discharge does not occur if the voltage Vr2 is lower than the voltage Vsc, and when the voltage Vers is lower than the voltage Vsc, the voltage Vsc is applied to the scan electrodes SC1 to SCn in the period T3. This is because a strong discharge is generated in the discharge cell, and the wall charges in the discharge cell are excessively erased, and the subsequent discharge may not be normally generated.
- the effect of reducing the amplitude of the address pulse necessary for generating a stable address discharge in the address period can be obtained.
- FIG. 7 is a characteristic diagram showing the relationship between the voltage Vr2 and the write pulse (amplitude) in one embodiment of the present invention.
- the horizontal axis represents the voltage Vr2
- the vertical axis represents the magnitude of the address pulse (amplitude) necessary for generating a stable address discharge.
- the experiment for obtaining the characteristics shown in FIG. 7 was performed with the voltage Vers set to a voltage of 190 (V). Therefore, the magnitude of the write pulse (amplitude) when the voltage Vr2 shown in FIG. 7 is set to the voltage 190 (V) represents the result of measurement without generating the erase ramp voltage L5.
- the magnitude of the address pulse (amplitude) necessary for generating a stable address discharge can be reduced.
- the magnitude of the write pulse (amplitude) when the voltage Vr2 is set to the voltage 190 (V) is about 65 (V), but the voltage Vr2 is set to the voltage 220 (V).
- the magnitude of the write pulse (amplitude) when set is about 56 (V). Therefore, in the plasma display device used in the experiment, by setting the voltage Vr2 to the voltage 220 (V), the write pulse (amplitude) is set to about 9 (V) compared to when the voltage Vr2 is set to the voltage 190 (V). It can be seen that it can be reduced.
- the second erasing discharge is generated in addition to the first erasing discharge, so that there is a difference in the discharge starting voltage when the first erasing discharge is generated between the discharge cells. Even if the discharge generation amount varies, the discharge generation amounts when the second erase discharge is applied to the first erase discharge can be made substantially equal to each other in each discharge cell. This is considered to be possible to stably perform the write operation and the write operation.
- the voltage Vr2 may be set to a larger voltage value.
- the voltage Vr2 is increased, there is a possibility that a discharge cell in which an erasing discharge is generated despite the occurrence of the sustain discharge is generated.
- FIG. 8 is a characteristic diagram showing the relationship between the voltage Vr2 and the black luminance in one embodiment of the present invention.
- the horizontal axis represents the voltage Vr2
- the vertical axis represents the brightness of the black luminance.
- the black luminance does not change when the voltage Vr2 is equal to or lower than the voltage 210 (V), but the black luminance increases when the voltage Vr2 becomes the voltage 220 (V). This indicates that in the plasma display device used in the experiment, when the voltage Vr2 is set to the voltage 220 (V), a discharge cell in which an erasing discharge is generated is generated even though the sustain discharge is not generated.
- Vr2 it is desirable to set the voltage Vr2 to be equal to or lower than the voltage 210 (V) in order to prevent the erasure discharge from being erroneously generated (error occurrence).
- the magnitude of the address pulse (amplitude) necessary for generating a stable address discharge is reduced.
- An erroneous erasure discharge can be prevented and a good contrast image can be displayed on the panel.
- the voltage Vr2 reduces the magnitude of the address pulse (amplitude) necessary to generate a stable address discharge and is described with reference to FIG.
- the first ramp waveform voltage rising from the base potential to the first potential is applied to scan electrodes SC1 to SC1.
- the potential of scan electrode SC1 through scan electrode SCn is once set as the base potential, and then scan electrode SC1 through scan electrode SCn. Is applied to scan electrode SC1 through scan electrode SCn.
- the second ramp waveform voltage rising from the second potential to the third potential is applied to scan electrode SC1 through scan electrode SCn.
- erase ramp voltage L3 that rises from voltage 0 (V) to voltage Vers is applied to scan electrode SC1 through scan electrode SCn in the last period of the sustain period after generation of the sustain pulse ends. Subsequently, the potential of scan electrode SC1 through scan electrode SCn is set as the base potential, and then voltage Vsc is applied to scan electrode SC1 through scan electrode SCn, followed by erase ramp voltage L5 rising from voltage Vsc to voltage Vr2. Are applied to scan electrode SC1 through scan electrode SCn.
- the second potential is set to a potential lower than the first potential
- the third potential is set to a potential higher than the first potential
- the second erasing discharge is generated.
- the discharge generation amounts when the second erase discharge is applied to the first erase discharge can be made substantially equal to each other. Therefore, even in the panel 10 having the discharge cells miniaturized by high definition, the discharge generation amount of the erasure discharge can be made substantially equal to each other in the discharge cells, and the erasure operation is appropriately performed to perform the wall charge. Therefore, the initialization operation and the write operation after the erase operation can be stably performed.
- the base potential is 0 (V)
- the base potential is not limited to 0 (V) in the present invention.
- the base potential is a reference potential when a drive voltage is applied to the panel 10.
- the configuration in which the potential of scan electrode SC1 to scan electrode SCn is once lowered to the base potential after the first ramp waveform voltage has reached the first potential has been described.
- the configuration is not limited. For example, after the first ramp waveform voltage reaches the first potential, the potentials of scan electrode SC1 to scan electrode SCn are decreased from the first potential to the second potential, and then the second ramp waveform voltage is changed.
- the structure to apply may be sufficient.
- all-cell initialization waveform in the present invention is not limited to the waveform shown in the embodiment.
- the all-cell initializing waveform may be any waveform as long as the initializing discharge is generated in the discharge cell regardless of the operation of the immediately preceding subfield.
- the configuration in which the selection initialization waveforms (down-ramp voltage L4) generated in the selection initialization period are all generated with the same gradient has been described.
- the present invention does not select any of the selection initialization waveforms. It is not limited to the shape.
- the selective initialization waveform may have any waveform shape as long as the initializing discharge is generated only in the discharge cells that have generated the sustain discharge in the immediately preceding sustain period.
- the selection initialization waveform may be divided into a plurality of periods, and the selection initialization waveform may be generated by changing the gradient in each period.
- the voltage applied to the scan electrode 22 decreases at a relatively steep gradient (eg, ⁇ 8 V / ⁇ sec) until discharge occurs (eg, from voltage 0 (V) to ⁇ 100 (V)). After that (for example, from ⁇ 100 (V) to ⁇ 135 (V)), it gradually falls (for example, with a slope of ⁇ 2.5 V / ⁇ sec), and finally (for example, from ⁇ 135 (V)) (Down to ⁇ 160 (V)) may decrease at a relatively gentle slope (for example, ⁇ 1.0 V / ⁇ sec) to generate a selective initialization waveform. Even if it is such a structure, the effect similar to the above can be acquired. Further, with this configuration, it is possible to obtain an effect that the period required for generating the selective initialization waveform can be shortened as compared with the case where the down-ramp voltage L4 is generated.
- a relatively steep gradient eg, ⁇ 8 V / ⁇ sec
- the first subfield (subfield SF1) of one field is an all-cell initializing subfield
- the subsequent subfields for example, subfield SF2 to subfield SF8 are selective initializing subfields.
- the all-cell initialization subfield may be subfield SF2 or a subsequent subfield.
- the timing chart shown in FIG. 6 is merely an example in the embodiment of the present invention, and the present invention is not limited to these timing charts.
- the number of subfields constituting one field is not limited to the above number.
- the number of gradations that can be displayed on the panel 10 can be further increased by increasing the number of subfields to more than eight.
- the luminance weight of the subfield is set to a power of “2”, and the luminance weight of each subfield from subfield SF1 to subfield SF8 is (1, 2, 4, 8, 16, 32, The example of setting to 64, 128) has been described.
- the luminance weight set in each subfield is not limited to the above numerical values. For example, by providing redundancy to the combination of subfields that determine gradations such as (1, 2, 3, 7, 12, 31, 50, 98), it is possible to perform coding that suppresses the occurrence of moving image pseudo contours. Become.
- the number of subfields constituting one field, the luminance weight of each subfield, and the like may be appropriately set according to the characteristics of the panel 10, the specifications of the plasma display device 1, and the like.
- each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
- the drive circuit described above is merely an example, and the configuration of the drive circuit is not limited to the configuration described above.
- scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group.
- two-phase driving which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group.
- the present invention can also be applied to a driving method.
- the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other, that is, the arrangement of the electrodes provided on the front plate is “... , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,...
- the specific numerical values shown in the present embodiment for example, the slopes of the ramp waveform voltages of the ramp-up voltage L1, the ramp-down voltage L2, the erase ramp voltage L3, the ramp-down voltage L4, and the erase ramp voltage L5 are as follows:
- the screen size is 50 inches and the number of display electrode pairs 24 is set based on the characteristics of the panel 10 and is merely an example in the embodiment.
- the present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.
- the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.
- the present invention is useful as a plasma display device and a method for driving a panel even in a high-definition panel because it can perform stable writing operation by appropriately adjusting wall charges and improve image display quality. It is.
- SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Control signal generation circuit 50 Sustain pulse generation circuit 51
- Initialization waveform generation circuit 52 Scan pulse generation circuit 53, 54, 55 Miller integration circuit Q1, Q2, Q3, Q4, Q5, Q6 , QH1 to QHn, QL1 to QLn Switching element C1, C2, C3, C31 Capacitor Di31 Diode R1, R2, R3 Resistance L1 Up-ramp voltage L2, L4 Down-ramp voltage L3, L5 Erase lamp voltage
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Abstract
Description
図1は、本発明の一実施の形態におけるプラズマディスプレイ装置に用いるパネル10の構造を示す分解斜視図である。ガラス製の前面基板21上には、走査電極22と維持電極23とからなる表示電極対24が複数形成されている。そして、走査電極22と維持電極23とを覆うように誘電体層25が形成され、その誘電体層25上に保護層26が形成されている。
期間T1では、スイッチング素子QH1~スイッチング素子QHnをオフにし、スイッチング素子QL1~スイッチング素子QLnをオンにした状態を維持する。
消去ランプ電圧L3が電圧Versに到達した後は、入力端子IN3を「Lo」にする。具体的には、入力端子IN3への定電流入力を停止する。こうして、ミラー積分回路55の動作を停止する。
期間T3では、維持パルス発生回路50のクランプ回路によって基準電位Aを電圧0(V)に維持したまま、スイッチング素子QH1~スイッチング素子QHnをオンにし、スイッチング素子QL1~スイッチング素子QLnをオフにする。これにより、基準電位Aに電圧Vscを重畳した電圧を、走査電極SC1~走査電極SCnに印加する。このとき基準電位Aは電圧0(V)であるので、走査電極SC1~走査電極SCnには電圧Vscが印加される。
期間T4では、スイッチング素子QH1~スイッチング素子QHnをオンにし、スイッチング素子QL1~スイッチング素子QLnをオフにした状態を維持する。
消去ランプ電圧L5が電圧Vr2に到達した後は、入力端子IN3を「Lo」にする。具体的には、入力端子IN3への定電流入力を停止する。こうして、ミラー積分回路55の動作を停止する。
期間T6では、図示はしていないが、維持パルス発生回路50のクランプ回路により、基準電位Aは電圧0(V)に維持する。そして、スイッチング素子QH1~スイッチング素子QHnをオフにし、スイッチング素子QL1~スイッチング素子QLnをオンにする。これにより、走査電極SC1~走査電極SCnの電圧はベース電位である電圧0(V)まで低下する。
選択初期化期間である期間T7では、スイッチング素子QH1~スイッチング素子QHn、スイッチング素子QL1~スイッチング素子QLnは、期間T6と同じ状態を維持する。また、図示はしていないが、スイッチング素子Q4をオフにして、ミラー積分回路53、ミラー積分回路55および維持パルス発生回路50を基準電位Aから電気的に分離する。
10 パネル
21 前面基板
22 走査電極
23 維持電極
24 表示電極対
25,33 誘電体層
26 保護層
31 背面基板
32 データ電極
34 隔壁
35 蛍光体層
41 画像信号処理回路
42 データ電極駆動回路
43 走査電極駆動回路
44 維持電極駆動回路
45 制御信号発生回路
50 維持パルス発生回路
51 初期化波形発生回路
52 走査パルス発生回路
53,54,55 ミラー積分回路
Q1,Q2,Q3,Q4,Q5,Q6,QH1~QHn,QL1~QLn スイッチング素子
C1,C2,C3,C31 コンデンサ
Di31 ダイオード
R1,R2,R3 抵抗
L1 上りランプ電圧
L2,L4 下りランプ電圧
L3,L5 消去ランプ電圧
Claims (4)
- 複数の走査電極を有するプラズマディスプレイパネルと、
初期化期間と書込み期間と維持期間とを有するサブフィールドを1フィールド内に複数設けて階調表示するサブフィールド法による駆動電圧を発生して前記走査電極に印加する走査電極駆動回路とを備え、
前記走査電極駆動回路は、
前記維持期間の最後に、ベース電位から第1の電位まで上昇する第1の傾斜波形電圧を前記走査電極に印加し、
続いて前記走査電極の電位を前記第1の電位以下の第2の電位とし、
続いて前記第2の電位から前記第1の電位よりも高い第3の電位まで上昇する第2の傾斜波形電圧を前記走査電極に印加する
ことを特徴とするプラズマディスプレイ装置。 - 前記走査電極駆動回路は、
前記第1の傾斜波形電圧が前記第1の電位に到達した後、
前記走査電極の電位を一旦前記ベース電位とし、その後、前記走査電極の電位を前記ベース電位から前記第2の電位とし、
続いて前記第2の電位から前記第3の電位まで上昇する前記第2の傾斜波形電圧を前記走査電極に印加する
ことを特徴とする請求項1に記載のプラズマディスプレイ装置。 - 複数の走査電極を有するプラズマディスプレイパネルを、初期化期間と書込み期間と維持期間とを有するサブフィールドを1フィールド内に複数設けて階調表示するサブフィールド法により駆動するプラズマディスプレイパネルの駆動方法であって、
前記維持期間の最後に、ベース電位から第1の電位まで上昇する第1の傾斜波形電圧を前記走査電極に印加し、
続いて前記走査電極の電位を前記第1の電位以下の第2の電位とし、
続いて前記第2の電位から前記第1の電位よりも高い第3の電位まで上昇する第2の傾斜波形電圧を前記走査電極に印加する
ことを特徴とするプラズマディスプレイパネルの駆動方法。 - 前記第1の傾斜波形電圧が前記第1の電位に到達した後、
前記走査電極の電位を一旦前記ベース電位とし、その後、前記走査電極の電位を前記ベース電位から前記第2の電位とし、
続いて前記第2の電位から前記第3の電位まで上昇する前記第2の傾斜波形電圧を前記走査電極に印加する
ことを特徴とする請求項3に記載のプラズマディスプレイパネルの駆動方法。
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CN2011800373158A CN103038810A (zh) | 2010-08-02 | 2011-07-29 | 等离子显示装置以及等离子显示面板的驱动方法 |
US13/702,277 US20130222358A1 (en) | 2010-08-02 | 2011-07-29 | Plasma display apparatus and plasma display panel driving method |
KR1020137001535A KR20130030813A (ko) | 2010-08-02 | 2011-07-29 | 플라스마 디스플레이 장치 및 플라스마 디스플레이 패널의 구동 방법 |
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- 2011-07-29 US US13/702,277 patent/US20130222358A1/en not_active Abandoned
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