WO2012003790A1 - Procédé, dispositif et système de test parallèle de circuits intégrés - Google Patents

Procédé, dispositif et système de test parallèle de circuits intégrés Download PDF

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Publication number
WO2012003790A1
WO2012003790A1 PCT/CN2011/076808 CN2011076808W WO2012003790A1 WO 2012003790 A1 WO2012003790 A1 WO 2012003790A1 CN 2011076808 W CN2011076808 W CN 2011076808W WO 2012003790 A1 WO2012003790 A1 WO 2012003790A1
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Prior art keywords
test
circuit
output
input
wafer
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PCT/CN2011/076808
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English (en)
Chinese (zh)
Inventor
林正浩
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上海芯豪微电子有限公司
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Publication of WO2012003790A1 publication Critical patent/WO2012003790A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

Definitions

  • the invention belongs to the field of integrated circuits, and in particular relates to a parallel test method, device and system for an integrated circuit.
  • a typical semiconductor fabrication process is in a thin, uniform wafer of semiconductor material (wafer A plurality of identical rectangular dies are fabricated on the substrate. The grains are separated by a scribe line with a width of 60 to 80 microns. a mask is often placed on the scribe line (mask The alignment mark and the test component of the wafer acceptance test (WAT) that monitors the quality during production.
  • WAT wafer acceptance test
  • the lithography machine exposes one area at a time, called the lithography area (stepper field) Each lithographic area contains one or more dies.
  • the wafer prober uses a pin test card ( Pobe card ) contacts the pad of the die to be tested, transmits the test stimulus generated by the test program to the die to be tested, and the measured die responds to the input to generate a corresponding output, which is transmitted to the test device via the pin test card ( The tester is compared with the expected result. If the two are equal/matched, the measured die is considered to be functional. Test one die at a time.
  • Pobe card pin test card
  • a measured die passes all test procedures, its position is recorded for preparation for subsequent packaging. Tested dies that have not passed the test will be marked with ink or stored in a location called a wafer map ( Wafermap )document. When all the tests are completed, the wafer will be cut along the scribe line, the properly functional dies that are separated will be packaged, and the failed dies will be discarded. The packaged chip will be tested after packaging and the functionally correct chip will be delivered to the customer.
  • Wafermap wafer map
  • Figure 1 is a schematic diagram of a general wafer test in which a wafer to be tested (101) is placed on a wafer test device ( 102), the tester (103) transmits the test stimulus generated by the test vector generator (104) to the pin test card on the test head (106) through the input cable (105) (107)
  • the needle card (107) inputs the data into the die (108) to be tested, and reads the operation result from the die (108) to be tested, passing the test head (106) and the output cable (111). Passed to the tester (103), the tester (103) sends the result to the comparator (109) and compares it with the expected result (110) to determine whether the die (107) to be tested has failed.
  • the size of wafers has increased from 1 inch to 12 Inches, the parallelism of die production is constantly increasing, and it can accommodate nearly 10,000 grains per wafer.
  • the wafer test time is proportional to the number of die on the wafer, the test time becomes extremely long, and the test cost becomes very high.
  • the probe Probe
  • the time to move to another die after testing one die is 100ms ⁇ 250ms This time cannot be used for testing and was wasted. This further increases test time and increases test costs.
  • the cost of testing and packaging has accounted for about 25% to 30% of the total production cost. Even reached 50%.
  • test equipment to die connection delay limits the test frequency, the test can only be performed at a lower frequency.
  • Another method is to implement on-wafer chip self-testing.
  • the following three patents relate to this method, but are different from this patent.
  • Patent No. 200510008164.X The Chinese patent 'wafers that can perform aging and electrical testing and their implementation methods' propose a method for simultaneous aging and electrical testing on a wafer.
  • the method sets an aging pattern generating circuit on the wafer (aging Pattern generation circuit)
  • the circuit can generate non-functional, continuously inverted excitations into the die while performing aging and electrical testing without the need to output test results to the test equipment.
  • Patent No. 200410046002.0 The Chinese patent 'Semiconductor wafer with test circuit and manufacturing method' proposes a method for accurately measuring the chip voltage on a wafer.
  • the method sets a test circuit on the scribe line, so that the output impedance is much smaller than the impedance of the probe, and the input impedance is much larger than the output impedance of the die, so that the probe can accurately measure the reference voltage of each electrode pad of the die.
  • Patent No. 86105604 The Chinese patent 'Circuit Structure for Testing Integrated Circuit Components' proposes a test circuit structure based on circuit components on a substrate.
  • the circuit components under test are formed as an integrated circuit on a common substrate and are operable via common supply and input lines on the substrate.
  • the test circuit and the switch unit of the circuit structure are formed as an integrated circuit on the same substrate, and the switch unit can be controlled by the test circuit and inserted in the connection between the test circuit and the circuit component, and the expected value is transmitted to the substrate for use.
  • the circuit is compared for comparison.
  • the test circuit is equipped with an output circuit that transmits the test result.
  • the self-test uses the central unit of the test circuit to compare the actual and expected values to determine whether the component is qualified or not, and serially tests.
  • the invention proposes a parallel on a common substrate (parallel Test a plurality of functionally identical microelectronic circuits (microelectronic circuit)
  • An integrated circuit test method, apparatus, and system comprising a plurality of units that perform the same test excitation on a common substrate, and a plurality of units to be tested by a comparison device (device under test, DUT).
  • the output signal is compared in parallel with the expected result, or the signals of the corresponding output ends of the plurality of measured units are compared with each other by the comparing device to detect the failed unit under test.
  • the invention realizes parallel testing of thousands of units to be tested without substantially increasing the test channel.
  • the present invention provides an integrated circuit test method for testing a plurality of functionally identical microelectronic circuits in parallel on a common substrate;
  • the substrate may be a wafer or a single integrated circuit chip ( An integrated circuit chip ), which may also be a circuit board; wherein the method includes:
  • the present invention also provides an integrated circuit testing method for testing a plurality of functionally identical microelectronic circuits in parallel on a common substrate;
  • the substrate may be a wafer, a single integrated circuit chip, or a circuit board;
  • the method includes:
  • the present invention provides a wafer comprising a plurality of functionally identical dies to be tested, wherein the functional modules of the plurality of dies or the plurality of dies having the same function are the units to be tested; wherein the wafer is on the wafer Also included is an auxiliary test device fabricated by a semiconductor process; the auxiliary test device may be partially located inside the unit to be tested, or may be entirely located outside the unit to be tested, including:
  • the output circuit is connected to a plurality of register circuits, and outputs a comparison result of the corresponding comparison device and position information of the corresponding measured unit.
  • the auxiliary test device on the wafer of the present invention When the auxiliary test device on the wafer of the present invention is located inside the die to be tested, the auxiliary test device can be set to be inactive when the measured die is working normally (dis When the auxiliary test device is located outside the die to be tested, the electrical connection between the auxiliary test device and the die to be tested can be completely cut off when the wafer is cut.
  • the additional test pads required for testing on the wafer of the present invention can be placed in the die or placed on the cutting track (scribe Line ) can also be placed in the unused corner pad of the die, and can also be placed in the unused pad of the die (no connection pad) Position; during testing, the probe contacts a port pad or test pad corresponding to a single or a plurality of dies on the wafer, and the power and signal can be transmitted to the wafer through the input channel.
  • the grains in the defined area can be placed in the die or placed on the cutting track (scribe Line ) can also be placed in the unused corner pad of the die, and can also be placed in the unused pad of the die (no connection pad) Position; during testing, the probe contacts a port pad or test pad corresponding to a single or a plurality of dies on the wafer, and the power and signal can be transmitted to the wafer through the input channel.
  • the unit under test on the wafer of the present invention can wirelessly obtain power by means of electromagnetic waves.
  • the power supply circuit on the wafer of the present invention can also be connected to the power input terminals of a plurality of units to be tested.
  • the power supply circuit on the wafer of the present invention may be composed of hardwired or configurable (configurable)
  • the switch circuit is constructed or composed of a hardwired and configurable switch circuit.
  • the input path on the wafer of the present invention can be connected by a wired interconnection circuit electrically connected to the signal input end of the unit under test, or a direct transmission mode of electromagnetic waves, or a hybrid connection of electrical interconnection of wired interconnection circuits and direct transmission of electromagnetic waves. And a control signal is input to the plurality of measured units on the wafer.
  • the wired connection between the input path on the wafer and the unit under test and the comparison device of the present invention may be formed by hard wiring, or by a configurable switching line, or by a combination of hard wiring and configurable switching lines.
  • the input path on the wafer of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal.
  • the conversion includes, but is not limited to, conversion of a digital signal to an analog signal or conversion of an analog signal to a digital signal.
  • the on/off of the circuit connection in the wired interconnection circuit can be configured by an external device in a parallel or serial configuration manner.
  • the circuit connection corresponding to the input end is configured to be turned on, and the circuit connection corresponding to the output end is configured to be disconnected.
  • connection in the direction away from the position where the test excitation source is located is turned on and the connection in the opposite direction is disconnected, thereby forming each The propagation network of the same test excitation input between the units is measured so that the plurality of units under test obtain the same test excitation.
  • the wired interconnect circuit of the present invention includes a drive-connectable connection between each of the measured dies corresponding to the input. Configuring the connection between the different measured dies corresponding to the input end, according to the position of the test excitation source, turning on the drive connection away from the position where the test excitation source is located and disconnecting the opposite direction
  • the driving connection can form a propagation network of the same test excitation input between the measured crystal grains, so that each measured crystal obtains the same test excitation.
  • the comparing device on the wafer of the present invention is configured to sample the signal of the output end of each of the plurality of tested units and compare them with the corresponding expected result input from the input path, or to measure the plurality of measured
  • the signals of the output of each unit under test in the unit and the corresponding output of the unit under test are sampled and compared with each other.
  • the comparing means on the wafer of the present invention may comprise switching means coupled to the unit under test for converting the signal at the output prior to comparison.
  • the comparison device on the wafer of the present invention may further comprise a result merging compression device for temporally and spatially merging compression of the comparison result.
  • the merging compression in time that is, the comparing means may further include accumulation connected to the unit to be tested ( Accumulate circuit for accumulating and registering the output of the comparison device.
  • the spatial merge compression combines the comparison results of the adjacent plurality of outputs of the same measured unit into one result.
  • the comparing device for testing the unit under test on the wafer in parallel, for applying the same excitation to the input end of each unit under test, outputting, converting and comparing the output and the expectation of the output end of the output end Whether the results are equal / Match, or output, convert, and compare the corresponding output outputs of a plurality of measured units.
  • the output of the output terminal may be a signal value on an external output port of the unit under test, or may be a signal value inside the unit under test.
  • the output sampling point of the output terminal may be an external output port of the unit under test, or may be a sampling point inside the unit under test.
  • the sampled sample can be any form of signal including, but not limited to, a digital signal, an analog signal.
  • the conversion includes, but is not limited to, simulating a conversion of a signal such as current, voltage, impedance, etc. to a digital signal or a conversion of a digital signal to an analog signal.
  • the comparison may be a parallel comparison between the running results of the tested units and the expected results of the incoming, or may be a parallel comparison between the operating results of the tested units.
  • a single or multiple output signals of a single or a plurality of measured units can be sampled to ensure that the change of the signal at the output or the output is correct to avoid Some errors, such as a power failure, cause the unit under test to be inoperable, but the results of the operation show a valid misjudgment.
  • the singular or plural output signals may be singular bits or a plurality of bits of the digital output, or may be one or more ports of the simulated output.
  • the plurality of bits or ports may be taken from different units to be tested.
  • the sampling judgment may be performed by sampling the corresponding single or plural operation result signals and sending them to an external device for judgment, or may use the functional modules on the wafer to sample the corresponding single or plural operation result signals. Judgment.
  • the functional modules include, but are not limited to, a counter.
  • the determining method includes, but is not limited to, checking whether the number of signal changes recorded by the counter is consistent with expectations.
  • the above-mentioned sampling and judging method can be described by taking a microprocessor die as an example.
  • This embodiment is implemented on the premise of the technical solution of the present invention, but the present invention is not limited by the embodiment.
  • the corresponding counter has a storage function that can store the recorded value. The counter is initially zero. After the test vector is started, the logic value of the signal is detected every internal clock cycle of the microprocessor, and each logic is detected. 1 , the corresponding counter increments 1 . After all test vectors have been run, if the value stored in the corresponding counter is consistent with the expected value, it means that the test is valid, and the tested unit can be determined according to the corresponding test characteristics. If the value stored in the corresponding counter does not match the expected value, it means that the test is invalid or the unit under test is invalid.
  • DC characteristics of the unit under test are compared to determine whether the DC characteristic value satisfies the requirements.
  • the comparison includes, but is not limited to, a comparison with a reference DC characteristic, and a comparison between a plurality of measured unit DC characteristic values.
  • the comparison means may be a device that includes only sampling and comparison functions, or may be a device that includes sampling, conversion, and comparison functions.
  • the operation result may be sampled first, and then the samples obtained by sampling may be compared; or the running results may be continuously compared, and the continuous comparison result may be sampled as an actual comparison result.
  • the comparison device may also include a failure determination function.
  • the specific determination method is: if the output signal of the output of the unit under test is equal to the expected result / Matching, it can be determined that the unit under test is a valid unit; if the output signal of the output of the unit under test is not equal to the expected result / If there is no match, it can be determined that the unit under test is a suspected failure unit.
  • the specific determination method is: the output signal of the output of each unit under test is compared with the output signal of the corresponding output of the adjacent single or multiple units under test, if all comparisons are completely equal / If the match is made, the unit under test can be determined to be a valid unit, otherwise the unit under test can be determined to be a suspected failed unit. For the suspected failed unit, further judgment can be made according to a simple rule, which can be implemented on the wafer including the unit under test, or can be implemented outside the wafer including the unit under test. Since the number of effective units in the measured unit is far more than the number of failed units, for the suspected failed unit, the conventional test excitation can be separately performed as needed to determine whether it is a true failed unit.
  • the comparing means may be means for judging whether the two inputs are equal, that is, the comparison result is correct when the two inputs are equal, and the comparison result is an error when the two inputs are not equal; or may be used to judge the difference between the two inputs. Whether the value is within a predetermined range, that is, when the difference between the two inputs is within the predetermined interval, the comparison result is correct, and if the difference between the two inputs is not within the predetermined interval, the comparison result is an error.
  • the port of the unit under test on the wafer of the present invention is used as an input and test/output bidirectional ( Bi-directional) multiplexing, which sets the corresponding input path connected to the port to high impedance when the port is used as an output.
  • the output bidirectional multiplexer can also have an additional output corresponding to the port for testing the bidirectional multiplexed port.
  • the input and test/output bi-directional multiplexers and the additional outputs are both coupled to a comparison device.
  • the output circuit on the wafer of the present invention may be constructed of hardwired or constructed of configurable switch lines or by a combination of hardwired and configurable switch lines.
  • the output circuit for testing the unit under test on the wafer in parallel can output position information of a plurality of measured units in the wafer and the result of the corresponding comparison device to the probe, probe card or test Machine.
  • the output circuit can be configurable or fixed. When the output circuit is configurable, it includes an output path and a connection switch, and each output path is connected to a single number or a plurality of comparison devices. According to the configuration of the conduction connection switch, different output paths at both ends of the connection switch can be connected into a single number of output paths. According to the configuration, the connection switches are disconnected, and the different output paths at both ends of the connection switch are independent output paths.
  • the connection switch can be omitted.
  • the output mode of the output circuit includes, but is not limited to, a serial output, such as serial output of a single number of output paths to output corresponding output information, or parallel output, such as multi-probe parallel acquisition of corresponding output information from a plurality of output paths, or
  • the serial parallel hybrid outputs the corresponding output information. If the output circuit only contains a single number of output paths, all output information can be obtained sequentially by serial shift. If the output circuit includes a plurality of output paths, the comparison result may be sequentially obtained from the plurality of output paths in parallel by using multiple probes, or the comparison result may be sequentially obtained from the plurality of output paths by using a single number or a plurality of sets of probes in turn.
  • the output information outputted by the output circuit may be a determination result of whether each of the measured units fails, or may be a comparison result output by the comparison device corresponding to the output end of the measured unit.
  • the input channel and the output circuit for testing the unit under test on the wafer in parallel can be established at the same time by serially inputting configuration information, or can be established step by step by inputting configuration information multiple times.
  • the input channel can transmit input excitation and expected results from the unit under test where the probe is located to all of the units under test.
  • the output circuit can output test information of all the tested units or the output of the measured unit to the unit under test where the probe is located.
  • the design of the input channel and the output circuit of the present invention is higher than the design reliability of the unit under test, and has a self-detection function, which can be pre-tested once after the establishment is completed to ensure the input channel and the output circuit. The correctness of itself.
  • the probe can be moved to re-establish the input channel and output circuit from the other unit under test, and the self-test is repeated.
  • the test excitation for self-test can be transmitted to each unit under test through the input channel, and then the test excitation of the self-test is serially derived through the output circuit, thereby realizing the input channel and the output circuit. test.
  • the input channel for testing the unit under test on the wafer in parallel may be located on the wafer including the unit under test, and the specific location on the wafer includes but is not limited to the unit under test
  • the inside and the part are outside the unit to be tested on the wafer and all outside the unit to be tested on the wafer.
  • the wires used to form the input channel or output circuit can be placed in the scribe line or placed within or through the die.
  • the means and wires placed in the scribe line are automatically cut off during die cutting without affecting the function of the die itself.
  • the test pads placed in the corner pads and vacant pads also do not affect the function of the die itself.
  • the alignment marks can be moved to the corner pad locations of the die.
  • the auxiliary test device can be placed within the die, or placed in a scribe line or placed on another wafer and coexisted with a test structure for wafer acceptance testing.
  • the method of coexistence may be to bypass the wafer for acceptance testing (WAT) Test structure or share WAT test structures in certain locations, such as borrowing test pads from the WAT test structure for stimulus input.
  • WAT wafer for acceptance testing
  • capacitors can be fabricated in the scribe line to mimic the load to be driven by the measured die output, making the test more realistic.
  • Part or all of the layout of the auxiliary test device on the wafer of the present invention may be automatically laid out by computer software ( Place and route tool ) is automatically generated based on a few basic cells.
  • One solution is to perform multiple tests on a shared base integrated circuit.
  • the multiple test can first test the complete long test program of a large number of tested units at a low speed, complete the functional test, and then partition the high-speed test of the critical path short test program of a small number of tested units to test the speed of the tested unit.
  • Another solution is to use the integrated circuit test system described below.
  • the invention provides an integrated circuit parallel test system, including a wafer to be tested and a probe card (probe card) And a test machine; wherein the test wafer may include all or part of an auxiliary test device fabricated by a semiconductor process; the probe card may be composed of another substrate including some or all of the auxiliary test devices;
  • the machine has multiple power supplies ( Power supply ) and corresponding current limiter ), it can shunt all the units under test on the wafer while providing sufficient current to ensure that the unit under test can work at a given operating frequency and can cut off the corresponding power supply when any of the units under test are short-circuited.
  • the system of the present invention is capable of performing self-tests to eliminate errors in the auxiliary test device itself, including the ability to establish input paths and output circuits on the wafer, and to maintain or reconstruct inputs based on test results of the input and output circuits. Path and output circuit.
  • the auxiliary testing device of the system of the present invention comprises:
  • the output circuit is connected to a plurality of register circuits, and outputs a comparison result of the corresponding comparison device and position information of the corresponding measured unit.
  • the electrical connection between the auxiliary test device located outside the die on the wafer to be tested and the die to be tested can be completely cut off when the wafer is cut.
  • the unit under test can obtain power wirelessly by means of electromagnetic waves.
  • the power supply circuit in the system of the present invention can also be connected to the power input terminals of a plurality of units to be tested.
  • wired power supply circuit may be composed of hardwired wires, or may be composed of configurable switch lines, or a combination of hardwired and configurable switch lines.
  • the input path in the auxiliary test device in the system of the present invention can be electrically connected by a wired interconnection circuit connected to a signal input end of the unit under test, or directly transmitted by electromagnetic waves, or electrically connected by a wired interconnection circuit and directly transmitted by electromagnetic waves.
  • the data signal and the control signal are input to a plurality of units to be tested on the wafer.
  • the wired connection between the input path of the auxiliary test device and the unit under test and the comparison device in the system of the present invention may be composed of hardwired or configurable switch lines, or hardwired and configurable switch lines. Combined composition.
  • the input path in the auxiliary test device in the system of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal.
  • the comparing device in the auxiliary testing device in the system of the present invention is configured to sample the signal of the output end of each of the plurality of tested units and compare them with the corresponding expected result input from the input path, or to a plurality of The signals of the output of each of the units under test and the corresponding outputs of the other unit under test are sampled and compared with each other.
  • the comparison means in the auxiliary test apparatus of the system of the present invention may include conversion means coupled to the unit under test for converting the signal on the output prior to comparison.
  • the comparing means in the auxiliary testing device of the system of the present invention may further comprise a result merging compression means for temporally and spatially merging compression of the comparison result.
  • the port of the unit under test is used as an input and test /
  • the output is bidirectionally multiplexed, and the corresponding input path connected to the port is configured to be high impedance when the port is used as an output.
  • the output circuit in the auxiliary test device of the system of the present invention may be constructed of hardwired, or constructed of configurable switch lines, or a combination of hardwired and configurable switchwires.
  • Another substrate constituting the probe card in the system of the present invention includes, but is not limited to, a wafer or a printed circuit board; the other substrate can simultaneously supply all or part of the power of all or part of the unit under test on the tested wafer and
  • the signal input port provides power and test excitation.
  • the probe card and the tested wafer pass the bump (bulb)
  • the connection may be located on the probe card, or on the wafer to be tested, or on the probe card and the wafer to be tested.
  • the other end of the other substrate is connected to the test machine.
  • a solder ball on a wafer can be used as a probe, and other wafers or other circuit boards can be pressed onto the wafer to be tested, and some or all of the tested units on the tested wafer can be tested in parallel.
  • the comparators for testing may be located on the wafer under test or on other wafers or other boards.
  • the other wafers include, but are not limited to, the same process as the wafer to be tested and a process behind the wafer to be tested.
  • the other wafers or other boards include, but are not limited to, wafers or boards of the same size as the wafer being tested, or wafers or boards larger than the wafer being tested.
  • the other wafer or other circuit board is structurally including, but not limited to, through a through silicon via ( TSV, through silicon via) wafer or circuit board with through holes and metal wires, and wafers with integrated circuit blocks on both sides.
  • a printed circuit board with a metal wire as a probe card
  • a solder ball as a probe to transmit power and test excitation through the metal wire through the solder ball to all or part of the unit under test. Or part of the input port.
  • the probe card is electrically connected to the tested wafer, and the test excitation and/or power supply can be transmitted to the plurality of units under test by electromagnetic wave.
  • test machine features in the system of the present invention include:
  • the configuration information corresponding to the connection relationship between the device under test and the auxiliary test device on the wafer can be generated or stored, and the corresponding configuration information can be adjusted according to the coordinates of the die where the current probe is located, and the configuration information is transmitted to the wafer. ;
  • test machine features in the system of the present invention may include the ability to generate or store data signals and control signals for testing the unit under test on the corresponding wafer, i.e., test excitation, and to transmit the test stimulus to the wafer.
  • test machine features in the system of the present invention can include the ability to generate or store an expected result of a corresponding test stimulus and to transmit the expected result to the wafer.
  • the test machine feature in the system of the present invention may include the ability to classify the unit under test according to whether the comparison result satisfies the test requirement, and record and output the position information of the unit under test on the wafer or on the wafer and in the die. .
  • the present invention provides an integrated circuit chip including a plurality of functional modules to be tested, wherein the plurality of functional modules having the same function are the tested units to be tested; wherein the integrated circuit chip further includes an auxiliary testing device.
  • the auxiliary test device only when the integrated circuit chip is in test mode ( Test mode).
  • Test mode includes, but is not limited to, a plurality of units to be tested running the same input excitation in parallel; the auxiliary test device may be partially located inside the unit to be tested, or may be wholly or partially located outside the unit to be tested, including:
  • one input terminal is connected to the output of the device to be tested to be tested, the other input terminal is connected to the corresponding output terminal of the other device under test, or is connected to a corresponding input circuit for inputting the expected result;
  • the output circuit is connected to the output ends of the plurality of comparison devices, and outputs the comparison result of the corresponding comparison device and the position information of the corresponding measured unit.
  • the input circuit can electrically input the data signal and the control signal to the unit under test in the integrated circuit chip through a wired interconnection circuit connected to the signal input end of the unit under test.
  • the input circuit in the integrated circuit chip of the present invention may further comprise a conversion device connected to the device under test for converting the input signal and then inputting to the input terminal.
  • connection of the input circuit to the unit under test and the comparison device in the integrated circuit chip of the present invention may be composed of a hard-wired line, or a configurable switch line, or a combination of hard-wired and configurable switch lines.
  • test excitation source for generating the data signal and the control signal in the integrated circuit chip of the present invention may be external to the integrated circuit chip, or may be inside the integrated circuit chip, and may also be generated by externally generating test excitation and stored in the Within the integrated circuit chip.
  • the comparison device in the integrated circuit chip of the present invention may further comprise conversion means connected to the unit under test for converting the signal on the output before comparison.
  • the comparing means in the integrated circuit chip of the present invention may further comprise a result merging compression means for temporally and spatially merging compression of the comparison result.
  • the output circuit of the integrated circuit chip of the present invention may be composed of hard-wired or configurable switch lines, or a combination of hard-wired and configurable switch lines.
  • the integrated circuit chip of the present invention can output the position of the unit under test in the substrate and the result of the corresponding comparison device through the output circuit, and can also save the test result in the memory inside the integrated circuit chip.
  • the integrated circuit chip of the present invention can mark the failed function module to be tested according to the test result stored in the memory, and include the integrated circuit if the effective function module having the same function as the failed function module is redundant. Chip soft / The hardware system can replace the failed function module with a redundant effective function module to achieve self-repair.
  • the invention provides a circuit board comprising a plurality of tested units with the same function, wherein the unit to be tested is a packaged integrated circuit chip to be tested ( a packaged chip; wherein the circuit board has a plurality of chip sockets for connecting to the unit under test; and the circuit board has an interface for connecting to the test machine ( Interface ); the circuit board also has an auxiliary test device, including:
  • the circuit board of the present invention may further include at least one buffer chip. Connected to the device under test and the test machine interface through an electrical connection.
  • the circuit board of the present invention wherein the test excitation of the unit under test can be transmitted from the test machine directly to the plurality of units under test via an electrical connection on the circuit board, or buffered from the test machine via the buffer chip. Then, it is transmitted to a plurality of measured units through an electrical connection, or transmitted from the test machine to the plurality of measured units in the form of electromagnetic waves via an electromagnetic wave generator.
  • Each of the comparison chips in the circuit board of the present invention has a complex array dedicated input port, and all of the dedicated input ports of all the comparison chips are respectively connected to the output of the plurality of slots through electrical connection one by one. a port and an input/output multiplexing port; the comparison chip is capable of receiving an output signal of the test unit after the test unit is excited by an electrical connection, and receiving each output signal of each measured unit and the other measured unit The corresponding output signals are compared in parallel to generate a comparison result.
  • Each of the comparison chips in the circuit board of the present invention has a complex array dedicated input port, and all of the dedicated input ports of all the comparison chips are respectively connected to the output of the plurality of slots through electrical connection one by one. a port and an input/output multiplexing port; the comparison chip further has an electrical connection with the test machine interface for receiving an expected result; and the comparison chip is capable of receiving an output signal of the test unit after the test unit is excited by the electrical connection And comparing each received output signal of each measured unit with the corresponding expected result to generate a comparison result.
  • the comparison chip in the circuit board of the present invention may further comprise a result merging compression device for performing temporal and spatial merging compression on the comparison result to generate a test result.
  • test result of the comparison chip to the unit under test is transmitted back to the test machine through an electrical connection.
  • the circuit board of the present invention may further include only one type of chip; the chip includes functions of a comparison chip and a buffer chip.
  • the complete function of the circuit board in the circuit board of the present invention may be implemented by a plurality of electrically connected circuit boards; one of the plurality of circuit boards may implement a part of the complete function or the complete function.
  • the technical solution of the present invention can stimulate the same test through the input channel and / Or the expected results are transmitted to all of the units under test in the selected area on the substrate at a time, while existing methods, devices, and systems can only test the stimulus and / Or the expected result is transmitted to one unit under test at a time. Even if the multi-probe test machine is used, it is essentially tested in turn, and it is impossible to test all the units tested in parallel;
  • the comparison in the technical solution of the present invention may be a parallel comparison between the output signals of all the tested units and the expected results, and the existing methods, devices, and systems respectively perform the respective signals of the output of the measured unit and the expected results.
  • the comparison in the technical solution of the present invention may also be a parallel comparison between the signals of the output units of the tested units that are not known to be effective, and the existing methods, devices, and systems all have the output signals of the measured units and Knowing the reference value comparison, the known reference value includes the value stored in the test instrument or the result of the operation of the known effective unit.
  • the invention adopts a method for parallel testing of a plurality of integrated circuits under test, and can test a single or a plurality of integrated circuits to be tested in one operation, and test N with respect to a single test integrated circuit and test one by one.
  • the die requires N*(M+L) test time.
  • the test method of the present invention only needs M+L+N*R test time (where M is the time of moving the card or moving the package after the package is tested, L To perform the test stimulus time, R is the time to output the test feature, R is much smaller than M+L Therefore, the present invention can reduce the test time of the integrated circuit by an order of magnitude, reduce the test cost, and shorten the mass production time of the product formation; the invention can appropriately increase the length of the test excitation and improve the test coverage because the input excitation operation time is greatly reduced. Rate, effectively reducing the leak rate.
  • the invention has no additional requirements on the number of test bench channels , to help reduce the cost of testing; for wafer testing, when the comparison device is integrated on the wafer, the delay of transmission of high-frequency signals through the cable can be avoided, so that higher frequency testing can be performed, or low-end testing can be used.
  • the station conducts high-end testing.
  • Figure 1 is a schematic diagram of a general wafer test (prior art).
  • FIG. 2 is a flow chart of testing the shared base integrated circuit test apparatus of the present invention with expected results.
  • 3 is a flow chart of testing of the shared base integrated circuit test apparatus of the present invention without expected results.
  • Figure 4 is a schematic diagram of the structure of the grain output compared to the expected results.
  • Figure 5 is a schematic diagram showing the structure in which the crystal outputs are compared with each other.
  • Figure 6 is a schematic diagram of the comparator within and outside the die.
  • Figure 7 is a schematic diagram of the determination of die failure during the test.
  • Fig. 8 is an embodiment of the positional relationship of adjacent units to be tested in the present invention.
  • Figure 9 is a schematic diagram of the comparison of the operation results to analog signals.
  • Figure 10 is an embodiment of the present invention for a power supply mode.
  • Figure 11 is a diagram showing possible positional distributions of an embodiment of the present invention for alignment mark locations on a wafer.
  • Figure 12 is a diagram showing the structure of the input channel and the structure of the output circuit in the lithography area on the wafer.
  • Figure 13 is an embodiment of the present invention for a circuit connection configuration when the dies are compared with each other.
  • Figure 14 is an embodiment of the present invention for a configuration method.
  • Figure 15 is a schematic diagram of a wafer test input path and test feature export path.
  • Figure 16 is a schematic diagram of a wafer with a large power interface.
  • Figure 17 is a schematic diagram of wafer testing of RF dies.
  • Figure 18 is a schematic diagram of a self-test wafer.
  • Figure 19 is a diagram of a new wafer test system.
  • Figure 20 is a diagram showing the internal test structure of a multi-operation unit/multi-core integrated circuit chip.
  • Figure 21 is a schematic diagram of the wiring pattern of the die output to the comparator.
  • Figure 22 is a four embodiment of wafer testing on a wafer under test using other wafers.
  • Figure 23 is an example of DC testing of the measured die.
  • Figure 24 is a complementary metal oxide semiconductor (complementary Metal-oxide-semiconductor, CMOS) Example of image sensor testing.
  • CMOS complementary Metal-oxide-semiconductor
  • Figure 25 It is an embodiment of a wafer test machine that provides sufficient power for a specified number of units under test at rated voltage.
  • Figure 26 is a diagram showing a test result table for storing test results when testing functional modules in an integrated circuit chip using the present invention.
  • Figure 27 is a test circuit diagram compared to the expected results.
  • Figure 28 is a cross-sectional view of a wafer test using a circuit board.
  • Figure 29 is an embodiment of a packaged integrated circuit test device.
  • Figures 30A-B and 31A-B are four embodiments of the present invention.
  • the technical idea of the present invention is a plurality of integrated circuits under test/die with the same structure and function /
  • the functional chips perform the same input excitation, each generating a running result, and the running results are compared with each other in parallel or in parallel with the expected result to detect the failed integrated circuit/die/function chip.
  • FIG. 2 It is a flow chart of testing the shared base integrated circuit test device of the present invention with expected results.
  • the comparison device in this embodiment does not include a failure determination function.
  • step one (202 )
  • step 2 (203)
  • step three (205)
  • the sampling results of each unit under test are sampled and compared with the expected results, and the comparison result is recorded.
  • the number of comparisons of the samples depends on the requirements of the test accuracy.
  • step four ( 206), as a result of the determination, the position information of the unit under test and the corresponding determination result are generated.
  • step 5 (207) to output the position information of the unit under test and the corresponding determination result.
  • the comparison device in this embodiment includes a failure determination function. First go to step one (302 ), input the excitation, and then go to step 2 (303) to run each unit under test in parallel. Then go to step three (304 The sampling results of each unit under test are sampled, and the sampling results of the running results between the units to be tested are compared, and the comparison features are recorded. The number of times this sample is compared depends on the accuracy of the test. After the sampling comparison of the running results of all test incentives is completed, proceed to step four ( 306), generating a determination result of the unit under test.
  • step five outputting the position information of the unit under test and the corresponding determination result.
  • the test feature is a suspected failure unit or a failure unit determination result.
  • the result of the determination may be failure unit coordinate information or other information that can locate the failed unit.
  • the suspected failed unit can be retested as needed, or the suspected failed unit can be simply considered to be truly invalid according to the requirements.
  • a failed unit can be physically marked.
  • FIG 4 is a schematic diagram of the structure of the grain output compared to the expected results.
  • Bidirectional switch ( 403 ), bidirectional switch ( 404 ), the bidirectional switch ( 443 ), the bidirectional switch ( 444 ) is configured to transmit to the right, and the wired interconnect circuit ( 402 ) passes the left incoming excitation ( 401 ) through the input pad ( 406 )
  • the input pad (407) and the input pad (408) are respectively introduced into the die (409), the die (410), and the die (411).
  • the lower running results are respectively transmitted to the comparator (414) and the comparator (415) through the respective output pads (425), output pads (426), and output pads (427). ), comparator (416).
  • the comparison/decision results of the comparator (414), the comparator (415), and the comparator (416) are stored in the feature register (417) and the feature register, respectively. 418), in the feature register (419).
  • the initial value of all feature registers is set by the external control signal or by self-excitation.
  • Feature register (417 ), the feature register ( 418 ), the feature register ( 419 ) and other feature registers can be connected into a shift register chain ( 420 ) for outputting the position information of the measured die and corresponding comparison / judgement result.
  • the excitation ( 401 ) can be directly connected to the internal module by the input pad ( 406 ), the input pad ( 407 ), and the input pad ( 408 ), comparing / The determination result may be directly outputted by a metal wire without using the output pad (425), the output pad (426), and the output pad (427).
  • the comparator can have a single or multiple inputs.
  • FIG. 5 is a schematic diagram showing the structure in which the crystal outputs are compared with each other.
  • Bidirectional switch ( 503 ), bidirectional switch ( 504 Configuring to transmit to the right, the wired interconnect circuit (502) passes the left incoming stimulus (501) through the input pad (505), the input pad (506), and the input pad (507).
  • the result of the underside of the die (509) is transferred to the comparator via the output pad (512) (514)
  • the comparator (515), the result of the operation under the die (508) is passed through the output pad (511) to the comparator (514) for comparison with the output of the die (509).
  • Grain (510 The lower run result is compared to the output of the die (509) via the output pad (513) to the comparator (515). Comparison of comparator ( 514 ), comparator ( 515 ) / The determination results are stored in the feature register (516) and the feature register (517), respectively. The initial value of all feature registers is set by the external control signal or by self-excitation. When the comparator input is not equal / When there is no match, the internal value of the feature register changes and only changes once, that is, if the output of the adjacent die is not equal/mismatched once, the relevant die is marked as a suspected failed die.
  • Feature register 516
  • the feature register (517) and other feature registers may be coupled into a shift register chain (518) for outputting position information of the measured die and corresponding comparison/decision result test feature values.
  • Incentive 501
  • the input pad ( 505 ), input pad ( 506 ), and input pad ( 507 ) can be directly connected to the internal module by metal wires.
  • the comparison / determination result can also pass through the output pad ( 511 ) ), the output pad (512), and the output pad (513) are directly outputted by metal wires.
  • the comparator can have a single or multiple inputs.
  • Figure 6 (a) is a schematic diagram of the comparator as it is inside the die.
  • Transmission network (601
  • the expected result or the running result of the adjacent die is input into the current die through the pad (603) of the input/output port (I/O pin) (602), and the corresponding operation result of the current die (604) )
  • the output driver (606) in the input/output port (602) is set to high impedance, and the input driver (608) is turned on.
  • Figure 6 (b) is a schematic diagram of the comparator when it is outside the die.
  • the current die operation result (611) is passed through the output driver ( 612) comparing the output of the pad (613) to the comparator (614) with the expected result from the pad (616) or the running result of the adjacent die (615).
  • Figure 7 It is a schematic diagram for determining the failure of the die during the test.
  • the operation results on the four sides of each measured die are compared with the running results on the corresponding sides of the adjacent measured die by a comparison device, wherein the comparison result is equal /
  • the matching comparison device icon is white and the comparison result is not equal /
  • the mismatched comparison device icon is black.
  • all means for determining whether the die has failed may be on the wafer or on an off-wafer test machine.
  • Figure 7 (a ) is a schematic diagram of the test case when there is no failure crystal, wherein the operation results of the measured crystal grains ( 701 ) on the four sides pass through the connection line ( 707 ) and the measured crystal grain ( 702 ), and the measured crystal grain ( 703 ) ), the measured die (704), the measured result of the corresponding side of the measured die (705) are compared, and the comparator (706) is shown in white to indicate the measured die (701) and the measured die (704)
  • the comparison of the corresponding sides is equal/matched, and the comparisons on the four sides of the figure are completely equal/matched, so that the measured grain (701) can be determined to be a normal grain.
  • Figure 7 (b) is a schematic diagram of the test situation when the measured die partially fails, the measured die (711 ) on the four sides, respectively, compared with the operation results of the measured die ( 712 ), the measured die ( 713 ), the measured die ( 714 ), and the measured die ( 715 ), where the comparator ( 716 And the comparator (717) is shown in black, which means that the measured die (711) is not equal/mismatched with the measured die (712) and the measured die (714), and the connection (718) ), connect (719) to its corresponding connection.
  • the measured grain (711) is equal to the measured grain (713) and the measured grain (715) on the corresponding side. Matching, so it can be determined that the measured die (711) is partially failed.
  • Figure 7 (c) is a schematic diagram of the test case when the measured die is completely failed, the measured die (721) and the measured die ( 722), the measured die (723), the measured die (724), the measured die (725) on the four sides of the corresponding operation results are all unequal / mismatch, as shown in the comparator ( 726), comparator (727), comparator (728), comparator (729), comparator (730), comparator (731), comparator (732), comparator ( 733) is all black, and the connection (734) is the connection between the unit under test (721) and the comparator (726). Therefore, the measured crystal grain can be determined (721 ) is a failure grain.
  • the comparison result of each port can be compared by the logic circuit, and only one comparison result is output, and the comparison result is spatially compressed; the comparison result can be accumulated by the accumulation circuit to realize the compression of the comparison result in time. After compression, the bandwidth requirements of the output circuit can be reduced and the test process can be accelerated.
  • FIG. 8 is an embodiment of the positional relationship of adjacent units to be tested in the present invention.
  • Figure 8 (a) is a schematic diagram of the normal placement position, the unit under test ( 801 ), the unit under test ( 802 ), the unit under test ( 803 ), and the unit under test ( 804)
  • each output port of the unit under test is compared with an output port on the corresponding side of the adjacent unit under test by a connection, such as an output port of the unit under test (801) and a unit under test (802).
  • Corresponding output ports are compared.
  • the connection line (813) in the figure is a connection between the corresponding output port of the unit under test (802) and the unit under test (804).
  • Figure 8 ( b
  • the placement position of each unit to be tested is in a rotating relationship with the placement position of the adjacent unit to be tested, such as the placement position of the unit under test (806) and the unit under test (805) and the unit under test.
  • the placement position of 808 is 180 degree rotation
  • the position of the unit under test (808) is 180 degrees with the position of the unit under test (806) and the unit under test (807). Degree rotation relationship.
  • the connection (814) is the unit under test (806)
  • Figure 8 (c As a schematic diagram of the position of the mirror, the position of each unit to be tested is mirrored with the position of the adjacent unit to be tested, such as the position of the unit under test (809) and the unit under test (810) and the unit under test.
  • the placement position of 811) is mirror image, and the position of the unit under test (811) is respectively placed with the unit under test (809) and the unit under test (812).
  • the placement position is mirrored.
  • the output port of the unit under test is closer to the corresponding output port position of the adjacent unit under test, and it is more convenient to connect the lines.
  • the connection (815) is the unit under test (810)
  • This embodiment is more suitable for testing non-directional chips such as RFID.
  • Figure 9 is a schematic diagram of the comparison of the operation results to analog signals.
  • Grain (901 The result of the operation is an analog signal, the analog signal converter (902) is used to convert the sampling of the signal, and the converted result is sent to the digital comparator (903) to generate whether the two crystal grains are equal / Match the comparison/judgment result and store the comparison/decision result in the feature register (904).
  • Grain (901 The input can be a direct analog signal input, or a digital signal can be input after digital analog conversion.
  • FIG 10 is an embodiment of the present invention for a power supply mode.
  • Power pad for all die (1001) in the wafer (1002) ) All can be connected to the global power network (1003), or the partition power supplies are connected together to form multiple local power networks.
  • the ground pad (1004) can also be fully connected to the ground grid (1005) Or a partition connection to form multiple local ground networks.
  • the ground pads in the global or partition can all be connected together, and each power pad is connected to a global or partitioned power network via a large PMOS device.
  • the gate of the PMOS device is connected to a configurable network that controls the on and off of each die supply.
  • the pads are constructed of metal, placed on the outside of the die or on the die, and may be joined to the structure of the present invention by metal wires.
  • Figure 11 (a) is an embodiment of the present invention for alignment mark positions. 60 microns -80 between each die on the wafer
  • the micron dicing track (1101), the alignment mark (1102) is used for the alignment of each reticle, typically within the scribe line (1101), and occupies all of the layout layers. Since the present invention requires a cutting path ( 1101) The long connection is designed.
  • the alignment mark can be moved to the corner pad (1104) of the die.
  • Input channel, comparison device and output circuit can be used with WAT for wafer acceptance testing
  • the test structures coexist.
  • the coexistence method can be to bypass the WAT test structure or share the WAT test structure at certain locations, such as borrowing a needle pad from the WAT test structure for the input of the stimulus.
  • Figure 11 ( b ) is a possible location map of the needle pad on the wafer.
  • a test pad for the test network for incoming clocks, configuration information, and the like.
  • a position (1112), B position (1113); can also be placed on the die (1111)
  • the corner pad such as the C position (1114).
  • the needle test pad in the cutting path (1101), such as the D position (1117), E position (1118).
  • Figure 11 (c ) is a possible location map of the pad when using flip chip or wafer level chip packages.
  • the probe card can use a vacant pad on the die (1212) (1122) ) to use as a needle pad.
  • FIG. 12 is a structural diagram of an input channel and an output circuit structure of a lithography area on a wafer.
  • Figure 12 ( a) is the input channel structure diagram inside the lithography area on the wafer
  • Figure 12 (b) is the structure diagram of the measured crystal output circuit in the lithography area on the wafer.
  • the test stimulus is passed through the pin test card (1201) and through the wire on the scribe line on the wafer (such as a wire ( 1202)) respectively transferred to the measured die in the lithography area (1206) (such as the measured die (1203) )), where the connection on the scribe line has been determined at the layout stage and cannot be changed throughout the test phase.
  • the wire on the scribe line on the wafer such as a wire ( 1202)
  • the measured die in the lithography area (1206) such as the measured die (1203)
  • FIG. 13 is an embodiment of the present invention for a circuit connection configuration when the crystal grains are compared with each other
  • FIG. 13 (a) It is a top view of this embodiment
  • Figure 13 (b) shows the connection details among the three crystal grains.
  • the probe of the pin test card ( 1316 ) falls on a die ( 1311
  • the incoming input stimulus can be transmitted to the corresponding input pads of the die (1310), die (1312) through the wired interconnect circuit (1302).
  • Wired interconnection circuit (1302 ) consists of a number of basic transmission units ( 1303 ).
  • Basic transmission unit (1303) through bidirectional switch (1304) The guaranteed signal can be transmitted from the left (right) to the right (left), or from the upper (lower) to the lower (top), and the bidirectional switch is configured by the configuration network, so that the pin test card (1316)
  • the input excitation at any of the dies can be transmitted to all dies.
  • the bidirectional switch (1304) is unidirectional, and when the output is compared, the bidirectional switch (1304) is turned off.
  • Bidirectional switch 1304) When it is a single-conduction, its conduction direction can be determined by the configuration memory (1308), or it can be controlled by the unit under test/output control pad (1309) and configuration memory (1308). )decided together.
  • the driver (1305) of the basic transmission unit (1303) does not cause attenuation of signal transmission. If the attenuation is not large, the wired interconnect circuit can also have no driver ( 1305). If necessary, a latch can be added to the wired interconnect circuit to transmit the signal in a pipelined manner.
  • the bidirectional switch (1304) is configured to be disconnected, the pad (1301) The output of the die is transmitted as an output pad, at which point the comparator (1306) operates.
  • the pad (1301) is input / The output pad, the separate input pad or the output pad connection method is a subset of this embodiment.
  • Figure 14 It is an embodiment of the present invention directed to a configuration method.
  • the wired interconnect circuit and the output circuit have different topologies.
  • the input excitation requires transmission from the probe drop point to the four sides in the shortest path, and the output circuit is serially passed through each unit to be tested. At each node, the wired interconnect circuit and the output circuit do not necessarily have the same direction of transmission.
  • the purpose of this embodiment is to establish a comparison of all the units to be tested simultaneously by serial configuration. /
  • the determination result is serially outputted to the unit under test where the probe is located, and the wired interconnection circuit that configures the input excitation from the unit under test to which the probe is located.
  • the method adopted is to establish a chain passing through each unit to be tested from the position of the probe in a point-by-point configuration by point-by-point transmission.
  • the reverse of this chain is a true comparison.
  • Judging the direction of the result transmission, while establishing this chain the transmission direction of the wired interconnection circuit is also configured.
  • the configuration information of each node transmitted through the chain includes: wired interconnect circuit structure configuration information and output circuit structure configuration information.
  • the specific approach is to take the probe position ( 1401)
  • the configuration information and clock (1427) are serially transmitted to all nodes through the network (1402), as shown in Figure 14 (a).
  • nodes For nodes ( 1408 For example, the clock signal and node configuration information (1427) are transmitted from above, and the configuration memory of the transmission direction of the excitation signal on the node (1408) is configured (1308). And a derivation direction configuration register (1407) that controls the output direction of the output circuit.
  • the Export Direction Configuration Register ( 1407 ) indicates a comparison to the right / The decision result output circuit (including forward clock transfer, forward configuration information transfer, and reverse comparison / decision result transfer channel).
  • the configuration memory ( 1308 ) indicates that the input stimulus is passed down ( 1414 ) ).
  • the clock signal and node configuration information arrives at the node (1403) from the left node (1408), and the node is configured (1403).
  • the configuration memory (1308) of the transmission direction of the excitation signal and the control comparison/decision result derivation direction configuration register (1407) The configuration memory (1308) of the transmission direction of the excitation signal and the control comparison/decision result derivation direction configuration register (1407).
  • Export Direction Configuration Register ( 1407 ) Instructs to continue to build a comparison/decision result output circuit to the right (including forward clock transfer, forward configuration information transfer, and reverse comparison / decision result transfer channel).
  • Configuring memory ( 1308 ) indicates that the input stimulus is passed down (1404).
  • the clock signal and node configuration information arrives at the node (1406) from the left node (1403), and the node is configured ( 1406)
  • the configuration memory (1308) of the transmission direction of the excitation signal and the control comparison/decision result derivation direction configuration register (1407) The configuration memory (1308) of the transmission direction of the excitation signal and the control comparison/decision result derivation direction configuration register (1407).
  • Export Direction Configuration Register ( 1407 ) Instructs to continue to build a comparison/decision result output circuit to the right (including forward clock transfer, forward configuration information transfer, and reverse comparison / decision result transfer channel).
  • Configuring memory ( 1308 ) indicates that the input stimulus is passed down (1488). After each node is configured, configure memory (1308) and export direction configuration register (1407) ) does not change due to subsequent configuration information passing through the node. However, when the power is turned off and the reset signal is externally supplied, all are set to the initial values.
  • node configuration information and clock transmission path ( 1427 ) So through the node configuration information and clock transmission path ( 1427 ), node configuration information and clock transmission path ( 1415 ), node configuration information and clock transmission path ( 1405 ), node configuration information, and clock transmission path ( 1420 ) ) Pass all node configuration information and clocks in turn, and transfer them to the required link nodes as needed.
  • By comparing/determining the result transmission path (1429), comparing/determining the result transmission path (1430), comparing / The decision result transmission path (1431) establishes a reverse comparison/decision result output circuit, and outputs all the comparison features, and the transmission direction configuration of the input excitation is also completed while the output circuit is established.
  • Figure 14 (b) is a connection diagram of a node (1408), a node (1403), and a node (1406).
  • Figure 15 (a) is a schematic diagram of a wafer test input channel, which is a top view; pin test card (1501) The excitation is transmitted to each die (1504) through the input channel (1503) on the wafer to be tested (1502), where the input channel (1503) ) can be configured to select the excitation transmission path.
  • the needle card (1501 The test excitation can be transmitted without moving, saving test time; it can also be configured to select partial region transmission stimulus for sub-regional testing.
  • Figure 15 (b) is a schematic diagram of a wafer comparison/decision result output circuit, which is also a top view; the wafer to be tested ( 1502) There is a comparison/decision result output circuit (1505) that connects all the die to be tested (1504) Characteristic register; all the characteristic registers form a shift register, and the comparison/decision result can be read by serial shifting of the shift register, and all comparisons can be read without moving the pin test card (1501). / judgement result. It is also possible to configure only the comparison/judgment results of partial areas. Comparison / decision result output circuit (1505 The pre-test can be done once after the establishment is completed to ensure the correctness of the input channel and the comparison/decision output circuit itself.
  • the input can be passed from the pin test card (1501) to the node (1506). ), after passing through the comparison/decision result output circuit, it is read from the node (1507) through the pin test card (1501), and the two are compared with each other, equal / A match means that the pretest is passed, otherwise, the pretest is not passed. If the pretest is not passed, you can move the card (1501) to re-establish the input channel and compare from another unit under test / The result output circuit is determined and the self-test is repeated. In the self-test mode, the self-test excitation is transmitted to each unit under test through the input channel, and then by comparison / The determination result output circuit serially derives the excitation for self-test described above.
  • Figure 15 (a) and Figure 15 (b) use the input channels and comparisons established in Figure 14 / The result output circuit is determined.
  • Figure 16 is a schematic diagram of a wafer with a large power interface; in addition to having a common die on a wafer (1601) ( 1602), there are also several large power interfaces (1603), which are available (1603) ) A hard-wired connection to the power supply of the surrounding die. Since it can pass through a large power source, it can simultaneously supply multiple dies in one area and allow the dies to be tested at higher frequencies. This requires a dedicated probe that can be used with a large power supply.
  • Figure 17 is a schematic diagram of wafer testing of RF dies.
  • the pin test card (1703) An antenna input pad for each die (eg, die (1702)) on the wafer (1701) has a corresponding receive antenna or coupler (eg, receive antenna and coupler (1704) )), by means of electromagnetic wave transmission through the antenna to the corresponding measured RF die (such as the measured RF die (1702)) input test excitation and power supply, each measured RF die (such as the measured RF die (1702) )) Run the test stimulus and transfer the results to the corresponding comparator through the connection on the wafer (1701) through each measured die (eg, the measured RF die (1702) ) Comparison of the results of the operation or comparison with the expected results to obtain a comparison / determination result, comparison / determination results through the needle test card (1703) The output probe on the ) is transmitted to the signature device to enable wafer testing of the RF die. Test excitation and power supply can be transmitted
  • Figure 18 is a schematic diagram of the self-test wafer.
  • the test excitation generator (1801) is integrated on the wafer (1803).
  • the test excitation generated by the connection is transmitted to each measured die (such as the measured die (1802)) through the connection, and the output port of each measured die (such as the measured die (1802)) also passes.
  • a complete test environment has been formed on the entire wafer (1803), and in the case of power-on, the entire wafer (1803) All wafers can be tested independently without the involvement of an external test machine, and the comparison/decision results are output to the signature device via the output probe on the card.
  • the test excitation generating device ( 1801 ) can also be integrated into the scribe line ( 1804 ) on the wafer ( 1803 ) without occupying the die position.
  • Figure 19 is a diagram of a new wafer test system; the structure includes a tester (1901), a dedicated test device ( 1902), the two are connected by a cable (1903) to test the wafer under test (1905) on the wafer testing machine (1904).
  • This special test device ( 1902 A large power supply can be provided.
  • the probe (1906) on the dedicated test device (1902) can be in contact with the power/ground of all the dies on the tested wafer (1905) to realize the wafer to be tested (1905). Power is supplied to the full wafer or part of the wafer area.
  • the excitation generated by the tester (1901) can be transmitted to the plurality of units to be tested in parallel through a dedicated test device (1902) to drive the wafer to be tested (1905) ) All or part of the measured die, each die simultaneously runs the input excitation at high speed; the comparison / determination result will be exported to the tester ( 1901 ) through the dedicated test device ( 1902 ) and the cable ( 1903 ) In the test, if the test result is a comparison result, the tester (1901) The suspected failed unit will be determined based on the comparison result of the output. The system can also test the suspected failure unit separately according to the operation result, and has the function of marking the failure unit.
  • Figure 20 is a diagram showing the internal test structure of a multi-operation unit/multi-core integrated circuit chip, as shown in the figure, in the multi-operation unit / Inside the multi-core integrated circuit chip (2011), the test excitation generator (2001) generates test excitations and transmits them to each unit under test (such as the unit under test (2002), the unit under test (2004). ), the unit under test (2007), the unit under test (2009), where the unit under test is an arithmetic unit or processor core inside the multi-operation unit/multi-core integrated circuit chip.
  • each unit under test (such as the unit under test ( 2002), the unit under test (2004), the unit under test (2007), the unit under test (2009) run the test stimulus, and the operation result is transmitted to the corresponding comparator (such as the comparator (2003). ), comparator (2005), comparator (2006), comparator (2008) are compared with each other to obtain comparison/judgment results, and the test results are written into the feature register (2010) ), thus enabling the implementation of multiple arithmetic unit/multicore in the chip.
  • each unit to be tested (such as the unit under test (2002), the unit under test (2004), the unit under test (2007)
  • the test results of the unit under test (2009) are tested by mutual comparison.
  • the test results of the unit under test can also be compared with the expected results.
  • Figure 21 is a schematic diagram of the wiring pattern of the die output to the comparator.
  • Comparator ( 2103 ), comparator ( 2104 ) The output pad (2110) of the die (2101), the die (2102), and the output pad (in the cutting area (2107), the cutting area (2109)) 2108)
  • the connection between the comparator (2103) and the comparator (2104) must pass through the cutting path to determine the cut-off area (2105) ), to ensure that the comparator can only work when the chip is tested. After the chip is cut, the connection between the output pad and the comparator of the die is completely cut off, and the comparator does not load the output pad.
  • Figure 22 is a four embodiment of wafer testing on a wafer under test using other wafers.
  • Figure 22 (a The mid-test wafer (2201) is overlaid on the wafer (2202) as part of the test system for testing.
  • the test wafer (2201) is divided into the wafer to be tested (2202).
  • the position on the test wafer (2201) corresponding to the die of the wafer under test (2202) (2204) is used to place the solder ball (2205)
  • the vacant position (2203) on the corner of the test wafer (2201) is used to connect the test cable (2206).
  • Figure 22 (c Is a cross-sectional view of the embodiment, the solder balls (2205) on the test wafer (2201) correspond one-to-one with the pads on the wafer under test (2202), and the flattening device (2210) is pressed against the test wafer ( 2201), so that the pads of the two wafers and the solder balls are in tight contact.
  • the test cable (2206) can pass through the fixture (2208) by using a gap between the two wafers formed by the pad and the ball phase. ) Connect directly to the vacant position ( 2203 ) on the corner of the test wafer ( 2201 ).
  • the results of the test stimulus can be compared on the wafer under test or transmitted back to the test wafer and compared using a comparator on the test wafer.
  • Test wafer (2211) is better than the wafer under test (2202)
  • Test cable (2206) can be directly connected to the test wafer (2211) through the fixture (2208) to extend the portion of the wafer under test (2202), which can solve Figure 22.
  • the test cable (2206) should not be too thick.
  • the test power/test excitation is transmitted to the test wafer (2211) through the test cable during the test, and the test wafer is passed ( 2211)
  • the solder ball (2212) is transferred to the wafer under test (2202) Corresponding pads for each die on the substrate as an input to the test.
  • the results of the test stimulus can be compared on the wafer under test or transmitted back to the test wafer and compared using a comparator on the test wafer.
  • Figure 22 (e) is a third embodiment.
  • the wafer to be tested (2215) and the test wafer (2211) The original size is the same, but the wafer under test (2215) is cut off, the test wafer (2211) is a complete wafer, and the test power/test excitation is transmitted to the test wafer via the test cable (2211) ), through the solder ball (2212) on the test wafer (2211) transferred to the wafer under test (2215) Corresponding pads for each die on the substrate as an input to the test.
  • the results of the test stimulus can be compared on the wafer under test or transmitted back to the test wafer and compared using a comparator on the test wafer.
  • the wafer to be tested in this embodiment ( 2215) It is only cut off one side, but in practical applications, the multilateral can be cut according to different needs.
  • Figure 22 (f) is a fourth embodiment, the test wafer (2214) is with through silicon vias (TSV) Wafer.
  • TSV through silicon vias
  • the test cable (2216) does not need to be directly connected to the front side of the test wafer (2214), but is connected to the back side of the test wafer (2214) through the TSV.
  • the via transmits the test power/test stimulus to the wafer under test (2202).
  • the flattening device and the fixing member are omitted.
  • solder pads on the test wafer can be used to contact the solder balls on the wafer under test, and the tin on the wafer can be tested.
  • the ball contacts various soldering methods such as solder balls on the wafer to be tested.
  • Figure 23 is an example of DC testing of the measured die.
  • a pad of the die (2301) is tested /
  • a current source (2303) is connected to the solder ball (2302).
  • the current source (2303) is applied to the measured die through the pad/tin ball (2302) (2301).
  • a certain amount of power supply at this time the pad / solder ball ( 2302 ) generates a potential difference corresponding to the ground ( GND ), and the solder pad / solder ball can be known through an analog to digital conversion device ( 2304 ) ( 2302 ) )
  • the voltage value By comparing this voltage value with the reference DC characteristic voltage value, it can be determined whether the DC characteristic value satisfies the requirement.
  • Figure 24 is an embodiment of a test for a complementary metal oxide semiconductor (CMOS) image sensor.
  • the wafer ( The die on 2401) is a CMOS image sensor.
  • a light-emitting device (2404) can be applied to the wafer (2401) to some or all of the CMOS
  • the image sensor emits light of different brightness and chromaticity.
  • the probe (2405) of the dedicated pin test card (2403) does not block the light emitted by the light-emitting device (2404) and is associated with one of the wafers (2401) Corresponding pad contacts for CMOS image sensors.
  • Figure 25 It is an embodiment of a wafer test machine that provides sufficient power for a specified number of units under test at rated voltage.
  • Power supply unit (2501 ) Provides a power supply for testing all of the tested dies at the same time.
  • the test driver (2502) in the test excitation and power supply (2501) provides power from the test interface (2503) via the probe ( 2505) Parallel transmission to all of the measured dies in the wafer under test ( 2504 ) to achieve simultaneous testing of all measured dies.
  • the test interface (2503 ) can be implemented in wafers or on boards.
  • Figure 26 It is a schematic diagram of a test result table for storing a determination result when the functional module in the integrated circuit chip is tested by the present invention.
  • the judgment result is saved in the test result table (2601), each label (2602) Corresponding to a unit under test in the system, the information at the position indicates the state of the unit under test, where '?' indicates that the corresponding unit under test is not tested, and 'X' indicates that the corresponding unit under test is invalid, '0' Indicates that the corresponding measured unit is normal.
  • the test result table can be in the integrated circuit chip or outside the integrated circuit chip.
  • the storage medium may be volatile or non-volatile; it may be one-time writes that are not changed, or may be erasable and write-once.
  • the failed function module When the effective function module with the same function as the failed function module has redundancy, the failed function module is bypassed, and the redundant function module is replaced by the redundant effective function module to ensure that the system can operate normally, improve the yield, and realize the system. Self-healing feature.
  • Figure 27 is a test circuit diagram compared to the expected results. Test pads ( 2703 ) or pads that fall into the scribe line ( 2704), the input signal is the expected operation result of the die (2701) and the die (2702). The expected result is passed to the comparator via the transfer path ( 2705 ) ( 2708 ) And the comparator (2709), compared with the output of the die (2701) (2713), the output of the die (2702) (2714), compare / The result of the judgment is stored in the register (2711) and the register (2712).
  • Figure 28 is a cross-sectional view of a wafer test using a circuit board.
  • the board ( 2801 ) is passed through the fixture ( 2803 ) is fixed above the wafer under test ( 2805 ).
  • the circuit board ( 2801 ) can also have a trace channel ( 2807) Connected solder balls (2804) whose position corresponds to the position of all pads of the wafer under test (2805), and the flattening device (2811) is pressed on the circuit board (2801) ), so that the solder ball ( 2804 ) is in tight contact with the solder pad.
  • test excitation can be routed through the circuit board (2801) trace channel (2807) and solder balls ( 2804) is passed to the wafer under test (2805), so that all power supplies and test excitations of all the dies on the tested wafer (2805) pass through the solder balls on the circuit board (2801) (2804) ) incoming.
  • the test equipment passes the test cable (2813) and the circuit board (2801) on the trace channel (2807) and the solder ball (2804) from the wafer under test (2805). Receive test results on).
  • the position of the solder ball (2804) on the circuit board (2801) can also be compared with the wafer to be tested (2805).
  • the pad portion on the corresponding portion corresponds to the solder ball (2804) on the input circuit board (2801) of the die, and some of the input passes through the wafer under test (2805)
  • the input channel on the substrate is passed from the pads of other dies.
  • the soldering pad (2804) may not be included on the board (2801), but has a pad connected to the trace channel (2807).
  • the wafer to be tested ( The test pads on 2805) need to be connected to the corresponding solder balls, the pad position on the board (2801) and the wafer to be tested (2805).
  • the position of the solder ball on the whole corresponds to all or part of it.
  • the test device in this embodiment is not shown.
  • Figure 29 (a) shows an embodiment of a packaged integrated circuit test device.
  • On the test board ( 2901 ) There are a plurality of units to be tested (2902), a buffer comparison chip (2903), and an input/output interface (2904) for communicating with the test machine.
  • Unit under test ( 2902 ) is located in the slot of the circuit board, and its input end is connected to the buffer output end of the buffer comparison chip ( 2903 ); the output end of the unit under test ( 2902 ) is compared with the buffer comparison chip ( 2903 ) A set of inputs for comparison are connected; the remaining inputs of the buffer comparison chip (2903) are connected to the interface (2904) for receiving test excitations and expected results.
  • Buffer comparison chip ( 2903 Included is a buffer circuit for signal driving and a comparison circuit for comparison, wherein the buffer circuit can drive amplify the test excitation so that it can be transmitted to a plurality of units under test on the test board ( 2901 ) ( 2902), the comparison result can also be driven to be amplified so that it can be sent back to the test machine.
  • the test stimulus generated by the test machine can be buffered by the input/output interface (2904) (2903) ) input to a plurality of units under test ( 2902 ) for testing, and the operation result of the unit under test ( 2902 ) is input to the buffer comparison chip ( 2903 ) and the test machine through the interface ( 2904 ) The expected results of the input are compared, and the comparison result is transmitted back to the test machine through the interface (2904) to determine whether the unit under test (2902) is valid.
  • the two sets of buffer comparison chips (2903) for comparison can be compared with different units to be tested (2902)
  • the corresponding outputs are connected, and the outputs of different units under test (2902) are compared with each other.
  • the unit to be tested can be performed without the test machine providing the expected result (2902). Effective and suspected failure.
  • test excitation performed by different units under test may be simultaneously (or in parallel) run (or executed) in real time; the comparison between the operation result of the unit under test and the expected result or the result of operation with other units under test may be simultaneous ( Or parallel) run (or execute) in real time.
  • the buffer circuit for driving amplification of the test excitation can be omitted; if the driving result of the comparison from the comparison circuit is sufficiently large, then the operation can be omitted.
  • the comparison circuit or buffer circuit may also be located on other circuit boards connected to the test circuit board.
  • the input excitation of the unit under test ( 2902 ) can also come from electromagnetic waves.
  • Figure 29 (b) shows another embodiment of a packaged integrated circuit test device.
  • test board ( 2911 ) There are only a plurality of units under test (2915) and electrical connection interfaces (2912).
  • circuit board ( 2918 ) On the other circuit board ( 2918 ), there are a plurality of buffer comparison chips ( 2916 ) and an electrical connection interface ( 2914), and an input/output interface (2919) for communicating with the test machine.
  • Multiple test boards (2911) through electrical connection interface (2912) and circuit board (2918) The power-on connection interface ( 2914 ) is connected to form a set of test devices, and the three-dimensional effect diagram is shown in Figure 29 (c).
  • Test unit on test board ( 2911 ) ( 2915 The input and output ports are connected to the electrical connection interface (2912).
  • the test machine passes through the input and output interface ( 2919 ), the electrical connection interface ( 2914 ) and the electrical connection interface ( 2912
  • the test stimulus is input to the unit under test (2915), and the expected result is input to the buffer comparison chip (2916) through the input/output interface (2919).
  • Buffer comparison chip ( 2916) The operation result of the unit under test (2915) is compared with the expected result through the electrical connection interface (2914) and the electrical connection interface (2912), and the unit under test is determined (2915). )is it effective.
  • the buffer comparison chip ( 2916 ) can also be used as a different unit to be tested ( 2915 The corresponding outputs are compared with each other. At this time, it is not necessary for the test machine to provide the expected result, and the determination of the effective and suspected failure of the unit under test (2915) can be performed.
  • the input excitation of the unit under test (2915) may also be partially or fully derived from electromagnetic waves.
  • Figures 30A-B and 31A-B are four embodiments of a test system employing the present invention.
  • the same components use the same reference numerals.
  • the same components are not otherwise described in other embodiments.
  • test system 3000 includes wafer 3009 and wafer 3009 Connected tester 3002.
  • the wafer 3009 includes a plurality of measured crystal grains 3001, each of which contains a functional unit to be fabricated, such as an adder, a memory, a microprocessor, and a SOC. , logic operators, RF circuits that implement certain functions, CMOS sensors, etc.
  • test auxiliary circuit of the present invention as shown in Figures 30A-B and 31A-B includes an input line 3008 and an output line 3009.
  • Tester 3002 communicates bidirectionally via input line 3008 and output line 3009 with the functional units in each of the tested die 3001.
  • Input line 3008 It is connected to the access terminal 3003 of each measured die (or functional unit) 3001.
  • the die terminal 3006 is connected to an input of each comparator 3005.
  • Input line 3008 Can be used for each measured die 3001 Transfer test incentives.
  • Digital circuit test excitation typically includes operational instructions, data, control signals, clocks, power supplies, and the like; while analog circuit test excitations typically include analog signals, control signals, and power supplies. In the present invention, the test excitation may also include expected results of the operation of the measured die.
  • each register 3004 is connected to the output of the corresponding comparator 3005, and each register 3004 The output is connected to output line 3009.
  • the tester 3002 located outside the wafer passes through the input line 3008 and passes through the access terminal 3003 of each measured die 3001.
  • a test stimulus is transmitted to each of the measured die 3001 on the same wafer (which may include expected results of operation of each of the measured die).
  • Tester 3002 also passes input line 3008 The expected result is transmitted to one of the access terminals of each comparator 3005.
  • the measured die 3001 (or functional unit) According to its design function, the test excitation can be run (or executed) in real time (or in parallel), and the operation result is output from the output terminal 3006 of each measured die to the comparator 3005. Another access point.
  • the comparator 3005 compares the operation result with the expected result, and the comparison result of the measured die 3001 (or the functional unit) can be simultaneously (or in parallel) stored in the comparator 3005.
  • the corresponding output is connected to the corresponding register 3004.
  • the comparison result in each register 3004 is transmitted back to the tester 3002 through the output line 3009 by the tester 3002. It is determined whether the corresponding measured die 3001 is functioning normally according to the comparison result of each of the returns (that is, the tested functional unit is a normal unit or a failed unit).
  • each comparator 3005 is not connected to the input line 3008.
  • a corresponding die terminal 3006 connected to the comparator 3005 and a comparator 3005 of another adjacent die The inputs are connected to form a link to the die terminal 3006.
  • the other line connections are the same as the test auxiliary circuit of the present invention as shown in Fig. 30A.
  • its input line 3008 transmits only test excitations and does not transmit the expected results.
  • the tester 3002 located outside the wafer passes through the input line 3008.
  • the measured die can run (execute) the test excitation in real time (or in parallel) and transmit the operation result from the output of each measured die to the access terminals of the plurality of comparators. Measured grain in the upper left corner
  • the output of the output of the output terminal 3006 is transmitted not only to the access terminal of the comparator 3015 but also to the adjacent comparator 3014 via the internal connection 3011.
  • the access side while participating in the comparison between the two comparators. Taking the comparator 3015 as an example, one of the access terminals receives the output from the measured die 3013.
  • the other access terminal receives the operation results of other measured dies transmitted through the internal connection 3010, and compares the two to obtain a comparison result.
  • the comparison of the measured die can be simultaneously (or in parallel) stored in register 3004 connected to the output of the comparator. Individual registers 3004 The comparison results are transmitted back to the tester 3002 through the output line 3009, and the tester 3002 determines the corresponding measured die according to the comparison result of each return (3001, 3013). Whether the function is normal (ie, the functional unit under test is a normal unit or a failed unit).
  • a sensing area 3018 is provided on each of the measured crystal grains, and the sensing area 3018 It can convert light into an analog signal, a digital signal or an image signal.
  • the die with the sensing region can be a CMOS sensor die.
  • the light source is located in the out-of-wafer light source 3102 in the form of light 3019 A portion of the test stimulus is sent and received by sensor 3018 of each die 3101 being tested.
  • the remaining test excitations are passed through the tester 3002 through the input line 3008 through the access terminals of each of the tested dies 3101. 3103 transmits to a plurality of measured dies (3101) on the same wafer.
  • the tester 3002 also transmits the expected result to the comparator 3005 via the input line 3008.
  • the measured die can run (or perform) test excitation in real time (or in parallel) and output the operation result from the output terminal 3106 of each measured die to the comparator 3005.
  • the comparator 3005 compares the operation result with the expected result, and the comparison result of the measured die (or functional unit) can be simultaneously (or in parallel) stored in the register connected to the output of the comparator 3005. 3004.
  • the comparison result in each register 3004 is transmitted back to the tester 3002 through the output line 3009, and the tester 3002 determines the corresponding measured die according to the comparison result of each return.
  • the 3101 is functioning properly (that is, the functional unit under test is a normal unit or a failed unit).
  • the operating results of the measured dies are compared with each other, and the comparison result is transmitted back to the tester 3002 to determine the corresponding measured die 3101. Whether the function is normal (that is, the functional unit under test is a normal unit or a failed unit).
  • the functional paths of the crystals detected by the embodiment of Fig. 31A, which are converted into analog signals, digital signals or image signals, are also detected.
  • a receiving/transmitting antenna 3017 is provided on each of the measured dies, and the receiving/receiving/ The transmitting antenna 3017 can change the magnetic signal into an analog signal or a digital signal.
  • the die with the transmit/transmit antenna can be a radio frequency tag (RFID) die.
  • Tester 3002 passes the cable during the test operation 3021 transmits part of the test excitation to the receiving/transmitting device 3020, and performs wireless signal transmission through the receiving/transmitting antenna 3117 of the receiving/transmitting device 3020, from each measured die. The 3201's receive/transmit antenna 3017 is received.
  • the remaining test excitations are passed through the tester 3002 through the input line 3008 through the access terminals of the respective die 3201. Transfer to all measured die 3201 on the same wafer.
  • the receiving/transmitting antenna 3017 It can be fabricated on the same wafer using a semiconductor process, or it can be temporarily connected during testing.
  • the tester 3002 also transmits the expected result to the comparator via the input line 3008.
  • the measured die 3201 can run (or perform) test excitation in real time (or in parallel) and output the operation result from the output 3206 of each measured die to the comparator 3005. Another access point.
  • the comparator 3005 compares the operation result with the expected result, and the comparison result of the measured die 3001 (or the functional unit) can be simultaneously (or in parallel) stored in the comparator 3005.
  • the output is connected to the register (3004).
  • the comparison results in the respective registers (3004) are transmitted back to the tester 3002 via the output line 3009, by the tester 3002. It is determined whether the corresponding measured die 3201 is functioning normally according to the comparison result of each of the returns. Can also use a similar figure 30B
  • the operating results of the measured dies are compared with each other, and the comparison result is transmitted back to the tester 3002 to determine the corresponding measured die 3201. Whether the function is normal (that is, the functional unit under test is a normal unit or a failed unit).
  • the antenna transceiving functional path is also detected by the die detected by the embodiment of Fig. 31B.
  • the test auxiliary circuit of the present invention includes an input line 3008 and an output line 3009.
  • the path for the die to be measured can be dynamically set.
  • An embodiment of the dynamic setting of input line 3008 and output line 3009 is depicted in Figures 12-15 and associated description.
  • the output line of the test auxiliary circuit of the present invention 3009 A control circuit is included to serially output the comparison result of the measured die, so that the corresponding position of the comparison result of each die on the wafer can be found.
  • An embodiment of the control circuit is shown in Figures 14 and 15 And related descriptions are described.
  • the test auxiliary circuit of the present invention also has a power supply circuit for supplying power to all or part of the functional unit, the input circuit, the output circuit, and the decision circuit.
  • a power supply circuit for supplying power to all or part of the functional unit, the input circuit, the output circuit, and the decision circuit.
  • An embodiment of the power supply circuit is depicted in Figure 10 and related description.
  • a certain area on the wafer is dedicated to contact with the test probe to input power and excitation to the functional unit, the input circuit, the output circuit, and the decision circuit, and to read out the judgment result.
  • An embodiment of this is shown in Figure 16. And related descriptions are described.
  • test auxiliary circuit is disposed in the scribe line of the wafer. Examples of Figures 1 , 4 , 5 and 11 And related descriptions are described.
  • test auxiliary circuit can be self-tested. An embodiment thereof is described in Fig. 16 and related description.
  • test auxiliary circuit is fabricated using a wafer fabrication process. An embodiment thereof is described in Fig. 16 and related description.
  • the comparator can be a device for judging whether the two inputs are equal, that is, the comparison result is correct when the two inputs are equal, and the comparison result is an error when the two inputs are not equal; or can be used to determine the difference between the two inputs. Whether the value is within a predetermined range, that is, when the difference between the two inputs is within the predetermined interval, the comparison result is correct, and if the difference between the two inputs is not within the predetermined interval, the comparison result is an error.
  • the test auxiliary circuit of the present invention can be used as a standard unit form for the layout designer to use in a normal layout and routing process, and no additional workload is added to the layout designer.
  • the test aid circuit can be made using the same materials and processes as the substrate. For wafers, test aids can be added while masking is being designed and fabricated using the same semiconductor process, requiring no additional steps and costs in the semiconductor manufacturing stage. In the parallel test phase, using the test program corresponding to the test auxiliary circuit, it is convenient to locate the failed test unit and it is easy to use.

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Abstract

L'invention porte sur un procédé, un dispositif et un système de test de circuits intégrés. Une pluralité d'unités sous test (UUT) et une pluralité de dispositifs servant à comparer des résultats d'opération d'UUT sont inclus sur une base partagée. Différentes UUT exécutent une même excitation d'entrée; chacune donne un résultat d'opération qui est comparé par le dispositif de comparaison correspondant, donnant des caractéristiques de comparaison qui sont utilisées comme base pour éliminer par filtrage des UUT invalides. La présente invention réduit les coûts de test, raccourcit le temps pour réaliser une production en série, et abaisse le taux de perte.
PCT/CN2011/076808 2010-07-05 2011-07-04 Procédé, dispositif et système de test parallèle de circuits intégrés WO2012003790A1 (fr)

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US11413861B2 (en) 2019-02-06 2022-08-16 Hewlett-Packard Development Company, L.P. Pulldown devices
US11780223B2 (en) 2019-02-06 2023-10-10 Hewlett-Packard Development Company, L.P. Pulldown devices
CN110596591A (zh) * 2019-10-25 2019-12-20 四川诚邦浩然测控技术有限公司 新能源电机在线测试系统

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