WO2012000316A1 - 一种隔离区、半导体器件及其形成方法 - Google Patents

一种隔离区、半导体器件及其形成方法 Download PDF

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Publication number
WO2012000316A1
WO2012000316A1 PCT/CN2011/071093 CN2011071093W WO2012000316A1 WO 2012000316 A1 WO2012000316 A1 WO 2012000316A1 CN 2011071093 W CN2011071093 W CN 2011071093W WO 2012000316 A1 WO2012000316 A1 WO 2012000316A1
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WIPO (PCT)
Prior art keywords
sidewall
trench
semiconductor substrate
isolation region
forming
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Ceased
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PCT/CN2011/071093
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English (en)
French (fr)
Inventor
尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to GB1122114.0A priority Critical patent/GB2486978B/en
Priority to US13/119,129 priority patent/US9082717B2/en
Priority to CN2011900000514U priority patent/CN202585379U/zh
Publication of WO2012000316A1 publication Critical patent/WO2012000316A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • Isolation zone semiconductor device and method of forming same
  • the present invention relates to the field of semiconductor technology, and in particular to an isolation region, a semiconductor device, and a method of forming the same. Background technique
  • a method of forming a semiconductor device includes: first, as shown in FIGS. 1 and 2, an active region 20 and an isolation region 12 surrounding the active region 20 are formed on a semiconductor substrate 10; subsequently, as shown in FIG. 3 and 4, forming a gate stack structure including a gate dielectric layer 22, a gate electrode 24 formed on the gate dielectric layer 22, and a sidewall spacer surrounding the gate dielectric layer 22 and the gate electrode 24.
  • a cap layer is further formed on the gate, the cap layer is usually silicon nitride, which can prevent the gate from being damaged during operation.
  • the cap layer is no longer labeled, the gate stack structure is formed on the active region 20 and extends to the isolation region 12; and then, as shown in FIG. 5 and FIG. 6, The gate stack structure and the isolation region 12 are masks, and the semiconductor substrate 10 having a partial thickness in the active region 20 is removed to form the recess 30; finally, a semiconductor material is formed in the recess 30 to The recess 30 is filled to form a source and drain region.
  • the present invention provides a semiconductor device and a method of forming the same, which are advantageous for reducing leakage.
  • the present invention provides an isolation region, the isolation region includes a first recess and an insulating layer filling the first recess, the first recess is embedded in the semiconductor substrate, and the first recess includes a sidewall, a bottom wall, and a second sidewall extending from the bottom wall and connected to the first sidewall, wherein an angle between the first sidewall and a normal of the semiconductor substrate is greater than a standard value.
  • an angle between the first sidewall and a normal line of the semiconductor substrate is 5 to 20 degrees.
  • the second sidewall and the first sidewall are connected to the first contact and the second contact, and the first contact to the first The junction between the second sidewall and the normal of the semiconductor substrate is increased.
  • a semiconductor device comprising the above-described isolation region, the semiconductor device further comprising a source and drain region, the source and drain regions comprising a second recess and a semiconductor layer filling the second recess, wherein The semiconductor substrate material is sandwiched between the second recess and the first sidewall and the second sidewall.
  • the semiconductor layer is Sii-xGex for a PMOS device; and Si: C for an NMOS device.
  • a method of forming an isolation region comprising:
  • an angle between the sidewall and a normal line of the semiconductor substrate is 5°-20°.
  • the method further includes: performing an etching operation on the second trench to expand the second trench.
  • a method of forming a semiconductor device comprising: forming the isolation region by the above method, wherein the isolation region is for spacing an active region;
  • the semiconductor layer is Si 1-x Ge x for a PMOS device, and Si: C for an NMOS device.
  • the technical solution provided by the present invention has the following advantages: by increasing the gap between the first sidewall (ie, the sidewall of the first trench) and the normal of the semiconductor substrate
  • the cross-sectional area of the isolated isolation region may be smaller than the opening area under the premise that the opening area of the isolation region is the same; and in the subsequent step, the opening of the isolation region is used as a mask Forming a source/drain region, and forming a trench for carrying material of the source and drain regions, using an anisotropic etching process such that the active region of the isolation region is connected to the isolation region The area is removed, and parallel to the half In any section of the conductor substrate, since the cross-sectional area of the isolation region is reduced, the active region connected to the isolation region will not be removed, that is, the embedded isolation region is still connected to the An active region material (ie, the semiconductor base material), in other words, the semiconductor base material remains between the trench and the isolation region, that is, each wall of the trench is the semiconductor base material (wherein
  • 1 and 2 are schematic structural views of the prior art after forming an active region
  • FIG. 3 and FIG. 4 are schematic structural views of the prior art after forming a gate stack structure
  • FIG. 5 and FIG. 6 are schematic structural views of the prior art after forming a groove
  • FIG. 7 to FIG. 9 are schematic structural views showing a source/drain region formed in the prior art
  • FIG. 10 to FIG. 12 are schematic structural views of the prior art after forming a contact region
  • Figure 13 is a schematic view showing the structure of the first embodiment of the isolation region of the present invention.
  • Figure 14 is a schematic structural view showing a second embodiment of the isolation region of the present invention.
  • FIG. 15 is a schematic structural view of an embodiment of a semiconductor device of the present invention.
  • 16 is a schematic structural view showing a first trench formed in a first embodiment of the method for forming an isolation region according to the present invention
  • 17 is a schematic structural view showing a second trench formed in a first embodiment of the method for forming an isolation region according to the present invention
  • FIG. 18 is a schematic structural view showing a second trench formed in a second embodiment of the method for forming an isolation region according to the present invention.
  • FIG. 19 is a schematic structural view showing an insulating layer formed in a first embodiment of the method for forming an isolation region according to the present invention
  • FIG. 20 is a schematic structural view showing an isolation region formed in an embodiment of a method for forming a semiconductor device according to the present invention
  • Figure 22 is a schematic view showing the structure after forming a third trench in the embodiment of the method for forming a semiconductor device of the present invention.
  • Fig. 23 is a view showing the structure of a semiconductor layer in the embodiment of the method for forming a semiconductor device of the present invention. detailed description
  • the present invention may repeat reference numerals and/or letters in different embodiments. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides an isolation region including a first recess 120 and an insulating layer 140 filling the first recess 120.
  • the first recess 120 is embedded in a semiconductor substrate.
  • the first groove 120 includes a first sidewall 122, a bottom wall 126, and a second sidewall 124 extending from the bottom wall 126 and connected to the first sidewall 122.
  • the angle between a sidewall 122 and the normal of the semiconductor substrate 100 is greater than a standard value.
  • the standard value means: In practice, when etching the groove 120, if the design requires that the angle between the sidewall of the groove 120 and the normal line of the semiconductor substrate 100 is a But due to craft or The need for the process (such as the presence of process errors and to improve the subsequent filling effect), the actual angle to meet the design requirements is ⁇ + ⁇ , at this time, ⁇ is the standard value.
  • the semiconductor substrate 100 is a silicon substrate.
  • the semiconductor substrate 100 may further include other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or phosphating. Indium; further, the semiconductor substrate 100 preferably includes an epitaxial layer; the semiconductor substrate 100 may also include a silicon-on-insulator (SOI) structure.
  • the insulating layer 140 may be silicon nitride, silicon oxynitride or undoped silicon oxide.
  • the angle between the first sidewall 122 and the normal of the semiconductor substrate 100 may be 5° to 20°, such as 8°, 10° or 15°.
  • the cross-sectional area of the isolated isolation region may be smaller than the opening area under the same opening area of the isolation region; and then in a subsequent step, the trench for carrying the source/drain region material and the isolation may be
  • the semiconductor substrate 100 material remains between the regions, gp, such that each wall of the trench is a material of the semiconductor substrate 100, which is advantageous for reducing a gap at a boundary between the source/drain region formed and the isolation region. The possibility.
  • the present invention also provides an isolation region on any of the sections perpendicular to the semiconductor substrate 100 (as an example, as shown in Figure 14)
  • the second side wall 124 and the first side wall 122 are connected to the first contact 1224 and the second contact 1242, and the second side wall 124 is formed by the first contact 1224 and the second contact 1242.
  • An angle with the normal to the semiconductor substrate 100 increases. It is advantageous to enlarge the cross-sectional area of the region defined by the second side wall 124, and then, when the insulating layer 140 is used to fill the region to form the isolation region, it is advantageous to enhance the isolation effect.
  • the second sidewall 124 may have a curved or polygonal shape (not shown).
  • the present invention provides a semiconductor device including the above-described isolation region (taking the second embodiment as an example), the semiconductor device further including a gate stack structure (the gate stack structure including a gate) a dielectric layer 102, a gate 104 formed on the gate dielectric layer 102, and a sidewall 106 surrounding the gate dielectric layer 102 and the gate 104 to facilitate reducing parasitic capacitance; in other embodiments, The side wall 106 may also be located on the gate dielectric layer 102 and surround the gate 104) and source and drain regions (taking the embedded source and drain regions as an example), wherein the source and drain regions include a second recess 144 and a semiconductor layer 146 filling the second recess 144, the second recess 144 and the first sidewall 122 and the second sidewall 124 sandwich the semiconductor substrate 100 material (as shown in the figure) Marked by the dashed box).
  • the semiconductor device further including a gate stack structure (the gate stack structure including a gate) a dielectric layer 102, a gate
  • each wall of the second recess 144 is the material of the semiconductor substrate 100, and the material of the semiconductor substrate 100 is used as a seed. Crystal, facilitating uniformity in all directions in the second groove 144
  • the semiconductor layer 146 for forming the source and drain regions is grown to further reduce the possibility of forming a gap at the boundary between the source and drain regions formed and the isolation region 142.
  • the semiconductor layer may be Sii— x Ge x (X may range from 0.1 to 0.7, and may be flexibly adjusted according to process requirements, such as 0.2, 0.3, 0.4. , 0.5 or 0.6, there is no special description in this document, the value of X is the same, no longer repeat); for NMOS devices, the semiconductor layer can be Si: C (the atomic percentage of C can be 0.2 % ⁇ 2%, such as 0.5%, 1% or 1.5%, the content of C can be flexibly adjusted according to the process requirements. Unless otherwise specified in this document, the atomic percentage of C is the same, no longer repeat) .
  • the semiconductor layer may be a semiconductor material that has been ion-doped, for example, Sii.xGex or Si:C which may be N-type or P-type.
  • the ion doping operation may be directly formed during the process of generating the semiconductor material 182 (eg, a reactant containing a dopant ion component is entangled in a reactant that generates the semiconductor material 182); After the semiconductor material 182 is formed by an ion implantation process, the ion doping operation can be performed by any conventional ion implantation process, and will not be described again.
  • the method forms the source and drain regions, it is advantageous to reduce the stress loss of the source and drain regions.
  • the invention also provides a method for forming an isolation region, comprising:
  • a first trench 220 is formed on the semiconductor substrate 200, and the sidewall 222 of the first trench 220 is between the normal line of the semiconductor substrate 200 (as indicated by a broken line in the figure). The angle is greater than the standard value.
  • the semiconductor substrate 200 is a silicon substrate.
  • the semiconductor substrate 200 may further include other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide; 200 preferably includes an epitaxial layer; the semiconductor substrate 200 may also include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the step of forming the first trench 220 includes: first, sequentially forming silicon oxide on the semiconductor substrate 200 (which may be formed by a thermal oxidation process or a deposition process) and silicon nitride (which may be formed by a deposition process); Forming a patterned photoresist layer on the silicon nitride; and then patterning the silicon nitride and silicon oxide with the patterned photoresist layer as a mask to Forming a hard mask 224 (ie, to make the structure clear, the hard mask 224 is illustrated to include silicon oxide and silicon nitride formed on the silicon oxide); then, the patterned photo-resistance is removed Etchant layer; Finally, a portion of the thickness of the semiconductor substrate 200 is etched using the hard mask 224.
  • the inventors of the present invention believe that in the prior art, the reason for forming a gap between the source and drain regions and the isolation region is that: the source and drain regions are formed by filling a trench with a semiconductor material, and the semiconductor material is formed by an epitaxial process; Forming the trench with the gate stack structure and the isolation region as a mask, that is, after forming the trench, sidewalls of the isolation region are exposed; in other words, in each wall of the trench Having both a semiconductor substrate material and a sidewall of the isolation region; and when the semiconductor material is formed by an epitaxial process, the semiconductor substrate material is seeded, gp, as the wall of the trench The sidewall of the isolation region is incapable of providing the seed crystal; further, the inventors of the present invention have found that the growth rate of the semiconductor material in different crystal orientations is also different, specifically, the directions of (100) and (10) In contrast, the growth rate of the semiconductor material in the (1 1 1 ) direction is slow; in practice, the direction generally perpendicular to the semiconductor substrate
  • the inventors of the present invention believe that if the semiconductor base material is left or formed on the sidewall of the isolation region, in other words, the proportion of the semiconductor base material in each wall of the trench is increased. , that is, by supplementing the semiconductor base material having different crystal orientations as a seed crystal, filling the gap with the supplemented seed epitaxially grown semiconductor material, thereby facilitating reduction or even elimination of the source/drain region and the isolation interval Gap, which reduces leakage.
  • the first trench 220 may be formed by an etching process.
  • the angle between the sidewall 222 and the normal of the semiconductor substrate 200 may be 5° to 20°, such as 8°, 10° or 15°.
  • a mask 240 is formed on the sidewall 222, and the second trench 260 is formed on the semiconductor substrate 200 by the mask 240.
  • the mask 240 may be any semiconductor material different from the material of the semiconductor substrate 200, such as silicon nitride, silicon oxynitride or undoped silicon oxide; the mask 240 material may be subsequently filled with the trench
  • the insulating layer material forming the isolation region is the same. If the insulating layer material that subsequently fills the trench to form the isolation region is undoped silicon oxide, the mask material may be undoped silicon oxide, which is beneficial to the present invention.
  • the technical solution provided by the invention is compatible with the prior art.
  • the mask 240 can be formed using a selective deposition process.
  • the second trench 260 may be formed using an etching process.
  • the method further includes: performing an etching operation on the second trench 260 to expand the second trench 260.
  • Expanding the second trench 260 may be performed using an isotropic or anisotropic etch process Operation. Taking the expanding operation by an isotropic etching process as an example, as shown in FIG. 18, at this time, in any section perpendicular to the semiconductor substrate 200 (as shown in the cross section), the second trench The sidewall 262 of the trench 260 may have a curved topography; if the expanding operation is performed by an anisotropic etching process, the sidewall of the second trench 260 may have a polygonal shape (not shown).
  • Performing an etching operation on the second trench 260 to enlarge the second trench 260 may increase a cross-sectional area of the second trench 260, and then filling the second trench 260 with an insulating layer At the time, it helps to enhance the isolation effect.
  • an insulating layer 280 is formed to fill the first trench 220 and the second trench 260.
  • the insulating layer 280 may be silicon nitride, silicon oxynitride or undoped silicon oxide. Forming the insulating layer
  • the mask 240 may or may not be removed (in this embodiment, the mask is removed or the mask material is the same as the insulating layer material).
  • the hard mask 224 will also be removed before the subsequent steps are performed.
  • the present invention also provides a method of forming a semiconductor device, comprising: first, as shown in FIG. 20, the isolation region 142 is formed by the above method (such as the second embodiment of the isolation region described above), and the isolation region is used for spacing Active region 148; subsequently, as shown in FIG. 21, a gate stack structure is formed on the semiconductor substrate 100 (the same as described in the foregoing semiconductor device embodiment, and will not be described again), the gate stack structure is throughout a source region 148 and extending to the isolation region 142; then, as shown in FIG. 22, using the gate stack structure and the isolation region as a mask, forming a third trench 150 in the active region ; Finally, as shown in FIG. 23, the semiconductor layer 152 is filled in the third trench 150 to form source and drain regions.
  • the third trench 150 may be formed using an anisotropic etch process.
  • the material of the semiconductor layer 152 is the same as that described in the foregoing semiconductor device embodiment, and will not be described again.
  • the cross-sectional area of the buried isolation region can be made under the same opening area of the isolation region Less than the opening area; and in the subsequent step, the source and drain regions are formed by using the opening of the isolation region as a mask, and when forming a third trench for carrying material of the source and drain regions, An anisotropic etching process, such that at the opening of the isolation region, the active region connected to the isolation region is removed, and on any section parallel to the semiconductor substrate, due to the isolation region The cross-sectional area is reduced, the active region connected to the isolation region will no longer be removed, ⁇ , the embedded isolation region is still connected to the active region material (ie, the semiconductor substrate material), in other words Retaining the semiconductor base material between the third trench and the isolation region, That is, each wall of the third trench is the semiconductor base material, and the semiconductor base material is used as a seed crystal, which is favorable for uniformly growing in the groove in each direction to form the source and

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Description

一种隔离区、 半导体器件及其形成方法
技术领域
本发明涉及半导体技术领域， 具体来说， 涉及一种隔离区、 半导体器件及其 形成方法。 背景技术
当前， 形成半导体器件的方法包括： 首先， 如图 1和图 2所示， 在半导体基 底 10上形成有源区 20和环绕所述有源区 20的隔离区 12 ; 随后， 如图 3和图 4 所示， 形成栅堆叠结构 （所述栅堆叠结构包括栅介质层 22， 形成于所述栅介质层 22上的栅极 24以及环绕所述栅介质层 22和所述栅极 24的侧墙 26， 实践中， 所 述栅极上还形成有盖层， 所述盖层通常为氮化硅， 可防止所述栅极在操作过程中 受损伤， 为描述方便， 本文件内的文字和附图中， 不再标示所述盖层） ， 所述栅 堆叠结构形成于所述有源区 20上并延伸至所述隔离区 12; 再后， 如图 5和图 6 所示， 以所述栅堆叠结构和所述隔离区 12为掩膜， 去除所述有源区 20内部分厚 度的所述半导体基底 10， 以形成凹槽 30; 最后， 在所述凹槽 30中生成半导体材 料， 以填充所述凹槽 30， 形成源漏区。
然而， 如图 7至图 9所示， 实践中发现， 在所述源漏区 32和所述隔离区 12 的交界处， 形成有缝隙 34; 继而， 如图 10至图 12所示， 使得后续在所述源漏区 32上形成接触区 36 (如金属硅化物层） 时， 所述接触区 36易经所述缝隙 34而到 达结区， 进而导致漏电。 发明内容
为了解决上述问题， 本发明提供了一种半导体器件及其形成方法， 利于减少 漏电。
本发明提供的一种隔离区， 所述隔离区包括第一凹槽和填充所述第一凹槽的 绝缘层， 所述第一凹槽嵌于半导体基底中， 所述第一凹槽包括第一侧壁、 底壁和 由所述底壁延伸并接于所述第一侧壁的第二侧壁， 其中， 所述第一侧壁与所述半 导体基底的法线间的夹角大于标准值。
可选地， 所述第一侧壁与所述半导体基底的法线间的夹角为 5〜20°。 可选地， 在垂直于所述半导体基底的任一剖面上， 所述第二侧壁与所述第一 侧壁接于第一接点和第二接点， 由所述第一接点至所述第二接点， 所述第二侧壁 与所述半导体基底的法线间的夹角增大。
一种半导体器件， 所述半导体器件包含上述的隔离区， 所述半导体器件还包 括源漏区， 所述源漏区包括第二凹槽和填充所述第二凹槽的半导体层， 其中， 所 述第二凹槽与所述第一侧壁和第二侧壁之间夹有所述半导体基底材料。
可选地， 所述半导体基底材料为 Si 时， 对于 PMOS器件， 所述半导体层为 Sii-xGex; 对于 NMOS器件， 所述半导体层为 Si:C。
一种隔离区的形成方法， 包括：
在半导体基底上形成第一沟槽， 所述第一沟槽的侧壁与所述半导体基底的法 线间的夹角大于标准值；
在所述侧壁上形成掩膜， 利用所述掩膜在半导体基底上形成第二沟槽； 形成绝缘层， 以填充所述第一沟槽和所述第二沟槽。
可选地， 所述侧壁与所述半导体基底的法线间的夹角为 5°〜20°。
可选地， 在形成所述绝缘层之前， 还包括： 对所述第二沟槽执行刻蚀操作， 以扩大所述第二沟槽。
一种半导体器件的形成方法， 包括- 以上述的方法形成所述隔离区， 所述隔离区用以间隔有源区；
在所述半导体基底上形成栅堆叠结构， 所述栅堆叠结构贯穿所述有源区并延 伸至所述隔离区；
以所述栅堆叠结构和所述隔离区为掩膜， 在所述有源区内形成第三沟槽； 在所述第三沟槽中填充半导体层， 以形成源漏区。
可选地， 所述半导体基底材料为 Si 时， 对于 PMOS器件， 所述半导体层为 Si1-xGex ; 对于 NMOS器件， 所述半导体层为 Si:C。
与现有技术相比， 釆用本发明提供的技术方案具有如下优点- 通过增大所述第一侧壁 （即， 第一沟槽的侧壁） 与所述半导体基底的法线间 的夹角， 可在所述隔离区的开口面积相同的前提下， 使嵌入的所述隔离区的横截 面积小于所述开口面积； 而在后续步骤中， 是以所述隔离区的开口为掩膜形成源 漏区的， 且在形成用以承载源漏区材料的槽时， 釆用各向异性刻蚀工艺， 使得在 所述隔离区的开口处， 接于所述隔离区的所述有源区被去除， 而在平行于所述半 导体基底的任一截面上， 由于所述隔离区横截面积减小， 接于所述隔离区的所述 有源区将不再被去除， 即， 嵌入的所述隔离区仍接于所述有源区材料 （即所述半 导体基底材料） ， 换言之， 在所述槽和所述隔离区之间残留有所述半导体基底材 料， 即， 所述槽的各壁均为所述半导体基底材料 （其中， 由于所述槽和所述隔离 区之间残留有所述半导体基底材料， 而使靠近所述隔离区的所述槽的侧壁由所述 隔离区材料变更为所述半导体基底材料） ， 再在所述槽中以所述半导体基底材料 为籽晶生长源漏区材料（所述半导体基底材料为 Si时， 对于 PMOS器件， 所述半 导体层为 S .xGex; 对于 NMOS器件， 所述半导体层为 Si:C ) 时， 利于减少在形 成的所述源漏区与所述隔离区的交界处形成缝隙的可能性； 进而， 由于缝隙的减 少， 还可在所述槽中形成所述源漏区材料时减少应力损失；
通过在垂直于所述半导体基底的任一剖面上， 由所述第一接点至所述第二接 点， 所述第二侧壁与所述半导体基底的法线间的夹角增大， 利于扩大由所述第二 侧壁限定的区域的横截面积， 继而， 利用所述绝缘层填充所述区域进而形成所述 隔离区时， 利于增强隔离效果； 或者， 通过在形成所述绝缘层之前， 对所述第二 沟槽执行刻蚀操作， 以扩大所述第二沟槽， 可增加所述第二沟槽的横截面积， 继 而， 以所述绝缘层填充所述第二沟槽时， 利于增强隔离效果。 附图说明
下列各剖视图均为沿对应的俯视图中给出的剖线（ΑΑ'、 ΒΒ' )切割已形成的结构 后获得。
图 1和图 2所示为现有技术中形成有源区后的结构示意图；
图 3和图 4所示为现有技术中形成栅堆叠结构后的结构示意图；
图 5和图 6所示为现有技术中形成凹槽后的结构示意图；
图 7至图 9所示为现有技术中形成源漏区后的结构示意图；
图 10至图 12所示为现有技术中形成接触区后的结构示意图；
图 13所示为本发明隔离区第一实施例的结构示意图；
图 14所示为本发明隔离区第二实施例的结构示意图；
图 15所示为本发明半导体器件实施例的结构示意图；
图 16所示为本发明隔离区的形成方法第一实施例中形成第一沟槽后的结构示意 图； 图 17所示为本发明隔离区的形成方法第一实施例中形成第二沟槽后的结构示意 图；
图 18所示为本发明隔离区的形成方法第二实施例中形成第二沟槽后的结构示意 图；
图 19所示为本发明隔离区的形成方法第一实施例中形成绝缘层后的结构示意图； 图 20所示为本发明半导体器件的形成方法实施例中形成隔离区后的结构示意图； 图 21所示为本发明半导体器件的形成方法实施例中形成栅堆叠结构后的结构示 意图；
图 22所示为本发明半导体器件的形成方法实施例中形成第三沟槽后的结构示意 图；
图 23所示为本发明半导体器件的形成方法实施例中形成半导体层后的结构示意 图。 具体实施方式
下文的公开提供了许多不同的实施例或例子用来实现本发明提供的技术方 案。 虽然下文中对特定例子的部件和设置进行了描述， 但是， 它们仅仅为示例， 并且目的不在于限制本发明。
此外， 本发明可以在不同实施例中重复参考数字和 /或字母。 这种重复是为了 简化和清楚的目的， 其本身不指示所讨论的各种实施例和 /或设置之间的关系。
本发明提供了各种特定工艺和 /或材料的例子， 但是， 本领域普通技术人员可 以意识到的其他工艺和 /或其他材料的替代应用， 显然未脱离本发明要求保护的范 围。 需强调的是， 本文件内所述的各种区域的边界包含由于工艺或制程的需要所 作的必要的延展。
如图 13所示， 本发明提供了一种隔离区， 所述隔离区包括第一凹槽 120和填充 所述第一凹槽 120的绝缘层 140， 所述第一凹槽 120嵌于半导体基底 100中， 所 述第一凹槽 120包括第一侧壁 122、 底壁 126和由所述底壁 126延伸并接于所述 第一侧壁 122的第二侧壁 124， 其中， 所述第一侧壁 122与所述半导体基底 100 的法线 （如图中虚线所标示） 间的夹角大于标准值。
本文件内， 所述标准值意指： 实践中， 在刻蚀所述凹槽 120时， 若设计要求 所述凹槽 120的侧壁与所述半导体基底 100的法线间的夹角为 a, 但由于工艺或 制程的需要 （如存在工艺误差及为改善后续填充效果） ， 实际获得满足设计要求 的所述夹角为 α+Δα, 此时， Δα即为标准值。
其中， 在本实施例中， 所述半导体基底 100 为硅衬底， 在其他实施例中， 所述 半导体基底 100还可以包括其他化合物半导体，如碳化硅、砷化镓、砷化铟或磷化铟； 此外， 所述半导体基底 100优选地包括外延层； 所述半导体基底 100也可以包括绝 缘体上硅（SOI)结构。 所述绝缘层 140可为氮化硅、 氮氧化硅或未掺杂的氧化硅。
在本实施例中，所述第一侧壁 122与所述半导体基底 100的法线间的夹角可以 为 5°〜20°， 如 8°, 10°或 15°。 可在隔离区的开口面积相同的前提下， 使嵌入的所 述隔离区的横截面积小于所述开口面积； 继而在后续步骤中， 可在用以承载源漏 区材料的槽和所述隔离区之间残留有所述半导体基底 100材料， gp， 使所述槽的 各壁均为所述半导体基底 100材料， 利于减少在形成的所述源漏区与所述隔离区 的交界处形成缝隙的可能性。
特别地， 在所述隔离区的第二实施例中， 本发明还提供了一种隔离区， 在垂直 于所述半导体基底 100的任一剖面（作为示例， 如图 14所示的剖面） 上， 所述第 二侧壁 124与所述第一侧壁 122接于第一接点 1224和第二接点 1242， 由所述第 一接点 1224至所述第二接点 1242， 所述第二侧壁 124与所述半导体基底 100的 法线间的夹角增大。利于扩大由所述第二侧壁 124限定的区域的横截面积， 继而， 利用所述绝缘层 140填充所述区域进而形成所述隔离区时， 利于增强隔离效果。 需说明的是， 在垂直于所述半导体基底 100的任一剖面上， 所述第二侧壁 124可 具有弧形或折线 （图未示） 形等形貌。
如图 15所示， 本发明提供了一种半导体器件， 所述半导体器件包含上述隔离区 (以第二实施例为例） ， 所述半导体器件还包括栅堆叠结构 （所述栅堆叠结构包 括栅介质层 102、形成于所述栅介质层 102上的栅极 104和环绕所述栅介质层 102 及所述栅极 104 的侧墙 106, 以利于减小寄生电容； 在其他实施例中， 所述侧墙 106还可位于所述栅介质层 102上且环绕所述栅极 104 )和源漏区（以嵌入式的源 漏区为例） ， 其中， 所述源漏区包括第二凹槽 144和填充所述第二凹槽 144的半 导体层 146， 所述第二凹槽 144与所述第一侧壁 122和第二侧壁 124之间夹有所 述半导体基底 100材料 （如图中虚框所标示） 。 即， 在形成用以承载源漏区材料 的所述第二凹槽 144时，所述第二凹槽 144的各壁均为所述半导体基底 100材料， 再以所述半导体基底 100材料为籽晶， 利于在所述第二凹槽 144中沿各方向均匀 地生长用以形成所述源漏区的半导体层 146， 进而利于减少在形成的所述源漏区 与所述隔离区 142的交界处形成缝隙的可能性。
在所述半导体基底 100为 Si时，对于 PMOS器件，所述半导体层可为 Sii— xGex ( X的取值范围可为 0.1〜0.7, 可以根据工艺需要灵活调节， 如 0.2、 0.3、 0.4、 0.5 或 0.6， 本文件内未作特殊说明处， X的取值均与此相同， 不再赘述）； 对于 NMOS 器件， 所述半导体层可为 Si:C ( C的原子数百分比可以为 0.2%〜2%, 如 0.5%、 1 %或 1 .5%， C的含量可以根据工艺需要灵活调节， 本文件内未作特殊说明处， C 的原子数百分比均与此相同， 不再赘述） 。 需说明的是， 所述半导体层可以是已 完成离子惨杂的半导体材料， 如， 可以是 N型或 P型的 Sii.xGex或 Si:C。 所述离 子掺杂操作可以在生成所述半导体材料 182的过程中直接形成 （如在生成所述半 导体材料 182的反应物中惨入包含掺杂离子成分的反应物） ； 也可以在生成所述 半导体材料 182后， 再经由离子注入工艺形成， 可釆用任何传统的离子注入工艺 执行所述离子掺杂操作， 不再赘述。
采用上述材料形成所述源漏区， 利于利用所述源漏区提供的应力调节半导体器件 沟道区内的应力， 以改善所述沟道区内载流子的迁移率； 采用本发明提供的方法形成 所述源漏区时， 利于减少所述源漏区的应力损失。
本发明还提供了一种隔离区的形成方法， 包括：
首先， 如图 16所示， 在半导体基底 200上形成第一沟槽 220 , 所述第一沟槽 220的侧壁 222与所述半导体基底 200的法线 （如图中虚线所标示） 间的夹角大 于标准值。
所述半导体基底 200为硅衬底， 在其他实施例中， 所述半导体基底 200还可以 包括其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷化铟； 此外， 所述半导体基 底 200优选地包括外延层； 所述半导体基底 200也可以包括绝缘体上硅（SOI)结构。
形成第一沟槽 220的步骤包括： 首先， 在所述半导体基底 200上顺次形成氧 化硅 （可采用热氧化工艺或淀积工艺形成） 及氮化硅 （可采用淀积工艺形成） ； 随后， 在所述氮化硅上形成图形化的光致抗蚀剂层； 再后， 以所述图形化的光致 抗蚀剂层为掩膜， 图形化所述氮化硅和氧化硅， 以形成硬掩膜 224 (即， 为使结 构清晰， 图示的所述硬掩膜 224包含氧化硅和形成于所述氧化硅上的氮化硅） ； 然后， 去除所述图形化的光致抗蚀剂层； 最后， 利用所述硬掩膜 224， 刻蚀部分 厚度的所述半导体基底 200。 本发明的发明人认为， 现有技术中， 在源漏区和隔离区之间形成缝隙的原因 在于： 所述源漏区通过以半导体材料填充沟槽构成， 所述半导体材料采用外延工 艺生成； 形成所述沟槽时以所述栅堆叠结构和所述隔离区为掩膜， 即， 形成所述 沟槽后， 将暴露所述隔离区的侧壁； 换言之， 所述沟槽的各壁中， 既包括半导体 基底材料， 也包括所述隔离区的侧壁； 而采用外延工艺生成所述半导体材料时， 是以所述半导体基底材料为籽晶的， gp， 作为所述沟槽的壁的所述隔离区的侧壁 无法提供所述籽晶； 此外， 本发明的发明人发现， 所述半导体材料沿不同晶向的 生长速率也不同， 具体地， 与（100 )和（1 10 )方向相比， 所述半导体材料沿（1 1 1 ) 方向的生长速率较慢；而实践中，通常垂直于所述半导体基底 100的方向为（100 ) 方向， 而平行于所述半导体基底 100的方向为 （1 10) 方向， 则 （1 1 1 ) 方向斜交 于 （100 ) 和 （1 10 ) 方向， gp， 由于所述半导体材料沿 （1 1 1 ) 方向的生长速率较 慢， 将使所述半导体材料在此方向上形成倾斜的侧面 （沿 （1 1 1 ) 方向） ， 所述倾 斜的侧面和所述隔离区的侧壁之间即形成缝隙。
由此， 本发明的发明人认为， 如果在所述隔离区的侧壁上保留或形成有所述 半导体基底材料， 换言之， 增加所述沟槽的各壁中所述半导体基底材料所占的比 例， 即， 通过补充具有不同晶向的所述半导体基底材料作为籽晶， 以经补充的籽 晶外延生长的半导体材料填充上述缝隙， 利于减小甚至消除所述源漏区和所述隔 离区间的缝隙， 进而减少漏电。
在本实施例中， 可釆用刻蚀工艺形成所述第一沟槽 220。 所述侧壁 222与所述 半导体基底 200的法线间的夹角可以为 5°〜20°， 如 8°, 10°或 15°。
随后， 如图 17所示， 在所述侧壁 222上形成掩膜 240， 利用所述掩膜 240在 半导体基底 200上形成第二沟槽 260。
所述掩膜 240可为异于所述半导体基底 200材料的任何半导体材料， 如氮化 硅、 氮氧化硅或未掺杂的氧化硅； 所述掩膜 240材料可与后续填充所述沟槽而形 成隔离区的绝缘层材料相同， 如后续填充所述沟槽而形成隔离区的绝缘层材料为 未惨杂的氧化硅时， 所述掩膜材料可为未惨杂的氧化硅， 利于本发明提供的技术 方案与现有技术的兼容。 所述掩膜 240可采用选择性沉积工艺形成。 可采用刻蚀 工艺形成所述第二沟槽 260。
在其他实施例中， 还可包括： 对所述第二沟槽 260执行刻蚀操作， 以扩大所 述第二沟槽 260。可采用各向同性或各向异性刻蚀工艺执行扩大所述第二沟槽 260 的操作。 以采用各向同性刻蚀工艺执行所述扩大操作为例， 如图 18所示， 此时， 在垂直于所述半导体基底 200 的任一剖面 （如图示剖面） 上， 所述第二沟槽 260 的侧壁 262可具有弧形形貌； 若采用各向异性刻蚀工艺执行所述扩大操作， 所述 第二沟槽 260的侧壁可具有折线形形貌 （图未示） 。
对所述第二沟槽 260执行刻蚀操作， 以扩大所述第二沟槽 260， 可增加所述 第二沟槽 260的横截面积， 继而， 以绝缘层填充所述第二沟槽 260时， 利于增强 隔离效果。
再后， 如图 19所示， 形成绝缘层 280， 以填充所述第一沟槽 220和所述第二 沟槽 260。
所述绝缘层 280可为氮化硅、 氮氧化硅或未惨杂的氧化硅。 形成所述绝缘层
280之前， 去除或不去除所述掩膜 240均可 （本实施例中， 以去除所述掩膜或所 述掩膜材料与所述绝缘层材料相同时为例） 。 在进行后续步骤之前， 所述硬掩膜 224也将被去除。
本发明还提供了一种半导体器件的形成方法， 包括： 首先， 如图 20所示， 以 上述方法形成所述隔离区 142 (如上述隔离区第二实施例） ， 所述隔离区用以间 隔有源区 148 ; 随后， 如图 21所示， 在所述半导体基底 100上形成栅堆叠结构（与 前述半导体器件实施例中描述的相同， 不再赘述） ， 所述栅堆叠结构贯穿所述有 源区 148并延伸至所述隔离区 142; 再后， 如图 22所示， 以所述栅堆叠结构和所 述隔离区为掩膜， 在所述有源区内形成第三沟槽 150; 最后， 如图 23所示， 在所 述第三沟槽 150 中填充半导体层 152， 以形成源漏区。 可采用各向异性刻蚀工艺 形成所述第三沟槽 150。 所述半导体层 152材料与前述半导体器件实施例中所描 述的相同， 不再赘述。
通过增大所述第一沟槽的侧壁与所述半导体基底的法线间的夹角， 可在所述 隔离区的开口面积相同的前提下， 使嵌入的所述隔离区的横截面积小于所述开口 面积； 而在后续步骤中， 是以所述隔离区的开口为掩膜形成源漏区的， 且在形成 用以承载源漏区材料的第三沟槽时， 釆用各向异性刻蚀工艺， 使得在所述隔离区 的开口处， 接于所述隔离区的所述有源区被去除， 而在平行于所述半导体基底的 任一截面上， 由于所述隔离区横截面积减小， 接于所述隔离区的所述有源区将不 再被去除， δΡ， 嵌入的所述隔离区仍接于所述有源区材料 （即所述半导体基底材 料） ， 换言之， 在所述第三沟槽和所述隔离区之间残留有所述半导体基底材料， 即， 所述第三沟槽的各壁均为所述半导体基底材料， 再以所述半导体基底材料为 籽晶， 利于在所述槽中沿各方向均匀地生长用以形成所述源漏区的半导体材料， 进而利于减少在形成的所述源漏区与所述隔离区的交界处形成缝隙的可能性。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、 结构、 制 造、 物质组成、 手段、 方法及步骤。 根据本发明的公开内容， 本领域技术人员将容易 地理解， 对于目前已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或歩骤， 它们在执行与本发明描述的对应实施例大体相同的功能或者获得大体相 同的结果时， 依照本发明的教导， 可以对它们进行应用， 而不脱离本发明所要求保护 的范围。

Claims

1、 一种隔离区， 所述隔离区包括第一凹槽和填充所述第一凹槽的绝缘层， 所 述第一凹槽嵌于半导体基底中， 所述第一凹槽包括第一侧壁、 底壁和由所述底壁 延伸并接于所述第一侧壁的第二侧壁， 其特征在于： 所述第一侧壁与所述半导体 基底的法线间的夹角大于标准值。
2、 根据权利要求 1所述的隔离区， 其特征在于： 所述第一侧壁与所述半导体 基底的法线间的夹角为 5°〜20°。权
3、 根据权利要求 1所述的隔离区， 其特征在于： 在垂直于所述半导体基底的 任一剖面上， 所述第二侧壁与所述第一侧壁接于第一接点和第二接点， 由所述第 一接点至所述第二接点， 所述第二侧壁与所述半导体基底的法线间的夹角增大。
求
4、 一种半导体器件， 所述半导体器件包含权利要求 1至 3中任一项所述的隔 离区， 所述半导体器件还包括源漏区， 所述源漏区包括第二凹槽和填充所述第二 凹槽的半导体层， 其特征在于： 所述第二凹槽与所述第一侧壁和第二侧壁之间夹 有所述半导体基底材料。
5、 根据权利要求 4所述的半导体器件， 其特征在于： 所述半导体基底材料为 Si时， 对于 PMOS器件， 所述半导体层为 Sii.xGex; 对于 NMOS器件， 所述半导 体层为 Si:C。
6、 一种隔离区的形成方法， 其特征在于， 包括- 在半导体基底上形成第一沟槽， 所述第一沟槽的侧壁与所述半导体基底的法 线间的夹角大于标准值；
在所述侧壁上形成掩膜， 利用所述掩膜在半导体基底上形成第二沟槽； 形成绝缘层， 以填充所述第一沟槽和所述第二沟槽。
7、 根据权利要求 6所述的方法， 其特征在于： 所述侧壁与所述半导体基底的 法线间的夹角为 5°〜 20°。
8、 根据权利要求 6所述的方法， 其特征在于， 在形成所述绝缘层之前， 还包 括： 对所述第二沟槽执行刻蚀操作， 以扩大所述第二沟槽。
9、 一种半导体器件的形成方法， 其特征在于， 包括- 以权利要求 6至 8中任一项所述的方法形成所述隔离区， 所述隔离区用以间 隔有源区； 在所述半导体基底上形成栅堆叠结构， 所述栅堆叠结构贯穿所述有源区并延 伸至所述隔离区；
以所述栅堆叠结构和所述隔离区为掩膜， 在所述有源区内形成第三沟槽， 所 述第三沟槽与所述隔离区之间夹有所述半导体基底材料；
在所述第三沟槽中填充半导体层， 以形成源漏区。
10、根据权利要求 9所述的方法， 其特征在于： 所述半导体基底材料为 Si时， 对于 PMOS器件， 所述半导体层为 S .xGex; 对于 NMOS器件， 所述半导体层为 Si:C。
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