WO2011162725A1 - Transistor à nanofils et son procédé de fabrication - Google Patents

Transistor à nanofils et son procédé de fabrication Download PDF

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WO2011162725A1
WO2011162725A1 PCT/SG2011/000222 SG2011000222W WO2011162725A1 WO 2011162725 A1 WO2011162725 A1 WO 2011162725A1 SG 2011000222 W SG2011000222 W SG 2011000222W WO 2011162725 A1 WO2011162725 A1 WO 2011162725A1
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gate
nanowire
dielectric layer
oxide
region
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PCT/SG2011/000222
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Navab Singh
Nansheng Shen
Zhixian Chen
Guo Qiang Patrick Lo
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Agency For Science, Technology And Research
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
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    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • Various embodiments relate to a nanowire transistor and a method for manufacturing the nanowire transistor, a memory cell including the nanowire transistor and a method for manufacturing the memory cell, and a memory device including the memory cell.
  • CMOS complementary metal oxide semiconductor
  • LDD lightly doped drain
  • lateral non-uniformity in channel doping reduction in junction depth
  • vertical non uniformity in well doping including pocket and HALO implants are a few examples.
  • the performance of scaled devices has been further improved by introducing stressors in the structure to improve the mobility (H.-S.P. Wong, "Beyond Conventional transistor", IBM J. Res. And Dev., vol. 46, no. 2/3, pp. 133-168, 2002; K.-W.
  • FIG. 1 shows a schematic cross-sectional view 100 of an evolution of multiple-gate transistors in order of increasing gate electrostatic control.
  • the device structure progresses from single gated planar to fully gate-all-around nanowire MOSFETs.
  • the gate-all-around (GAA) structure appears to be the most resistant to short channel effects among all the emerging device structures for a given silicon body thickness.
  • Simulations E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, "Design considerations and comparative investigation of ultra-thin SOI, double-gate and cylindrical nanowire FETs", in IEEE ESSDERC Proceeding, 2006, pp. 371-374.
  • the gate length can be scaled to 5 nm with the corresponding scaling of the intrinsic nanowire channel body.
  • the cylindrical geometry gives inverse logarithmic dependence of the gate capacitance on the channel diameter, and, thus, the gate length in these devices can be scaled with wire diameter without reducing the gate dielectric thickness.
  • GAA nanowire devices when fabricated on a lateral platform, suffer from practical challenges in defining shorter length wires due to the corner rounding effect in lithography. Gate uniformity and wire shape control are the other concerns.
  • the device area scaling also follows the conventional scaling rule. In this regard, vertical wire devices are found more suitable than lateral. Nevertheless, controlling junctions in nanowire is even more challenging, and the impact of poor junction control on device performance and reliability can be significant.
  • SONOS memory cell uses standard MOS transistor as a base device. Fabricated on nanowires in a gate-all-around (GAA) configuration, SONOS cells have shown great performance with promises towards density improvement (Fu J, Singh N, Buddharaju KD, Teo SHG, Shen C, Jiang Y, Zhu CX, Yu MB, Lo GQ, Balasubramanian N, Kwong DL, Gnani E, Baccarani G, "Si-nanowire based gate-all-around nonvolatile SONOS memory cell", IEEE Electron Device Letters, Volume 29 Issue 5, pp 518-521, 2008).
  • GAA gate-all-around
  • FIG. 2A shows a CMOS inverter logic 201 using a planar device, for example as represented by 200 for an n-gate device
  • FIG. 2B shows a CMOS inverter logic 221 using a vertical wire device, for example a p-gate device 220a and an n-gate device 220b, for area comparison of the devices and the inverter logic to illustrate the scaling advantages of the devices based on vertical wire configuration.
  • the parameter F is the minimum feature size or half pitch for the corresponding technology node.
  • the planar device CMOS inverter 201 includes a p-gate 202 coupled to a source 204 and a drain 206, and an n-gate 208 coupled to a source 210 and a drain 212.
  • the vertical wire CMOS inverter 221 includes a p-gate device 220a with a p-gate 222 surrounding a part of the vertical wire, with the top part of the wire not covered by the gate 222 forming the source/drain 224, and an n-gate device 220b with an n-gate 226 surrounding a part of the vertical wire, with the top part of the wire not covered by the gate 224 forming the source/drain 228. While not shown in FIG. 2B, the bottom part of the respective wire of the p-gate device 220a and the n-gate device 220b are not covered by the p-gate 222 and the n-gate 226, thereby forming another respective source/drain.
  • the device area (e.g. of the n-gate device 200) is approximately 8F (i.e. 2F x 4F) while the inverter area is approximately 40 F 2 (i.e. 10F x 4F).
  • the device area (e.g. of the p-gate device 220a and the n-gate device 220b) is approximately 4F 2 (i.e. 2F x 2F) while the inverter area is approximately 12F 2 (i.e. 6F x 2F).
  • the vertical wire device (e.g.
  • CMOS inverter logic 221 occupies a device area that is approximately 50% of the device area occupied by the n-gate device 200 of the CMOS inverter logic 201.
  • An even bigger advantage is in terms of the resulting circuits, e.g. a CMOS inverter can be fabricated in an area of approximately 12F 2 using vertical wires against an area of approximately 40F in planar technology. It is assumed that device matching is accomplished through gate length, thus both n- and p-MOS occupy the same area.
  • the junction capacitances decrease with the area and ultimately the circuit speed is increased significantly.
  • the inverter delay is expected to be reduced by ⁇ 6x compared to that of the planar device.
  • the power consumption, P fCV (where f is frequency, C is capacitance and V is operating voltage) is also reduced by 60% of the planar devices.
  • FIGS. 3A to 3C explain possible issues due to non self aligned gate structure in vertical wire devices of the prior art.
  • FIG. 3A shows a schematic of a vertical wire device 300 with the gate 302 aligned with the source and drain (e.g. 304a, 304b).
  • FIG. 3B shows a schematic of a vertical wire device 320 with the gate 322 aligned with the top electrode (source/drain) 324a but under-lapped with the bottom electrode (source/drain) 324b, resulting in a higher parasitic resistance.
  • FIG. 3A shows a schematic of a vertical wire device 300 with the gate 302 aligned with the source and drain (e.g. 304a, 304b).
  • FIG. 3B shows a schematic of a vertical wire device 320 with the gate 322 aligned with the top electrode (source/drain) 324a but under-lapped with the bottom electrode (source/drain) 324b, resulting in a higher parasitic resistance.
  • FIG. 3C shows a schematic of a vertical wire device 340 with the gate 342 aligned with the top electrode (source/drain) 344a but overlapped with the bottom electrode 344b, resulting in a higher parasitic capacitance.
  • the vertical wire devices 300, 320, 340 include an opposite polarity region 303, 323, 343, respectively.
  • the opposite polarity region 303 has a polarity that is opposite to that of the source and drain (e.g. 304a, 304b) and the gate 302.
  • These opposite polarity regions 303, 323, 343, are called channels or channel regions, which are separated from their respective source and drain by junctions.
  • the doping in the channel is of an opposite conductivity type to the source and drain.
  • an N-type device has an n-type source/drain (i.e. n-doped) but a p-type channel (i.e. p-doped).
  • doping type of the gate follows that of the source/drain.
  • the vertical wire devices 300, 320, 340 further include a gate dielectric 306, 326, 346, respectively, which serves to electrically isolate the respective gate from the respective channel and source/drain regions.
  • the gate dielectric 306 serves to electrically isolate the gate 302 from the channel 303 and the source/drain regions 304a, 304b. Summary
  • a nanowire transistor may include a carrier; a vertical nanowire structure extending from the carrier, the vertical nanowire structure including a channel region, and the vertical nanowire structure being made of the same material as the carrier; a gate insulator region covering at least a portion of the vertical nanowire structure; and at least one gate region covering at least a portion of the gate insulator region.
  • a memory cell may include a nanowire transistor as described above and wherein the gate insulator region includes a first dielectric layer configured to cover at least the portion of the vertical nanowire structure; a second dielectric layer; and a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and wherein a bandgap of the second dielectric layer is smaller than a respective bandgap of the first dielectric layer and the third dielectric layer.
  • a memory device may include a memory cell as described above.
  • a method for manufacturing a nanowire transistor may include removing material from a carrier to form a vertical nanowire structure extending from the carrier; covering at least a portion of the vertical nanowire structure with a gate insulator material to form a gate insulator region; and covering at least a portion of the gate insulator region with a gate material to form at least one gate region.
  • a method for manufacturing a memory cell may include the method for manufacturing a nanowire transistor as described above, and wherein covering at least a portion of the vertical nanowire structure with the gate insulator material comprises forming a first dielectric layer to cover at least the portion of the vertical nanowire structure; forming a second dielectric layer; and forming a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and wherein a bandgap of the second dielectric layer is smaller than a respective bandgap of the first dielectric layer and the third dielectric layer.
  • FIG. 1 shows a schematic cross-sectional view of an evolution of multiple-gate transistors in order of increasing gate electrostatic control of the prior art.
  • FIGS. 2A and 2B show CMOS inverter logic using a planar device and a vertical wire device respectively of the prior art.
  • FIGS. 3A to 3C show possible issues due to non self aligned gate structure in vertical wire devices of the prior art.
  • FIG. 4 A shows a schematic block diagram of a nanowire transistor, according to various embodiments.
  • FIG. 4B shows a schematic block diagram of a nanowire transistor, according to various embodiments.
  • FIG. 4C shows a schematic block diagram of a memory cell, according to various embodiments.
  • FIG. 5 shows a flow chart illustrating a method for manufacturing a nanowire transistor, according to various embodiments.
  • FIG. 6 shows a schematic cross sectional view of a nanowire transistor, according to various embodiments.
  • FIG. 7 shows a schematic cross-sectional view of a fabrication process for manufacturing a nanowire transistor, according to various embodiments.
  • FIG. 8 shows scanning electron microscope (SEM) images of structures formed during a fabrication process for manufacturing a nanowire transistor, according to various embodiments.
  • the width of each image is about 1 ⁇ .
  • FIG. 9 shows a transmission electron microscope (TEM) image of a nanowire transistor, according to various embodiments.
  • FIG. 10A shows a plot of drain current-gate voltage (I d -V g ) characteristics of a nanowire transistor, for different drain voltages (V d ), according to various embodiments.
  • FIG. 10B shows a plot of drain current-drain voltage (I d -V d ) characteristics of a nanowire transistor, for different gate voltages (V g ), according to various embodiments.
  • FIGS. 11A and 1 IB show cross-sectional transmission electron microscope (TEM) images respectively of a vertical silicon nanowire gate-all-around junction-less SONOS and an oxide-nitride-oxide (ONO) gate stack, according to various embodiments.
  • TEM transmission electron microscope
  • FIG. 12 shows a plot of drain current-gate voltage (I d -V g ) characteristics of a junction-less SONOS of various embodiments and a junction-based SONOS.
  • FIG. 13 shows a plot of drain current-gate voltage (Ia-V g ) characteristics of junction-less SONOS with different nanowire diameters, according to various embodiments.
  • FIG. 14 shows a plot of drain current-gate voltage (I d -V g ) characteristics of junction-less SONOS with different channel doping concentrations, according to various embodiments.
  • FIG. 15 shows plots of simulated electric field distributions of junction-less
  • SONOS for different nanowire diameters, according to various embodiments.
  • FIG. 16 shows plots of simulated electric field distributions of junction-less SONOS for different channel doping concentrations, according to various embodiments.
  • FIGS. 17A and 17B show plots of programming characteristics of junction-less
  • SONOS memory cells for different gate voltages, according to various embodiments.
  • FIG. 17C shows a plot of programming characteristics of a junction-based
  • FIGS. 18A and 18B show plots of erasing characteristics of junction-less SONOS memory cells for different gate voltages, according to various embodiments.
  • FIG. 18C shows a plot of erasing characteristics of a junction-based SONOS memory cell for different gate voltages.
  • FIG. 19 shows a plot of programming/erasing (P/E) speed of junction-less SONOS memory cells for different nanowire diameters, according to various embodiments.
  • FIG. 20 shows a plot of multi-bit programming characteristics of a junction-less SONOS memory cell, according to various embodiments.
  • FIG. 21 A shows a plot of retention characteristics at 85°C for junction-less SONOS memory cells of various embodiments and a junction-based SONOS memory cell.
  • FIG. 2 IB shows a plot of endurance characteristics at 85°C for junction-less SONOS memory cells of various embodiments and a junction-based SONOS memory cell.
  • FIG. 22A shows a schematic cross-sectional view of a 3-D memory device based on vertical junction-less silicon nanowire SONOS memory cells, according to various embodiments.
  • FIG. 22B shows a schematic of an equivalent circuit for the embodiment of FIG. 22A. Detailed Description
  • Various embodiments provide a semiconductor nanowire device and a method for manufacturing the same.
  • various embodiments may provide a vertical nanowire device and a method for manufacturing the same.
  • Various embodiments may provide a vertical nanowire device (e.g. a vertical nanowire transistor) free of any junction and a method of fabricating the same, which is simple and involves fewer processes.
  • the vertical nanowire device may include a gate- all-around (GAA) wire architecture for improved control of short channel effects (SCE), a vertical architecture for improved size scaling per device/circuit and reduced power, and a junction-less architecture so that the device may be free from challenges associated with junction control and non-self aligned gate in the vertical architecture.
  • GAA gate- all-around
  • SCE short channel effects
  • a vertical architecture for improved size scaling per device/circuit and reduced power
  • a junction-less architecture so that the device may be free from challenges associated with junction control and non-self aligned gate in the vertical architecture.
  • Various embodiments may provide self-aligned vertical wire GAA transistors or devices.
  • the term "self-aligned" as applied to a junction-less device may mean that the junction-less device behaves like a self
  • junction-less vertical nanowire device e.g. a junction-less vertical nanowire transistor
  • a junction-less vertical nanowire transistor that is free of any physical or chemical junction (e.g. a p-n junction), as the junction-less vertical nanowire device is based on electrical doping.
  • junction-less nanowire transistors of various embodiments may also provide a self-aligned gate with the source/drain regions when the transistors or devices are in operation, thereby providing self-aligned "junctions".
  • the gate is self-aligned as different regions, for example the channel, source and drain regions, are formed electrically rather than by doping.
  • the channel may be formed electrically by removing the depletion, thereby creating carriers in the nanowire region under the gate.
  • depletion is formed, followed by inversion, in order to create the channel.
  • junction-less nanowire transistors of various embodiments in the ON state, at least substantially the entire body of the nanowire functions as the channel or channel region in contrast to a surface channel for a junction-based nanowire device or transistor, while in the OFF state, the channel in the junction-less nanowire transistor is depleted using the gate work function.
  • Various embodiments may provide vertical nanowire devices (e.g. a vertical nanowire transistors), for example a gate-all-around (GAA) junction-less MOSFETs using CMOS compatible technology, based on vertical silicon nanowires having diameters of approximately 100 nm or less (i.e. ⁇ 100 nm), for example between about 5 nm to about 80 nm, between about 20 nm to about 60 nm or about 40 nm to about 50 nm.
  • the device of various embodiments may be more symmetric, with minimal or no overlap parasitic capacitance, with minimal or no under-lap parasitic resistance, more reliable and provide improved performances, compared to conventional (junction-based) vertical nanowire MOSFETs.
  • various embodiments may provide a more efficient and cost-effective method for fabricating highly scalable and high-performance transistors.
  • Various embodiments may provide highly scalable single crystalline silicon channels based on silicon nanowires (with nanowire diameters down to sub-20 nm) with thermally grown oxide on the silicon nanowires, for use in forming memory devices. This may alleviate or minimize any reliability issues, such as sub-threshold swing, leakage, threshold voltage Vt distribution and data retention.
  • Various embodiments may provide a channel region or channel length of approximately 200 nm or less (i.e. ⁇ 200 nm), for example between about 50 nm to about 180 nm, between about 100 nm to about 150 nm or about 100 nm to about 200 nm.
  • Various embodiments may provide a high-k dielectric/metal gate stack, where the parameter k refers to dielectric constant.
  • the nanowire transistors of various embodiments may offer a wider effective channel volume, higher density, lower power consumption, higher speed, with a larger turn-on current I on , and better electrostatic control, and may be fabricated on bulk wafers (e.g. bulk silicon wafer) and SOI wafers, thereby providing a low-cost approach.
  • bulk wafers e.g. bulk silicon wafer
  • SOI wafers SOI wafers
  • the nanowire transistors may offer a chemically simpler structure.
  • Various embodiments may provide a nanowire transistor that may be vertically stacked, for example for memory applications.
  • the stacked memory may have a plurality of cells per wire, e.g. 4 physical cells per wire.
  • Various embodiments may also provide a high performance GAA junction-less, vertical silicon nanowire-based, silicon-oxide-nitride-oxide-silicon (SONOS) memory, for example for three dimensional (3-D) (e.g. 3-D multi-level integration) ultra-high density applications.
  • SONOS silicon-oxide-nitride-oxide-silicon
  • the GAA nanowire architecture may be used for SONOS type nonvolatile memory applications where the gate dielectric has to be necessarily thicker, as the gate length in the devices with the GAA nanowire architecture may be scaled with wire diameter without reducing the gate dielectric thickness.
  • the vertical nanowire-based junction-less SONOS memory or memory cells of various embodiments may be stacked vertically, and involve simple fabrication method, with less manufacturing cost.
  • Various embodiments of the junction-less SONOS memory realized on vertical silicon nanowire GAA channel may have full memory functionality, for example for nanowire diameters down to about 20 nm, and having a high W ratio
  • Various embodiments may provide a scalable architecture, in the form of GAA nanowire devices, which may be provided to replace planar CMOS at the 22 nm technology node and below, for example for logic and memory circuits and applications.
  • FIG. 4A shows a schematic block diagram of a nanowire transistor 400, according to various embodiments.
  • the nanowire transistor 400 includes a carrier 402, a vertical nanowire structure 404 extending from the carrier 402, the vertical nanowire structure 404 comprising a channel region 406, and the vertical nanowire structure 404 being made of the same material as the carrier 402, a gate insulator region 408 covering at least a portion of the vertical nanowire structure 404, and at least one gate region 410 covering at least a portion of the gate insulator region 408.
  • the carrier 402, the vertical nanowire structure 404 and the channel region 406 may form a continuous structure.
  • the gate insulator region 408 surrounds at least the portion of the vertical nanowire structure 404, and the at least one gate region 410 surrounds at least the portion of the gate insulator region 408.
  • FIG. 4B shows a schematic block diagram of a nanowire transistor 420, according to various embodiments.
  • the nanowire transistor 420 may include elements of the embodiment of the nanowire transistor 400 of FIG. 4A.
  • the nanowire transistor 420 may further include an insulator material 424 covering at least a portion of a base of the vertical nanowire structure 404.
  • the term "base” may mean a bottom part or a portion near the bottom part of the vertical nanowire structure 404, proximal to the carrier 402. In various embodiments, the same insulator may be used with the transistor 400.
  • the insulator material 424 may be an oxide or a nitride.
  • the oxide may be any oxide (e.g. silicon dioxide), for example deposited using plasma- enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) or high-density plasma (HDP).
  • PECVD plasma- enhanced chemical vapor deposition
  • LPCVD low-pressure chemical vapor deposition
  • HDP high-density plasma
  • the insulator material 424 may be a PECVD low-k dielectic layer such as black diamond, or a spin coat layer of a low-k dielectric such as silk.
  • the channel region 406 and the carrier 402 may be doped with doping atoms 426 of a conductivity type.
  • the channel region 406 and the carrier 402 may be doped with doping atoms 426 of the same conductivity type.
  • the nanowire transistor 420 may further include a first source/drain region 428 coupled to the channel region 406, and a second source/drain region 430 coupled to the carrier 402, wherein the first source/drain region 428 and the second source/drain region 430 are doped with doping atoms 426 of the same conductivity type as the channel region 406.
  • the carrier 402, the channel region 406, the first source/drain region 428 and the second source/drain region 430 may be doped with doping atoms 426 of the same conductivity type.
  • the first source/drain region 428 may be formed from a portion of the vertical nanowire structure 404, e.g. a top portion or a tip of the vertical nanowire structure 404, or the first source/drain region 428 may be part of the vertical nanowire structure 404, for example at a position distal from the carrier 402.
  • the second source/drain region 430 may be formed from a portion of the carrier 402, or the second source/drain region 430 may be part of the carrier 402. In various embodiments, the second source/drain region 430 may be formed from a portion of the vertical nanowire structure 404, or may be part of the vertical nanowire structure 404, for example at a position proximal to the carrier 402, for example at the base of the vertical nanowire structure 404.
  • the vertical nanowire structure 404, the channel region 406 and the first source/drain region 428 may form a continuous structure.
  • the carrier 402 and the second source/drain region 430 may form a continuous structure.
  • the carrier 402, the vertical nanowire structure 404, the channel region 406, the first source/drain region 428 and the second source/drain region 430 may form a continuous structure.
  • the nanowire transistor 420 may further include an isolation oxide 432 disposed between the at least one gate region 410 and at least one of the first source/drain region 428 and the second source/drain region 430.
  • the isolation oxide 432 may be a HDP, PECVD or LPCVD oxide.
  • the channel region 406 is free of a junction (i.e. the channel region 406 is not isolated from the first source/drain region 428 and the second source/drain region 430 with a respective junction), such as a p-n junction.
  • the gate insulator region 408 includes a gate oxide, such as silicon oxide.
  • Various embodiments may also provide a memory cell including a nanowire transistor of the embodiments of FIGS. 4A or 4B.
  • the memory cell may include a plurality of the nanowire transistors.
  • the data storage in the memory cell may be in the form of discrete change trapping inside the gate dielectric (e.g. the gate insulator material) or by incorporating a floating gate.
  • Various embodiments may further provide a memory device including a memory cell, the memory cell including one or more nanowire transistors of the embodiments of FIGS. 4A or 4B.
  • the memory device may include a plurality of memory cells. The plurality of memory cells may be formed on the same nanowire transistor.
  • FIG. 4C shows a schematic block diagram of a memory cell 440, according to various embodiments.
  • the memory cell 440 may include elements of the embodiments of the nanowire transistor 400 of FIG. 4A and/or the nanowire transistor 420 of FIG. 4B.
  • the gate insulator region 408 includes a first dielectric layer 442a configured to cover at least the portion of the vertical nanowire structure 404, a second dielectric layer 442b, and a third dielectric layer 442c, wherein the second dielectric layer 442b is disposed between the first dielectric layer 442a and the third dielectric layer 442c, and wherein a bandgap of the second dielectric layer 442b is smaller than a respective bandgap of the first dielectric layer 442a and the third dielectric layer 442c.
  • all of the first dielectric layer 442a, the second dielectric layer 442b, and the third dielectric layer 442c may not be of the same material.
  • the second dielectric layer 442b is of a material with a lower bandgap than the material of the first dielectric layer 442a and the third dielectric layer 442c in order to maintain the charges trapped inside the well of the gate insulator material created by the differences in the bandgaps among the three dielectric layers.
  • the first dielectric layer 442a and the third dielectric layer 442c may be of the same material.
  • each of the first dielectric layer 442a and the third dielectric layer 442c includes an oxide, for example silicon oxide (Si0 2 ), aluminium oxide (A1 2 0 3 ) or hafnium oxide (Hf0 2 ), or any high-k dielectric material.
  • oxide for example silicon oxide (Si0 2 ), aluminium oxide (A1 2 0 3 ) or hafnium oxide (Hf0 2 ), or any high-k dielectric material.
  • the second dielectric layer 442b includes a material selected from the group consisting of a nitride (e.g. silicon nitride), an oxide (e.g. aluminium oxide or hafnium oxide), polycrystalline silicon (i.e. polysilicon), amorphous silicon and a metal.
  • a nitride e.g. silicon nitride
  • an oxide e.g. aluminium oxide or hafnium oxide
  • polycrystalline silicon i.e. polysilicon
  • amorphous silicon a metal.
  • the second dielectric layer 442b may include any high-k dielectric material.
  • each of the first dielectric layer 442a, the second dielectric layer 442b and the third dielectric layer 442c are of high-k dielectric materials or only the second dielectric layer 442b is of a high-k dielectric material.
  • the memory cell 440 may be a floating gate memory.
  • the nitride dielectric layer may be configured to store charges and the memory cell 440 may be a non-volatile memory cell.
  • the second dielectric layer 442b may include nanocrystals, for example polysilicon nanocrystals, germanium nanocrystals or metal nanocrystals.
  • the entire second dielectric layer 442b may be made up of the nanocrystals or the second dielectric layer 442b may include the nanocrystals on a surface of the second dielectric layer 442b.
  • the second dielectric layer 442b may be used for discrete charge trapping and the memory cell 440 may be a nanocrystal memory.
  • Various embodiments may provide a memory device including a memory cell.
  • the memory cell may be of the embodiment of FIG. 4C.
  • the memory device may further include a nanowire transistor of the embodiments of FIG 4A or 4B, wherein the nanowire transistor may be configured to couple to the memory cell.
  • the memory cell and the nanowire transistor may be provided on the same level, for example side by side, on the same carrier, with their own respective vertical nanowire structure.
  • the memory cell and the nanowire transistor may be provided on one continuous vertical nanowire structure. In other words, the memory cell and the nanowire transistor may share one common continuous vertical nanowire structure.
  • the memory cell may be arranged over the nanowire transistor (e.g. in a vertical stack), and the respective vertical nanowire structure of the memory cell and the nanowire transistor is the same vertical nanowire structure (i.e. the memory cell and the nanowire transistor share one common continuous vertical nanowire structure), and the respective carrier of the memory cell and the nanowire transistor is the same carrier (i.e. the memory cell and the nanowire transistor are formed on a common carrier.
  • the respective vertical nanowire structure of the memory cell and the nanowire transistor is the same vertical nanowire structure (i.e. the memory cell and the nanowire transistor share one common continuous vertical nanowire structure)
  • the respective carrier of the memory cell and the nanowire transistor is the same carrier (i.e. the memory cell and the nanowire transistor are formed on a common carrier.
  • the memory device may include a second memory cell, wherein the memory cell and the second memory cell may be arranged one over the other on the same vertical nanowire structure, for example in a vertical stack.
  • the memory device may include a plurality of the memory cells, where at least two of the plurality of memory cells are arranged one over the other (e.g. in a vertical arrangement or a vertical stack). Therefore, various embodiments may provide a memory device including a vertical stack of memory cells of various embodiments.
  • the respective vertical nanowire structure of the at least two memory cells of the plurality of memory cells arranged one over the other may be a common continuous vertical nanowire structure. In other words, each vertical nanowire structure may form part of each of the memory cells in the stack arrangement, thereby providing a common continuous vertical nanowire structure through the stacked memory cells.
  • a memory cell is arranged over a nanowire transistor (e.g. in a stack arrangement) or where a further memory cell is arranged over a memory cell (e.g. two memory cells arranged in a vertical stack and arranged over the nanowire transistor (e.g. in a stack arrangement)
  • the memory cell or cells and the nanowire transistor share one common continuous vertical nanowire structure formed on a carrier.
  • the memory cell or cells are formed at an elevated position or positions from the surface of the carrier, and that the memory cell or cells may not have its respective separate carrier but share the same carrier as that of the nanowire transistor.
  • the memory cell may be a silicon-oxide- nitride-oxide-silicon (SONOS) memory cell and the memory device may be a SONOS memory device.
  • SONOS silicon-oxide- nitride-oxide-silicon
  • FIG. 5 shows a flow chart 500 illustrating a method for manufacturing a nanowire transistor, according to various embodiments.
  • material is removed from a carrier to form a vertical nanowire structure extending from the carrier.
  • the carrier may be etched to remove material from the carrier in order to form the vertical nanowire structure, such that the vertical nanowire structure is made of the same material as the carrier and that the carrier and the vertical nanowire structure may be a continuous structure.
  • At 504 at least a portion of the vertical nanowire structure is covered with a gate insulator material to form a gate insulator region. In various embodiments, at least the portion of the vertical nanowire structure is surrounded with the gate insulator material.
  • At 506 at least a portion of the gate insulator region is covered with a gate material to form at least one gate region. In various embodiments, at least the portion of the gate insulator region is surrounded with the gate material.
  • the method may further include covering at least a portion of a base of the vertical nanowire structure with an insulator material.
  • the insulator material may be an oxide or a nitride.
  • the oxide may be any oxide (e.g. silicon dioxide), for example deposited using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) or high- density plasma (HDP).
  • the insulator material may be a PECVD low-k dielectic layer such as black diamond, or a spin coat layer of a low-k dielectric such as silk.
  • the carrier may be doped with doping atoms of a conductivity type prior to removal of material from the carrier, such that the vertical nanowire structure formed extending from the carrier comprises a channel region, and the vertical nanowire structure being made of the same material as the carrier.
  • the method may further include forming a first source/drain region coupled - to the channel region, forming a second source/drain region coupled to the carrier, and doping the first source/drain region and the second source/drain region with doping atoms of the same conductivity type as the channel region.
  • the carrier may be doped to a particular doping depth in the carrier such that a top portion or region of the carrier is doped. Subsequently, material is removed from the carrier to form a vertical nanowire structure such that the length of the vertical nanowire structure is less than the doping depth so that the vertical nanowire structure has the same material with the doping atoms as that of the doped portion of the carrier.
  • the vertical nanowire structure and the carrier may be doped with doping atoms for forming a channel region in the vertical nanowire structure, a first source/drain region coupled to the channel region and a second source/drain region coupled to the carrier, wherein the doping atoms are of a conductivity type (e.g. p-conductivity type or n-conductivity type).
  • the vertical nanowire structure and the carrier are doped after the formation of the nanowire or the vertical nanowire structure.
  • an isolation oxide may be disposed between the at least one gate region and at least one of the first source/drain region and the second source/drain region.
  • the isolation oxide may be a HDP, PECVD or LPCVD oxide.
  • the method may be free of forming a junction in the channel region.
  • the method may be free of forming a junction between the channel region and the first source/drain region and the second source/drain region.
  • Various embodiments may provide a method for manufacturing a memory cell. The method may include the method for manufacturing a nanowire transistor as described above.
  • the method for manufacturing a memory cell may further include forming the gate insulator material, including forming a first dielectric layer to cover at least the portion of the vertical nanowire structure, forming a second dielectric layer, and forming a third dielectric layer, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer, and wherein a bandgap of the second dielectric layer is smaller than a respective bandgap of the first dielectric layer and the third dielectric layer.
  • Each of the first dielectric layer and the third dielectric layer may include an oxide, for example silicon oxide (Si0 2 ), aluminium oxide (A1 2 0 3 ) or hafnium oxide (Hf0 2 ) or any high-k dielectric material.
  • the second dielectric layer may include a material selected from the group consisting of a nitride (e.g. silicon nitride), an oxide (e.g. aluminium oxide or hafnium oxide), polycrystalline silicon (i.e. polysilicon), amorphous silicon and a metal.
  • the nitride dielectric layer may be configured to store charges.
  • the second dielectric layer may include any high-k dielectric material.
  • the method for manufacturing a memory cell may further include providing nanocrystals, for example silicon nanocrystals, germanium nanocrystals or metal nanocrystals, in the second dielectric layer.
  • nanocrystals for example silicon nanocrystals, germanium nanocrystals or metal nanocrystals
  • a reference to "a vertical nanowire structure” may include a reference to "a plurality of vertical nanowire structures".
  • Each vertical nanowire structure of the plurality of vertical nanowire structure may be of the embodiments of FIGS. 4A or 4B.
  • different vertical nanowire structures may be doped with doping atoms of different conductivity types. In other words, some vertical nanowire structures may be p-doped while other vertical nanowire structures may be n-doped.
  • junction-less and “free of a junction” with respect to a device may mean that the device does not include a physical junction or a chemical junction, for example such as a p-n junction, between the source/drain and channel, as at least substantially the entire nanowire is doped with doping atoms of the same conductivity type.
  • channel region may mean a channel or a conduction path, for example for the flow of electrons.
  • the vertical nanowire structure under the gate may be the channel region, thereby providing a volumetric channel region.
  • the vertical nanowire structure may have a diameter in a range of between about 10 nm to about 200 nm, for example between about 50 nm to about 150 nm, between about 80 nm to about 120 nm, or between about 10 nm to about 100 nm.
  • the three dielectric layers of the gate insulator material at the gate insulator region may be an oxide-nitride-oxide (ONO) stack or arrangement.
  • ONO oxide-nitride-oxide
  • source/drain region may mean a region which may be interchangeably configured as a source or a drain.
  • the source/drain region may be configured as a source or a drain, depending on the need in a circuit or in an application.
  • the doping atoms may be of a p-conductivity type such that a material doped with such doping atoms may be p-doped or the doping atoms may be an n-conductivity type such that a material doped with such doping atoms may be n-doped.
  • p-doped may mean a host material that is doped with doping atoms that may accept weakly-bound outer electrons from the host material, thereby creating vacancies left behind by the electrons, known as holes. Such doping atoms are also generally referred to as acceptor atoms.
  • n-doped may mean a host material that is doped with doping atoms that may provide extra conduction electrons to the host material, thereby resulting in an electrically conductive n-doped host material with an excess number of mobile electrons (negatively charged carriers).
  • doping atoms are also generally referred to as donor atoms.
  • the host material may be doped or implanted with Group III doping atoms or elements, for example boron (B), aluminium (Al) or gallium (Ga), to form a p-doped material, or doped or implanted with Group V doping atoms or elements, for example phosphorus (P), arsenic (As) or antimony (Sb), to form an n-doped material.
  • Group III doping atoms or elements for example boron (B), aluminium (Al) or gallium (Ga)
  • Group V doping atoms or elements for example phosphorus (P), arsenic (As) or antimony (Sb), to form an n-doped material.
  • doping may be carried out with a dopant concentration of between about 1 10 /cm " to about 5 x 10 /cm " .
  • the at least one gate region may include a plurality of gate regions.
  • a plurality of gate regions may be provided along the length or longitudinal axis of the vertical nanowire structure,
  • the plurality of gate regions may provide a plurality of cells (e.g. memory cells), enabling storage of multiple data bits for the foot print of one transistor.
  • the carrier may include a semiconductor.
  • the carrier may be a planar semiconductor layer.
  • the semiconductor may be silicon or germanium.
  • the carrier may be a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the germanium carrier may be disposed over a substrate, wherein the substrate comprises silicon.
  • the germanium carrier may be a layer of germanium on the substrate.
  • the vertical nanowire structure is made of the same material as the carrier.
  • the vertical nanowire structure may be made of the same material as the top surface or portion (e.g. a thickness of a few micron or less, e.g. ⁇ 5 ⁇ ) of the carrier.
  • the top surface or portion of the carrier may be p-doped or n-doped, for fabricating CMOS devices, or the top surface or portion of the carrier may include a layer of material disposed on the carrier, for example a layer of high mobility material such as germanium, on silicon.
  • the nanowire transistor may be a field effect transistor, such as a metal semiconductor field effect transistor (MESFET), a metal oxide, semiconductor field effect transistor (MOSFET) or a metal insulator semiconductor field effect transistor (MISFET).
  • MOSFET metal semiconductor field effect transistor
  • MOSFET metal oxide, semiconductor field effect transistor
  • MISFET metal insulator semiconductor field effect transistor
  • doping with doping atoms of the p-conductivity type may provide a p-channel MOSFET (PMOS FET) while doping with doping atoms of the n-conductivity type may provide a n-channel MOSFET (NMOS FET).
  • PMOS FET p-channel MOSFET
  • NMOS FET n-channel MOSFET
  • FIG. 6 shows a schematic cross sectional view of a nanowire transistor 600, according to various embodiments.
  • the nanowire transistor 600 includes a carrier 602, which may be part of a wafer (e.g. silicon wafer) 604.
  • the carrier 602 may be doped with doping atoms of n-conductivity type or p-conductivity type.
  • the nanowire transistor 600 includes a vertical nanowire structure 606 extending from the carrier 602, the vertical nanowire structure 606 being made of the same material as the carrier 602.
  • the vertical nanowire structure 606 and the carrier 602 may be a continuous structure, for example the vertical nanowire structure 606 may be etched from the carrier 602.
  • the vertical nanowire structure 606 includes a channel region 608, which may be doped with doping atoms of the same conductivity type as that of the carrier 602.
  • the nanowire transistor 600 includes a gate insulator region 610 covering at least a portion of the vertical nanowire structure 606, and a gate region 612 covering at least a portion of the gate insulator region 610.
  • the nanowire transistor 600 includes a source/drain region, for example as represented by the square box 614a, and another source/drain region, for example as represented by the square box 614b.
  • the source/drain region 614a is coupled to the channel region 608, while the source/drain region 614b is coupled to the carrier 602 and the channel region 608.
  • the source/drain regions 614a, 614b may be provided at other locations on the nanowire transistor 600.
  • the nanowire transistor 600 is a junction-less (i.e. free of a juntion) device as there is no junction (e.g. p-n junction) formed between the source/drain regions 614a, 614b, and the channel region 608, in comparison to the prior art of FIGS. 3A to 3C.
  • the nanowire transistor 600 is junction-less as the whole nanowire structure 606 has the same conductivity type doping. Fabrication and experimental data
  • FIG. 7 shows a schematic cross-sectional view of a fabrication process 700 for manufacturing a nanowire transistor, according to various embodiments.
  • FIG. 8 shows SEM images of structures formed during a fabrication process for manufacturing a nanowire transistor, according to various embodiments. The SEM images of FIG. 8 are obtained using a tilted top view SEM. For illustration and clarity purposes, only one vertical nanowire structure is shown in FIGS. 7 and 8.
  • the nanowire transistor (e.g. a junction-less GAA-vertical nanowire NMOS transistor) may be fabricated on a bulk silicon wafer (e.g. polycrystalline silicon). Wafers with a layer of approximately 50 A screening oxide may be used.
  • the silicon wafer is implanted with phosphorous (P) to form n-doped silicon (e.g. n+ silicon) and annealed to achieve various uniform doping concentration of aprroximately 1 x 10 cm " to approximately 5x 10 cm " over the silicon wafer.
  • the doping process produces a deep and uniform doped region, including source/drain doping.
  • a structure 701 may be obtained, including an undoped silicon wafer 702 and an n-doped silicon region (n+ Si) 704.
  • the concentration of the dopants may be varied with the nanowire diameter or to adjust the threshold voltage.
  • the implantation process may be optional.
  • a layer of silicon nitride (Si 3 N 4 ) or silicon oxide (Si0 2 ), acting as a hard mask, may be optionally deposited on the structure 701.
  • Circular resist patterns having diameters substantially similar or bigger than the required wire diameter may be patterned on the hard mask layer.
  • the resist circular patterns or dots may be subsequently trimmed to the required diameters, for example about 50 nm to about 100 nm.
  • Plasma dry-etch may be carried out to etch the hard mask layer and the underlying doped silicon, thereby transferring the resist patterns to the underlying silicon, to form silicon pillars.
  • different etching processes may be used, for example a C 4 F + SF 6 based etch for silicon.
  • the critical dimensions used for the mask may be about 200 nm, for patterning a dot/pillar on the wafer which may then be transformed into nanowire through etching and oxidation.
  • FIG. 8 shows an SEM image 800 of a silicon pillar 801. Part of the hard mask layer 802 may be observed at the tip of the silicon pillar 801.
  • Sacrificial oxidation at high temperature for example between about 800°C to about 1100°C
  • silicon oxide (Si0 2 ) may be carried out to reduce the roughness of the pillar sidewalls as well as to reduce the diameters of the silicon pillars in order to form nanowires.
  • the sacrificial oxide is removed by a wet etch process, and vertical nanowires with diameters of approximately 20 to 40 nm may be obtained.
  • the final wire diameter depends on the thickness of the sacrificial oxide along with the wire diameter before oxidation.
  • a structure 706 may be obtained, including a silicon nanowire 708, dry-etched and formed from the n-doped silicon region 704.
  • FIG. 8 shows an SEM image 804 of a silicon nanowire 806 formed, after removal of the sacrificial oxide.
  • a high density plasma (HDP) oxide e.g. silicon oxide
  • PECVD oxide having poor conformality may be deposited, followed by a wet etch-back to form an isolation layer.
  • the oxide isolation layer provides a separation between the gate and source.
  • the isolation oxide may also be formed with any thick oxide deposition, that is thicker than the nanowire height, and then polishing using, for example, chemical mechanical polish process, and then etch back in a dry plasma or a wet solution such as diluted hydrofluoric acid (DHF) or buffered oxide etch (BOE).
  • DHF diluted hydrofluoric acid
  • BOE buffered oxide etch
  • a 45 A thick gate oxide is grown on the sidewall of the silicon nanowires, followed by a deposition of approximately 50 nm of amorphous silicon (a- silicon or a-silicon) via low pressure chemical vapor deposition (LPCVD).
  • LPCVD low pressure chemical vapor deposition
  • a dry oxidation process at about 850°C may be performed to grow the gate oxide.
  • deposited oxides such as Si0 2 or any high-k dielectrics may be used.
  • the deposited amorphous silicon may be implanted with boron (B) to form a gate electrode.
  • B boron
  • the nanowires, the gate oxide and the amorphous silicon form a gate stack.
  • polycrystalline silicon poly-silicon
  • a structure 710 may be obtained, including a layer of HDP oxide 712, a layer of gate oxide 714 and a layer of amorphous silicon 716 (gate electrode).
  • FIG. 8 shows an SEM image 808 of a silicon nanowire 806 and a layer of HDP oxide 810, exposing the upper portion of the nanowire 806.
  • doping of the deposited amorphous silicon 716 may be optional.
  • a gate definition process is then carried out, which may include removal of parts of the gate oxide 714 and the amorphous silicon 716 of the gate stack to define a gate pad, and deposition of HDP oxide and wet etching of the deposited HDP oxide to expose the top portion or cap of the amorphous silicon 716 to define the gate length. In further embodiments, this process may be achieved by deposition of a thick gate dielectric, followed by polishing and an etch back process.
  • a structure 718 may be obtained, including a gate pad 719 and a layer of HDP oxide 720, which has been etched back to expose the top portion of the amorphous silicon 716.
  • FIG. 8 shows an SEM image 812 of a gate stack 813 covered with a gate oxide and amorphous silicon, and a gate pad 814, after a gate-etch.
  • FIG. 8 also shows an SEM image 816 of a HDP oxide 818 and an exposed top portion of the gate stack 813 (e.g. the gate tip), after etch-back of the deposited HDP oxide.
  • the exposed top portion of the amorphous silicon 716 may be subsequently wet etched in a tetramethylammonium hydroxide (TMAH) solution or etched using a dry isotropic etch process, e.g. in a SF 6 based plasma, and the underlying gate oxide is also etched to expose the underlying tip of the silicon nanowire 708.
  • TMAH tetramethylammonium hydroxide
  • the gate oxide may be etched in DHF solution or using a dry etch process. In embodiments where a dry etch process is used, the gate oxide may be etched during the gate-etch, due to limited selectivity of different materials and the gate oxide being thin.
  • the polysilicon may be etched using a dry isotropic etch process, e.g. in a SF 6 based plasma.
  • a structure 722 may be obtained, showing the exposed tip of the silicon nanowire 708.
  • FIG. 8 shows an SEM image 820 of the exposed tip of the nanowire 806, after etching of the exposed gate stack tip.
  • a spacer such as a silicon nitride (S13N4) spacer or a silicon oxide (Si0 2 ) spacer, may be deposited on the sidewall of the exposed tip of the nanowire 708 of the structure 722 to provide isolation.
  • a spacer such as a silicon nitride (S13N4) spacer or a silicon oxide (Si0 2 ) spacer, may be deposited on the sidewall of the exposed tip of the nanowire 708 of the structure 722 to provide isolation.
  • a pre-metal dielectric layer e.g. undoped silicon glass (USG), HDP oxide
  • USG undoped silicon glass
  • HDP oxide high-density polysilicon
  • the pre-metal dielectric layer provides a separation between the gate and drain.
  • Contact holes are then etched for the gate and source (which is coupled to the base of the nanowire 708), followed by metallization, for example using tantalum nitride/aluminium/tantalum nitride (TaN/Al/TaN), tungsten (W) or copper (Cu), for filling the contact holes and forming contacts.
  • Metal etch may be performed to define different contacts.
  • a structure 724 may be obtained, including a gate contact 726, a drain contact 728 and a source contact 730.
  • FIG. 8 shows an SEM image 822 of metal contacts after a metal etch. Three metal contacts are formed, including a gate contact 824, a drain contact 826 and a source contact 828. It should be appreciated that the drain contacts 728, 826 and the source contacts 730, 828 may be interchangeable (e.g. the contact labelled as 826 may be the source contact while the contact labelled as 828 may be the drain contact), depending on the need in the circuit or device.
  • FIG. 9 shows a TEM image 900 of an NMOS transistor, according to various embodiments.
  • the inset shows a close-up image 902 of the nanowire channel 904.
  • the diameter of the nanowire channel 904 is about 20 nm. However, it should be appreciated that other diameters may be formed.
  • FIG. 10A shows a plot 1000 of drain current-gate voltage (Id-V g ) transfer characteristics of a nanowire transistor, for different drain voltages (V d ), according to various embodiments.
  • FIG. 10A shows the results for a drain voltage at about 0.05 V (as represented by 1002a) for a nanowire transistor, and for drain voltages at about 0.05 V (as represented by 1002b) and at about 1.2 V (as represented by 1004) for a nanowire transistor.
  • Schottky contact like behaviour is observed from the results 1002a, which may be resolved or alleviated by, for example, increasing the doping at the nanowire tip or siliciding the tip.
  • the results shown in FIG. 10A show that the fabricated vertical junction-less nanowire transistor of various embodiments exhibit an ON/OFF ratio of approximately 10 , a sub-threshold slope (SS) of approximately 65 mV/dec and a drain induced barrier lowering (DIBL) of approximately 0 mV/V.
  • SS sub-threshold slope
  • DIBL drain induced barrier lowering
  • FIG. 10B shows a plot 1010 of drain current-drain voltage (I d -V d ) output characteristics of a nanowire transistor, for different gate voltages (V g ), according to various embodiments.
  • the results of FIG. 10B are obtained for a gate length (Lg) of approximately 150 nm.
  • FIG. 10B shows the results for gate voltages at 0 V(as represented by 1012), at about 0.5 V (as represented by 1014), at about 1.5 V (as represented by 1016) and at about 2.0 V (as represented by 1018).
  • the results shown in FIG. 10B show a relatively slow turn-on in the I d -V d characteristics due to Schottky barrier formation with the metal contacts.
  • the turn-on may be improved by increasing the doping level at the ends of the nanowires and/or silicide the ends of the nanowires with a low barrier height metal.
  • the fabrication process for manufacturing a vertical silicon nanowire (SiNW) based junction-less (JL) SONOS memory cell of various embodiments is now described. Reference is made to FIGS. 7 and 8 for illustration and understanding purposes.
  • the fabrication process of the SONOS memory cell are similar to the fabrication process of the nanowire transistor of various embodiments as described above, except for the gate dielectric.
  • the SONOS gate dielectric may include an oxide- nitride-oxide (ONO) stack while the nanowire transistor includes an oxide or includes only an oxide.
  • both the nanowire based junction-less SONOS memory cell and the nanowire transistor may be provided or formed side by side or on the same vertical nanowire structure.
  • the nanowire transistor may be provided on a 1 st level and the memory cell may be provided on a 2° level and other higher level or both the nanowire transistor and the memory may be provided on the same level, depending on the design and applications.
  • An implantation process is carried out at an energy of approximately 170 keV with various dopant concentrations of phosphorous (P) (e.g. P + -doped or heavily doped with P) on a wafer (e.g. silicon wafer), followed by an annealing process in a furnace at about 1000°C for about 3 hours, in order to form a uniform dopant profile in a portion of the wafer to form n-doped silicon (e.g. n+ silicon).
  • P phosphorous
  • n-doped silicon e.g. n+ silicon
  • a top-down approach may then be used to form vertical silicon nanowires of various diameters, with downscaling of the diameters to approximately 20 nm.
  • a similar process for forming vertical silicon nanowires in the context of the nanowire transistor as described with reference to FIGS. 7 and 8 may be used.
  • a structure similar to structure 706 of FIG. 7 and also as shown in the SEM image 804 of FIG. 8 may be obtained.
  • a high density plasma (HDP) oxide e.g. silicon oxide
  • any non-conformal oxide or any low dielectric constant (i.e. low-k) materials may then be deposited, followed by a wet etch-back to form an isolation layer.
  • planarization, followed by etch back may also be used as to create such isolation.
  • an oxide-nitride-oxide (ONO) stack may be formed directly on the silicon nanowires to at least substantially cover or surround the silicon nanowires.
  • the ONO stack may include a tunneling thermal oxide (e.g. silicon oxide) with a thickness of approximately 5 nm, a trapping layer of LPCVD silicon nitride with a thickness of approximately 7nm (i.e. the silicon nitride is formed via low pressure chemical vapor deposition (LPCVD)), and a blocking LPCVD oxide (e.g. silicon oxide) with a thickness of approximately 7 nm.
  • the layer of tunneling thermal oxide is formed on the sidewalls of the silicon nanowires, followed by the layer of silicon nitride and the layer of blocking oxide.
  • LPCVD poly-silicon as control gate may be deposited, followed by phosphorus (P) (e.g. P + -doped or heavily doped with P) implantation and activation.
  • P phosphorus
  • the gate stack including the nanowire, the ONO stack and the poly-silicon may be patterned and etched to define a gate pad.
  • a HDP oxide may then be deposited and wet etched-back to define the gate length.
  • a structure similar to structure 718 of FIG. 7 and also as shown in the SEM image 812 of FIG. 8 may be obtained. Based on the structure 718 of FIG. 7, the ONO stack may be represented as 714 and the poly-silicon may be represented as 716.
  • the exposed tip of the gate stack may then be processed to remove the poly-Si in a TMAH solution and the ONO stack in a HF/H3PO4 solution.
  • a structure similar to structure 722 of FIG. 7 and also as shown in the SEM image 820 of FIG. 8 may be obtained.
  • deposition of a HDP oxide and etch-back may be performed to create gate to drain isolation and to expose the tip of the nanowire.
  • Contact holes to the gate pad and source (which is coupled to the base of the nanowire) are created, for example via etching, and metallisation of TaN/Al/TaN is performed to form metal contacts. Alloy annealing at about 420°C in about 10% hydrogen (H 2 ) may be performed.
  • a structure similar to structure 724 of FIG. 7 and also as shown in the SEM image 822 of FIG. 8 may be obtained.
  • JL-SONOS junction-less SONOS
  • FIGS. 11A and 1 1B show cross-sectional transmission electron microscope (TEM) images 1100 and 1120 respectively of a vertical silicon nanowire gate-all-around junction-less SONOS 1101 and an oxide-nitride-oxide (ONO) gate stack 1 122.
  • TEM transmission electron microscope
  • the SONOS 1101 includes a nanowire 1102 with a diameter of about 20 nm and a gate length of about 120 nm.
  • the SONOS 1101 also includes a gate 1104, a source 1106 and a drain 1108.
  • the inset shows a close-up image 1110 of the nanowire channel 1112.
  • the well-defined ONO stack 1122 has a stack of thermal oxide 1124 / nitride 1126 / blocking oxide 1128, with a dimension of about 5 nm/7 nm/7 nm.
  • the thermal oxide 1124 is provided on the sidewall of the silicon nanowire 1130, with the silicon nanowire 1130 heavily-doped with a doping concentration of approximately lxl0 19 /cm "3 .
  • the TEM image 1102 also shows a layer of polysilicon 1132.
  • FIGS 1 1A and 1 IB illustrate an embodiment that may be provided, other embodiments with different parameters or dimensions, for example the dimensions of the nanowire diameter, gate length and the ONO stack and the doping concentration of the nanowire, may be provided.
  • FIG. 12 shows a plot 1200 of drain current-gate voltage (I d -V g ) characteristics of a junction-less SONOS (as represented by 1202) of various embodiments and a junction- based SONOS (as represented by 1204).
  • the Id-V g characteristics of the junction-less SONOS 1202 and the junction-based SONOS 1204 are obtained for a nanowire diameter of about 20 nm.
  • the channel doping for the junction-less SONOS is approximately 1 x 10 19 /cm "3 . It should be appreciated that in various embodiments, the channel doping for a junction-less SONOS may be varied from about 1 x 10 17 /cm "3 to about 5 x 10 20 /cm "3 .
  • the JL-SONOS shows comparable I d -V g characteristics (switching function) to the junction-based SONOS, with a turn-off current (I 0ff ) down to approximately 1 x 10 "14 A. This may be attributed to the highly scaled wire channel and therefore better gate control owing to the GAA structure. Therefore, when a negative bias is applied on the channel, the channel electrons may be fully-depleted and the device may be at least substantially completely turned off.
  • FIG. 13 shows a plot 1300 of drain current-gate voltage (I d -V g ) characteristics of junction-less SONOS with different nanowire diameters, according to various embodiments.
  • the I d -V g characteristics are obtained for junction-less SONOS with a channel doping concentration of approximately 1 x 10 19 /cm "3 , for nanowire diameters of about 20 nm, about 40 nm, about 50 nm and about 110 nm, with the arrow 1302 showing the results in the direction of increasing nanowire diameter.
  • the channel electrons may be more difficult to be completely depleted and the body effect may increase the I 0ff .
  • FIG. 14 shows a plot 1400 of drain current-gate voltage (I d -V g ) characteristics of junction-less SONOS with different channel doping concentrations, according to various embodiments.
  • the I d -V g characteristics are obtained for junction-less SONOS with a nanowire diameter of about 20 nm, for channel doping concentrations of approximately 1 x 10 17 /cm "3 (as represented by 1402) and approximately 1 x 10 19 /cm "3 (as represented by 1404). While a more negative V g may be needed for full depletion, the junction-less SONOS with heavily doped (i.e. 1 x 10 19 /cm "3 ) channel exhibits a higher I on /I 0ff ratio due to its higher channel conductivity in the normally-on mode, and therefore a much higher [0176] FIG.
  • FIG. 15 shows plots 1500, 1502 of simulated electric field distributions of junction-less SONOS for different nanowire diameters, according to various embodiments.
  • the simulated electric field distributions are obtained for the silicon nanowire channel and ONO stack at V g of about 4.5 V and a channel doping concentration of approximately 1 x 10 19 /cm ⁇ 3 , for nanowire diameters of about 20 nm and about 40 nm.
  • FIG. 16 shows plots 1600, 1602 of simulated electric field distributions of junction-less SONOS for different channel doping concentrations, according to various embodiments.
  • the simulated electric field distributions are obtained for the silicon nanowire channel and ONO stack at V g of about 4.5 V and a nanowire diameter of about 20 nm, for channel doping concentrations of approximately 1 x 10 I7 /cm "3 and approximately 1 x 10 19 /cm "3 .
  • FIGS. 15 and 16 show increased fields for junction-less SONOS with a smaller diameter and a heavily doped channel, which may lead to improved programming at low gate voltages.
  • FIGS. 17A to 17C and 18A to 18C show the programming/erasing (P/E) characteristics of junction-less SONOS (JL-SONOS) and junction-based SONOS with different channel doping concentrations.
  • JL-SONOS may be programmed and erased using Fowler-Nordheim (FN) tunneling with a pulse applied on the gate, with the source and drain grounded.
  • FN Fowler-Nordheim
  • FIGS. 17A and 17B show plots 1700, 1704 of programming characteristics of junction-less SONOS memory cells for different gate voltages, according to various embodiments, while FIG. 17C shows a plot 1708 of programming characteristics of a junction-based SONOS memory cell for different gate voltages.
  • the programming characteristics shown in FIGS. 17A and 17B for the junction- less SONOS memory cells are obtained for channel doping concentrations of approximately 1 x 10 17 /cm "3 and approximately 1 x 10 I9 /cm "3 respectively.
  • the programming characteristics shown in FIG. 17C are obtained for a junction-based SONOS memory cell with an undoped channel.
  • the programming characteristics shown in FIGS. 17A to 17C are obtained for a nanowire diameter of about 20 nm.
  • FIGS. 17A and 17B are obtained for gate voltages of about 12 V, about 13 V, about 14 V, about 15 V and about 18 V, with the arrows 1702 (FIG. 17A) and 1706 (FIG. 17B) showing the results in the direction of increasing voltage.
  • FIG. 17C are obtained for gate voltages of about 12 V, about 14 V, about 15 V, about 16V and about 18 V, with the arrow 1710 showing the results in the direction of increasing voltage.
  • FIGS. 18A and 18B show plots 1800, 1804 of erasing characteristics of junction- less SONOS memory cells for different gate voltages, according to various embodiments, while FIG. 18C shows a plot 1808 of erasing characteristics of a junction-based SONOS memory cell for different gate voltages.
  • the erasing characteristics shown in FIGS. 18A and 18B for the junction-less SONOS memory cells are obtained for channel doping concentrations of approximately 1 x 10 17 /cm "3 and approximately 1 x 10 19 /cm "3 respectively.
  • the erasing characteristics shown in FIG. 18C are obtained for a junction-based SONOS memory cell with an undoped channel.
  • the erasing characteristics shown in FIGS. 18A to 18C are obtained for a nanowire diameter of about 20 nm.
  • the erasing characteristics shown in FIGS. 18A and 18B are obtained for gate voltages of about -12 V, about -13 V, about -14 V, about -15 V and about -18 V, with the arrows 1802 (FIG. 18 A) and 1806 (FIG. 18B) showing the results in the direction of increasing negative voltage.
  • the erasing characteristics shown in FIG. 18C are obtained for gate voltages of about -12 V, about -14 V, about -15 V, about -16V and about -18 V, with the arrow 1810 showing the results in the direction of increasing negative voltage.
  • FIGS. 18A to 18C A comparison between the P/E speed characteristics for the junction-based SONOS and JL-SONOS show that memory cells or devices with lower channel doping concentrations exhibit faster erase speed, as shown in FIGS. 18A to 18C.
  • SONOS relies mainly on the hole injection from the channel for erasing, n-type doped channel may make hole tunnelling more difficult due to the increased barrier height for holes.
  • FIG. 19 shows a plot 1900 of programming/erasing (P/E) speed of junction-less SONOS memory cells for different nanowire diameters, according to various embodiments.
  • the results obtained are shown in terms of a threshold voltage shift ( ⁇ ) at a program (PGM) voltage of about 15 V and an erase (ERS) voltage of about - 15V for junction-less SONOS with a channel doping concentration of about 1 x 10 19 /cm "3 , for nanowire diameters of about 20 nm and about 40 nm.
  • PGM program
  • ERS erase
  • junction-less SONOS memory cells with a smaller nanowire diameter exhibit faster programming and erasing speeds, as a result of enhanced electric field in the tunnel oxide layer and reduced electric field in the blocking oxide of the ONO stack, due to the reduced curvatures of the nanowire.
  • FIG. 20 shows a plot 2000 of multi-bit programming characteristics of a junction- less SONOS memory cell, according to various embodiments. The results are obtained for a junction-less SONOS memory cell with a nanowire diameter of about 20 nm and a channel doping concentration of approximately 1 x 10 19 /cm "3 , for different gate bias voltages of about 13 V, about 14 V and about 18 V for about 1 ms. As shown in FIG.
  • the junction-less SONOS memory cell is able to store 2 bits per cell using four states “00" (erase), "01” (program gate bias voltage of about 13 V), “10” (program gate bias voltage of about 14 V) and “1 1” (program gate bias voltage of about 18 V) with each state defined at a different transistor threshold voltage, V t , of greater than 1 V (i.e. > 1 V).
  • FIG. 21 A shows a plot 2100 of retention characteristics at 85°C for junction-less SONOS memory cells of various embodiments and a junction-based SONOS memory cell.
  • the high temperature retention characteristics shown in FIG. 21 A show that the heavily-doped junction-less SONOS memory cells with a channel doping concentration of about 1 x 10 19 /cm "3 exhibit less voltage shift (AV th ) as compared to lightly doped junction-less SONOS memory cells with a channel doping concentration of about
  • FIG. 21 A shows that the memory window may be maintained for up to 10 5 seconds.
  • FIG. 21B shows a plot 2120 of endurance characteristics at 85°C for junction- less SONOS memory cells of various embodiments and a junction-based SONOS memory cell.
  • the endurance characteristics (cycling characteristics) shown in FIG. 2 IB show that the junction-less SONOS memory cells with different channel doping concentrations of about 1 x 10 17 /cm "3 and about 1 x 10 19 /cm "3 or the junction-based SONOS with an undoped channel are able to maintain the P/E window even after 10 4 cycles at about 85°C.
  • FIG. 22A shows a schematic cross-sectional view of a 3-D memory device 2200 based on vertical junction-less silicon nanowire SONOS memory cells, according to various embodiments.
  • the 3-D memory device 2200 is a 3-D multi-level stacked NAND structure using the junction-less SONOS as the building blocks. As there is no junction for both the selection gate transistors and memory cells, the integration process may be simplified.
  • the 3-D memory device 2200 includes a plurality of memory cells, for example as represented by 2202a and 2202b for two memory cells, arranged in a vertical stack.
  • the 3-D memory device 2100 further includes a plurality of vertical nanowire structures, for example as represented by 2204a and 2204b for two vertical nanowire structures.
  • each of the vertical nanowire structures 2204a and 2204b is provided for the plurality of memory cells 2202a and 2202b, such that continuous vertical nanowire structures 2204a and 2204b are provided through the stacked memory cells 2202a and 2202b of the 3-D memory device 2200.
  • the 3-D memory device 2200 may further include a plurality of bit lines (BL) 2206, based on the plurality of vertical nanowire structures 2204a and 2204b, a plurality of control gates (CG) 2208, an upper select gate (USG) 2210, a lower select gate (LSG) 2212 and a select line (SL) 2214.
  • BL bit lines
  • CG control gates
  • USG upper select gate
  • LSG lower select gate
  • SL select line
  • FIG. 22B shows a schematic of an equivalent circuit 2240 for the embodiment of FIG. 22A.
  • Features in the equivalent circuit 2240 of FIG. 22B that are equivalent to that of the 3-D memory device 2200 of FIG. 22 A are denoted with the same reference numbers.

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Abstract

La présente invention concerne un transistor à nanofils qui comprend un support, une structure de nanofils verticaux s'étendant depuis le support, ladite structure comprenant une région de canal et étant constituée du même matériau que le support, une région d'isolant de grille recouvrant au moins une partie de la structure de nanofils verticaux, et au moins une région de grille recouvrant au moins une partie de la région d'isolant de grille. Dans divers modes de réalisation, il n'y a pas de jonction dopée entre la région de canal et les régions de source/drain du transistor à nanofils.
PCT/SG2011/000222 2010-06-25 2011-06-22 Transistor à nanofils et son procédé de fabrication WO2011162725A1 (fr)

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