WO2011131143A1 - 阵列基板及其制造方法和液晶显示器 - Google Patents

阵列基板及其制造方法和液晶显示器 Download PDF

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Publication number
WO2011131143A1
WO2011131143A1 PCT/CN2011/073157 CN2011073157W WO2011131143A1 WO 2011131143 A1 WO2011131143 A1 WO 2011131143A1 CN 2011073157 W CN2011073157 W CN 2011073157W WO 2011131143 A1 WO2011131143 A1 WO 2011131143A1
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Prior art keywords
electrode
line
additional
common electrode
gate
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PCT/CN2011/073157
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English (en)
French (fr)
Inventor
谢振宇
陈旭
龙春平
徐少颖
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北京京东方光电科技有限公司
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Priority to US13/380,989 priority Critical patent/US9753335B2/en
Publication of WO2011131143A1 publication Critical patent/WO2011131143A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a liquid crystal display. Background technique
  • a liquid crystal display is a commonly used flat panel display, and a Thin Film Transistor Liquid Crystal Display (TFT-LCD) is a mainstream product in a liquid crystal display.
  • the liquid crystal panel is an important component in the TFT-LCD, and generally includes an array substrate and a color filter substrate provided to the cartridge with a liquid crystal layer interposed therebetween.
  • FIG. 1A is a partial top plan view of a conventional array substrate
  • FIG. 1B is a side cross-sectional view taken along line A-A of FIG. 1A.
  • the array substrate includes a base substrate 1; the base substrate 1 is formed with data lines 5 and gate lines 2 crossing each other; and the data lines 5 and the gate lines 2 are arranged to form pixels arranged in a matrix form.
  • Each of the pixel units includes a TFT switch and a pixel electrode 11;
  • the TFT switch includes a gate electrode 3, a source electrode 7, a drain electrode 8 and an active layer 61;
  • the gate electrode 3 is connected to the gate line 2, and the source electrode 7 is connected to the data line 5,
  • the drain electrode 8 is connected to the pixel electrode 11, and the active layer 61 is formed between the source electrode 7 and the drain electrode 8 and the gate electrode 3.
  • the data line 5, the gate line 2, the gate electrode 3 of the TFT switch, the source electrode 7, the drain electrode 8, the active layer 61, and the pixel electrode 11 may be collectively referred to as a conductive pattern.
  • the conductive patterns disposed in the same layer may be realized by a space arrangement, and the conductive patterns disposed in the different layers may be realized by spacing the insulating layers sandwiched therebetween. Further, the conductive patterns provided in the different layers may be electrically connected to each other by the via holes passing through the insulating layers therebetween.
  • the image signal voltage is input to the pixel electrode through the data line through the TFT switch. Since the pixel electrode is required to maintain the image signal voltage in a display period of one frame, a storage capacitor (Cs) is required to be formed in each pixel unit to maintain the image signal voltage on the pixel electrode.
  • a storage capacitor There are mainly two ways of forming a storage capacitor in the prior art, and one method is called a gate line based storage capacitor (Cs on Gate), and its structure is as shown in Figs. 1A and 1B.
  • the pixel electrode 11 in each pixel unit extends to the gate line 2 of the adjacent pixel unit, and the overlapping portion of the pixel electrode 11 and the adjacent gate line 2 forms a storage capacitor.
  • the array substrate further includes a common electrode line 12 which is formed in the same layer as the gate line 2 but does not intersect, and a portion where the pixel electrode 11 overlaps with the common electrode line 12 forms a storage capacitor.
  • the common electrode line 12 and the ohmic contact layer 62 formed over the active layer 61 to reduce the active layer 61 and the source. Contact resistance between the electrode 7 and the drain electrode 8.
  • An embodiment of the present invention provides an array substrate, including: a substrate substrate; data lines and gate lines crossing each other formed on the substrate, wherein the data lines and the gate lines are surrounded by a matrix Formally arranged pixel units, each pixel unit comprising a thin film transistor (TFT) switch and a pixel electrode; a common electrode line formed on the base substrate; and the additional electrode formed over the gate line, wherein The additional electrode and the gate line are spaced apart from each other by a gate insulating layer, and the additional electrode is electrically connected to the common electrode line; wherein the pixel electrode extends to the upper side of the additional electrode with a passivation layer Overlapped with the additional electrode, the pixel electrode overlaps the additional electrode and the common electrode line to form a storage capacitor.
  • TFT thin film transistor
  • Another embodiment of the present invention provides a method of fabricating an array substrate, including the steps of respectively forming a gate line, a common electrode line, a data line, a thin film transistor (TFT) switch, and a pixel electrode on a base substrate, the gate line And the data lines intersect to form pixel units arranged in a matrix form, each of the pixel units including a TFT switch and a pixel electrode, wherein an additional electrode is formed while forming the data line, so that the additional electrode is located at the Above the gate line, the additional electrode and the gate line are spaced apart from each other by a gate insulating layer, and the additional electrode is electrically connected to the common electrode line; the pixel electrode extends above the additional electrode and The additional electrodes overlap, and the pixel electrode overlaps the additional electrode and the common electrode line to form a storage capacitor.
  • TFT thin film transistor
  • Still another embodiment of the present invention provides a liquid crystal display comprising a liquid crystal panel, wherein: the liquid crystal panel comprises a color filter substrate and an array substrate as described above.
  • 1A is a partial top plan view of a conventional array substrate
  • Figure 1B is a side elevational cross-sectional view taken along line A-A of Figure 1A;
  • FIG. 2A is a partial top plan view showing another array substrate of the prior art
  • Figure 2B is a side elevational cross-sectional view taken along line BB of Figure 2A;
  • FIG. 3A is a partial top plan view of an array substrate according to a first embodiment of the present invention
  • FIG. 3B is a side cross-sectional view of the array substrate taken along line C-C of FIG. 3A;
  • FIG. 4 is a partial top plan view of an array substrate according to Embodiment 2 of the present invention
  • FIG. 5A is a partial top plan view of the array substrate according to Embodiment 3 of the present invention
  • FIG. 5B is a side cross-sectional view taken along line DD of FIG. Schematic;
  • FIG. 6 is a partial top plan view of an array substrate according to Embodiment 4 of the present invention
  • FIG. 7A is a partial top plan view of the array substrate according to Embodiment 5 of the present invention
  • FIG. 7B is a side cross-sectional view taken along line EE of FIG. 7A. Schematic;
  • FIG. 8A is a partial top plan view of an array substrate according to a fifth embodiment of the present invention
  • FIG. 8B is a side cross-sectional view taken along line F-F of FIG. 7A;
  • FIG. 9A is a partial top plan view showing the structure of the array substrate according to the sixth embodiment of the present invention
  • FIG. 9B is a side cross-sectional view along line G-G of FIG. 9A;
  • FIG. 10A is a partial top plan view of a second embodiment of the present invention
  • FIG. 10B is a side cross-sectional view taken along line I-I of FIG. 10A. detailed description
  • FIG. 3A is a partial top plan view of the array substrate 100 according to the first embodiment of the present invention
  • FIG. 3B is a side cross-sectional view taken along line C-C of FIG. 3A.
  • the array substrate 100 includes a base substrate 1, which may be a glass substrate or a plastic substrate.
  • a plurality of data lines 5 and a plurality of gate lines 2 crossing each other are formed on the base substrate 1.
  • the data line 5 and the gate line 2 enclose a pixel unit arranged in a matrix form.
  • Each of the pixel units includes a thin film transistor (TFT) switch and a pixel electrode 11 for controlling whether or not each pixel unit is used for display.
  • the TFT switch includes a gate electrode 3, a source electrode 7, a drain electrode 8 and The source layers 61 are disposed to each other to obtain a layer structure.
  • the gate electrode 3 of the TFT switch is connected to the gate line 2
  • the source electrode 7 is connected to the data line 5
  • the drain electrode 8 is connected to the pixel electrode 11
  • the active layer 61 is formed on the source electrode 7 and the drain electrode 8 and the gate electrode 3. between.
  • the data line 5, the gate line 2, the gate electrode 3 of the TFT switch, the source electrode 7, the drain electrode 8, the active layer 61, and the pixel electrode 11 may be collectively referred to as a conductive pattern.
  • the conductive patterns disposed in the same layer may be realized by a space arrangement, and the conductive patterns disposed in the different layers may be realized by spacing between the insulating layers sandwiched therebetween.
  • the conductive patterns disposed in different layers may be electrically connected to each other by via holes passing through the insulating layers.
  • the pixel electrodes 11 may be connected to the drain electrodes 8 through the passivation layer vias 10.
  • a common electrode line 12 is also formed on the array substrate 100.
  • the common electrode lines 12 are formed in the same layer as the gate lines 2 and the patterns of each other are spaced apart from each other.
  • An additional electrode 13 is formed above the gate line 2 (in a direction perpendicular to the substrate 1), and the gate electrode 2 is spaced apart from each other by the gate insulating layer 4, and the additional electrode 13 is electrically connected to the common electrode line 12.
  • the common electrode line 12 is formed in the same layer as the gate line 2
  • the additional electrode 13 is electrically connected to the common electrode line 12 through the additional via holes 14, 15.
  • the pattern of the pixel electrode 11 extends above the additional electrode 13 and the additional electrode 13 overlaps each other through the passivation layer 9.
  • a portion where the pixel electrode 11 overlaps the additional electrode 13 and the common electrode line 12 forms a storage capacitor, the pixel electrode 11 serves as one electrode of the storage capacitor, and the additional electrode 13 and the common electrode line 12 serve as the other electrode of the storage capacitor.
  • the additional via hole specifically includes a first via hole 14 and a second via hole 15 formed in the passivation layer 9 covering the data line 5 and the additional electrode 13 and located at the additional electrode 13 Above.
  • the second via hole 15 is formed in the gate insulating layer 4 and the passivation layer 9, and is located above the common electrode line 12.
  • a jumper 16 is formed on the passivation layer 16, and the jumper 16 connects the additional electrode 13 and the common electrode line 12 through the first via 14 and the second via 15.
  • the technical solution can utilize the existing array substrate manufacturing process to etch the additional via holes 14 and 15 while etching to form the passivation layer vias 10, and form the jumper wires 16 by etching to form the pixel electrodes 11.
  • the additional electrode 13 may be connected to the common electrode line 12 in various manners.
  • the shape of the additional electrode 13 is designed not only above the gate line but also partially over the common electrode line 12, through the additional via of the gate insulating layer ( Not shown) is connected to the common electrode line 12. In this configuration, it is not necessary to form the jumper 16 as shown above.
  • the technical solution of the present embodiment combines the storage capacitor based on the gate line 2 and the storage capacitor based on the common electrode line 12, and the additional electrode 13 formed above the gate line 2 is a separate electrode region.
  • a storage capacitor is formed between the domain and the pixel electrode 11.
  • the overlapping area between the common electrode line 12 and the pixel electrode 11 also forms a storage capacitor, and the two parts of the storage capacitor together constitute the storage capacitor of the pixel unit.
  • C the capacitance value
  • ⁇ the dielectric constant
  • k the electrostatic force constant
  • S the facing area of the two electrodes of the capacitor
  • d is the capacitance of the two electrodes The distance between them.
  • the distance between the gate line and the pixel electrode is larger than the distance between the additional electrode and the pixel electrode, so this embodiment of the present embodiment
  • the value of the partial storage capacitor is also improved compared with the prior art; on the other hand, since the parasitic capacitance is reduced, the structure of the embodiment can optimize the resistance-capacitance delay characteristic and improve the picture quality with respect to the gate-based storage capacitor structure.
  • FIG. 4 is a partial top plan view of an array substrate 200 according to a second embodiment of the present invention.
  • the difference between this embodiment and the first embodiment is that the additional electrodes 13 on each gate line 2 and two adjacent pixel units
  • the common electrode lines 12 are all electrically connected.
  • This technical solution can be easily realized by appropriately changing the number and position of the additional via holes, and changing the pattern of the jumper wires 16 in which the jumper wires 16 are respectively formed in the adjacent two pixel cells.
  • the upper vias 151, 152 are electrically connected to the two common electrode lines 12.
  • the technical solution of the embodiment can not only optimize the storage capacitor, but also connect the adjacent common electrode lines formed by the rows through the additional electrodes, thereby avoiding the common voltage difference between the common electrode lines of each row, and making the common voltage uniformity in the common electrode lines more uniform. High, this can avoid flickering of the pixel unit during display.
  • FIG. 5A is a partial top plan view of an array substrate 300 according to Embodiment 3 of the present invention
  • FIG. 5B is a side cross-sectional view along line D-D of FIG. 5A.
  • the technical solution of the present embodiment differs from the first embodiment in that the common electrode line 12 is formed in the same layer as the data line 5 and the patterns are spaced apart from each other, and the additional electrode 13 is formed integrally with the common electrode line 12. As shown in FIG. 5A, the common electrode line 12 extending from the longitudinal direction of the additional electrode 13 extends laterally parallel to the gate line 2 over the gate line 2 to overlap the gate line 2 via the gate insulating layer 4.
  • the technical solution of this embodiment still has the advantage of increasing the storage capacitor, and the area of the common electrode line can be reduced under the premise of forming the equivalent storage capacitor value, thereby providing the aperture ratio of the pixel unit.
  • the present embodiment also omits the process of forming the additional electrode via and the jumper.
  • FIG. 6 is a partial top plan view of an array substrate 400 according to Embodiment 4 of the present invention.
  • a pass-through hole 17 is formed in the passivation layer 9 on the common electrode line 12 in adjacent pixel units on each side of each data line 5, and a passivation layer on the data line 5 is formed.
  • a communication line 18 is formed on the ground, and the communication line 18 is connected to the common electrode line 12 in the adjacent pixel unit through the connection hole 17.
  • the technical solution of the embodiment can not only optimize the storage capacitors, but also connect adjacent common electrode lines formed in columns to avoid storing a common voltage difference between the common electrode lines of the columns, so that the common voltage uniformity in the common electrode lines is higher. This can avoid flickering of the pixel unit during display.
  • Embodiments of the present invention also provide a method of fabricating an array substrate, the method comprising: forming a gate line, a gate electrode, a common electrode line, a data line, an active layer, a source electrode, a drain electrode, and a pixel electrode on the base substrate, respectively.
  • a step of patterning wherein, while forming the data line pattern, a pattern of additional electrodes is further formed, the additional electrode is located above the gate line, and the gate electrode is separated from each other by the gate insulating layer, and the additional electrode and the common
  • the electrode lines are electrically connected; the pattern of the formed pixel electrodes extends over the additional electrodes to overlap the additional electrodes, and the portion of the pixel electrodes overlapping the additional electrodes and the common electrode lines forms a storage capacitor.
  • the steps of forming the gate lines, the gate electrodes, the common electrode lines, the data lines, the active layer, the source electrodes, the drain electrodes, and the pixel electrode patterns are in various forms, and a typical four-time mask process will be described below as an example.
  • the method for manufacturing an array substrate provided in Embodiment 5 of the present invention includes the following steps:
  • Step 710 forming a pattern including the gate line 2, the gate electrode 3, and the common electrode line 12 on the base substrate 1.
  • the patterns of the common electrode line 12 and the gate line 2 are spaced apart from each other, and the formed structure is as shown in FIGS. 7A and 7B.
  • the base substrate 1 may be a glass substrate or a plastic substrate.
  • Step 710 may specifically deposit a metal thin film by a magnetron sputtering method, the metal thin film may be an opaque metal, such as aluminum, molybdenum, etc., and then patterned by a masking process through a mask. Processes such as development and etching form the desired pattern.
  • Step 720 forming a gate insulating layer 4 on the base substrate 1 forming the above pattern, and the gate insulating layer 4 can be plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor)
  • PECVD PECVD Deposition
  • Step 730 forming a pattern including the data line 5, the active layer 61, the source electrode 7, the drain electrode 8, and the additional electrode 13 on the gate insulating layer 4, and the specific structure is as shown in Figs. 8A and 8B.
  • Step 730 may specifically be to perform a half exposure mask etch with a two-tone mask to form a pattern.
  • Step 740 forming a passivation layer 9 on the base substrate 1 on which the above pattern is formed.
  • Step 750 forming a passivation layer via 10 and an additional via in the passivation layer 9, the passivation layer via 10 corresponding to the position of the drain electrode 8, and the additional vias 14, 15 respectively corresponding to the additional electrode 13 and the common electrode line
  • Step 760 forming a pattern including the pixel electrode 11 and the jumper wire 16 on the base substrate 1 forming the above pattern, and the jumper wire 16 is connected to the additional electrode 13 and the common electrode line 12 through the additional via holes 14, 15, the structure of which can be seen 3A and 3B are shown.
  • the structure shown in Figs. 4A and 4B can also be formed depending on the positions of the additional vias 14, 15 and the jumper wires 16.
  • a third additional via located in the adjacent pixel unit may be formed in the passivation layer, and the third additional via is formed in the passivation layer and the gate insulating layer and corresponds to the adjacent The position of the common electrode line in the pixel unit, whereby the jumper formed on the passivation layer thereafter passes through the first, second, and third additional vias to connect the common electrode, the common electrode line, and the common among the adjacent pixel units Electrode wire. It has the advantages of increasing the storage capacitor value and increasing the aperture ratio of the pixel unit, and utilizes the original process of manufacturing the array substrate without increasing the process difficulty.
  • the method for manufacturing an array substrate provided in Embodiment 6 of the present invention includes the following steps:
  • Step 101 forming a pattern including the gate line 2 and the gate electrode 3 on the base substrate 1, as shown in Figs. 9A and 9B.
  • Step 102 forming a gate insulating layer 4 on the base substrate 1 on which the above pattern is formed.
  • Step 103 forming a pattern including the data line 5, the active layer 61, the source electrode 7, the drain electrode 8, the additional electrode 13, and the common electrode line 12 on the gate insulating layer 4, the common electrode line 12 and the additional electrode 13 - body formation.
  • the common electrode line 12 extending from the longitudinal direction of the additional electrode 13 extends laterally parallel to the gate line 2 over the gate line 2 to overlap the gate line 2 via the gate insulating layer 4.
  • Step 104 forming a passivation layer 9 on the base substrate 1 on which the above pattern is formed.
  • Step 105 forming a passivation layer via 10 in the passivation layer 9, the passivation layer via 10 corresponding to the position of the drain electrode 8.
  • Step 106 forming a pattern including the pixel electrode 11 on the base substrate 1 on which the above pattern is formed, the structure of which can be seen in Figs. 5A and 5B.
  • the passivation layer via 10 it is also possible to form the passivation layer via 10 simultaneously with the formation of the via hole 17 and the common via hole 17 formed in the adjacent pixel unit on both sides of each data line 5.
  • a pattern of the connecting lines 18 is formed at the same time as the pixel electrode 11 is formed, and the connecting line 18 is connected to the common electrode line 12 in the adjacent pixel unit through the connecting through hole 17.
  • the embodiment of the present invention further provides a liquid crystal display comprising a liquid crystal panel, wherein the liquid crystal panel comprises a color filter substrate and an array substrate provided by any embodiment of the present invention.

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Description

阵列基板及其制造方法和液晶显示器 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和液晶显示器。 背景技术
液晶显示器是目前常用的平板显示器，其中薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display, 简称 TFT-LCD )是液晶显示器中的主 流产品。 液晶面板是 TFT-LCD 中的重要部件， 一般包括对盒设置的阵列基 板和彩膜基板， 其间填充液晶层。
图 1A为现有阵列基板的局部俯视结构示意图， 图 1B为图 1A中沿 A-A 线的侧视剖切结构示意图。如图 1A和 1B所示，该阵列基板包括衬底基板 1 ; 衬底基板 1上形成有彼此交叉的数据线 5和栅线 2; 数据线 5和栅线 2围设 形成矩阵形式排列的像素单元； 每个像素单元包括 TFT开关和像素电极 11 ; TFT开关包括栅电极 3、 源电极 7、 漏电极 8和有源层 61 ; 栅电极 3连接栅 线 2, 源电极 7连接数据线 5, 漏电极 8连接像素电极 11 , 有源层 61形成在 源电极 7和漏电极 8与栅电极 3之间。 上述数据线 5、 栅线 2、 TFT开关的 栅电极 3、 源电极 7、 漏电极 8、 有源层 61以及像素电极 11可统称为导电图 案。对于各导电图案之间的绝缘， 同层设置的导电图案可通过间隔设置实现， 异层设置的导电图案可通过夹在中间的绝缘层进行间隔来实现。 另外， 异层 设置的导电图案可通过穿过之间的绝缘层的过孔来相互电连接。
在 TFT-LCD的显示过程中， 通过数据线经 TFT开关向像素电极输入图 像信号电压。 因为需要像素电极在一帧的显示周期中保持该图像信号电压， 所以在每个像素单元中需要形成存储电容 (Storage Capacitor, 简称 Cs), 以维 持像素电极上的图像信号电压。现有技术中主要有两种形成存储电容的方式， 一种方式称为基于栅线的存储电容（ Cs on Gate ),其结构如图 1A和 1B所示。 每个像素单元中的像素电极 11会延伸到相邻像素单元的栅线 2上，像素电极 11和相邻栅线 2的这部分重叠区域就形成了存储电容。
另一种方式称为基于公共电极线的存储电容（Cs on Common ), 其结构 如图 2A和 2B所示。 在这种方式中， 阵列基板还包括公共电极线 12, 其与 栅线 2同层形成但不相交， 像素电极 11与公共电极线 12重叠的部分就形成 了存储电容。 图 2A和 2B所示的结构中， 相比于图 1A和 1B的不同之处在 于公共电极线 12以及形成在有源层 61之上的欧姆接触层 62,以减小有源层 61与源电极 7和漏电极 8之间的接触电阻。 发明内容
本发明的一个实施例提供一种阵列基板， 包括： 衬底基板； 形成在所述 衬底基板上的彼此交叉的数据线和栅线， 其中所述数据线和所述栅线围设形 成矩阵形式排列的像素单元， 每个像素单元包括薄膜晶体管 ( TFT )开关和像 素电极； 所述衬底基板上形成的公共电极线； 和形成在所述栅线的上方的所 述附加电极， 其中所述附加电极和所述栅线之间以栅绝缘层相互间隔， 且所 述附加电极与所述公共电极线电连接； 其中， 所述像素电极延伸至所述附加 电极的上方间隔着钝化层与所述附加电极重叠， 所述像素电极与所述附加电 极和公共电极线重叠形成存储电容。
本发明的另一个实施例提供一种阵列基板的制造方法， 包括在衬底基板 上分别形成栅线、 公共电极线、 数据线、 薄膜晶体管（TFT )开关和像素电极 的步骤， 所述栅线和所述数据线交叉以形成矩阵形式排列的像素单元， 每个 像素单元包括 TFT开关和像素电极， 其中在形成所述数据线的同时， 还形成 附加电极， 以使所述附加电极位于所述栅线的上方， 所述附加电极和所述栅 线之间以栅绝缘层相互间隔， 且所述附加电极与所述公共电极线电连接； 所 述像素电极延伸至所述附加电极的上方与所述附加电极重叠， 所述像素电极 与所述附加电极和公共电极线重叠形成存储电容。
本发明的又一个实施例提供一种液晶显示器， 包括液晶面板， 其中： 所 述液晶面板包括彩膜基板和如上所述的阵列基板。 附图说明
图 1A为现有一种阵列基板的局部俯视结构示意图；
图 1B为图 1A中沿 A-A线的侧视剖切结构示意图；
图 2A为现有另一种阵列基板的局部俯视结构示意图； 图 2B为图 2A中沿 B-B线的侧视剖切结构示意图；
图 3A为本发明实施例一提供的阵列基板的局部俯视结构示意图； 图 3B为图 3A中沿 C-C线的侧视剖切结构示意图；
图 4为本发明实施例二提供的阵列基板的局部俯视结构示意图； 图 5A为本发明实施例三提供的阵列基板的局部俯视结构示意图； 图 5B为图 5A中沿 D-D线的侧视剖切结构示意图；
图 6为本发明实施例四提供的阵列基板的局部俯视结构示意图； 图 7A为本发明实施例五所制造阵列基板的局部俯视结构示意图一； 图 7B为图 7A中沿 E-E线的侧视剖切结构示意图；
图 8A为本发明实施例五所制造阵列基板的局部俯视结构示意图二； 图 8B为图 7A中沿 F-F线的侧视剖切结构示意图；
图 9A为本发明实施例六所制造阵列基板的局部俯视结构示意图一； 图 9B为图 9A中沿 G-G线的侧视剖切结构示意图；
图 10A为本发明实施例六所制造阵列基板的局部俯视结构示意图二； 图 10B为图 10A中沿 I-I线的侧视剖切结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有作出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
图 3A为本发明实施例一提供的阵列基板 100的局部俯视结构示意图， 图 3B为图 3A中沿 C-C线的侧视剖切结构示意图。
如图 3A和 3B所示， 该阵列基板 100包括衬底基板 1 , 衬底基板 1可以 为玻璃基板或塑料基板。 衬底基板 1上形成有彼此交叉的多条数据线 5和多 条栅线 2。 数据线 5和栅线 2围设形成矩阵形式排列的像素单元。 每个像素 单元包括薄膜晶体管 （TFT )开关和像素电极 11 , TFT开关用于控制每个像 素单元的是否用于显示。 TFT开关包括栅电极 3、 源电极 7、 漏电极 8和有 源层 61 , 它们彼此设置以得到层结构。 对于每个像素单元， TFT开关的栅电 极 3连接栅线 2, 源电极 7连接数据线 5, 漏电极 8连接像素电极 11 , 有源 层 61形成在源电极 7和漏电极 8与栅电极 3之间。 上述数据线 5、 栅线 2、 TFT开关的栅电极 3、 源电极 7、 漏电极 8、 有源层 61以及像素电极 11可统 称为导电图案。 对于各导电图案之间的绝缘， 同层设置的导电图案可通过间 隔设置实现，异层设置的导电图案可通过夹在之间的绝缘层进行间隔来实现。 另外， 异层设置的导电图案可通过穿过之间的绝缘层的过孔来相互电连接， 例如， 像素电极 11可通过钝化层过孔 10与漏电极 8相连。
该阵列基板 100上还形成公共电极线 12。 本实施例中， 公共电极线 12 与栅线 2同层形成且彼此的图案相互间隔。 栅线 2的上方（垂直于衬底基板 1的方向）形成有附加电极 13 , 附加电极 13和栅线 2之间以栅绝缘层 4相互 间隔， 且附加电极 13与公共电极线 12电连接。 当公共电极线 12与栅线 2 同层形成时， 附加电极 13通过附加过孔 14、 15与公共电极线 12电连接。像 素电极 11的图案延伸至附加电极 13的上方与附加电极 13通过钝化层 9彼此 重叠。像素电极 11与附加电极 13和公共电极线 12重叠的部分形成存储电容， 像素电极 11作为存储电容的一个电极，附加电极 13和公共电极线 12作为存 储电容的另一个电极。
在本实施例中， 附加过孔具体包括第一过孔 14和第二过孔 15, 第一过孔 14形成在覆盖数据线 5和附加电极 13的钝化层 9中， 且位于附加电极 13的 上方。 第二过孔 15形成在栅绝缘层 4和钝化层 9中， 且位于公共电极线 12 的上方。 钝化层 9上形成有跨接线 16, 跨接线 16穿过第一过孔 14和第二过 孔 15连接附加电极 13和公共电极线 12。 该技术方案可以利用已有的阵列基 板制造工艺， 在刻蚀形成钝化层过孔 10的同时刻蚀形成附加过孔 14、 15 , 利 用刻蚀形成像素电极 11的工艺同时形成跨接线 16。
附加电极 13与公共电极线 12的连接方式可以有多种， 例如， 设计附加 电极 13的形状不仅在栅线上方， 还部分延伸至公共电极线 12的上方， 通过 栅绝缘层的附加过孔 (未示出）与公共电极线 12相连。在这种结构中则无需 形成如上所示的跨接线 16。
本实施例的技术方案结合了基于栅线 2的存储电容和基于公共电极线 12 的存储电容两种形式，形成在栅线 2上方的附加电极 13是一个独立的电极区 域， 与像素电极 11之间形成了存储电容。 同时， 公共电极线 12与像素电极 11之间的重叠区域也形成了存储电容，这两部分存储电容共同构成了像素单 元的存储电容。
平板电容的电容值计算公式为： C=sS/4 kd, 其中， C为电容值， ε为介 电常数， k为静电力常量， S为电容两电极的正对面积， d为电容两电极间的 距离。 本发明的实施例的技术方案， 一方面以附加电极增加了存储电容的正 对面积， 因此可以提高存储电容值， 或者在保持相同存储电容值的前提下可 以减小公共电极线的面积， 从而提高像素单元的开口率； 另一方面， 在基于 栅线的存储电容方式中， 栅线和像素电极之间的距离比附加电极与像素电极 之间的距离大， 所以本实施例技术方案的这部分存储电容值也比现有技术有 所提高； 再一方面， 由于减小了寄生电容， 本实施例的结构相对于基于栅线 的存储电容结构还可以优化阻容延迟特性， 提高画面品质。
实施例二
图 4为本发明实施例二提供的阵列基板 200的局部俯视结构示意图， 本 实施例与实施例一的区别在于，每条栅线 2上的附加电极 13与相邻的两个像 素单元中的公共电极线 12均电连接。该技术方案可以通过适当改变附加过孔 的数量和位置， 以及改变跨接线 16的图案来简单的实现， 在图 4中跨接线 16通过分别形成在相邻两个像素单元中的公共电极线 12上方的过孔 151、 152 与这两条公共电极线 12电连接。
本实施例的技术方案不仅可以优化存储电容， 而且通过附加电极将成行 形成的相邻公共电极线相连， 避免各行公共电极线之间存储公共电压差， 使 公共电极线中的公共电压均匀性更高， 这样可以避免像素单元在显示过程中 发生的闪烁现象。
实施例三
图 5A为本发明实施例三提供的阵列基板 300的局部俯视结构示意图， 图 5B为图 5A中沿 D-D线的侧视剖切结构示意图。
本实施例的技术方案与实施例一的区别在于：公共电极线 12与数据线 5 同层形成且图案相互间隔，附加电极 13与公共电极线 12一体形成。如图 5A 所示， 附加电极 13 自纵向延伸的公共电极线 12在栅线 2之上平行于栅线 2 横向延伸从而经栅绝缘层 4与栅线 2重叠。 本实施例的技术方案仍然具有增加存储电容的优势， 在形成同等存储电 容值的前提下可以减小公共电极线的面积， 从而提供像素单元的开口率。 另 夕卜， 相比于实施例一的技术方案， 本实施例还省略了形成附加电极过孔和跨 接线的工艺。
实施例四
图 6为本发明实施例四提供的阵列基板 400的局部俯视结构示意图。 本 实施例以实施例三为基础， 每条数据线 5两侧相邻像素单元中的公共电极线 12上的钝化层 9中分别形成有连通过孔 17 ,在数据线 5的钝化层 9上形成有 连通线 18,该连通线 18穿过连通过孔 17连接相邻像素单元中的公共电极线 12。
本实施例的技术方案不仅可以优化存储电容， 而且将成列形成的相邻公 共电极线相连， 避免各列公共电极线之间存储公共电压差， 使公共电极线中 的公共电压均匀性更高， 这样可以避免像素单元在显示过程中发生的闪烁现 象。
本发明实施例还提供了一种阵列基板的制造方法， 该方法包括在衬底基 板上分别形成栅线、 栅电极、 公共电极线、 数据线、 有源层、 源电极、 漏电 极和像素电极图案的步骤， 其中， 在形成数据线图案的同时， 还同步形成附 加电极的图案， 该附加电极位于栅线的上方， 附加电极和栅线之间以栅绝缘 层相互间隔， 且附加电极与公共电极线电连接； 形成的像素电极的图案延伸 至附加电极的上方与附加电极重叠， 该像素电极与附加电极和公共电极线重 叠的部分形成存储电容。
形成栅线、 栅电极、 公共电极线、 数据线、 有源层、 源电极、 漏电极和 像素电极图案的步骤有多种形式，下面以典型的四次掩模工艺为例进行说明。
实施例五
本发明实施例五提供的阵列基板的制造方法包括如下步骤：
步骤 710、 在衬底基板 1上形成包括栅线 2、 栅电极 3和公共电极线 12 的图案， 公共电极线 12与栅线 2的图案相互间隔， 所形成的结构如图 7A和 7B所示。 衬底基板 1可以为玻璃基板或塑料基板。
步骤 710具体可以通过磁控溅射方法沉积一层金属薄膜， 该层金属薄膜 可以为不透光的金属， 例如铝、 钼等， 而后釆用构图工艺， 通过掩模板曝光、 显影和刻蚀等工艺形成所需图案。
步骤 720、 在形成上述图案的衬底基板 1上形成栅绝缘层 4, 栅绝缘层 4 可通过等离子体增强化学气相沉积 （ Plasma Enhanced Chemical Vapor
Deposition, 简称 PECVD )等方法沉积绝缘材料而成。
步骤 730、 在栅绝缘层 4上形成包括数据线 5、 有源层 61、 源电极 7、 漏 电极 8和附加电极 13的图案， 具体结构如图 8A和 8B所示。
步骤 730具体可以是釆用双色调掩模板进行半曝光掩模刻蚀来形成图案。 步骤 740、 在形成上述图案的衬底基板 1上形成钝化层 9。
步骤 750、 在钝化层 9中形成钝化层过孔 10和附加过孔， 钝化层过孔 10 对应漏电极 8的位置， 附加过孔 14、 15分别对应附加电极 13和公共电极线
12的位置；
步骤 760、 在形成上述图案的衬底基板 1上形成包括像素电极 11和跨接 线 16的图案， 跨接线 16穿过附加过孔 14、 15连接附加电极 13和公共电极 线 12, 其结构可参见图 3A和 3B所示。 根据附加过孔 14、 15和跨接线 16位 置的不同， 还可以形成图 4A和 4B所示的结构。
在本实施例的基础上， 还可以在钝化层中形成位于相邻像素单元中的第 三附加过孔， 第三附加过孔形成于钝化层和栅极绝缘层中并对应于相邻像素 单元中的公共电极线的位置， 由此之后在钝化层上形成的跨接线穿过第一、 第二和第三附加过孔连接附加电极、 公共电极线和相邻像素单元中的公共电 极线。 具有提高存储电容值和提高像素单元开口率的优点， 且利用了原有制造阵列 基板的工艺， 不增加工艺难度。
实施例六
本发明实施例六提供的阵列基板的制造方法包括如下步骤：
步骤 101、 在衬底基板 1上形成包括栅线 2和栅电极 3的图案， 如图 9A 和 9B所示。
步骤 102、 在形成上述图案的衬底基板 1上形成栅绝缘层 4。
步骤 103、 在栅绝缘层 4上形成包括数据线 5、 有源层 61、 源电极 7、 漏 电极 8、 附加电极 13和公共电极线 12的图案， 该公共电极线 12与附加电极 13—体形成。 如图 10A和 10B所示， 附加电极 13 自纵向延伸的公共电极线 12在栅线 2之上平行于栅线 2横向延伸从而经栅绝缘层 4与栅线 2重叠。
步骤 104、 在形成上述图案的衬底基板 1上形成钝化层 9。
步骤 105、 在钝化层 9中形成钝化层过孔 10, 该钝化层过孔 10对应漏电 极 8的位置。
步骤 106、在形成上述图案的衬底基板 1上形成包括像素电极 11的图案， 其结构可参见图 5A和 5B所示。
在本实施例的基础上，还可以：在形成钝化层过孔 10的同时还可以同步 形成连通过孔 17, 连通过孔 17形成在每条数据线 5两侧相邻像素单元中的 公共电极线 12上方；在形成像素电极 11的同时还同步形成连通线 18的图案， 该连通线 18穿过连通过孔 17连接相邻像素单元中的公共电极线 12,具体结 构可参见图 6所示。 具有提高存储电容值和提高像素单元开口率的优点， 且利用了原有制造阵列 基板的工艺， 不增加工艺难度。
本发明实施例还提供了一种液晶显示器， 包括液晶面板， 其中， 该液晶 面板包括彩膜基板和本发明任一实施例所提供的阵列基板。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其 限制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术 人员应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或 者对其中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技 术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、 一种阵列基板， 包括：
衬底基板；
形成在所述衬底基板上的彼此交叉的数据线和栅线， 其中所述数据线和 所述栅线围设形成矩阵形式排列的像素单元， 每个像素单元包括薄膜晶体管 ( TFT )开关和像素电极；
所述衬底基板上形成的公共电极线； 和
形成在所述栅线的上方的所述附加电极， 其中所述附加电极和所述栅线 之间以栅绝缘层相互间隔， 且所述附加电极与所述公共电极线电连接；
其中， 所述像素电极延伸至所述附加电极的上方间隔着钝化层与所述附 加电极重叠， 所述像素电极与所述附加电极和公共电极线重叠形成存储电容。
2、 根据权利要求 1所述的阵列基板， 其中：
每条所述栅线上方的所述附加电极与相邻的两个所述像素单元中的公共 电极线电连接。
3、 根据权利要求 2所述的阵列基板， 其中：
所述公共电极线与所述栅线同层形成且相互间隔。
4、 根据权利要求 1所述的阵列基板， 其中：
所述公共电极线与所述栅线同层形成且相互间隔。
5、 根据权利要求 4所述的阵列基板， 其中：
所述附加电极通过附加过孔及跨接线与所述公共电极线电连接， 所述附加过孔包括第一过孔和第二过孔， 所述第一过孔形成在覆盖所述 数据线和附加电极的所述钝化层中， 且位于所述附加电极的上方， 所述第二 过孔形成在所述栅绝缘层和钝化层中， 且位于所述公共电极线的上方；
所述跨接线形成在所述钝化层上并穿过所述第一过孔和所述第二过孔连 接所述附加电极和所述公共电极线。
6、 根据权利要求 1所述的阵列基板， 其中：
所述公共电极线与所述数据线同层形成且图案相互间隔， 所述附加电极 与所述公共电极线一体形成。
7、 根据权利要求 6所述的阵列基板， 其中：
每条数据线两侧相邻像素单元中在所述钝化层中分别形成有对应于各自 的公共电极线的连通过孔， 所述钝化层上形成有连通线， 所述连通线穿过所 述连通过孔连接相邻像素单元中各自的公共电极线。
8、 根据权利要求 4所述的阵列基板， 其中：
所述栅绝缘层中形成有对应于所述公共电极线的附加过孔， 所述附加电 极通过所述附加过孔与所述公共电极线电连接。
9、 一种阵列基板的制造方法， 包括在衬底基板上分别形成栅线、 公共电 极线、 数据线、 薄膜晶体管（TFT )开关和像素电极的步骤， 所述栅线和所述 数据线交叉以形成矩阵形式排列的像素单元， 每个像素单元包括 TFT开关和 像素电极， 其中：
在形成所述数据线的同时， 还形成附加电极， 以使所述附加电极位于所 述栅线的上方， 所述附加电极和所述栅线之间以栅绝缘层相互间隔， 且所述 附加电极与所述公共电极线电连接； 所述像素电极延伸至所述附加电极的上 方与所述附加电极重叠， 所述像素电极与所述附加电极和公共电极线重叠形 成存储电容。
10、 根据权利要求 9所述的阵列基板的制造方法， 其中， 在所述衬底基 板上分别形成所述栅线、 所述公共电极线、 所述数据线、 所述 TFT开关、 所 述像素电极和所述附加电极的步骤包括：
a )在所述衬底基板上形成包括所述栅线、所述 TFT开关的栅电极和所述 公共电极线， 所述公共电极线与所述栅线相互间隔；
b )在步骤 a之后在所述衬底基板上形成栅绝缘层；
c )在所述栅绝缘层上形成包括所述数据线、 所述 TFT开关的有源层、 源 电极和漏电极、 以及所述附加电极；
d )在步骤 c之后在所述衬底基板上形成钝化层， 所述钝化层中形成有对 应所述漏电极的钝化层过孔； 和
e )在所述钝化层上形成所述像素电极， 所述像素电极通过所述钝化层过 孔与所述漏电极电连接。
11、 根据权利要求 10所述的阵列基板的制造方法， 其中，
在步骤 d中， 在所述钝化层中还形成第一附加过孔和第二附加过孔， 所 述第一附加过孔形成在所述钝化层中并对应于所述附加电极的位置， 所述第 二附加过孔形成于所述钝化层和所述栅极绝缘层中并对应于所述公共电极线 的位置；
在步骤 e中， 在所述钝化层上还形成跨接线， 所述跨接线穿过所述第一、 第二附加过孔连接所述附加电极和所述公共电极线。
12、 根据权利要求 11所述的阵列基板的制造方法， 其中，
在步骤 d中， 在所述钝化层中还形成位于相邻像素单元中的第三附加过 孔， 所述第三附加过孔形成于所述钝化层和所述栅极绝缘层中并对应于所述 相邻像素单元中的公共电极线的位置，
所述跨接线穿过所述第一、 第二和第三附加过孔连接所述附加电极、 所 述公共电极线和所述相邻像素单元中的公共电极线。
13、 根据权利要求 10所述的阵列基板的制造方法， 其中， 在所述栅绝缘 层中形成有附加过孔， 在所述栅绝缘层上形成的所述附加电极通过所述附加 过孔与所述公共电极线电连接。
14、 根据权利要求 9所述的阵列基板的制造方法， 其中， 在所述衬底基 板上分别形成所述栅线、 所述公共电极线、 所述数据线、 所述 TFT开关、 所 述像素电极和所述附加电极的步骤包括：
a )在所述衬底基板上形成包括所述栅线和所述 TFT开关的栅电极； b )在步骤 a之后在所述衬底基板上形成栅绝缘层；
c )在所述栅绝缘层上形成包括所述数据线、 所述 TFT开关的有源层、 源 电极和漏电极、 所述附加电极和所述公共电极线， 所述公共电极线与所述附 加电极一体形成；
d )在步骤 c之后在所述衬底基板上形成钝化层， 在所述钝化层中形成钝 化层过孔， 所述钝化层过孔对应所述漏电极的位置； 以及
f )在所述钝化层上形成包括像素电极。
15、 根据权利要求 14所述的阵列基板的制造方法， 其中：
在步骤 d中， 还在每条数据线两侧相邻像素单元中的公共电极线上方的 所述钝化层中分别形成连通过孔；
在步骤 f 中， 还在所述钝化层上形成连通线， 所述连通线穿过所述连通 过孔连接相邻像素单元中的所述公共电极线。
16、 一种液晶显示器， 包括液晶面板， 其中： 所述液晶面板包括彩膜基 板和权利要求 1所述的阵列基板。
PCT/CN2011/073157 2010-04-23 2011-04-22 阵列基板及其制造方法和液晶显示器 WO2011131143A1 (zh)

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