WO2011130993A1 - 一种半导体器件结构及其形成方法 - Google Patents

一种半导体器件结构及其形成方法 Download PDF

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Publication number
WO2011130993A1
WO2011130993A1 PCT/CN2010/077339 CN2010077339W WO2011130993A1 WO 2011130993 A1 WO2011130993 A1 WO 2011130993A1 CN 2010077339 W CN2010077339 W CN 2010077339W WO 2011130993 A1 WO2011130993 A1 WO 2011130993A1
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layer
metal gate
gate
oxygen
thickness
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French (fr)
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陈世杰
王文武
王晓磊
韩锴
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/063,693 priority Critical patent/US20110254063A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates to the field of semiconductor fabrication and design, and more particularly to a semiconductor structure and a method of forming the same. Background technique
  • SiO 2 As the gate dielectric and heavily doped polysilicon as the gate electrode material when manufacturing MOS devices.
  • the Si0 2 gate dielectric in MOS transistors is approaching its limits. For example, in the 65-nm process, the thickness of the Si0 2 gate has dropped to 1.2 nm, which is about 5 silicon atomic layer thicknesses. If it continues to shrink, leakage current and power consumption will increase dramatically. At the same time, problems such as doping of boron atoms, polysilicon depletion effects, and excessive gate resistance caused by polysilicon gate electrodes will become more and more serious. Therefore, for technologies of 32 nm and below, the sharp increase in leakage current and power consumption will be solved by the development of new materials, new processes and new device structures.
  • CMOS devices with nodes of 45 nm and below require a gate dielectric of EOT (equivalent oxide thickness) not exceeding 1 nm to improve gate-to-channel control, so thicker Si0 2 interface layers are difficult to achieve, especially in 32 nm and 22 nm process technology, the EOT of the gate dielectric even need to achieve even 0.7nm 0.5nm or less, the thickness of the Si0 2 interface layer common high-k / metal gate process is reached 0.5-0.7 nm. Therefore, reducing EOT, especially reducing the EOT contribution of the Si0 2 interface layer, has become a key challenge in the new generation of high-k/metal gate technology.
  • EOT equivalent oxide thickness
  • a typical oxygen absorbing process involves inserting an oxygen absorbing metal layer between the high k gate dielectrics and attenuating the oxygen in the interface layer by high temperature annealing.
  • the "oxygen-absorbing metal” is introduced into the high-k gate medium.
  • the "oxygen-absorbing metal” directly causes the change of the high-k gate medium, so that The performance of MOS devices has other adverse effects. Summary of the invention
  • the object of the present invention is to solve at least one of the above technical drawbacks, in particular, by introducing an "indirect oxygen gettering process" to achieve an effect of reducing both the EOT of the device and the negative influence of the high k dielectric layer.
  • an aspect of the present invention provides a gate structure of a MOS semiconductor device, comprising: a substrate; an interface layer film formed over the substrate; and a high k formed on the interface layer film a gate dielectric layer; and a metal gate formed over the high-k gate dielectric layer, the metal gate including a metal gate work function layer, an oxygen gettering element barrier layer, and a metal gate oxygen gettering layer in order from bottom to top , metal gate barrier layer and polysilicon layer.
  • Another aspect of the invention provides a MOS semiconductor device comprising the gate structure as described above.
  • a further aspect of the present invention provides a method of forming a gate structure of the above MOS semiconductor device, comprising the steps of: providing a substrate; forming an interface layer film over the substrate; forming a high layer over the interface layer film a gate dielectric layer; a metal gate work function layer formed on the high-k gate dielectric layer; an oxygen gettering element barrier layer formed on the metal gate work function layer; and the oxygen gettering element barrier layer Forming a metal gate oxygen gettering layer; forming a metal gate blocking layer over the metal gate oxygen gettering layer; forming a polysilicon layer over the metal gate blocking layer; and rapidly thermal annealing to form a final gate structure.
  • the invention achieves isolation in the annealing process by introducing a metal gate oxygen absorbing layer into the metal gate
  • the outside oxygen enters the interface layer and absorbs oxygen in the interface layer, thereby thinning the interface layer, effectively reducing the EOT of the MOS device, and avoiding the diffusion of the "oxygen gettering element" by increasing the oxygen barrier element barrier layer.
  • Entering the high-k gate dielectric layer adversely affects it, making the integration of high-k/metal gate systems easier and device performance further improved.
  • FIGS. 2-8 are schematic diagrams showing an intermediate step of forming a gate structure of a MOS semiconductor device according to an embodiment of the present invention.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below on the "on" of the second feature may include the first and second features being formed in direct contact. Embodiments may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact.
  • the invention achieves the purpose of reducing the oxygen of the external MOS device into the interface layer and absorbing the oxygen in the interface layer by introducing a metal gate oxygen absorbing layer into the metal gate to achieve the purpose of reducing the EOT of the MOS device.
  • FIG. 1 is a schematic view showing a gate structure of a MOS semiconductor device according to an embodiment of the present invention.
  • the structure includes, in order from bottom to top, a semiconductor substrate 101, an interface layer film 102, a high-k gate dielectric layer 103, a metal gate 104, and a polysilicon layer 105.
  • the metal gate 104 includes a plurality of layers of materials, including: A gate work function layer 104-1, an oxygen gettering element barrier layer 104-2, a metal gate oxygen gettering layer 104-3, and a metal gate barrier layer 104-4.
  • the element in the metal gate oxygen gettering layer 104-3 shall have the ability to absorb oxygen from the interface layer during the heat treatment; and the purpose of increasing the oxygen gettering element barrier layer 104-2 is to block the diffusion of the "oxygen gettering element".
  • the high-k gate dielectric layer 103 adversely affects it.
  • the inventors can select various processes for manufacturing according to the above semiconductor structure, such as different types of product lines, different process flows, etc., but these processes
  • the fabricated semiconductor structure should be included in the scope of the present invention if it has substantially the same structure as the above-described structure of the present invention.
  • the method and the process for forming the above-described structure of the present invention will be specifically described below. It is also to be noted that the following steps are merely illustrative and not limiting of the present invention, and those skilled in the art may also Through other processes.
  • the method includes the following steps:
  • Step 1 A semiconductor substrate 101 is provided.
  • the substrate 101 is exemplified by Si, but in practical applications, the substrate may include any suitable semiconductor substrate material, specifically but not limited to Si, Ge, GeSi, GaAs, InP, GaInAs, SiC. , SOI (silicon on insulator) or any m/v compound semiconductor.
  • the substrate 101 can include various doping configurations in accordance with design requirements well known in the art, such as a p-type substrate or an n-type substrate. Additionally, substrate 101 can optionally include an epitaxial layer that can be altered by stress to enhance performance.
  • Step 2 An interfacial layer film 102 is grown on the substrate 101 to a thickness of about 0.2 to 0.8 nm, as shown in FIG. In the embodiment of the present invention, the interface layer film 102 is a SiO 2 film.
  • Step 3 A high-k gate dielectric layer 103 is grown on the interfacial layer film 102 to a thickness of about 1-3 nm, as shown in FIG.
  • the high-k dielectric layer includes hafnium oxide (HfO 2 ), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and combinations thereof, and/or other suitable materials.
  • the high-k gate dielectric layer 103 may be formed by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the high-k dielectric layer 103 is an HfO 2 film, and is formed by an ALD technique.
  • Step 4 A metal gate work function layer 104-1 having a thickness of about 5-30 nm is deposited on the high-k dielectric film 103, as shown in FIG.
  • the material of the metal gate work function layer 104-1 includes TaC, HfC, TiC, TiN, TiSiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, RuTa x , NiTa x , TaN, MoSiN, MoN x , TiCN, TaAlC, TiAlN,
  • the metal gate work function layer 104-1 is a TaN film. PtSi x , NiSi x , Pt, Ru, Ir, Mo, Hf u x , RuO x or a combination thereof.
  • Step 5 An oxygen gettering element barrier layer 104-2 is deposited on the metal gate work function layer 104-1 to a thickness of about 2-15 nm as shown in FIG.
  • the material of the oxygen gettering element barrier layer 104-2 includes TiN, TaN, Hf, TiSiN, TaSiN, HfSiN or a combination thereof, and in the embodiment of the present invention, the oxygen gettering element barrier layer 104-2 is TiN.
  • Step 6 depositing a metal gate oxygen gettering layer 104-3 on the oxygen gettering element barrier layer 104-2, the thickness of which is about 10-10 nm, as shown in FIG. 6, the metal gate oxygen gettering layer 104-3
  • the element in the film must have the ability to absorb oxygen from the interface layer during the heat treatment, including Ti, Hf, Al, Be, Mg, or a combination thereof.
  • the metal gate oxygen gettering layer is Ti.
  • Step 7 A metal gate barrier layer 104-4 is deposited over the metal gate oxygen gettering layer 104-3 to a thickness of 2-15 nm, as shown in FIG.
  • the material of the metal gate barrier layer 104-4 includes TiN, TaN, Hf, TiSiN, TaSiN, HfSiN or a combination thereof.
  • the metal gate barrier layer 104-4 is a TiN film.
  • steps 4-7 can be carried out using conventional deposition processes such as sputtering, PLD, MOCVD, ALD, PEALD or other suitable methods.
  • Step 8 depositing a polysilicon layer 105 on the metal gate barrier layer (104-3) to a thickness of about 30-70 nm, as shown in FIG.
  • Step 9 The structure is subjected to a rapid thermal annealing treatment.
  • the heat treatment temperature is about 300-1000 ° C, The time is about 5-300s.
  • the processed structure is shown in Figure 1.
  • the thickness of the SiO2 interface layer is about 0-0.5.
  • the invention achieves the isolation of external oxygen into the interface layer in the annealing process by introducing a metal gate oxygen gettering layer into the metal gate, thereby preventing the thickness of the Si0 2 interface layer from increasing. And by using the oxygen absorption technology, the thickness of the Si0 2 interface layer with the original thickness of 0.2-0.8 nm is reduced to 0.5 nm or less during the annealing process, and even completely removed, effectively reducing the EOT of the device. In addition, by adding oxygen to remove the element barrier layer, the "oxygen gettering element" is prevented from diffusing into the high-k gate dielectric layer, which adversely affects the integration of the high-k/metal gate system, and the device performance is further improved. .

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Description

一种半导体器件结构及其形成方法
技术领域
本发明涉及半导体制造及设计技术领域， 特别涉及一种半导体结构及 其形成方法。 背景技术
在微电子技术发展的数十年历程中， 逻辑芯片制造商制造 MOS 器件 时， 一直釆用 Si02作为栅介质、 重掺杂的多晶硅作为栅电极材料。 但是， 随着特征尺寸的不断缩小， MOS晶体管中的 Si02栅电介质已临近了极限。 例如， 在 65纳米工艺中， Si02栅的厚度已降至 1.2纳米， 约为 5个硅原子 层厚度， 如果再继续缩小， 漏电流和功耗将急剧增加。 同时， 由多晶硅栅 电极引起的掺杂硼原子扩散、 多晶硅耗尽效应以及过高的栅电阻等问题也 将变得越来越严重。 因此， 对于 32纳米及以下各技术代， 急剧增加的漏电 流和功耗等问题将亟待新材料、 新工艺及新器件结构的开发来解决。
为降低漏电流和功耗， 目前有一种改进技术是釆用"高 k/金属栅"结构。 目前， 国际上各主要半导体公司都已开始着手面向 32纳米及以下技术代的 "高 k/金属栅"技术的开发。 Intel披露出在釆用高 k栅介质材料后， 器件的 漏电流降为原来的十分之一。 但是， 在高 k/金属栅工艺中， 由于必须釆用 的高温退火工艺， 因此致使 Si02界面层在退火工艺中变厚。 另一方面， 45nm及以下节点的 CMOS器件需要 EOT (等效氧化层厚度） 不超过 lnm 的栅介质来提高栅极对沟道的控制能力，因此较厚的 Si02界面层难以实现， 尤其在 32纳米及 22纳米工艺技术中， 栅介质的 EOT甚至需要达到 0.7nm 甚至 0.5nm以下，而普通高 k /金属栅工艺中的 Si02界面层的厚度就达到了 0.5-0.7纳米。 因此， 缩小 EOT, 特别是缩小 Si02界面层所贡献的 EOT成 为了新一代高 k/金属栅技术中的一个关键挑战。
研究过程中我们发现， 在高温退火过程中， 当外界氛围中的氧不能进 入到栅介质结构里时， 一些金属薄膜或其他不饱和氧化介质薄膜对高 k栅 介质和半导体衬底间的界面层 （如 Si02 ) 中的氧具有"吸除"作用， 原因是 这些金属或不饱和氧化介质材料的吉布斯自由能变远大于半导体衬底 （如
Si ) , 这意味着这些金属的氧化物或不饱和氧化介质的饱和氧化物比半导 体衬底的氧化物更加稳定和容易形成。 因此， 在高温热处理过程中， 界面 层中的氧被驱动与这些"氧吸除金属或不饱和氧化介质"形成金属氧化物， 从而导致界面层厚度变小， 甚至消失。
一种典型的氧吸除工艺方法是在高 k 栅介质中间插入一氧吸除金属 层， 通过高温退火来吸除界面层中的氧。 但这种高 k栅介质里引入"氧吸除 金属"的"直接氧吸除工艺"仍有一些不足， 比如这种"氧吸除金属"会直接导 致高 k栅介质的改变， 以至于对 MOS器件的性能产生其他不利的影响。 发明内容
本发明的目的旨在至少解决上述的技术缺陷之一， 尤其是通过引入 "间接氧吸除工艺" ， 达到既减小器件的 EOT, 又不对高 k介质层产生负 面影响的效果
为达到上述目的，本发明一方面提出一种 MOS半导体器件的栅极结构， 包括： 衬底； 形成在所述衬底之上的界面层薄膜； 形成在所述界面层薄膜 之上的高 k栅介质层； 和形成在所述高 k栅介质层之上的金属栅极， 所述 金属栅极从下至上依次包括金属栅功函数层、 氧吸除元素阻挡层、 金属栅 氧吸除层、 金属栅阻挡层和多晶硅层。
本发明另一方面提出一种 MOS 半导体器件， 包括如上所述的栅极结 构。
本发明再一方面提出一种形成上述 MOS 半导体器件的栅极结构的方 法， 包括以下步骤： 提供衬底； 在所述衬底之上形成界面层薄膜； 在所述 界面层薄膜之上形成高 k栅介质层； 在所述高 k栅介质层之上形成金属栅 功函数层； 在所述金属栅功函数层之上形成氧吸除元素阻挡层； 在所述氧 吸除元素阻挡层之上形成金属栅氧吸除层； 在所述金属栅氧吸除层之上形 成金属栅阻挡层； 在所述金属栅阻挡层之上形成多晶硅层； 快速热退火处 理形成最终栅极结构。
本发明通过在金属栅中引入金属栅氧吸除层来达到在退火工艺中隔绝 外界氧气进入界面层和吸除界面层中的氧的目的， 从而减薄界面层， 有效 地减小 MOS器件的 EOT, 并且通过增加氧吸除元素阻挡层， 从而避免 "氧 吸除元素"扩散进入高 k栅介质层而对其产生不利影响，使得高 k/金属栅系统 的集成更为容易， 器件性能得到进一步提高。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从下面 的描述中变得明显， 或通过本发明的实践了解到。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 本发明的附图是示意性的， 因此并没有按比 例绘制。 其中：
图 1为本发明实施例的 MOS半导体器件的栅极结构示意图； 图 2-8为形成本发明实施例的 MOS半导体器件的栅极结构的中间步骤 示意图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发 明， 而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结 构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以 在不同例子中重复参考数字和 /或字母。 这种重复是为了简化和清楚的目 的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明 提供了的各种特定的工艺和材料的例子， 但是本领域普通技术人员可以意 识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一 特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触 的实施例 , 也可以包括另外的特征形成在第一和第二特征之间的实施例 , 这样第一和第二特征可能不是直接接触。
本发明通过在金属栅中引入金属栅氧吸除层来达到在退火工艺中隔绝 外界氧气进入界面层和吸除界面层中的氧的目的， 以此来达到降低 MOS 器件 EOT的目的。
如图 1所示，为本发明实施例提出的 MOS半导体器件的栅极结构示意 图。 该结构从下至上依次包括： 半导体衬底 101、 界面层薄膜 102、 高 k栅 介质层 103、 金属栅极 104以及多晶硅层 105 , 其中， 金属栅极 104包括多 层材料层， 具体包括： 金属栅功函数层 104-1、 氧吸除元素阻挡层 104-2、 金属栅氧吸除层 104-3和金属栅阻挡层 104-4。 金属栅氧吸除层 104-3中的 元素须具备在热处理过程中从界面层吸除氧的能力； 而增加氧吸除元素阻 挡层 104-2的目的在于阻挡 "氧吸除元素" 扩散进入高 k栅介质层 103而 对其产生不利影响。
为了更清楚的理解本发明提出的上述半导体器件的栅极结构， 本发明 术人员能够根据上述半导体结构选择多种工艺进行制造， 例如不同类型的 产品线， 不同的工艺流程等等， 但是这些工艺制造的半导体结构如果釆用 与本发明上述结构基本相同的结构， 达到基本相同的效果， 那么也应包含 在本发明的保护范围之内。 为了能够更清楚的理解本发明， 以下将具体描 述形成本发明上述结构的方法及工艺， 还需要说明的是， 以下步骤仅是示 意性的， 并不是对本发明的限制， 本领域技术人员还可通过其他工艺实现。
如图 2-8所示，为形成本发明实施例上述 MOS半导体器件的栅极结构 的中间步骤示意图， 该方法包括以下步骤：
步骤 1 : 提供半导体衬底 101。 在本实施例中， 衬底 101 以 Si为例， 但实际应用中， 衬底可以包括任何适合的半导体衬底材料， 具体可以是但 不限于 Si、 Ge、 GeSi、 GaAs、 InP、 GaInAs、 SiC、 SOI (绝缘体上硅）或者 任何 m/ v族化合物半导体等。 根据现有技术公知的设计要求（例如 p型衬 底或者 n型衬底） ， 衬底 101 可以包括各种掺杂配置。 此外， 衬底 101可 以可选地包括外延层， 可以被应力改变以增强性能。 步骤 2: 在衬底 101上生长界面层薄膜 102, 其厚度约为 0.2-0.8nm, 如图 2所示。 在本发明实施例中， 界面层薄膜 102为 Si02薄膜。
步骤 3 :在界面层薄膜 102上生长高 k栅介质层 103 ,其厚度为约 l-3nm, 如图 3所示。 高 k介质层包括二氧化铪（Hf02 ) 、 HfSiO、 HfSiON、 HfTaO, HfTiO, HfZrO及其组合， 以及 /或者其他合适的材料。 高 k栅介质层 103 可以通过例如化学气相沉积（CVD )或者原子层沉积（ALD ) 的工艺来形成。 在本发明实施例中， 该高 k介质层 103为 Hf02薄膜， 并且釆用 ALD技术生 成。
步骤 4: 在高 k介质薄膜 103上淀积金属栅功函数层 104-1 , 其厚度为约 5-30nm, 如图 4所示。 金属栅功函数层 104-1的材料包括 TaC、 HfC、 TiC、 TiN、 TiSiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 RuTax、 NiTax、 TaN、 MoSiN、 MoNx、 TiCN、 TaAlC、 TiAlN、 PtSix、 NiSix、 Pt、 Ru、 Ir、 Mo、 Hf ux、 RuOx或其组合等， 在本发明实施例中， 金属栅功函数层 104-1 为 TaN薄膜。
步骤 5: 在金属栅功函数层 104-1上淀积氧吸除元素阻挡层 104-2 , 其厚 度为约 2-15nm, 如图 5所示。 氧吸除元素阻挡层 104-2的材料包括 TiN、 TaN、 Hf 、 TiSiN、 TaSiN、 HfSiN或其组合等， 在本发明实施例中， 氧吸 除元素阻挡层 104-2为 TiN。
步骤 6: 在氧吸除元素阻挡层 104-2是上淀积金属栅氧吸除层 104-3 , 其厚度为约 l-10nm, 如图 6所示， 金属栅氧吸除层 104-3中的元素须具备 在热处理过程中从界面层吸除氧的能力， 包括 Ti、 Hf、 Al、 Be、 Mg或其 组合等， 在本发明实施例中， 该金属栅氧吸除层为 Ti。
步骤 7: 在金属栅氧吸除层 104-3上淀积金属栅阻挡层 104-4 , 其厚度 为 2-15nm, 如图 7所示。金属栅阻挡层 104-4的材料包括 TiN、 TaN、 Hf 、 TiSiN、 TaSiN、 HfSiN 或其组合等， 在本发明实施例中， 该金属栅阻挡层 104-4为 TiN薄膜。
需注意的是，步骤 4-7中的淀积可釆用常规沉积工艺，例如溅射、 PLD、 MOCVD、 ALD、 PEALD或其他合适的方法。
步骤 8 : 在金属栅阻挡层 （ 104-3 ) 上淀积多晶硅层 105 , 厚度为约 30-70nm, 如图 8所示。
步骤 9: 对该结构进行快速热退火处理。 热处理温度为约 300-1000 °C, 时间为约 5-300s。 处理后的结构如图 1 所示， 其 Si02界面层的厚度约为 0-0.5
本发明通过在金属栅中引入金属栅氧吸除层来达到在退火工艺中隔绝 外界氧气进入界面层， 从而防止了 Si02界面层的厚度增加。 并且利用氧吸 除技术， 使得原本厚度达 0.2-0.8nm的 Si02界面层在退火过程中厚度减少为 0.5纳米以下， 甚至完全去除， 有效地减小了器件的 EOT。 另外， 通过增加氧 吸除元素阻挡层， 避免 "氧吸除元素"扩散进入高 k栅介质层而对其产生不利 影响， 使得高 k/金属栅系统的集成更为容易， 器件性能得到进一步提高。
尽管已经示出和描述了本发明的实施例， 对于本领域的普通技术人员 而言， 可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例 进行多种变化、 修改、 替换和变型， 本发明的范围由所附权利要求及其等 同限定。

Claims

权 利 要 求
1、 一种 MOS半导体器件的栅极结构， 其特征在于， 包括：
衬底；
形成在所述衬底之上的界面层薄膜；
形成在所述界面层薄膜之上的高 k栅介质层； 和
形成在所述高 k栅介质层之上的金属栅极， 所述金属栅极从下至上依 次包括金属栅功函数层、 氧吸除元素阻挡层、 金属栅氧吸除层、 金属栅阻 挡层和多晶硅层。
2、 如权利要求 1所述的栅极结构， 其特征在于， 所述界面层薄膜的厚 度为 0 - 0.5匪。
3、 如权利要求 1所述的栅极结构， 其特征在于， 所述高 k栅介质层的 厚度为 1 - 3nm。
4、 如权利要求 1所述的栅极结构， 其特征在于， 所述金属栅功函数层 的厚度为 5 - 30nm。
5、 如权利要求 1所述的栅极结构， 其特征在于， 所述氧吸除元素阻挡 层的厚度为 2 - 15nm。
6、 如权利要求 1所述的栅极结构， 其特征在于， 所述金属栅氧吸除层 的元素具备在热处理过程中从所述界面层薄膜吸除氧的能力。
7、 如权利要求 1所述的栅极结构， 其特征在于， 所述金属栅氧吸除层 的厚度为 1 - 10nm。
8、 如权利要求 1所述的栅极结构， 其特征在于， 所述金属栅阻挡层的 厚度为 2-15nm。
9、 如权利要求 1所述的栅极结构， 其特征在于， 所述多晶硅层的厚度 为 30 - 70 匪。
10、 一种 MOS半导体器件， 其特征在于， 包括权利要求 1-9任一项 所述的栅极结构。
11、 一种形成 MOS半导体器件的栅极结构的方法， 其特征在于， 包 括以下步骤： 提供衬底；
在所述衬底之上形成界面层薄膜；
在所述界面层薄膜之上形成高 k栅介质层；
在所述高 k栅介质层之上形成金属栅功函数层；
在所述金属栅功函数层之上形成氧吸除元素阻挡层:
在所述氧吸除元素阻挡层之上形成金属栅氧吸除层:
在所述金属栅氧吸除层之上形成金属栅阻挡层；
在所述金属栅阻挡层之上形成多晶硅层；
快速热退火处理形成最终栅极结构。
12、 如权利要求 1 所述的方法， 其特征在于， 所述界面层薄膜的厚 度为 0.2 - 0. 8匪。
13、 如权利要求 1 所述的方法， 其特征在于， 所述高 k栅介质层的 厚度为 1 - 3nm。
14、 如权利要求 1 所述的方法， 其特征在于， 所述金属栅功函数层 的厚度为 5 - 30nm。
15、 如权利要求 1 所述的方法， 其特征在于， 所述氧吸除元素阻挡 层的厚度为 2 _ 15nm。
16、 如权利要求 1 所述的方法， 其特征在于， 所述金属栅氧吸除层 的元素具备在热处理过程中从所述界面层薄膜吸除氧的能力
17、 如权利要求 6 所述的方法， 其特征在于， 所述金属栅氧吸除层 的厚度为 1 - 10nm。
18、 如权利要求 1 所述的方法， 其特征在于， 所述金属栅阻挡层的 厚度为 2-15nm。
19、 如权利要求 1 所述的方法， 其特征在于， 所述多晶硅层的厚度 为 30 - 70 匪。
20、 如权利要求 1 所述的方法， 其特征在于， 所述热退火处理的温 度为 300 - 1000。 C , 处理时间为 5 _ 300s
如权利要求 1 所述的方法， 其特征在于， 所述最终栅极结构中 的界面层薄膜的厚度为 0 - 0.5nmt
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