WO2011126049A1 - Comparateur, circuit amplificateur différentiel et convertisseur analogique/numérique - Google Patents

Comparateur, circuit amplificateur différentiel et convertisseur analogique/numérique Download PDF

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Publication number
WO2011126049A1
WO2011126049A1 PCT/JP2011/058723 JP2011058723W WO2011126049A1 WO 2011126049 A1 WO2011126049 A1 WO 2011126049A1 JP 2011058723 W JP2011058723 W JP 2011058723W WO 2011126049 A1 WO2011126049 A1 WO 2011126049A1
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Prior art keywords
transistor
period
voltage
comparison reference
input signal
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PCT/JP2011/058723
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English (en)
Japanese (ja)
Inventor
賢一 大畠
喜市 山下
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国立大学法人 鹿児島大学
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Priority to JP2012509685A priority Critical patent/JP5439590B2/ja
Publication of WO2011126049A1 publication Critical patent/WO2011126049A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45212—Indexing scheme relating to differential amplifiers the differential amplifier being designed to have a reduced offset

Definitions

  • the present invention relates to an analog / digital converter (AD converter) and a comparator suitable for use in an AD converter.
  • AD converter analog / digital converter
  • a parallel analog-to-digital converter can perform AD conversion at high speed by operating a comparator in parallel and performing a comparison between an analog input signal and a plurality of comparison reference voltages in parallel. Is possible.
  • n-bit parallel AD converter all-bit flash AD converter
  • (2 n ⁇ 1) comparators are required. Due to the large number of comparators, the parallel AD converter has a problem of high power consumption.
  • the comparator used in the AD converter includes a preamplifier unit that amplifies the difference between the analog input signal and the comparison reference voltage, and a latch unit that determines the sign of the output of the preamplifier unit.
  • the power consumption in the preamplifier section occupies most of the power consumption in the entire comparator.
  • a normal preamplifier unit requires a bias current source for biasing a transistor included in the preamplifier unit, and power is always consumed, so that it is difficult to reduce power consumption.
  • a steering (CS) amplifier has been proposed (for example, see Non-Patent Document 1).
  • the CS amplifier uses a charge source CS instead of a conventionally used current source and a load capacitance CL instead of a load resistance.
  • the CS amplifier sets the signal ⁇ to a high level (“H”, for example, 5 V) and the signal / ⁇ to a low level (“L”, for example, 0 V) in the reset period.
  • the CS amplifier sets the signal ⁇ to “L” and the signal / ⁇ to “H” during the amplification period. In this way, the CS amplifier performs amplification by moving the charge stored in the charge source CS to the load capacitor CL.
  • the CS amplifier does not use a current source through which a constant current flows, so that power consumption can be greatly reduced.
  • the CS amplifier does not perform amplification during the reset period. For this reason, the CS amplifier has a problem that a conventional offset cancellation method that is generally used cannot be applied. For this reason, only a bipolar transistor having a relatively small offset voltage has been applied as a transistor that controls amplification in the CS amplifier.
  • An object of the present invention is to enable offset cancellation while maintaining the low power consumption of a CS amplifier even when a MOS transistor is used as a drive element.
  • the comparator determines a magnitude relationship between the analog input signal and the comparison reference voltage based on a preamplifier unit that amplifies a difference between the analog input signal and the comparison reference voltage, and an output of the preamplifier unit.
  • a latch unit, and the preamplifier unit includes a transistor having a drain as an output terminal, a load capacitor connected to the output terminal, a charge source connected to a source of the transistor, the analog input signal, and the comparison
  • a compensation circuit that receives a reference voltage at an input terminal and has an output terminal connected to the gate of the transistor, and the compensation circuit includes a compensation circuit connected to the transistor in a first period in which the comparison reference voltage is input to the input terminal.
  • the gate and drain are connected, voltage information including information related to the offset voltage of the transistor is detected and stored, and the analog input is input to the input terminal. Signal and for compensating the offset voltage of the transistor using the voltage information stored in the first period to the second period is entered.
  • the analog-to-digital converter according to the present invention is an analog-to-digital converter that converts an input analog input signal into a digital signal, and each has a preamplifier section that amplifies a difference between the analog input signal and a comparison reference voltage.
  • a plurality of comparators that receive the comparison reference voltages different from each other, compare the comparison reference voltages with the analog input signal, and encode an output of the plurality of comparators to output the digital signal;
  • the preamplifier unit includes a transistor having a drain as an output terminal, a load capacitor connected to the output terminal, a charge source connected to a source of the transistor, the analog input signal, and the comparison reference voltage.
  • a compensation circuit having an input terminal and an output terminal connected to the gate of the transistor.
  • the gate and drain of the transistor are connected in a first period in which the comparison reference voltage is input to the input terminal, voltage information including information related to the offset voltage of the transistor is detected and stored, and the input terminal is The offset voltage of the transistor is compensated using the voltage information stored in the first period in the second period in which the analog input signal is input.
  • the compensation circuit detects and stores voltage information including information relating to the offset voltage in the first period, and cancels the offset voltage in the second period using the stored voltage information.
  • the offset can be canceled even if a MOS transistor is used as the drive element in the CS amplifier. Therefore, it is possible to provide a comparator having a preamplifier unit that can perform offset cancellation while maintaining the low power consumption of the CS amplifier, and an analog-digital converter using the comparator.
  • FIG. 1 is a diagram illustrating a configuration example of an analog-digital converter in the present embodiment.
  • FIG. 2 is a diagram illustrating a circuit configuration example of the preamplifier unit in the present embodiment.
  • FIG. 3 is a diagram for explaining the operation in the reset period of the preamplifier unit in the present embodiment.
  • FIG. 4 is a diagram for explaining the operation of the preamplifier section in the present embodiment during the amplification period.
  • FIG. 5A is a diagram for explaining the effect of offset compensation in the present embodiment.
  • FIG. 5B is a diagram for explaining the effect of offset compensation in the present embodiment.
  • FIG. 6A is a diagram illustrating another configuration example of the preamplifier unit in the present embodiment.
  • FIG. 6B is a diagram illustrating an offset voltage in the preamplifier unit illustrated in FIG. 6A.
  • FIG. 7 is a diagram illustrating another configuration example of the preamplifier unit in the present embodiment.
  • FIG. 8A is a diagram illustrating another configuration example of the analog-digital converter in the present embodiment.
  • FIG. 8B is a diagram illustrating another configuration example of the analog-digital converter in the present embodiment.
  • FIG. 9 is a diagram showing a circuit configuration of a conventional CS amplifier.
  • FIG. 10 is a diagram illustrating a circuit configuration example of the latch unit in the present embodiment.
  • FIG. 11 is a diagram illustrating another circuit configuration example of the latch unit according to the present embodiment.
  • FIG. 12A is a diagram illustrating a configuration example of a comparator according to the related art.
  • FIG. 12A is a diagram illustrating a configuration example of a comparator according to the related art.
  • FIG. 12B is a diagram illustrating a configuration example of the comparator according to the present embodiment.
  • FIG. 13 is a diagram illustrating another configuration example of the latch unit in the present embodiment.
  • FIG. 14 is a diagram illustrating another configuration example of the latch unit in the present embodiment.
  • FIG. 15 is a diagram illustrating another configuration example of the latch unit in the present embodiment.
  • FIG. 1 is a diagram illustrating a configuration example of an analog-digital converter (AD converter) according to an embodiment of the present invention.
  • FIG. 1 shows an example of a parallel AD converter (flash AD converter) that converts an input analog input signal VIN into an n-bit (n is a natural number) digital signal DT [n ⁇ 1: 0]. Yes.
  • n-bit a natural number
  • CMPi is a comparator (comparator), and ENC1 is an encoder.
  • the comparator CMPi receives the analog input signal VIN and the comparison reference voltage Vrefi.
  • the comparator CMPi compares the input analog input signal VIN with the comparison reference voltage Vrefi and outputs the comparison result.
  • the comparison reference voltage Vrefi is generated, for example, by dividing (for example, resistance voltage dividing) between the voltage VRH (reference voltage on the high potential side) and the voltage VRL (reference voltage on the low potential side).
  • dividing for example, resistance voltage dividing
  • each of the comparators CMPi has a preamplifier part and a latch part.
  • the preamplifier unit receives the analog input signal VIN and the comparison reference voltage Vrefi.
  • the preamplifier unit amplifies and outputs the difference (difference voltage) between the input analog input signal VIN and the comparison reference voltage Vrefi.
  • the latch unit determines the sign of the output of the preamplifier unit (finally determines a value of “1” or “0”) and outputs a determination result. In other words, the latch unit determines the magnitude relationship between the analog input signal VIN and the comparison reference voltage Vrefi based on the output of the preamplifier unit.
  • the encoder ENC1 receives a comparison result (an output from the latch unit of each comparator CMPi) between the analog input signal VIN and the comparison reference voltage Vrefi in each comparator CMPi.
  • the encoder ENC1 encodes these comparison results, converts them into digital signals DT [n-1: 0], and outputs them.
  • FIG. 2 is a diagram illustrating a circuit configuration example of the preamplifier unit in the present embodiment.
  • the preamplifier unit in the present embodiment is a circuit configuration of a CS (Charge-steering) amplifier by applying a CMOS manufacturing technology (process technology).
  • the preamplifier section in this embodiment is configured by applying a MOS (metal oxide semiconductor) transistor as a differential pair transistor (driving element) that controls amplification.
  • MOS metal oxide semiconductor
  • the preamplifier unit in this embodiment includes load capacitors CL1 and CL2, MOS transistors M1 and M2, charge source CS, detection capacitors CC1 and CC2, and switches SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52 and SW6 are provided.
  • the load capacities CL1 and CL2 form load elements.
  • the load capacitor CL1 has one electrode connected to the power supply voltage (Vcc) and the other electrode connected to the drain of the MOS transistor M1 via the switch SW21.
  • the load capacitor CL2 has one electrode connected to the power supply voltage (Vcc) and the other electrode connected to the drain of the MOS transistor M2 via the switch SW22.
  • switches SW11 and SW12 are provided in parallel with the load capacitors CL1 and CL2.
  • One electrode and the other electrode of the load capacitor CL1 can be connected by the switch SW11, and one electrode and the other electrode of the load capacitor CL2 can be connected by the switch SW12.
  • MOS transistors M1 and M2 form drive elements.
  • the MOS transistor M1 has a gate connected to one electrode of the detection capacitor CC1.
  • a positive-phase analog input signal VINP is supplied to the other electrode of the detection capacitor CC1 through the switch SW41, and a positive-phase comparison reference voltage VREFP is supplied through the switch SW51.
  • the gate of the MOS transistor M2 is connected to one electrode of the detection capacitor CC2.
  • a negative-phase analog input signal VINN is supplied to the other electrode of the detection capacitor CC2 via the switch SW42, and a negative-phase comparison reference voltage VREFN is supplied via the switch SW52.
  • the sources of the MOS transistors M1 and M2 are connected to one electrode of the charge source CS and to a reference potential (for example, ground) through the switch SW6.
  • the control signal ⁇ is supplied to the other electrode.
  • the drain and gate of the MOS transistor M1 can be connected by the switch SW31, and the drain and gate of the MOS transistor M2 can be connected by the switch SW32.
  • Each of the switches SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6 is composed of an arbitrary switching element or an arbitrary switching circuit.
  • an N channel MOS transistor may constitute a switch
  • a P channel MOS transistor may constitute a switch.
  • the switch may be constituted by a transfer gate composed of a pair of N channel MOS transistor and P channel MOS transistor.
  • each switch is in a conductive state (closed state, on state) when the supplied control signal ⁇ (or / ⁇ ) is at a high level (“H”, for example, the power supply voltage Vcc). In the case of a low level (“L”, for example, a reference potential), a non-conduction state (open state, off state) is assumed.
  • the preamplifier unit outputs the voltage at the connection point between the other electrode of the load capacitor CL1 and the switch SW21 as a reverse phase output signal VOUTN.
  • the preamplifier unit outputs the voltage at the connection point between the other electrode of the load capacitor CL2 and the switch SW22 as the positive phase output signal VOUTP.
  • the normal phase output signal VOUTP and the negative phase output signal VOUTN are output to a latch unit in the comparator.
  • the preamplifier section in this embodiment stores the charge in the charge source CS with the control signal ⁇ set to “H” and the control signal / ⁇ set to “L” during the reset period. Then, the preamplifier unit sets the control signal ⁇ to “L” and sets the control signal / ⁇ to “H” during the amplification period, and moves the charges stored in the charge source CS to the load capacitors CL1 and CL2, thereby amplifying the signals. Do.
  • the offset compensation is realized by paying attention to the fact that the main factor of the offset is the threshold voltage variation of the transistors M1 and M2 responsible for amplification.
  • the preamplifier unit in the present embodiment detects voltage information related to the threshold voltage including the offset voltage in the reset period and stores it in the detection capacitors CC1 and CC2, and uses the voltage information stored in the detection capacitors CC1 and CC2 in the amplification period. Cancel the offset.
  • the threshold voltages of the transistors M1 and M2 are VTH1 and VTH2, and the variations thereof are ⁇ VTH1 and ⁇ VTH2. 3 and 4, voltages corresponding to threshold voltage variations are schematically illustrated as voltage sources OV1 and OV2.
  • the control signal ⁇ is set to “H” and the control signal / ⁇ is set to “L”.
  • the switches SW11, SW12, SW31, SW32, SW51, SW52, and SW6 are in a conductive state (on state), and the switches SW21, SW22, SW41, and SW42 are in a nonconductive state ( Off state).
  • the switch SW41 when the switch SW41 is turned off and the switch SW51 is turned on, the potential of the node N11 becomes the comparison reference voltage VREFP. Further, when the switch SW21 is turned off and the switches SW31 and SW6 are turned on, the transistor M1 is connected between the gate and the drain, and the source is connected to the reference potential. Therefore, the transistor M1 discharges the electric charge stored in the detection capacitor CC1, so that the potential of the node N21 decreases. When the potential of the node N21 decreases to (VTH1 + ⁇ VTH1), the transistor M1 is turned off. That is, in the reset period, the potential of the node N21 finally becomes a constant value of (VTH1 + ⁇ VTH1).
  • the switch SW42 is turned off and the switch SW52 is turned on, so that the potential of the node N12 becomes the comparison reference voltage VREFN.
  • the switch SW22 is turned off and the switches SW32 and SW6 are turned on, the potential of the node N22 finally becomes a constant value of (VTH2 + ⁇ VTH2). Therefore, assuming that the capacitance of the detection capacitor CC2 is CV2, the charge of CV2 ⁇ (VREFN ⁇ (VTH2 + ⁇ VTH2)) is accumulated in the detection capacitor CC2. In this manner, voltage information related to the threshold voltage including the offset voltage ⁇ VTH2 is stored in the detection capacitor CC2.
  • the control signal ⁇ is set to “L” and the control signal / ⁇ is set to “H”.
  • the switches SW21, SW22, SW41, and SW42 are in a conductive state (ON state) and the switches SW11, SW12, SW31, SW32, SW51, SW52, and SW6 are in a nonconductive state during the amplification period. Off state).
  • the detection capacitor CC1 is connected in series between the input terminal of the positive-phase analog input signal VINP and the gate of the transistor M1.
  • the potential of the node N11 is the potential of the positive phase analog input signal VINP.
  • the charge accumulated in the detection capacitor CC1 during the reset period is stored. Therefore, the potential of the node N21 is (VINP ⁇ VREFP) + (VTH1 + ⁇ VTH1), and the potential of the node N31 is (VINP ⁇ VREFP) + VTH1.
  • the detection capacitor CC2 is connected in series between the input terminal of the negative-phase analog input signal VINN and the gate of the transistor M2. .
  • the potential of the node N12 becomes the potential of the negative-phase analog input signal VINN. Therefore, the potential of the node N22 is (VINN ⁇ VREFN) + (VTH2 + ⁇ VTH2), and the potential of the node N32 is (VINN ⁇ VREFN) + VTH2.
  • the voltage information stored in the detection capacitor CC1 during the reset period is used to cancel the threshold voltage variation ⁇ VTH1 of the transistor M1 that is the cause of the offset, and the potential (VINP ⁇ VREFP) + VTH1 is applied to the gate of the transistor M1. Is entered.
  • the voltage information stored in the detection capacitor CC2 during the reset period is used to cancel the threshold voltage variation ⁇ VTH2 of the transistor M2, which is a cause of the offset, and the potential (VINN ⁇ VREFN) + VTH2 is input to the gate of the transistor M2. Is done.
  • the transistor M1 is turned on / off according to the potential difference (VINP ⁇ VREFP), whereby the differential voltage between the positive phase analog input signal VINP and the positive phase comparison reference voltage VREFP is amplified and output as the negative phase output signal VOUTN. Is done.
  • the transistor M2 is turned on / off according to the potential difference (VINN ⁇ VREFN)
  • the differential voltage between the negative phase analog input signal VINN and the negative phase comparison reference voltage VREFN is amplified and output as the positive phase output signal VOUTP. Is done.
  • the preamplifier unit included in the comparator CMPi voltage information related to the threshold voltage including the offset voltage is detected and stored in the detection capacitors CC1 and CC2 during the reset period. During the period, the offset is canceled using the voltage information stored in the detection capacitors CC1 and CC2.
  • the circuit configuration of the CS amplifier is realized by applying the CMOS manufacturing technology, and the offset can be canceled even if the MOS transistor is used as the drive element. Therefore, a comparator having a preamplifier unit capable of performing offset cancellation can be provided by CMOS manufacturing technology while maintaining the low power consumption of the CS amplifier, and it is easy to integrate with other functional blocks and manufacture. Cost can be reduced. Further, by configuring the AD converter using the comparator, the power consumption of the AD converter can be greatly reduced.
  • the clock signal for driving the switch is ⁇ and / ⁇ .
  • the switch is composed of MOS transistors, the offset canceling effect may be reduced due to channel charge injection, clock feedthrough, or the like. In such a case, it is desirable to take an appropriate timing margin between the clocks using a conventionally known method such as a non-overlap clock.
  • FIG. 10 is a diagram illustrating a configuration example of the latch unit in the present embodiment.
  • the latch unit shown in FIG. 10 is obtained by applying the circuit technology of the CS amplifier to which the above-described CMOS manufacturing technology is applied to the latch unit.
  • M1, M2, M5, and M6 are MOS transistors (N channel MOS transistors), and M7 and M8 are MOS transistors (P channel MOS transistors).
  • CS is a charge source, and CC1 and CC2 are detection capacitors.
  • SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6, SW91, and SW92 are switches.
  • the reference potential input is the same potential VREF for both the positive phase input and the negative phase input.
  • components having the same functions as those shown in FIG. 2 are denoted by the same reference numerals, and redundant description of the components is omitted.
  • MOS transistors M5 and M7 are connected to form an inverter, and MOS transistors M6 and M8 are connected to form an inverter.
  • the output of one inverter is connected to the input of the other inverter, and positive feedback is applied. That is, the interconnection point between the drains of the MOS transistors M5 and M7 is connected to the gates of the MOS transistors M6 and M8, and the interconnection point between the drains of the MOS transistors M6 and M8 is connected to the gates of the MOS transistors M5 and M7.
  • switches SW91 and SW92 are connected to the outputs VOUTP and VOUTN of the latch unit, and the outputs VOUTP and VOUTN are connected to the power supply voltage (Vcc) and reset during the reset period.
  • the input signal is amplified by the MOS transistors M1 and M2, and is latched by the positive feedback circuit including the MOS transistors M5, M6, M7, and M8.
  • the latch unit illustrated in FIG. 10 with the preamplifier unit illustrated in FIG. 2 or FIG. 7, a comparator with low power consumption and a small offset voltage can be realized. .
  • FIG. 11 is a diagram illustrating another configuration example of the latch unit according to the present embodiment.
  • M1, M2, M5 and M6 are MOS transistors (N channel MOS transistors), and M7 and M8 are MOS transistors (P channel MOS transistors).
  • CC1 and CC2 are detection capacities.
  • SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6, SW91, SW92, and SW10 are switches.
  • the reference potential input is the same potential VREF for both the positive phase input and the negative phase input.
  • components having the same functions as those shown in FIGS. 2 and 10 are denoted by the same reference numerals, and redundant description of the components is omitted.
  • the sources of the MOS transistors M1 and M2 are connected to a reference potential (for example, ground) via the switch SW6 and to the reference potential via the switch SW10.
  • the clock signal / ⁇ 'for controlling the switch SW10 is a clock signal slightly delayed from the clock signal / ⁇ . By controlling the switch SW10 with the clock signal / ⁇ ', it is possible to prevent malfunction due to noise generated in the switches SW21, SW22, SW41, and SW42.
  • the potential of the outputs VOUTP and VOUTN of the latch unit can be reliably set to the reference potential (for example, 0 V) or the power supply voltage (Vcc), and the logic circuit connected to the next stage Can be driven without error.
  • the reference potential for example, 0 V
  • Vcc the power supply voltage
  • 5A and 5B are diagrams for explaining the effect of offset compensation of the preamplifier unit in the present embodiment.
  • 5A and 5B show simulation results relating to the offset voltage in the CS amplifier configured by applying the CMOS manufacturing technology.
  • the simulation results shown in FIGS. 5A and 5B are calculated using the Monte Carlo method on the assumption that the 90 nm CMOS manufacturing technology is used.
  • FIG. 5A shows a simulation result when the offset compensation function is not provided for comparison and reference
  • FIG. 5B shows a simulation result in the preamplifier unit having the offset compensation function in the present embodiment.
  • the offset voltage can be reduced to about 1/7 by applying the offset compensation technique in the present embodiment.
  • FIG. 6A is a diagram illustrating another configuration example of the preamplifier unit in the present embodiment.
  • Capacitive The example of a structure of the preamplifier part at the time of applying the averaging technique is shown.
  • PA1, PA2, PA3, PA4,... Are preamplifier units, and CAVP1, CAVP2, CAVP3,... And CAVN1, CAVN2, CAVN3,.
  • the positive phase side output of the preamplifier unit PAi and the positive phase side output of the preamplifier unit PA (i + 1) are coupled via the capacitor CAVPi.
  • the negative phase side output of the preamplifier part PAi and the negative phase side output of the preamplifier part PA (i + 1) are coupled via a capacitor CAVNi.
  • the offset voltage can be further reduced as shown in FIG. 6B.
  • 6B shows a case where LN1 applies the Capacitive Averaging technique (with capacity), and LN2 shows a case where the Capacitive Averaging technique is not applied (without capacity).
  • FIG. 7 is a diagram showing another configuration example of the preamplifier unit in the present embodiment.
  • FIG. 7 shows a configuration example of the preamplifier unit in the case where a positive feedback circuit is further provided.
  • CL1 and CL2 are load capacitors
  • M1 and M2 are MOS transistors (N channel MOS transistors)
  • M3 and M4 are MOS transistors (P channel MOS transistors).
  • CS and CSP are charge sources
  • CC1 and CC2 are detection capacitors.
  • SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6, SW7, and SW8 are switches.
  • components having the same functions as those shown in FIG. 2 are denoted by the same reference numerals, and redundant description of the components is omitted.
  • One electrode of the charge source CSP is connected to the power supply voltage (Vcc) via a switch SW7 that is controlled to be opened and closed by a control signal ⁇ , and is connected to the transistors M3 and M4 via a switch SW8 that is controlled to be opened and closed by a control signal / ⁇ . Connected to the source. Therefore, one electrode of the charge source CSP is connected to the power supply voltage (Vcc) in the reset period, and is connected to the sources of the transistors M3 and M4 in the amplification period. A control signal / ⁇ is supplied to the other electrode of the charge source CSP.
  • the drain of the transistor M3 and the gate of the transistor M4 are connected to the connection point between the switch SW21 and the other electrode of the load capacitor CL1 whose one electrode is connected to the power supply voltage (Vcc).
  • the gate of the transistor M3 and the drain of the transistor M4 are connected to the connection point between the switch SW22 and the other electrode of the load capacitor CL2 whose one electrode is connected to the power supply voltage.
  • one electrode is connected to the power supply voltage (Vcc) and the other electrode is set to “L” in the reset period, and charges are accumulated.
  • one electrode of the charge source CSP is connected to the sources of the transistors M3 and M4, so that the potential at the connection point between the load capacitor CL1 and the switch SW21 and the connection point between the load capacitor CL2 and the switch SW22 are connected. Based on the potential, the charge stored in the charge source CSP is supplied to the load capacitance.
  • the configuration shown in FIG. 7 can improve the gain and increase the gain.
  • FIG. 13 is a diagram illustrating another configuration example of the latch unit in the present embodiment.
  • the latch unit shown in FIG. 13 is similar to the latch unit shown in FIG. 10 and FIG. 11 by using the above-described offset cancellation technique with a double tail latch (for example, D. Scinkel et al., “A Double-Tail Latch-Type Voltage Sense Amplifier with 18 ps Setup-Hold Time ”, IEEE ISSCC Dig. of Tech. Papers, pp.314-315, Feb. (See 2007).
  • D. Scinkel et al. “A Double-Tail Latch-Type Voltage Sense Amplifier with 18 ps Setup-Hold Time ”, IEEE ISSCC Dig. of Tech. Papers, pp.314-315, Feb. (See 2007).
  • the latch portion shown in FIG. 13 has a two-stage configuration.
  • the circuit unit L1 in the first stage operates as a capacitive load amplifier having the input capacitor in the next stage as a load.
  • the second-stage circuit unit L2 latches the output of the first-stage circuit unit L1 using a positive feedback circuit, and outputs digital signals VOUTP and VOUTN.
  • M1, M2, M9, M10, M13, and M14 are MOS transistors (N-channel MOS transistors), and M11 and M12 are MOS transistors (P-channel MOS transistors).
  • CC1 and CC2 are detection capacities. SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6, SW10, and SW13 are switches.
  • the reference potential input is the same potential VREF for both the positive phase input and the negative phase input.
  • components having the same functions as those shown in FIGS. 2 and 11 are denoted by the same reference numerals, and redundant description of the components is omitted.
  • MOS transistors M9 and M11 are connected to form an inverter, and MOS transistors M10 and M12 are connected to form an inverter.
  • the output of one inverter is connected to the input of the other inverter, and positive feedback is applied. That is, the interconnection point between the drains of the MOS transistors M9 and M11 is connected to the gates of the MOS transistors M10 and M12, and the interconnection point between the drains of the MOS transistors M10 and M12 is connected to the gates of the MOS transistors M9 and M11.
  • the sources of the MOS transistors M9 and M10 are connected to the reference potential, and the sources of the MOS transistors M11 and M12 are connected to the power supply voltage (Vcc) via the switch SW13 controlled by the clock signal / ⁇ .
  • the MOS transistor M13 has a source connected to the reference potential and a drain connected to the gates of the MOS transistors M10 and M12.
  • the MOS transistor M14 has a source connected to the reference potential and a drain connected to the gates of the MOS transistors M9 and M11.
  • the output V1N of the first-stage circuit portion L1 is supplied to the gate of the MOS transistor M13, and the output V1P of the first-stage circuit portion L1 is supplied to the gate of the MOS transistor M14.
  • the latch unit shown in FIG. 13 operates in the same manner as the latch unit shown in FIG. 11, and during the reset period, the offset voltages of the MOS transistors M1 and M2 constituting the differential pair in the first-stage circuit unit L1. Is detected and stored in the detection capacitors CC1 and CC2. In the subsequent amplification period, the offset of the MOS transistors M1 and M2 constituting the differential pair is canceled using the voltage information stored in the detection capacitors CC1 and CC2, so that the offset of the latch unit can be reduced. become.
  • the first-stage circuit portion L1 that performs differential amplification and the second-stage circuit portion L2 that performs latching are cascade-connected, so that the voltage is lower than that of the latch portion shown in FIG. It is a configuration suitable for the conversion. Therefore, according to the configuration shown in FIG. 13, it is possible to realize a latch unit with a small offset voltage capable of low voltage operation.
  • FIG. 14 is a diagram illustrating another configuration example of the latch unit in the present embodiment.
  • the latch unit shown in FIG. 14 is obtained by applying the capacitive averaging technique to the latch unit shown in FIG. 14, each of L11, L12, L13, L14,... Corresponds to the first stage circuit section L1 in the latch section shown in FIG. 13, and each of L21, L22, L23, L24,. Corresponds to the second-stage circuit portion L2 in the latch portion shown in FIG. CAVP1, CAVP2, CAVP3,..., And CAVN1, CAVN2, CAVN3,.
  • the capacitive averaging technique By applying the capacitive averaging technique to the latch unit shown in FIG. 13, it is possible to average the offset voltage at the output of the first stage circuit units L11, L12, L13, L14,. According to the configuration shown in FIG. 14, the offset voltage can be further reduced as compared with the configuration shown in FIG. 13.
  • FIG. 15 is a diagram showing another configuration example of the latch unit in the present embodiment.
  • the latch unit shown in FIG. 15 further includes a positive feedback circuit in the first-stage circuit unit L1 in the latch unit shown in FIG. 13 to increase the gain of the first-stage circuit unit L1.
  • M1, M2, M9, M10, M13, and M14 are MOS transistors (N-channel MOS transistors), and M11, M12, M15, and M16 are MOS transistors (P-channel MOS transistors).
  • CC1 and CC2 are detection capacities, and CPF is a capacity.
  • SW11, SW12, SW21, SW22, SW31, SW32, SW41, SW42, SW51, SW52, SW6, SW10, SW13, and SW14 are switches.
  • the reference potential input is the same potential VREF for both the positive phase input and the negative phase input.
  • components having the same functions as those shown in FIGS. 2, 11, and 15 are denoted by the same reference numerals, and redundant description of the components is omitted.
  • the positive feedback circuit provided in the first-stage circuit unit L1 includes MOS transistors M15 and M16, a capacitor CPF, and a switch SW14.
  • the sources of the MOS transistors M15 and M16 are connected to the power supply voltage (Vcc) via the switch SW14 that is controlled to be opened and closed by the clock signal ⁇ .
  • the drain of the MOS transistor M15 and the gate of the MOS transistor M16 are connected to the node of the output V1N.
  • the gate of the MOS transistor M15 and the drain of the MOS transistor M16 are connected to the node of the output V1P.
  • the capacitor CPF has one electrode connected to the power supply voltage (Vcc) and the other electrode connected to the sources of the MOS transistors M15 and M16.
  • the positive feedback amount can be adjusted by the capacitance value of the capacitor CPF.
  • the capacitance value of the capacitor CPF For example, by increasing the capacitance value of the capacitor CPF, the gain of the first-stage circuit unit L1 can be increased.
  • the contribution of the offset from the second-stage circuit unit L2 can be reduced, and the offset voltage can be reduced as compared with the configuration shown in FIG.
  • the capacitive averaging technique can be applied to the latch unit shown in FIG. 15, and the offset voltage can be further reduced.
  • FIG. 12A and FIG. 12B the effect of the power reduction of the comparator in this embodiment is demonstrated.
  • the results of calculating the power consumption using a simulation when the operating frequency is 1 GHz and the standard deviation of the offset voltage is 0.6 mV or less under the 90 nm CMOS manufacturing technology are shown.
  • the power consumption of the comparator according to the prior art shown in FIG. 12A was compared with the power consumption of the comparator according to the present embodiment shown in FIG. 12B.
  • FIG. 12A is a diagram illustrating a configuration example of a comparator according to a conventional technique.
  • PA1, PA2, and PA3 are preamplifier units
  • L is a latch unit.
  • COP1, COP2, COP3, CON1, CON2, and CON3 are capacitors, and SW101, SW102, SW103, and SW104 are switches.
  • preamplifier units PA1, PA2, and PA3 in order to reduce the input conversion offset of the latch unit L, three stages of preamplifier units PA1, PA2, and PA3 are used.
  • the preamplifier sections PA1, PA2, and PA3 use differential amplifiers biased by a conventional constant current source.
  • offset information is stored in the capacitors COP1, COP2, COP3 and CON1, CON2, CON3 connected to the output terminals of the preamplifier units PA1, PA2, PA3, thereby canceling the offsets of the preamplifier units PA1, PA2, PA3. is doing.
  • the power consumption of the comparator is 1.7 mW.
  • FIG. 12B is a diagram illustrating a configuration example of the comparator according to the present embodiment.
  • OCPA is a preamplifier unit
  • CAN is a capacitive averaging network
  • OCL is a latch unit.
  • the preamplifier section OCPA is an offset cancelable CS amplifier whose circuit configuration is shown in FIG. 2
  • the latch section OCL is a latch section whose circuit configuration is shown in FIG.
  • the capacitive averaging network CAN shown in FIG. 6A is connected to the output of the preamplifier unit OCPA.
  • the preamplifier unit OCPA has a one-stage configuration.
  • the power consumption of the comparator is only 0.2 mW, and the power consumption can be greatly reduced by the present invention.
  • the parallel AD converter (all-bit flash AD converter) is described as an example, but the present invention is not limited to this.
  • the present invention can be applied to a subranging AD converter ⁇ subranging AD converter> as shown in FIG. 8A, or a successive approximation (successive approximation) AD converter ⁇ SAR (successive approximation register as shown in FIG. 8B. )
  • AD ⁇ ⁇ converter> is also applicable.
  • FIG. 8A is a diagram showing another configuration example of the analog-digital converter in the present embodiment.
  • FIG. 8A shows an example of a sub-ranging AD converter that converts an input analog input signal VIN into an n-bit (n is a natural number) digital signal DT [n ⁇ 1: 0].
  • reference numeral 71 denotes a sample hold amplifier (SHA).
  • amplifiers 72, 75 are parallel AD converters (flash AD converters), 73 is a digital-analog converter (DA converter), and 74 is a subtractor.
  • the first-stage parallel AD converter 72 performs AD conversion processing to determine the digital signal DT [n ⁇ 1: m], where m is an integer of 0 ⁇ m ⁇ (n ⁇ 1).
  • the parallel AD converter 75 performs AD conversion processing for determining the digital signal DT [m: 0].
  • the first-stage parallel AD converter 72 performs AD conversion processing on the higher-order bits of the digital signal DT [n ⁇ 1: 0]
  • the second-stage parallel AD converter 75 AD conversion processing is performed on the lower-order bits of the digital signal DT [n ⁇ 1: 0].
  • the input analog input signal VIN is sampled and held by the sample and hold amplifier 71 and supplied to the parallel AD converter 72 and the subtractor 74.
  • the parallel AD converter 72 performs AD conversion processing using the supplied analog input signal VIN, and the digital signal DT [n ⁇ 1: m] of the digital signals DT [n ⁇ 1: 0] is parallel.
  • the digital signal DT [n ⁇ 1: m] output from the parallel AD converter 72 is supplied to the DA converter 73 and output to the outside.
  • the digital signal DT [n ⁇ 1: m] supplied to the DA converter 73 is subjected to DA conversion processing, and an analog signal corresponding to the digital signal DT [n ⁇ 1: m] is output from the DA converter 73.
  • the analog signal output from the DA converter 73 from the analog input signal VIN output from the sample and hold amplifier 71 is subtracted by the subtractor 74 and supplied to the parallel AD converter 75.
  • the residual component obtained by subtracting the analog signal corresponding to the digital signal DT [n ⁇ 1: m] determined by the parallel AD converter 72 from the input analog input signal VIN becomes the parallel AD converter 75. To be supplied.
  • the parallel AD converter 75 performs AD conversion processing of the analog signal supplied from the subtractor 74, and the digital signal DT [m: 0] of the digital signals DT [n-1: 0] is converted into the parallel AD. Output from the converter 75. As described above, the input analog input signal VIN is converted into an n-bit digital signal DT [n ⁇ 1: 0] and output.
  • FIG. 8B is a diagram illustrating another configuration example of the analog-digital converter in the present embodiment.
  • FIG. 8B shows an example of a successive approximation (successive approximation) AD converter that converts an input analog input signal VIN into an n-bit (n is a natural number) digital signal DT [n ⁇ 1: 0].
  • 76 is a sample hold amplifier (SHA)
  • 77 is a comparator
  • 78 is a SAR circuit
  • 79 is a DA converter.
  • the comparator 77 is configured using, for example, the preamplifier unit shown in FIG.
  • the input analog input signal VIN is sampled and held by the sample and hold amplifier 76 and supplied to the comparator 77.
  • the comparator 77 compares the input analog input signal VIN with the output of the DA converter 79, and stores information indicating the magnitude relationship between the analog input signal VIN and the output of the DA converter 79 according to the comparison result.
  • the SAR circuit 78 sequentially determines the digital signal DT [n ⁇ 1: 0] bit by bit from the upper side based on the output from the comparator 77. Further, the SAR circuit 78 outputs a voltage generation code for generating a voltage to be compared with the analog input signal VIN next to the DA converter 79 according to the determined value.

Abstract

Cette invention se rapporte à un comparateur destiné à effectuer une comparaison entre un signal d'entrée analogique et une tension de référence de comparaison dans un convertisseur analogique/numérique, qui comprend : une unité de préamplification constituée de façon à inclure une capacité qui porte une charge; une source de charge; un transistor dans lequel un drain est connecté à la capacité qui porte une charge et dans lequel une source est connectée à la source de charge; et un circuit de compensation dans lequel le signal d'entrée analogique ou la tension de référence de comparaison est entré à une extrémité d'entrée et une extrémité de sortie est connectée à une grille d'un transistor; le circuit de compensation détectant des informations de tension qui comprennent des informations relatives à une tension de décalage dans une période de réinitialisation et stockant celles-ci, et compensant la tension de décalage à l'aide des informations de tension stockées dans une période d'amplification de façon à pouvoir exécuter une annulation de décalage tout en maintenant une faible consommation même si un transistor MOS est utilisé en tant qu'élément de commande dans un amplificateur CS.
PCT/JP2011/058723 2010-04-06 2011-04-06 Comparateur, circuit amplificateur différentiel et convertisseur analogique/numérique WO2011126049A1 (fr)

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KR101622788B1 (ko) * 2014-03-04 2016-05-20 고려대학교 산학협력단 전력소모를 줄일 수 있는 고효율 출력 드라이버 및 상기 출력 드라이버를 포함하는 송신기
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Publication number Priority date Publication date Assignee Title
CN103441736B (zh) * 2013-08-27 2016-02-10 西北工业大学 Cmos比较器的前置放大器电路
KR101622788B1 (ko) * 2014-03-04 2016-05-20 고려대학교 산학협력단 전력소모를 줄일 수 있는 고효율 출력 드라이버 및 상기 출력 드라이버를 포함하는 송신기
JPWO2018216677A1 (ja) * 2017-05-23 2020-01-09 株式会社村田製作所 比較回路

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